WO2013043954A4 - A high performance divider using feed forward, clock amplification and series peaking inductors - Google Patents

A high performance divider using feed forward, clock amplification and series peaking inductors Download PDF

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Publication number
WO2013043954A4
WO2013043954A4 PCT/US2012/056463 US2012056463W WO2013043954A4 WO 2013043954 A4 WO2013043954 A4 WO 2013043954A4 US 2012056463 W US2012056463 W US 2012056463W WO 2013043954 A4 WO2013043954 A4 WO 2013043954A4
Authority
WO
WIPO (PCT)
Prior art keywords
differential
differential cell
leg
coupled
balanced
Prior art date
Application number
PCT/US2012/056463
Other languages
French (fr)
Other versions
WO2013043954A2 (en
WO2013043954A3 (en
Inventor
Zaw Soe
Original Assignee
Tensorcom, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/243,986 external-priority patent/US8406710B1/en
Priority claimed from US13/243,908 external-priority patent/US8680899B2/en
Priority claimed from US13/243,880 external-priority patent/US8487695B2/en
Application filed by Tensorcom, Inc. filed Critical Tensorcom, Inc.
Priority to CN201280054536.0A priority Critical patent/CN104054267A/en
Priority to DE112012003966.1T priority patent/DE112012003966B4/en
Publication of WO2013043954A2 publication Critical patent/WO2013043954A2/en
Publication of WO2013043954A3 publication Critical patent/WO2013043954A3/en
Publication of WO2013043954A4 publication Critical patent/WO2013043954A4/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/50—Amplifiers in which input is applied to, or output is derived from, an impedance common to input and output circuits of the amplifying element, e.g. cathode follower
    • H03F3/505—Amplifiers in which input is applied to, or output is derived from, an impedance common to input and output circuits of the amplifying element, e.g. cathode follower with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/04—Frequency selective two-port networks
    • H03H11/12—Frequency selective two-port networks using amplifiers with feedback
    • H03H11/126—Frequency selective two-port networks using amplifiers with feedback using a single operational amplifier
    • H03H11/1286—Sallen-Key biquad
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45138—Two or more differential amplifiers in IC-block form are combined, e.g. measuring amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45394—Indexing scheme relating to differential amplifiers the AAC of the dif amp comprising FETs whose sources are not coupled, i.e. the AAC being a pseudo-differential amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/04—Frequency selective two-port networks
    • H03H11/12—Frequency selective two-port networks using amplifiers with feedback
    • H03H11/1213—Frequency selective two-port networks using amplifiers with feedback using transistor amplifiers

Abstract

A phase lock loop (PLL) is an important component in wireless systems. CMOS technology offers voltage controlled oscillator designs operating at 60 GHz. One of the difficulties is dividing the high frequency clock down to a manageable clock frequency using conventional CMOS. Although injection locked dividers can divide down this clock frequency, these dividers have limitations. A divide by 2 is presented that uses several techniques; feed forward, clock amplification and series peaked inductors to overcome these limitations.

Claims

AMENDED CLAIMS received by the International Bureau on 10 May 2013 (10.05.2013)
1. A switched differential amplifier comprising:
a first differential cell driven by a differential input signal;
a first load with a first center tap couples a first leg of the first differential cell to a first power supply;
a second load with a second center tap couples a second leg of the first differential cell to the first power supply;
a plurality of switches for coupling a source of the first differential cell to a second power supply; each of the plurality of switches receiving a different signal,
at least one of the different signals has a different phase than the remaining signals; and
the first and second center taps are coupled to a non-clocked version of the differential input signal.
2. The apparatus of claim 1, further comprising:
a second differential cell driven by the differential input signal;
each leg of the second differential cell corresponds to an equivalent leg in the first differential cell; a first leg of the second differential cell is coupled to the first center tap;
a second leg of the second differential cell is coupled to the second center tap; and
a transistor for coupling a source of the second differential cell to the second power supply, wherein an analog signal enables the transistor.
3. The apparatus of claim 1, wherein
the load is a series coupling of a resistor and a series peaking inductor.
4. The apparatus of claim 3, further comprising:
a capacitance coupled to each leg of the first differential cell forming a RLC network.
5. The apparatus of claim 4, whereby
the capacitance value can be electrically adjusted.
6. The apparatus of claim 5, wherein
an impedance of the series peaking inductor matches a magnitude of the electrically adjusted impedance of the capacitor.
7. The apparatus of claim 2, further comprising:
a current mirror coupled to the transistor that adjusts a current flow through the transistor.
8. The apparatus of claim 7, wherein
the current flow adjusts a resonant characteristic of a RLC network.
9. A differential amplifier comprising:
a first differential cell;
a first load with a first center tap couples a first leg of the first differential cell to a first power supply;
a second load with a second center tap couples a second leg of the first differential cell to the first power supply;
a current control for coupling the first differential cell to a second power supply;
a second differential cell;
each leg of the second differential cell corresponds to an equivalent leg in the differential cell; a first leg of the second differential cell is coupled to the first center tap;
a second leg of the second differential cell is coupled to the second center tap; and
a transistor for coupling a source of the second differential cell to the second power supply, wherein an analog signal enables the transistor.
10. The apparatus of claim 9, further comprising:
a plurality of switches coupled between the source of the differential cell and the current control; each of the plurality of switches receiving a different signal, and
at least one of the different signals has a different phase than the remaining signals.
11. The apparatus of claim 9, wherein
the load is a series coupling of a resistor and a series peaking inductor.
12. The apparatus of claim 9, further comprising:
a capacitance coupled to each leg of the differential cell forming an RLC network.
13. The apparatus of claim 12, whereby
the capacitance value can be electrically adjusted.
14. The apparatus of claim 13, wherein
an impedance of the series peaking inductor matches a magnitude of the electrically adjusted impedance of the capacitor.
15. The apparatus of claim 9, further comprising:
a current mirror coupled to the transistor that adjusts a current flow through the transistor.
16. The apparatus of claim 15, whereby
the current flow adjusts the characteristics of the resonant RLC network.
17. A divide by 2 apparatus comprising:
a clocked master differential amplifier with first balanced inputs and first balanced output leads; a complimentary clocked master memory storage unit with a first balanced memory leads coupled to the first balanced output leads;
a complimentary clocked slave differential amplifier with second balanced inputs coupled to the first balanced memory leads;
the complimentary clocked slave differential amplifier with second balanced output leads;
a clocked slave memory storage unit with a second balanced memory leads coupled to the second balanced output leads; and
the second balanced memory leads cross-coupled to the first balanced inputs; whereby
22 each of the clocked differential amplifiers and memory storage units use two switches in parallel to enabled or disable the differential amplifiers and memory storage units by applying a first high frequency clock to one switch and a second high frequency clock at the same frequency but with a different phase to the other switch.
18. The apparatus of claim 17, whereby
the first and second balanced memory leads provide the divide by 2 clock outputs.
19. The apparatus of claim 17, whereby
the different phase is 90°.
20. The apparatus of claim 17, whereby
a composite clock is the phasor addition of the two high frequency clocks.
23
PCT/US2012/056463 2011-09-23 2012-09-21 A high performance divider using feed forward, clock amplification and series peaking inductors WO2013043954A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201280054536.0A CN104054267A (en) 2011-09-23 2012-09-21 High performance divider using feed forward, clock amplification and series peaking inductors
DE112012003966.1T DE112012003966B4 (en) 2011-09-23 2012-09-21 High performance divider with pilot control, clock amplification and series equalizer coils

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US13/243,880 2011-09-23
US13/243,986 US8406710B1 (en) 2011-09-23 2011-09-23 Method and apparatus of minimizing extrinsic parasitic resistance in 60 GHz power amplifier circuits
US13/243,908 US8680899B2 (en) 2011-09-23 2011-09-23 High performance divider using feed forward, clock amplification and series peaking inductors
US13/243,880 US8487695B2 (en) 2011-09-23 2011-09-23 Differential source follower having 6dB gain with applications to WiGig baseband filters
US13/243,908 2011-09-23
US13/243,986 2011-09-23

Publications (3)

Publication Number Publication Date
WO2013043954A2 WO2013043954A2 (en) 2013-03-28
WO2013043954A3 WO2013043954A3 (en) 2013-06-06
WO2013043954A4 true WO2013043954A4 (en) 2013-07-04

Family

ID=47914878

Family Applications (3)

Application Number Title Priority Date Filing Date
PCT/US2012/056463 WO2013043954A2 (en) 2011-09-23 2012-09-21 A high performance divider using feed forward, clock amplification and series peaking inductors
PCT/US2012/056458 WO2013043950A1 (en) 2011-09-23 2012-09-21 A DIFFERENTIAL SOURCE FOLLOWER HAVING 6dB GAIN WITH APPLICATIONS TO WiGig BASEBAND FILTERS
PCT/US2012/056466 WO2013043957A2 (en) 2011-09-23 2012-09-21 Method and apparatus of minimizing extrinsic parasitic resistance in 60ghz power amplifier circuits

Family Applications After (2)

Application Number Title Priority Date Filing Date
PCT/US2012/056458 WO2013043950A1 (en) 2011-09-23 2012-09-21 A DIFFERENTIAL SOURCE FOLLOWER HAVING 6dB GAIN WITH APPLICATIONS TO WiGig BASEBAND FILTERS
PCT/US2012/056466 WO2013043957A2 (en) 2011-09-23 2012-09-21 Method and apparatus of minimizing extrinsic parasitic resistance in 60ghz power amplifier circuits

Country Status (3)

Country Link
CN (1) CN104054267A (en)
DE (1) DE112012003966B4 (en)
WO (3) WO2013043954A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103939068A (en) * 2014-04-16 2014-07-23 东北石油大学 Method for exploiting thickened oil or asphalt

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Also Published As

Publication number Publication date
CN104054267A (en) 2014-09-17
WO2013043954A2 (en) 2013-03-28
WO2013043957A3 (en) 2014-05-08
WO2013043954A3 (en) 2013-06-06
DE112012003966T5 (en) 2014-09-18
DE112012003966B4 (en) 2024-01-11
WO2013043950A1 (en) 2013-03-28
WO2013043957A2 (en) 2013-03-28

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