WO2013043954A2

WO2013043954A2 - A high performance divider using feed forward, clock amplification and series peaking inductors

Info

Publication number: WO2013043954A2
Application number: PCT/US2012/056463
Authority: WO
Inventors: Zaw Soe
Original assignee: Tensorcom, Inc.
Priority date: 2011-09-23
Filing date: 2012-09-21
Publication date: 2013-03-28
Also published as: DE112012003966B4; WO2013043957A2; DE112012003966T5; CN104054267A; WO2013043957A3; WO2013043954A4; WO2013043950A1; WO2013043954A3

Abstract

A phase lock loop (PLL) is an important component in wireless systems. CMOS technology offers voltage controlled oscillator designs operating at 60 GHz. One of the difficulties is dividing the high frequency clock down to a manageable clock frequency using conventional CMOS. Although injection locked dividers can divide down this clock frequency, these dividers have limitations. A divide by 2 is presented that uses several techniques; feed forward, clock amplification and series peaked inductors to overcome these limitations.

Description

A High Performance Divider Using Feed Forward, Clock Amplification ant! Series Peaking Inductors

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] The present, application is related to the co-filed U.S. application Ser, No, 13/243,880 filed on the same day herewith entitled "A Differential Source Follower having 6dB Gam with Applications to WiGig Baseband Filters", and the co-filed U.S. application Ser. No. 13/243,986 tiled on the same day herewith entitled "Method and Apparatus of Minimizing Extrinsic Parasitic Resistance in 60GHz Power Amplifier Circuits" both filed on September 23, 2011, which are invented by the same inventor as the present application and incorporated herein by reference in their entireties.

BACKGROUND OF THE INVENTION

[0002] The Federal Communications Commission (FCC) has allotted a spectrum of bandwidth in the 60GHz frequency range <57 to 64GHz). The Wireless Gigabit Alliance (WiGig) is targeting the standardization of this frequency band that will support data transmission rates up to 7 Gbps.

Integrated circuits, formed in semiconductor die, offer high frequency operation in this millimeter wavelength range of frequencies. Some of these integrated circuits util ize Complementary Metal Oxide Semiconductor (CMOS) while others can use either the Silicon-Germanium (SiGe) or Gallium Arsenide (GaAs) technology to form the dice in these designs. At 60GHz, achieving the desired parameters of frequency synthesis using VCOs and high performance dividers present difficult challenges.

[0003] Oscillator and frequency synthesizers are elements in communication systems. The highest performance circuits in a given technology are usually measured in some form of an on-chip oscillator, such as a ring oscillator using transistors or a resonate oscillator that uses transistors and reactive components in a regenerative connection. [0004] The frequency synthesizers are typicall phase locked loops (PLL). A PLL generates a high frequency clock signal using a voltage controlled oscillator (VCO) and compares this signal against a reference frequency. A stable low frequency signal based, for example, on a crystal is used as one of the reference frequencies within the phase lock loop. The negative feedback within the phase lock loop suppresses any phase noise due to the oscillator that generates the high frequency clock signal and allows the generation of stable high frequency clock signal s. A VCO is designed in. a given technology to achieve the maximum possible performance and push against the edge of technology boundaries to generate a high frequency clock signal. This clock signal has such a short duration ( 16 ps) at 60 GHz that any conventional computational CMOS gate being clocked by this signal would fail since the duration is so short, A prescalar is a circuit that divides down the high frequency clock signal to provide more time to calculate a computation. The conundrum is that the prescalar is itself a computational unit.

[0005] The prescalar produces a lower frequency clock signal which provides more time to demanding circuits so that they can perform their required functions. However, a conventional CMOS divide-hy-2 is not capable of operating at a clock rate of 60GHz. An injection locked divider is typically used to create a high frequency divider. But the injection locked divider has limitations; 1.) injection locked dividers have a very narrow locking range; and 2} commercial production of injection locked divider has not been well proven. Apparatus and methods are presented to overcome these limitations. A. divide-by ~2 is presented that incorporates these advances thereby eliminating the need for the injection locked divider.

BRIEF SUMMARY OF THE INVENTION

[0006] Various embodiments and aspects of the inventions will be described with reference to details discussed below and the accompanying drawings will illustrate the various embodiments. The following description and drawings are illustrative of the invention and are not to be construed as limiting the invention. Numerous specific details are described to provide a thorough

understanding of various embodiments of the present invention. However, in certatn instances, well- known or conventional details are not described in order to provide a concise discussion of embodiments of the present inventions.

[0007] As the power supply voltage reduces in the scal ing of i ntegraied circuits, the voltage headroom for analog integrated circuits decreases correspondingly. This makes the design of high- performance systems in a low power supply integraied circuit much more difficult and challenging. The CMOS VCO (Voltage Controlled Oscillator) in the MX can generate a clock signal operating in the 60GHz range of frequencies at reduced supply voltages. This clock signal needs to be divided down to a more manageable frequency before the remainder of the circuits on the chip can use this divided down clock signal. A divide by 2 is one of the first circuits to reduce the frequency of the clock signal to a more manageable frequency. The divide by 2 divides the high frequency clock signal (f) in half to generate a clock signal operating at half of the high frequency signal (f/2). N ote that the divide by 2 must be clocked at the high frequency rate (f). The period of a 60 GHz clock is about 16.6 ps while the delay through a device or transistor is slightly more than this. Thus, if conventional CMOS circuit techniques are applied to the divide by 2 clocked at 60GHz, conventional CMOS circuit techniques would prevent the operation of the divide by 2 since the delay through one CMOS device is larger than the clock period. This explains why designers are steered to the injection locked divider technique. Our technique offers a robust divide by 2 without resorting to the injection locked divider technique.

[0008] One of the embodiments of the disclosure removes the series bias transistor thereby increasing the headroom of differential amplifier. The increased headroom increases the dynamic range of applied signals. This feature allows faster performing circuits.

[0009] The conventional CMOS divide by 2 suffers from an RC delay caused by the capacitive load across the resistive load. A series peaking inductor is incorporated into each leg of the amplifier to tune out the output capacitance load that is coupled to the output of the differential amplifier. This effectively eliminates the RC delay thereby improving the performance of the circuit. [0010] Another embodiment use vector summation of two orthogonal clocks to create a composite clock signal that has an amplitude that is 41% larger. This clock signal is used to enable disable (switch) the differential amplifier and differential .memory of a flip flop. The increased amplitude of the composite clock signal increases the gate to source voltage applied to the switched transistor causing the composite clock signal to improve the performance of the circuit.

[001 1 ] An embodiment, uses feed ^"forward to a docked differential amplifier. However, the feed forward path is not docked. Instead, a current source regulates the current flow through the feed forward circuit, A current mirror can vary the current through the feed forward circiiit. Th s current can be reduced to 0 or varied to shift the resonant behavior of the RLC load. The first case removes the feed forward circuit's behavior by tri-stating the feed forward circuit while the second case can be used to improve performance of the divide by 2 or adjust the resonant circuit characteristics of the RLC circuit.

B IEF DESCRIPTION OF THE DRAWINGS

[0012] Please note that the drawings shown in this specification may not necessarily be drawn to scale and the relative dimensions of various elements in the diagrams are depicted schematically. T he inventions presented here may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be through and complete, and will fully convey the scope of the invention to those skiiled in the art. In other instances, well-known structures and fimctions have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiment of the invention. Like numbers refer to like elements in the diagrams.

[0013] FIG. la depicts a Phase look Loop (FIX),

[0014] FIG. lb shows dual modulus PLL with two counters 0015] FIG. 2a illustrates the PLL illustrated in FIG. J a with a di vider by 2 in the prescalar path in accordance with the present invention.

[0016] FIG, 2b depicts the dual modulus PLL illustrated in FIG, lb with a divide by 2 in the prescalar path in accordance with the present invention.

[00 j 7] FIG. 3a presents another dual modulus PLL in accordance with the present invention.

[0018] FIG-.3b illustrates a block representation of a divide by 2 in accordance with the present invention.

[00.1 ^'j FIG. 3c depicts a CMOS circuit implementation of a divide by 2 further identifying the latches in accordance with the present invention.

[0020] FIG. 4a illustrates the CMOS circuit implementation of a divide by 2 further identifying the components of the latches in accordance with the present invention,

[0021] FIG-. 4b presents the timi ng diagram of FIG. 4a in accordance with the present invention.

[0022] FIG. 4c depicts the master differential amplifier component of the divide by 2 in accordance with the present invention,

[0023] FIG. 5a presents the master differential amplifier component further partitioned into three regions in accordance with the present invention.

[0024] FIG. 5b illustrates a removal of one of the regions in accordance with the present invention.

[0025] FIG. 5c presents a series peaking inductor to compensate one of the remaining regions in accordance with the present invention. 0026] FIG. 5d illustrates a clock amplifier replacement in the last region in accordance with the present invention.

[0027] FIG, 5e depicts the vector addition providing the clock amplification in accordance with the present invention:.

[0028] FIG. 6a shows a timing diagram for the clock amplifier embodiment in accordance with the present invention.

[0029] FIG. 6b depicts a simplified model of the differential amplifier with the clock amplification devices in accordance with the present invention,

[0030] FIG, 6c illustrates the replacement of a single device and single clock for the clock amplifier of the circuit in FIG. 6b in accordance with the present invention.

[0031] FIG. 6d shows the window that the input signal D is vali d before and after the signal X changes state in accordance with the present invention.

[0032] FIG, 7a depicts the divide by 2 using several embodiments simultaneously in accordance with the present invention.

[0033] FIG. 7b illustrates a timing diagram for the divide by 2 in FIG. 7a in accordance with the present invention.

DETAILED DESCRIPTION OF THE .INVENTION

[0034] The inventions presented in this specification can he used in high frequency system designs.

Several embodiments are presented where any combination of these embodiments can be included into the circuit design. Although a divide by 2 is illustrated as benefiting from these techniques, these techniques can also be applied to other high speed circuits. [0035] FIG. la illustrates a conventional PLL. The reference frequency from a crystal of f f is divided down by the divide by R block 1-1 The low frequency signal is compared in the PDF (Phase and Frequency Detector) against the variable clock signal l The VCO 1-4 generates the high frequency signal f_mt. This signal is presented to the prescalar 1.-5 and is divided by N and compared against a reference signal in the PFD block 1 -2. The output of the PFD is low pass filtered (LPF 1-3) to generate a DC voltage that is applied to the VCO to adjust the high frequency signal f_mt.

[0036] in FIG. l b, a dual modulus prescalar is presented and allows division by one of two numbers. Depending on the value of the program counter -8 (value of P) or the swallow counter l~ 10 (value of S), the dual modulus prescalar 1-7 either divides the high frequency signal tout by N and or the quantity N +1. The value of P is always greater than the value of S. The S counter 1-10 and gate 1-9 counts down and divides f«a.by ^■+! until the S counter reaches zero, then the program counter is enabled and the prescalar divides by N for the remaining count within P. The f_nt signal is divided down by the reference divider 1-6 and compared within the PFD. The LPF and VCO blocks function as before. 0037] In FIG. 2s, the feedback path of the prescalar is partitioned into the two blocks. The first is a divide by 2 2-1 which divides f_(mt by two reducing this critical frequency by half. The clock period is now doubled to about 33 ps. Thus, one of the basic components in the prescalar function is the divide by 2 block 2-1 that divides the high frequency signal in half and doubles the amount of available processing time. By introducing a second divide by two (not shown), the clock period would then be 66 ps providing for much more time to perform additional processing within more complex circuit configurations. The remaining component of the prescalar 2-2 generates the clock signal that's compared against a reference signal in the PFD,

[00 8] FIG. 2b illustrates the dual modulus prescalar partitioned in series. The high frequency output clock signal f_mi is divided by two in 2-4. The remaining dual modulus prescalar block 2-3 now needs to only be concerned with a clock signal that has twice the period of the initial clock signal t_mi. If the period of time is still insufficient, an additional series divide by two can be inserted into the prescalar to further increase the available period of time available to the computation circuits.

[0039] FIG.3a illustrates another embodiment of PLL operating at 60 GHz, The phase and frequency detector FFD compares f _f against the output of the dual modulus prescalar. The PFD is applied to the charge pump 3-1 the output of the charge pump is filtered by the low pass filter LPF and applied to the voltage controlled oscillator. The VCO in this case is a quadrature VCO generating the real clock signals at 0° and 180° as well as generating the imaginary clock signals at 90° and 270°. The real and imaginary clock signals from the orthogonal signals and are called Q and CQ signals, respectively. All of the clock outputs of the VCO are loaded with matched loads to ensure that the relative phase differences between the real and imaginary generated clock signals remains orthogonal,

[0040] The Ci / C_Q clock signals are divided by 2 3-2 to reduce the frequency and increase the period of time for calculation. In addition, the signal is further divided by 2 3-3 but can now use a conventional di vide by 2 circuit structure. The remainder of the dual modulus prescalar is the modulus divide by three or four 3-4 and the divide by 3-5. The PLL is locked once up the prescaled high frequenc clock signal tracks the clock frequency reference signal,

[0041 ] A block diagram of a differential divide by two is illustrated in FIG. 3b. A. differential circuit operates on/generates differential or balanced input/output signals. The output of the differential flip-flop (DFF) is ted back to itself. This differential flip-flop requires the output and an output signal at the Q and Q outputs are feed back to the input and input bar signals D and the D to generate a clock outputs with a frequency that is half of the clock frequency being used to clock the differential flip-flop.

[0042] An MOS circuit schematic of the differential flip-flop is illustrated in FIG. 3c. The flip-flop consists of two latches in series; the first is the master latch and the second is called the slave latch. Each latch is structurally the same comprising a differential amplifier and a differential memor storage unit. Each alternately enabled in sequence. A bias control applied io transistor j regulates the power di.ssipaH.on and speed of the latch. The path is forked between transistors IN2 and N3 that are alternately enabled in sequence by the CK and CK signal. The differential amplifier comprises of the transistors and Ns along with the resistive loads Ri and R2 being enabled by the device 2 clocked by the C The dotted loop 3-7 contains a differential cei which includes the two transistors N and N5 coupled together at their source and exiting the dotted loop at a node 3-8 called the source. The gates of ₄ and N$ enter the dotted loo at 3-9 and O, respectively, and are called inputs. The drains of and s exit the dotted loop at 3- 1 and 342, respectively, and are called legs. The differentia! memory storage comprises transistors Ngatid N? that are cross coupled to each other. The differential amplifier is coupled to the differential memory storage unit and provided to the slave latch. The slave latch, as pointed out earlier, is a replica of the master latch with the exception that the CK signals, CK and CK, have been flipped. The outputs of the master latch are fed into the inputs of the differential amplifier of the slave l atch . The output signals of the differential memory storage unit in the slave latch are coupled to the input signals of the differential amplifier in the master latch. This provides the required feedback in the differential flip- flop to generate a clock output signal that has half the frequency of the clock signal used to clock the differential flip-flop,

[0043] in FIG. 4a, the master slave latch divide by two is redrawn where the master latch is composed of a master differential amplifier and a master memory while the slave latch is composed of the slave differential amplifier and the slave memory. A dotted box 4-1 contains the circuit clocked by CK. When CK goes low, the devices within box 4-1. become disabled, causing the master differential amplifier to become uncoupled from the slave memory cell. The leads 4-2 and 4- 3 only see the capacUi ve load within the dotted box 4-1. Thus, the output nodes 4-4 and 4-5 from the dotted box 4-1 are tri-stated or they are not being driven. With the CK signal goes high, the master differential amplifier detects the differential signal at its inputs, while the slave memory is enabled to hold the previously clocked results,

[0044] The timing diagram in FIG. 4b hel s to illustrate how the divide by 2 operates. The signals from top to bottom are the CK, CK, , X and Q. At 4-11, the CK is rising, the I) input to the master differential amplifier is high as shown causing X to go low 4-10 as indicated by the dotted line 4-15. Note that the D input has been valid for half the CK period 4-7 before the ri sing edge of CK and remains valid for an additional half of the CK period 4-9 after the rising edge of CK. This appears to be a setup and hold time respectively for the master differential amplifier to capture the input of D at node X but. it is more than that. At 4-12, the CK is rising, the D input to the slave differential amplifier is high (X) as shown causing Q to go high 4-17 as indicated by the dotted tine 4-16. Note that the X input has been valid for half the CK period 4-14 before the rising edge of CK and remains valid for an additional half of the CK period 4-13 after the rising edge of CK.

Similarly, as before, this appears to be a setup and hold time respectively for the slave differential amplifier to capture the signal on node X at Q. However, in both cases this setup and hold time can potentially be extended and still allow the differential flip-flop to operate properly.

[0045] Returning back to 4-11, when the CK is rising, CK is falling causing the elements inside the box 4-1 to be disabled. Thus, the load on the nodes X and X is purely capacitive and does not propagate past the box 4-1. The master differential ampli ier along with the capacitive load is illustrated in FIG. 4c when clock goes high. This is a very critical stage in the performance of the differential flipped since this stage must be able to extract out the information on the differential signal comprising of I) and D and transport that signal to the nodes X and X, respectively. As pointed out earlier, the period of the clock at 60 GHz is about 16.6 ps which are slightly greater than the gate delay of a single device, for example, the transistor )¾. The node 4-1.8 will barely reach the required voltage within the time period of 16.6 ps. Furthermore, the propagation delay through the transistors N4 and N5 have not even been addressed yet. Thus, the master differential amplifier within the conventional differential flip flop structure fails to perform at 60 GHz. Innovative solutions are required in order for the master differential amplifier within the differential flip-flop to be able to operate at 60 GHz,

[0046] Various embodiments of these innovative solutions are presented in FIG, 5 and FIG. 6. In FIG. 5a, the master differential amplifier is redrawn from FIG. 4 and three regions are identified within this circuit. The first region 5-1 encompasses the RC network of Rj and C| which introduces an RC time constant at node X. The second region 5-2 encompasses one of the switching transistors and the transistor driven by the CK signal ». This circuit is effectively two transistors in series which causes the propagation delay to surpass the time period of 16.6 ps. Finally the. last region 5-3 has isolated the bias transistor Nj. Each of these regions is analyzed so that the innovative solution that is presented is appreciated.

[0047] The embodiment depicted in FIG, 5b reveals that the bias transistor _} has been completely removed. The power supply for this circuit is a little over one volt and in terms of headroom every means to increase the headroom would be very desirable to help improve the performance of the circuit. Removing the biasing transistor increases the headroom but seems to lack the abilit to control the current in the circuit. This control will be added in later.

[0048] The embodiment illustrated in FIG. 5c shows series peaking inductors, Lj and L₂, added into each leg of the differential amplifier. The series peaking inductor resonates out the capacitance of Cj and removes the concern of the RC time constant identified earlier between the components Ri and€¾ In addition, although not shown, the capacitance Ci can be dynamically adjusted to a different value electronically such that the resonant peak of the RLC circuit comprising Lj, R_:i and Ci can be adjusted. The dynamically adjusted capacitance of Q is used to tune the response of the balance differential amplifier.

[0049] Another embodiment shown in FIG. 5d illustrates how the single clock signal applied previously to the single device N₂ is being replaced by two clock signals each being applied to one of the two parallel devices ^'i and «. These devi ces N₂ and ig can. also be viewed as switches since the clock signal folly enables or folly disables these devices. The original clock signal, CK, is equivalent to CQ or Q except for possibly a phase difference. Thus, the signal CQ is used to clock transistor j. Similarly the new device or transistor N» is clocked by the imaginary clock signal Cr. The clock, signals O leads the clock signal CQ by 90*. This phasor representation of the two clock signals Q and Ci are further illustrated in FIG. 5e. By adding these two phasers together, the effective amplitude of the clock signal is now square root of two (V2) greater than the magnitude of either Q or CQ. This additional amplitude improves the propagation delay of evaluating the signal at X or X. [0050] FIG. 6a further illustrates the amplitude of adding the two orthogonal clock signals Q and Co together. The clock CQ contributes portion 6-1 to C_¥I„„ while clock Q contributes portion 6-2 Cwm- The magnitude of C, and is (V2) times larger than either of the individual clock signals Q or Co. The duration of C «» 6-3 has the same duration as either of the individual clock signals.

[0051] The embodiment in FIG, 6b illustrates the feed forward innovation to help accelerate the evaluation of the signal at X and X. The new devices or transistors that have been added include the device j 5 controlled by the analog signal V»_b. Additionally, two transistors _.u, and Nj?, sharing a common source that is coupled to the drain of device M_J5. The drains of .¾ and j? each connect to the tap point 6-4 and 6-3 in to one of the l egs of the differential master amplifier. The dotted loop 6- 9 identifies the load coupled between the legs of the differential cell and the power supply. The tap point. 6-10 occurs between the series peaking inductor and the resistive load, for example, between Lz and R₂. Note that the path .from the tap point through device Nj$ to ground does not. contain an element that is clocked. So if the transistor I%is enabled, the signals D and D are applied to the gates of i6 and Nn to influence the two nodes X and X before the differential portion of the gate is enabled by the by either of the two clock signals Co or Ci If ¥„_¾ enables Nj¾, then this feed forward path helps to speed up the evaluation of the balance differential master amplifier,

[0052] To simplify the diagrams, the two transistors j and 1% as depicted in FIG. 6b are

combined into one controlled current source ic as is illustrated in FIG. 6c. Similarly, the effective combination of the individual clock signals CQ and Q is represented by the single clock signal Q,_IM as previously shown in FIG. 5c.

[0053] The waveforms for the master differential amplifier illustrated in FIG. 6c are provided in FIG. 6d. Assume thai: I) the waveform has been generated by slave latch (not shown) clocked by the Cam signal as illustrated in the two top waveforms; and 2) the voltage V»¾ is set to VSS to disable the feed forward path. The rising edge of the Cam event 6-6 enables the controlled current source in the slave latch and causes waveform 0 to change from a low to a high, Similarly, the next rising edge event 6-8 causes the waveform D to change state from a high to a low. The master differential amplifier in FIG. 6c is enabled when the rising edge of C_c«m is applied to the controlled current source I_c. Note that the rising edge of C_C<»_H occurs approximately in. between the rising and falling edges of waveform I). The waveform I) is "set up" ahead of time by 4-7 and waveform D is held for a "hold time" of 4-9. Once C_mm goes high at time 4- 10, the output of the master differential latch X goes low.

FIG. 7a illustrates one embodiment of a differential flip-flop configured to divide by 2 while FIG, 7b provides the corresponding waveforms. A clocked master differential amplifier with first balanced inputs (D and S) and first balanced output leads (X and X) coupled, to a complimentary clocked master memory storage unit with a first balanced memory leads (X and X) coupled to the first balanced output leads (X and X). A complimentary clocked slave differential amplifier with second balanced inputs (X and X) coupled to the first balanced memory leads (X and X). The complimentary clocked slave differential amplifier with second balanced output leads (Q and Q) coupled to a clocked slave memor storage unit with a second balanced memory leads (Q and Q) coupled to the second balanced output leads (Q and (}). and the second balanced memory leads cross-coupled to the first balanced inputs ( and D) providing the appropriate feedback. Each of the clocked differential amplifiers and memory storage units use two switches (devices, transistors, etc.) in parallel to enabled or disable the differential amplifiers and memory storage units. A first high frequency clock is applied to one switch and a second high frequency clock at the same frequency but with a different phase is applied to the other switch. These two switches are combined together and represented as a controlled current source t as described previously in FIG, 6c. The two high frequency clocks are represented by the single signal C«««. These controlled current source l_eh l_<a>_> Ics and 1*4 enable and control the master differential amplifier, the master memory, the slave differential amplifier and the slave memory, respectively.

[0054] For FIG. 7a, assume that V»b enables the devices or transistors « and N» so that the feed toward paths become operational. The amount of feed forward is controlled by the current through the devices or transistors 1\½ and j¾ A current source (not shown) is used to generate the voltage Vnb- The current control can be used to adjust the positioning of the resonant frequency of the amplifier. The master differential amplifier requires Ϊ) and I) inputs which are provided by a feedback path from the slave memory portion of the differentia! flip-flop. Thai is, the Q output of the balance differential amplifier is applied in the feedback path back to the D input and the Q output is fed back to the D input. Thus, in FIG, 7b, once the Cam clock transitions from a low to high (7-1 and 7-2) in the slave differentia! amplifier, the Q output is modified 7-3 from a low to high as illustrated by the rising edge of Q. The event 7-2 causes Q to change from a high to a low. Since Q is fed back to the D input of the differential flip-flop to create the divide by two, the D waveform is effectively identical to the Q waveform, it the Q waveforms that are fed back and applied to the master differential amplifier portion of the differential flip-flop.

[0055] The master differential amplifier is enabled when C_mm goes high as indicated by the event 7-5 in FIG. 7b. This event 7-6 causes X to decrease from a high to a low along the solid path of the waveform of FIG. 7b, Note that this transition occurs between the rising and falling edges of D causing the "setup" and "hold time" to have approximately equal durations. The feed forward path is enabled since V„b enables js. This feed forward path causes the falling edge of X to advance in time to the left, since D is high, X should go low earlier and this shift 7-7 is illustrated by the dotted portion of the falling edge curve of X, Note that the other feed forward path with, device I½ is disabled since S is at a logic zero. This signal is captured by the .master memory, and applied to the slave latch which operates in a similar manner when the Cam clock goes high.

[0056] The next time C«»_B goes high again is indicated by the event 7-8. The master differential, amplifie is enabled when€«_>,„ goes high again as before. This event 7-9 causes X to increase from a low to a high along the solid path of the waveform of FIG. 7b. At approximately the same time, the signal X (not shown) decreases from a high to a low. However, note the first feedback path comprising ¾; is disabled D is low) so X is not influenced by this first feed forward path. Instead, the second feed forward path with N₃₇ is enabled since D is high causing the X output to go low and shift the falling edge earlier.. The effect is coupled through the differential pair coupling of 4 and s causing X should to go high earlier and shift 7-10 and shift the rising edge curve of X as illustrated by the dotted portion of the waveform. This shift of the falling and rising edge is of X cannot exceed 90° or 16.6/4 ps or 4.16 ps at 60 GHz, otherwise the edge would occur in one of the other three quadrants. However, test measurements indicate that this edge can be shifted several picoseconds yet still allowing the divide by 2 to operate reliably at 60 GHz.

[0057] The widths of the devices ig to ISU is set to about a I to 3 ratio.

is increased in width decreasing this ratio, the shift of the waveforms at X and X advances too much and causes the flip- flop to fail On the other hand, if Nj« is decreased in width raising this ratio, the effect of the shift of the waveforms at X and X may be negligible.

[0058] Finally, it is understood that the above description are only illustrative of the principle of the current invention. Various alterations, improvements, and modifications will occur and are intended to be suggested hereby, and are within the sprit and scope of the invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, Rather, these embodiments are provided so that the disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the arts. It is understood that the various embodiments of the invention, although different, are not mutually exclusive, in accordance with these principles, those skilled in the art may devise numerous modifications without departing from the spirit and scope of the invention. Although the circuits were described using CMOS, the same circuit techniques can be applied to depletion mode devices and BJT or biploar circuits, since this tecnology allows the formation of current sources and source fol loowers. When a device is specified, the device can be a transistor such as an ^'N-MOS or P-MOS. The CMOS or SQ3 (Silicon on Insulator) technology provides two enhancement mode channel types; N-MOS (n-channel) and P-MOS (p-channel ) devices or transistors. Various embodiments have been described including: clock amplification, feed forward, series peaked inductors and headroom imporovement. Bach of these embodiments can be incorporated into a differential amplifier individually or combined in any combination.

Claims

What is claimed is: . A switched differential amplifier comprising:

a first differential cell;

a load with a center tap coupling each leg of the first differential cell, to a first power supply;

a plurality of switches coupling a source of the first differential cell to a second power supply; each of the plurality of switches receiving a different signal, and

at least one of the different signals has a different phase than the remaining signals,

2. The apparatus of claim t, further comprising:

a second differential cell ;

each leg of the second differential transistor corresponds to an equivalent leg in the first differential celt;

each leg of the second differentia! cell is coupled to the corresponding center taps; and

a single switch coupling a source of the second differential cell to the second power supply.

3. The apparatus of claim L whereby

the l ad is a series coupling of a resistor and a series peaking inductor.

4. The apparatus of claim 3, further comprising:

a capacitance coupled to each leg of the first differential cell forming an RLC network.

5. The apparatus of claim 4, whereby

the capacitance value can be electrically adjusted.

6. The apparatus of claim 5, whereby

an impedance of the series peaking inductor matches a magnitude of the electrically adjusted impedance of the capacitor.

7. The apparatus of claim 2, further comprising:

a current mirror coupled to the single switch that adjusts a current How through the single switch.

S. The apparatus of claim 7, whereby

the current flow adjusts a resonant characteristic of the RLC network.

9. A differential amplifier comprising:

a ^"first differentia! cell;

a load with a center tap coupl ing each leg of the first, differentia! cell to a first power supply;

a current control coupling the first differential cell to a second power supply;

a second differential cell;

each leg of the second differentia! transistor corresponds to an equivalent leg in the differential cell; each leg of the second differential eel! is coupled to the corresponding center taps; and

10, The apparatus of claim 9, further comprising:

a plurality of switches coupled between the source of the differential cell and the current control; each of the plurality of switches receiving a different signal, and

at least one of the different signals has a different, phase than the remai ning signals.

.

11. The appara tu s of claim 11, whereby

the load Is a series coupling of a resistor and a series peaking inductor.

12. The apparatus of claim 9, further comprising:

a capacitance coupled to each leg of the differential ceil forming an RLC network.

13, The apparatus of claim 13, whereby

the capacitance value can be electrically adjusted.

14. The apparatus of claim 14, whereby an impedance of the series peaking inductor matches a magnitude of the electrically adjusted impedance of the capacitor,

15, The apparatus of claim 9, further comprising:

a current mirror coupled to the single switch that adjusts a current flow through the single switch.

.

16. The apparatus of cl aim 16, whereby

the current flow adjusts the characteristics of the resonant RLC network.

17. A divide by 2 apparatus comprising:

a clocked master differential amplifier with first balanced inputs and first balanced output leads; a complimentary clocked master memory storage unit with a first balanced memor leads coupled to the first balanced output leads;

a complimentary clocked slave differential amplifier with second balanced inputs coupled to the first balanced memory leads;

the complimentary clocked slave differential amplifier with second balanced output leads;

a clocked slave memory storage unit with a second balanced memory leads coupled to the second balanced output leads, and

the second balanced memory leads cross-coup! ed io the first balanced inputs; whereby

each of the clocked differential amplifiers and memory storage units use two switches in parallel to enabled or disable the differential amplifiers and memory storage units by applying a first high frequency clock to one switch and a second high frequency clock at the same frequency but with a different phase to the other switch

IS. The apparatus of claim 17, whereby

the first and second balanced memory leads provide the divide by 2 clock outputs. 9. The apparatus of claim Π, whereby

the different phase is 9( . I^'he apparaius of claim 17, whereby

a composite clock is the phasor addition of the two high frequency clocks.