WO2013032049A1 - Dispositif de nanofil de silicium - Google Patents

Dispositif de nanofil de silicium Download PDF

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Publication number
WO2013032049A1
WO2013032049A1 PCT/KR2011/006483 KR2011006483W WO2013032049A1 WO 2013032049 A1 WO2013032049 A1 WO 2013032049A1 KR 2011006483 W KR2011006483 W KR 2011006483W WO 2013032049 A1 WO2013032049 A1 WO 2013032049A1
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WIPO (PCT)
Prior art keywords
conductive
nanowire
silicon substrate
silicon
nanowires
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PCT/KR2011/006483
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English (en)
Korean (ko)
Inventor
정석원
성우경
이국녕
이민호
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전자부품연구원
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Publication of WO2013032049A1 publication Critical patent/WO2013032049A1/fr

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
    • G01N27/26—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating electrochemical variables; by using electrolysis or electrophoresis
    • G01N27/403—Cells and electrode assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/7613—Single electron transistors; Coulomb blockade devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82B—NANOSTRUCTURES FORMED BY MANIPULATION OF INDIVIDUAL ATOMS, MOLECULES, OR LIMITED COLLECTIONS OF ATOMS OR MOLECULES AS DISCRETE UNITS; MANUFACTURE OR TREATMENT THEREOF
    • B82B1/00—Nanostructures formed by manipulation of individual atoms or molecules, or limited collections of atoms or molecules as discrete units
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
    • G01N27/26—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating electrochemical variables; by using electrolysis or electrophoresis
    • G01N27/403—Cells and electrode assemblies
    • G01N27/414—Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
    • G01N27/4146—Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS involving nanosized elements, e.g. nanotubes, nanowires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y35/00—Methods or apparatus for measurement or analysis of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors

Definitions

  • the present invention relates to silicon nanowire devices, and more particularly, to highly reliable silicon nanowire devices.
  • Nano-sized, small diameter materials have emerged as very important materials in recent years because of their unique electrical, optical, and mechanical properties. Therefore, researches on these nano-sized materials have been conducted in various fields, and recent researches on nano-structures show the potential as new optical device materials in the future due to phenomena such as quantum effects.
  • nanostructures not only a single electronic transistor device but also various chemical sensors and biosensors may be used, and thus are attracting attention as a new optical device material.
  • biosensors based on nanosensors using nanostructures such as nanowires, contain chemical or biomolecules or disease markers (enzymes, proteins, DNA, carbohydrates) to be detected on receptors immobilized on the surface of the nanostructures.
  • biomolecules or disease markers enzymes, proteins, DNA, carbohydrates
  • Nucleic acids, antigens, antibodies, etc. are specifically reacted and adsorbed on the surface of the nanostructures, so that only specific molecules can be effectively detected.
  • the nanowires produced by the growth method are generally aligned with another substrate, transferred, and then formed to form electrodes.
  • the transfer efficiency of the nanowires is affected by the thickness and length of the fabricated nanowires, and many process variables in the stamping process. Therefore, achieving perfect transfer efficiency requires a high level of skill and is difficult.
  • the present invention is to solve the above problems, an object of the present invention to provide a highly reliable silicon nanowire device.
  • Silicon nanowire device for achieving the above object is a first conductive silicon substrate; And second conductive nanowires formed on the first conductive silicon substrate and spaced apart from each other and connected to both ends of the first conductive silicon substrate.
  • the first conductive silicon substrate may be a p-type silicon substrate, and the second conductive nanowire may be an n-type nanowire.
  • the silicon nanowire device may further include an insulating layer formed between the first conductive silicon substrate and the second conductive nanowire.
  • the first conductive silicon substrate includes a silicon nanowire support part connected to both ends of the second conductive nanowire, and an upper portion of the silicon nanowire support part is doped with a second conductive type impurity, and is formed at both ends of the second conductive nanowire. Can be connected.
  • the second conductive nanowire may include a first conductive doped region in a region spaced apart from the first conductive silicon substrate.
  • the first conductive silicon substrate First conductive nanowires formed on the first conductive silicon substrate and spaced apart from each other and connected to both ends of the first conductive silicon substrate; And a second conductive well layer formed between the first conductive silicon substrate and the first conductive nanowire.
  • the first conductive silicon substrate may be a p-type silicon substrate
  • the first conductive nanowire may be a p-type nanowire
  • the second conductive well layer may be an n-type layer.
  • the first conductive nanowire may include a second conductive doped region in a region spaced apart from the first conductive silicon substrate.
  • the silicon nanowires according to the present invention are maintained in the substrate formed without the transfer process to other substrates after manufacture, the nanowires do not have a problem such as cutting, crushing, or short-circuit of the nanowires due to the transfer process. There is an effect of obtaining an element.
  • FIG. 1 is a perspective view of a silicon nanowire device according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of the silicon nanowire device of FIG. 1.
  • FIG. 3 is an equivalent circuit diagram of the silicon nanowire device of FIG. 1.
  • FIG. 4 is a cross-sectional view of a silicon nanowire device according to another exemplary embodiment of the present invention.
  • FIG. 5 is a perspective view of a silicon nanowire device according to another embodiment of the present invention.
  • FIG. 6 is a cross-sectional view of the silicon nanowire device of FIG. 5.
  • FIG. 1 is a perspective view of a silicon nanowire device according to an embodiment of the present invention
  • FIG. 2 is a cross-sectional view of the silicon nanowire device of FIG. 1
  • FIG. 3 is an equivalent circuit diagram of the silicon nanowire device of FIG. 1.
  • the silicon nanowire device 100 is formed on the first conductive silicon substrate 110 and the first conductive silicon substrate 110 and is spaced apart from both ends of the first conductive silicon substrate 110. It includes; and a second conductive nanowire 120 connected to.
  • the first conductive silicon substrate 110 is illustrated as a p-type silicon substrate
  • the second conductive nanowire 120 is illustrated as an n-type nanowire.
  • the method of forming a nanowire as shown in FIG. 1 may be performed by removing a portion of the silicon substrate to form a nano-sized structure floating in the upper air of the silicon substrate.
  • an oxide film is formed on at least one surface of a silicon substrate, and a trench structure is formed through a photolithography process and a silicon anisotropic etching process so as to leave a region corresponding to nanowires.
  • the silicon substrate when the silicon substrate is wet-etched using the silicon boiling solution, a silicon structure having an inverted triangle structure having a specific slope is formed due to the etching characteristic of the silicon substrate.
  • the silicon substrate may use a crystal structure of (100) direction.
  • the silicon oxide having an inverted triangle structure is converted into nanowires by performing a thermal oxidation process, and when the oxide film is removed, silicon nanowires having a floating shape on the silicon substrate can be obtained. The thickness of the nanowires can be properly adjusted through time control in the thermal oxidation process.
  • the second conductive nanowire 120 is in a form floating in the upper air of the first conductive silicon substrate 110, and is thus spaced between the second conductive nanowire 120 and the first conductive silicon substrate 110.
  • An insulating layer 140 such as an oxide film, is formed in the second layer to prevent contact between the first conductive silicon substrate 110 and the second conductive nanowire 120.
  • a nanowire device was manufactured by transferring a nanowire manufactured by this method to another substrate.
  • the silicon substrate itself is otherwise a substrate doped with the first conductivity type impurity.
  • the nanowires are second conductive nanowires 120.
  • the silicon nanowire device 100 is formed by doping the nanowires with impurities of a conductive type different from those of the silicon substrate. In this way, it is possible not only to solve the process problems when transferring nanowires to other substrates, but also to prevent device malfunction due to the current flowing through the silicon substrate.
  • the first conductive silicon substrate 110 of the present embodiment includes a silicon nanowire support 130 for supporting the second conductive nanowire 120.
  • the silicon nanowire support unit 130 is connected to both ends of the second conductive nanowire 120, and the second conductive doping is doped with a second conductive impurity, such as the second conductive nanowire 120.
  • the area is formed.
  • the second conductive doped region may be formed on the entire upper portion of the silicon nanowire support 130, or may be formed only on a portion as shown in FIG. 1.
  • FIG. 2 is a cross-sectional view of the second conductive nanowire 120 of the silicon nanowire device 100 of FIG. 1. Both ends of the second conductive nanowire 120 are connected to the first conductive silicon substrate 110.
  • the current flowing in the second conductive nanowire 120 is referred to as I nw , and one end of the second conductive nanowire 120 passes through the first conductive silicon substrate 110 at one end of the second conductive nanowire 120. Let I sub current flow to the other end.
  • the silicon nanowire device measures the change of the current flowing through the nanowire portion, it is important to measure the current I nw that flows through the nanowire.
  • the current may flow not only in the nanowire portion but also through the silicon substrate. Since the nanowires are nano-sized, the magnitude of the current flowing through the silicon substrate is much larger than that of the nanowire. Therefore, in the case of a nanowire connected to a silicon substrate, when used as it is, it is very difficult to measure the current I nw flowing through the nanowire because of the current I sub flowing through the silicon substrate.
  • the silicon substrate is the first conductive silicon substrate 110 and the nanowires are the second conductive nanowires 120 and are doped with impurities of different conductivity types. Therefore, a depletion layer 150 may be formed between the second conductive nanowire 120 and the first conductive silicon substrate 110. If the first conductive silicon substrate 110 is a p-type silicon substrate, and the second conductive nanowire 120 is an n-type nanowire, the first conductive silicon substrate 110 and the second conductive nanowire 120 may be used. The pn junction is formed between) to form a depletion layer as in a semiconductor.
  • FIG. 3 shows an equivalent circuit diagram of the silicon nanowire device of FIG. 1.
  • the left resistor represents the second conductive nanowire 120, which is a kind of resistor having an n-n-n doping structure.
  • the current flowing along the first conductive silicon substrate 110 is n-type second conductive again through the p-type first conductive silicon substrate 110 at one end of the n-type second conductive nanowire 120. Since it flows to the other end of the nanowire 120, it can be referred to as the n-channel MOSFET structure of npn.
  • the current I nw flowing to the second conductive nanowire 120 is determined by the size of the resistance such as the doping, the thickness, or the length of the nanowire, and the current I sub flowing to the first conductive silicon substrate 110 is When no channel is formed, it is the current through the FET. Since the current flowing through the nanowires should be superior to the current flowing through the silicon substrate, since the resistance change of the nanowires contributes predominantly to the change of the total current, the first conductive silicon substrate 110 may be in the condition of I nw >> I sub . Considering the characteristics of, the conditions of the second conductive nanowires 120 should be adjusted.
  • the silicon nanowire device 200 includes a first conductive silicon substrate 210 and a second conductive nanowire 220.
  • the first depletion layer 230 is formed between the first conductive silicon substrate 210 and the second conductive nanowire 220.
  • the second conductive nanowire 220 may include a first doped first conductive dopant that is the same as a conductive type impurity of the first conductive silicon substrate 210 in a region spaced apart from the first conductive silicon substrate 210. And a conductive doped region 240. Accordingly, the portion of the second conductive nanowire 220 that is connected to the first conductive silicon substrate 210 is doped with the second conductive impurity, and is spaced apart from the first conductive silicon substrate 210 to float in the air.
  • the first conductive doped region 240 doped with the first conductive dopant is formed in part of the doped region.
  • the first conductive silicon substrate 210 is a p-type silicon substrate and the second conductive nanowire 220 is an n-type nanowire
  • the first conductive type of the second conductive nanowire 220 may be used.
  • the doped region 240 is doped with p-type impurities.
  • the second conductive nanowire 220 is n-p-n bonded based on one end. Therefore, the second depletion layer 250 is present in the second conductive nanowire 220.
  • the second conductive nanowire 220 may function as a transistor device having an npn junction, and thus, as shown in FIG. 3, the second conductive nanowire ( Various circuits different from 120 may be implemented.
  • the silicon nanowire device 300 includes a first conductive silicon substrate 310 and a first conductive nanowire 320, and includes a first conductive silicon substrate 310 and a first conductive nano.
  • a second conductive well layer 340 is formed between the wires 320.
  • a first depletion layer 330 is formed between the first conductive silicon substrate 310 and the second conductive well layer 340, and the second conductive well layer 340 and the first conductive nanowire are formed.
  • the second depletion layer 350 is formed between the 320.
  • the first conductive nanowire 320 is a p-type nanowire, a p-type silicon substrate and a p-type nanowire.
  • the second conductive well layer 340 formed therebetween is an n-type layer.
  • the first conductive silicon substrate 310 is an n-type silicon substrate
  • the first conductive nanowire 320 may be an n-type nanowire
  • the second conductive well layer 340 may be a p-type layer.
  • the silicon nanowire device 300 includes two types of depletion layers including the depletion layer as the first depletion layer 330 and the second depletion layer 350. As described with reference to FIG. 3, the current flowing along the first conductive nanowire 320 should prevail over the current flowing along the first conductive silicon substrate 310.
  • the current flowing along the first conductive nanowire 320 is determined according to the resistance as a resistor such as doping, thickness, or length of the nanowire, and the current flowing through the first conductive silicon substrate 310 is adjusted by adjusting such factors.
  • Silicon nanowire device 300 should be designed to be more dominant. However, since the nanowire is a line resistance having a nano size, the variation of factors such as doping, thickness, and length is not wide.
  • the second conductive type is doped between the first conductive type nanowire 320 and the first conductive type silicon substrate 310 by doping the first conductive type impurity with another conductive type second conductive impurity.
  • the well layer 340 is formed, the flow of current flowing from both ends of the first conductive nanowire 320 through the first conductive silicon substrate 310 can be suppressed according to the current application direction, thereby providing a first conductive type.
  • the current flowing through the nanowires 320 can be more effectively dominated.
  • the first conductive nanowire when the first conductive nanowire further includes a second conductive doped region in a region spaced apart from the first conductive silicon substrate, the first conductive nanowire may be formed. One end may be used to form an npn junction or a pnp junction. Therefore, the first conductive nanowire further includes a separate depletion layer.
  • the silicon nanowire device having such a structure may include the second conductive nanowire 120 in which the first conductive nanowire functions as a transistor device of an npn junction (or a pnp junction), and thus acts as a kind of resistor as shown in FIG. 3.
  • Various circuits can be implemented.

Abstract

La présente invention concerne un dispositif de nanofil de silicium ayant une fiabilité élevée. Le dispositif de nanofil de silicium comprend : un premier substrat de silicium de type conducteur ; des seconds fils de type conducteur qui sont formés sur le premier substrat de silicium de type conducteur de manière à être séparés les uns des autres, et dont les deux extrémités sont reliées au premier substrat de silicium de type conducteur.
PCT/KR2011/006483 2011-08-31 2011-08-31 Dispositif de nanofil de silicium WO2013032049A1 (fr)

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US20160158998A1 (en) * 2014-12-08 2016-06-09 Canon Kabushiki Kaisha Imprint apparatus and method, and method of manufacturing article

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KR102395778B1 (ko) 2015-09-10 2022-05-09 삼성전자주식회사 나노구조체 형성방법과 이를 적용한 반도체소자의 제조방법 및 나노구조체를 포함하는 반도체소자

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JP2010505728A (ja) * 2006-10-05 2010-02-25 日立化成工業株式会社 高配列、高アスペクト比、高密度のシリコンナノワイヤー及びその製造方法
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KR20090003800A (ko) * 2007-07-03 2009-01-12 삼성전자주식회사 발광소자 및 그 제조방법

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Publication number Priority date Publication date Assignee Title
US20160158998A1 (en) * 2014-12-08 2016-06-09 Canon Kabushiki Kaisha Imprint apparatus and method, and method of manufacturing article

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