WO2013032049A1 - Silicon nanowire device - Google Patents

Silicon nanowire device Download PDF

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WO2013032049A1
WO2013032049A1 PCT/KR2011/006483 KR2011006483W WO2013032049A1 WO 2013032049 A1 WO2013032049 A1 WO 2013032049A1 KR 2011006483 W KR2011006483 W KR 2011006483W WO 2013032049 A1 WO2013032049 A1 WO 2013032049A1
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conductive
nanowire
silicon substrate
silicon
nanowires
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PCT/KR2011/006483
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French (fr)
Korean (ko)
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정석원
성우경
이국녕
이민호
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전자부품연구원
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
    • G01N27/26—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating electrochemical variables; by using electrolysis or electrophoresis
    • G01N27/403—Cells and electrode assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/7613—Single electron transistors; Coulomb blockade devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82B—NANOSTRUCTURES FORMED BY MANIPULATION OF INDIVIDUAL ATOMS, MOLECULES, OR LIMITED COLLECTIONS OF ATOMS OR MOLECULES AS DISCRETE UNITS; MANUFACTURE OR TREATMENT THEREOF
    • B82B1/00—Nanostructures formed by manipulation of individual atoms or molecules, or limited collections of atoms or molecules as discrete units
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
    • G01N27/26—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating electrochemical variables; by using electrolysis or electrophoresis
    • G01N27/403—Cells and electrode assemblies
    • G01N27/414—Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
    • G01N27/4146—Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS involving nanosized elements, e.g. nanotubes, nanowires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y35/00—Methods or apparatus for measurement or analysis of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors

Definitions

  • the present invention relates to silicon nanowire devices, and more particularly, to highly reliable silicon nanowire devices.
  • Nano-sized, small diameter materials have emerged as very important materials in recent years because of their unique electrical, optical, and mechanical properties. Therefore, researches on these nano-sized materials have been conducted in various fields, and recent researches on nano-structures show the potential as new optical device materials in the future due to phenomena such as quantum effects.
  • nanostructures not only a single electronic transistor device but also various chemical sensors and biosensors may be used, and thus are attracting attention as a new optical device material.
  • biosensors based on nanosensors using nanostructures such as nanowires, contain chemical or biomolecules or disease markers (enzymes, proteins, DNA, carbohydrates) to be detected on receptors immobilized on the surface of the nanostructures.
  • biomolecules or disease markers enzymes, proteins, DNA, carbohydrates
  • Nucleic acids, antigens, antibodies, etc. are specifically reacted and adsorbed on the surface of the nanostructures, so that only specific molecules can be effectively detected.
  • the nanowires produced by the growth method are generally aligned with another substrate, transferred, and then formed to form electrodes.
  • the transfer efficiency of the nanowires is affected by the thickness and length of the fabricated nanowires, and many process variables in the stamping process. Therefore, achieving perfect transfer efficiency requires a high level of skill and is difficult.
  • the present invention is to solve the above problems, an object of the present invention to provide a highly reliable silicon nanowire device.
  • Silicon nanowire device for achieving the above object is a first conductive silicon substrate; And second conductive nanowires formed on the first conductive silicon substrate and spaced apart from each other and connected to both ends of the first conductive silicon substrate.
  • the first conductive silicon substrate may be a p-type silicon substrate, and the second conductive nanowire may be an n-type nanowire.
  • the silicon nanowire device may further include an insulating layer formed between the first conductive silicon substrate and the second conductive nanowire.
  • the first conductive silicon substrate includes a silicon nanowire support part connected to both ends of the second conductive nanowire, and an upper portion of the silicon nanowire support part is doped with a second conductive type impurity, and is formed at both ends of the second conductive nanowire. Can be connected.
  • the second conductive nanowire may include a first conductive doped region in a region spaced apart from the first conductive silicon substrate.
  • the first conductive silicon substrate First conductive nanowires formed on the first conductive silicon substrate and spaced apart from each other and connected to both ends of the first conductive silicon substrate; And a second conductive well layer formed between the first conductive silicon substrate and the first conductive nanowire.
  • the first conductive silicon substrate may be a p-type silicon substrate
  • the first conductive nanowire may be a p-type nanowire
  • the second conductive well layer may be an n-type layer.
  • the first conductive nanowire may include a second conductive doped region in a region spaced apart from the first conductive silicon substrate.
  • the silicon nanowires according to the present invention are maintained in the substrate formed without the transfer process to other substrates after manufacture, the nanowires do not have a problem such as cutting, crushing, or short-circuit of the nanowires due to the transfer process. There is an effect of obtaining an element.
  • FIG. 1 is a perspective view of a silicon nanowire device according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of the silicon nanowire device of FIG. 1.
  • FIG. 3 is an equivalent circuit diagram of the silicon nanowire device of FIG. 1.
  • FIG. 4 is a cross-sectional view of a silicon nanowire device according to another exemplary embodiment of the present invention.
  • FIG. 5 is a perspective view of a silicon nanowire device according to another embodiment of the present invention.
  • FIG. 6 is a cross-sectional view of the silicon nanowire device of FIG. 5.
  • FIG. 1 is a perspective view of a silicon nanowire device according to an embodiment of the present invention
  • FIG. 2 is a cross-sectional view of the silicon nanowire device of FIG. 1
  • FIG. 3 is an equivalent circuit diagram of the silicon nanowire device of FIG. 1.
  • the silicon nanowire device 100 is formed on the first conductive silicon substrate 110 and the first conductive silicon substrate 110 and is spaced apart from both ends of the first conductive silicon substrate 110. It includes; and a second conductive nanowire 120 connected to.
  • the first conductive silicon substrate 110 is illustrated as a p-type silicon substrate
  • the second conductive nanowire 120 is illustrated as an n-type nanowire.
  • the method of forming a nanowire as shown in FIG. 1 may be performed by removing a portion of the silicon substrate to form a nano-sized structure floating in the upper air of the silicon substrate.
  • an oxide film is formed on at least one surface of a silicon substrate, and a trench structure is formed through a photolithography process and a silicon anisotropic etching process so as to leave a region corresponding to nanowires.
  • the silicon substrate when the silicon substrate is wet-etched using the silicon boiling solution, a silicon structure having an inverted triangle structure having a specific slope is formed due to the etching characteristic of the silicon substrate.
  • the silicon substrate may use a crystal structure of (100) direction.
  • the silicon oxide having an inverted triangle structure is converted into nanowires by performing a thermal oxidation process, and when the oxide film is removed, silicon nanowires having a floating shape on the silicon substrate can be obtained. The thickness of the nanowires can be properly adjusted through time control in the thermal oxidation process.
  • the second conductive nanowire 120 is in a form floating in the upper air of the first conductive silicon substrate 110, and is thus spaced between the second conductive nanowire 120 and the first conductive silicon substrate 110.
  • An insulating layer 140 such as an oxide film, is formed in the second layer to prevent contact between the first conductive silicon substrate 110 and the second conductive nanowire 120.
  • a nanowire device was manufactured by transferring a nanowire manufactured by this method to another substrate.
  • the silicon substrate itself is otherwise a substrate doped with the first conductivity type impurity.
  • the nanowires are second conductive nanowires 120.
  • the silicon nanowire device 100 is formed by doping the nanowires with impurities of a conductive type different from those of the silicon substrate. In this way, it is possible not only to solve the process problems when transferring nanowires to other substrates, but also to prevent device malfunction due to the current flowing through the silicon substrate.
  • the first conductive silicon substrate 110 of the present embodiment includes a silicon nanowire support 130 for supporting the second conductive nanowire 120.
  • the silicon nanowire support unit 130 is connected to both ends of the second conductive nanowire 120, and the second conductive doping is doped with a second conductive impurity, such as the second conductive nanowire 120.
  • the area is formed.
  • the second conductive doped region may be formed on the entire upper portion of the silicon nanowire support 130, or may be formed only on a portion as shown in FIG. 1.
  • FIG. 2 is a cross-sectional view of the second conductive nanowire 120 of the silicon nanowire device 100 of FIG. 1. Both ends of the second conductive nanowire 120 are connected to the first conductive silicon substrate 110.
  • the current flowing in the second conductive nanowire 120 is referred to as I nw , and one end of the second conductive nanowire 120 passes through the first conductive silicon substrate 110 at one end of the second conductive nanowire 120. Let I sub current flow to the other end.
  • the silicon nanowire device measures the change of the current flowing through the nanowire portion, it is important to measure the current I nw that flows through the nanowire.
  • the current may flow not only in the nanowire portion but also through the silicon substrate. Since the nanowires are nano-sized, the magnitude of the current flowing through the silicon substrate is much larger than that of the nanowire. Therefore, in the case of a nanowire connected to a silicon substrate, when used as it is, it is very difficult to measure the current I nw flowing through the nanowire because of the current I sub flowing through the silicon substrate.
  • the silicon substrate is the first conductive silicon substrate 110 and the nanowires are the second conductive nanowires 120 and are doped with impurities of different conductivity types. Therefore, a depletion layer 150 may be formed between the second conductive nanowire 120 and the first conductive silicon substrate 110. If the first conductive silicon substrate 110 is a p-type silicon substrate, and the second conductive nanowire 120 is an n-type nanowire, the first conductive silicon substrate 110 and the second conductive nanowire 120 may be used. The pn junction is formed between) to form a depletion layer as in a semiconductor.
  • FIG. 3 shows an equivalent circuit diagram of the silicon nanowire device of FIG. 1.
  • the left resistor represents the second conductive nanowire 120, which is a kind of resistor having an n-n-n doping structure.
  • the current flowing along the first conductive silicon substrate 110 is n-type second conductive again through the p-type first conductive silicon substrate 110 at one end of the n-type second conductive nanowire 120. Since it flows to the other end of the nanowire 120, it can be referred to as the n-channel MOSFET structure of npn.
  • the current I nw flowing to the second conductive nanowire 120 is determined by the size of the resistance such as the doping, the thickness, or the length of the nanowire, and the current I sub flowing to the first conductive silicon substrate 110 is When no channel is formed, it is the current through the FET. Since the current flowing through the nanowires should be superior to the current flowing through the silicon substrate, since the resistance change of the nanowires contributes predominantly to the change of the total current, the first conductive silicon substrate 110 may be in the condition of I nw >> I sub . Considering the characteristics of, the conditions of the second conductive nanowires 120 should be adjusted.
  • the silicon nanowire device 200 includes a first conductive silicon substrate 210 and a second conductive nanowire 220.
  • the first depletion layer 230 is formed between the first conductive silicon substrate 210 and the second conductive nanowire 220.
  • the second conductive nanowire 220 may include a first doped first conductive dopant that is the same as a conductive type impurity of the first conductive silicon substrate 210 in a region spaced apart from the first conductive silicon substrate 210. And a conductive doped region 240. Accordingly, the portion of the second conductive nanowire 220 that is connected to the first conductive silicon substrate 210 is doped with the second conductive impurity, and is spaced apart from the first conductive silicon substrate 210 to float in the air.
  • the first conductive doped region 240 doped with the first conductive dopant is formed in part of the doped region.
  • the first conductive silicon substrate 210 is a p-type silicon substrate and the second conductive nanowire 220 is an n-type nanowire
  • the first conductive type of the second conductive nanowire 220 may be used.
  • the doped region 240 is doped with p-type impurities.
  • the second conductive nanowire 220 is n-p-n bonded based on one end. Therefore, the second depletion layer 250 is present in the second conductive nanowire 220.
  • the second conductive nanowire 220 may function as a transistor device having an npn junction, and thus, as shown in FIG. 3, the second conductive nanowire ( Various circuits different from 120 may be implemented.
  • the silicon nanowire device 300 includes a first conductive silicon substrate 310 and a first conductive nanowire 320, and includes a first conductive silicon substrate 310 and a first conductive nano.
  • a second conductive well layer 340 is formed between the wires 320.
  • a first depletion layer 330 is formed between the first conductive silicon substrate 310 and the second conductive well layer 340, and the second conductive well layer 340 and the first conductive nanowire are formed.
  • the second depletion layer 350 is formed between the 320.
  • the first conductive nanowire 320 is a p-type nanowire, a p-type silicon substrate and a p-type nanowire.
  • the second conductive well layer 340 formed therebetween is an n-type layer.
  • the first conductive silicon substrate 310 is an n-type silicon substrate
  • the first conductive nanowire 320 may be an n-type nanowire
  • the second conductive well layer 340 may be a p-type layer.
  • the silicon nanowire device 300 includes two types of depletion layers including the depletion layer as the first depletion layer 330 and the second depletion layer 350. As described with reference to FIG. 3, the current flowing along the first conductive nanowire 320 should prevail over the current flowing along the first conductive silicon substrate 310.
  • the current flowing along the first conductive nanowire 320 is determined according to the resistance as a resistor such as doping, thickness, or length of the nanowire, and the current flowing through the first conductive silicon substrate 310 is adjusted by adjusting such factors.
  • Silicon nanowire device 300 should be designed to be more dominant. However, since the nanowire is a line resistance having a nano size, the variation of factors such as doping, thickness, and length is not wide.
  • the second conductive type is doped between the first conductive type nanowire 320 and the first conductive type silicon substrate 310 by doping the first conductive type impurity with another conductive type second conductive impurity.
  • the well layer 340 is formed, the flow of current flowing from both ends of the first conductive nanowire 320 through the first conductive silicon substrate 310 can be suppressed according to the current application direction, thereby providing a first conductive type.
  • the current flowing through the nanowires 320 can be more effectively dominated.
  • the first conductive nanowire when the first conductive nanowire further includes a second conductive doped region in a region spaced apart from the first conductive silicon substrate, the first conductive nanowire may be formed. One end may be used to form an npn junction or a pnp junction. Therefore, the first conductive nanowire further includes a separate depletion layer.
  • the silicon nanowire device having such a structure may include the second conductive nanowire 120 in which the first conductive nanowire functions as a transistor device of an npn junction (or a pnp junction), and thus acts as a kind of resistor as shown in FIG. 3.
  • Various circuits can be implemented.

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Abstract

The present invention relates to a silicon nanowire device having high reliability. The silicon nanowire device comprises: a first conductive-type silicon substrate; and second conductive-type nanowires which are formed on the first conductive-type silicon substrate so as to be separated from each other, and of which both ends are connected to the first conductive-type silicon substrate.

Description

실리콘 나노와이어 소자Silicon nanowire devices
본 발명은 실리콘 나노와이어 소자에 관한 것으로서, 보다 상세하게는, 신뢰성 높은 실리콘 나노와이어 소자에 관한 것이다. The present invention relates to silicon nanowire devices, and more particularly, to highly reliable silicon nanowire devices.
나노 크기의 작은 직경을 가지는 물질들은 독특한 전기적, 광학적, 기계적 특성 때문에 최근 들어 매우 중요한 물질로 대두되고 있다. 따라서, 이러한 나노 사이즈 물질에 대하여 여러 분야에서 연구가 진행되어 왔는데, 최근의 나노 구조에 관한 연구는 양자 효과와 같은 현상으로 미래의 새로운 광소자 물질로서의 가능성을 보여주고 있다. 특히, 나노 구조물의 경우, 단일 전자 트랜지스터 소자 뿐만 아니라 각종 화학 센서 및 바이오 센서 등으로 이용될 수 있어 새로운 광소자 재료로 각광받고 있다. Nano-sized, small diameter materials have emerged as very important materials in recent years because of their unique electrical, optical, and mechanical properties. Therefore, researches on these nano-sized materials have been conducted in various fields, and recent researches on nano-structures show the potential as new optical device materials in the future due to phenomena such as quantum effects. In particular, in the case of nanostructures, not only a single electronic transistor device but also various chemical sensors and biosensors may be used, and thus are attracting attention as a new optical device material.
예를 들어, 나노와이어와 같은 나노 구조물을 이용한 나노 센서를 기반으로 하는 바이오 센서는 나노 구조물 표면에 고정화되어 있는 리셉터에 검출하고자 하는 화학 인자나 바이오 분자, 질병 표지 인자(효소, 단백질, DNA, 탄수화물, 핵산, 항원, 항체 등)가 특이적으로 반응하여 나노 구조물 표면에 흡착되므로, 특정 분자만을 효과적으로 검출할 수 있다.For example, biosensors based on nanosensors using nanostructures, such as nanowires, contain chemical or biomolecules or disease markers (enzymes, proteins, DNA, carbohydrates) to be detected on receptors immobilized on the surface of the nanostructures. , Nucleic acids, antigens, antibodies, etc.) are specifically reacted and adsorbed on the surface of the nanostructures, so that only specific molecules can be effectively detected.
나노와이어를 제조하기 위하여는 일반적으로 성장법에 의해 제작된 나노와이어를 다른 기판으로 정렬하여 트랜스퍼시킨 후 전극을 형성시켜 제조한다. 이 때, 다른 기판으로 트랜스퍼시키는 공정 중에는 나노사이즈를 갖는 나노와이어의 특성상 이러한 트랜스퍼가 완전하지 않을 경우 소자 제작의 수율을 저하시킬 수 있다. 즉, 나노와이어의 트랜스퍼 효율은 제작된 나노와이어의 굵기 및 길이, 스탬핑 공정에서의 많은 공정변수들에 영향을 받기 때문에 완벽한 트랜스퍼 효율을 달성하는 것은 고도의 기술이 요구되며 어려운 공정이라 평가되었다.In order to manufacture the nanowires, the nanowires produced by the growth method are generally aligned with another substrate, transferred, and then formed to form electrodes. At this time, during the process of transferring to another substrate, if the transfer is not complete due to the characteristics of the nanowire having a nano-size, the yield of device fabrication can be reduced. That is, the transfer efficiency of the nanowires is affected by the thickness and length of the fabricated nanowires, and many process variables in the stamping process. Therefore, achieving perfect transfer efficiency requires a high level of skill and is difficult.
따라서, 트랜스퍼 공정과 같은 어렵고 낮은 수율의 공정 대신에 보다 쉬운 공정으로 높은 수율이면서 원하는 사이즈나 형태를 갖는 나노와이어의 제조에 대한 기술의 개발이 요청되었다. Accordingly, there has been a demand for the development of a technique for producing nanowires having a high yield and a desired size or shape in an easier process instead of a difficult and low yield process such as a transfer process.
본 발명은 상술한 문제점을 해결하기 위한 것으로, 본 발명의 목적은 신뢰성 높은 실리콘 나노와이어 소자를 제공하는데 있다. The present invention is to solve the above problems, an object of the present invention to provide a highly reliable silicon nanowire device.
이상과 같은 목적을 달성하기 위한 본 발명의 일 측면에 따른 실리콘 나노와이어 소자는 제1도전형 실리콘 기판; 및 제1도전형 실리콘 기판 상에 이격되어 형성되되, 양단이 제1도전형 실리콘 기판과 연결된 제2도전형 나노와이어;를 포함한다. Silicon nanowire device according to an aspect of the present invention for achieving the above object is a first conductive silicon substrate; And second conductive nanowires formed on the first conductive silicon substrate and spaced apart from each other and connected to both ends of the first conductive silicon substrate.
제1도전형 실리콘 기판은 p형 실리콘 기판이고, 제2도전형 나노와이어는 n형 나노와이어일 수 있다. The first conductive silicon substrate may be a p-type silicon substrate, and the second conductive nanowire may be an n-type nanowire.
실리콘 나노와이어 소자는 제1도전형 실리콘 기판 및 제2도전형 나노와이어의 이격된 사이에 형성된 절연층;을 더 포함할 수 있다. The silicon nanowire device may further include an insulating layer formed between the first conductive silicon substrate and the second conductive nanowire.
제1도전형 실리콘 기판은 제2도전형 나노와이어의 양단과 연결된 실리콘 나노와이어 지지부;를 포함하고, 실리콘 나노와이어 지지부의 상부는 제2도전형 불순물로 도핑되어 제2도전형 나노와이어의 양단과 연결될 수 있다. The first conductive silicon substrate includes a silicon nanowire support part connected to both ends of the second conductive nanowire, and an upper portion of the silicon nanowire support part is doped with a second conductive type impurity, and is formed at both ends of the second conductive nanowire. Can be connected.
제2도전형 나노와이어는 제1도전형 실리콘 기판과 이격된 영역에 제1도전형 도핑영역을 포함할 수 있다. The second conductive nanowire may include a first conductive doped region in a region spaced apart from the first conductive silicon substrate.
본 발명의 다른 측면에 따르면, 제1도전형 실리콘 기판; 제1도전형 실리콘 기판 상에 이격되어 형성되되, 양단이 제1도전형 실리콘 기판과 연결된 제1도전형 나노와이어; 및 제1도전형 실리콘 기판 및 제1도전형 나노와이어 사이에 형성된 제2도전형 우물층;을 포함하는 실리콘 나노와이어 소자가 제공된다. According to another aspect of the invention, the first conductive silicon substrate; First conductive nanowires formed on the first conductive silicon substrate and spaced apart from each other and connected to both ends of the first conductive silicon substrate; And a second conductive well layer formed between the first conductive silicon substrate and the first conductive nanowire.
제1도전형 실리콘 기판은 p형 실리콘 기판이고, 제1도전형 나노와이어는 p형 나노와이어이며, 제2도전형 우물층은 n형 층일 수 있다. The first conductive silicon substrate may be a p-type silicon substrate, the first conductive nanowire may be a p-type nanowire, and the second conductive well layer may be an n-type layer.
제1도전형 나노와이어는 제1도전형 실리콘 기판과 이격된 영역에 제2도전형 도핑영역을 포함할 수 있다. The first conductive nanowire may include a second conductive doped region in a region spaced apart from the first conductive silicon substrate.
본 발명에 따른 실리콘 나노와이어는 제조 후 다른 기판에의 트랜스퍼 공정없이 생성된 기판에 그대로 유지되므로 트랜스퍼 공정으로 인한 나노와이어의 절단이나 파쇄 및 단락 등의 문제가 발생하지 않아 우수한 성능의 신뢰성 높은 나노와이어 소자를 얻을 수 있는 효과가 있다. Since the silicon nanowires according to the present invention are maintained in the substrate formed without the transfer process to other substrates after manufacture, the nanowires do not have a problem such as cutting, crushing, or short-circuit of the nanowires due to the transfer process. There is an effect of obtaining an element.
도 1은 본 발명의 일실시예에 따른 실리콘 나노와이어 소자의 사시도이다. 1 is a perspective view of a silicon nanowire device according to an embodiment of the present invention.
도 2는 도 1의 실리콘 나노와이어 소자의 단면도이다. FIG. 2 is a cross-sectional view of the silicon nanowire device of FIG. 1.
도 3은 도 1의 실리콘 나노와이어 소자의 등가회로도이다. 3 is an equivalent circuit diagram of the silicon nanowire device of FIG. 1.
도 4는 본 발명의 다른 실시예에 따른 실리콘 나노와이어 소자의 단면도이다. 4 is a cross-sectional view of a silicon nanowire device according to another exemplary embodiment of the present invention.
도 5는 본 발명의 다른 실시예에 따른 실리콘 나노와이어 소자의 사시도이다.5 is a perspective view of a silicon nanowire device according to another embodiment of the present invention.
도 6은 도 5의 실리콘 나노와이어 소자의 단면도이다.6 is a cross-sectional view of the silicon nanowire device of FIG. 5.
이하, 첨부된 도면을 참조하여 본 발명의 실시형태를 설명한다. 그러나, 본 발명의 실시형태는 여러가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 이하 설명하는 실시형태로 한정되는 것은 아니다. 본 발명의 실시형태는 당업계에서 통상의 지식을 가진 자에게 본 발명을 보다 완전하게 설명하기 위해서 제공되는 것이다. 첨부된 도면에서 특정 패턴을 갖도록 도시되거나 소정두께를 갖는 구성요소가 있을 수 있으나, 이는 설명 또는 구별의 편의를 위한 것이므로 특정패턴 및 소정두께를 갖는다고 하여도 본 발명이 도시된 구성요소에 대한 특징만으로 한정되는 것은 아니다. Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, embodiments of the present invention may be modified in various other forms, and the scope of the present invention is not limited to the embodiments described below. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. In the accompanying drawings, there may be a component having a specific pattern or having a predetermined thickness, but this is for convenience of description or distinction. It is not limited only.
도 1은 본 발명의 일실시예에 따른 실리콘 나노와이어 소자의 사시도이고, 도 2는 도 1의 실리콘 나노와이어 소자의 단면도이며, 도 3은 도 1의 실리콘 나노와이어 소자의 등가회로도이다. 1 is a perspective view of a silicon nanowire device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of the silicon nanowire device of FIG. 1, and FIG. 3 is an equivalent circuit diagram of the silicon nanowire device of FIG. 1.
본 실시예에 따른 실리콘 나노와이어 소자(100)는 제1도전형 실리콘 기판(110) 및 제1도전형 실리콘 기판(110) 상에 이격되어 형성되되, 양단이 제1도전형 실리콘 기판(110)과 연결된 제2도전형 나노와이어(120);를 포함한다. 도 1에서 임의로 제1도전형 실리콘 기판(110)은 p형 실리콘 기판으로, 제2도전형 나노와이어(120)는 n형 나노와이어로 도시되어 있다. The silicon nanowire device 100 according to the present embodiment is formed on the first conductive silicon substrate 110 and the first conductive silicon substrate 110 and is spaced apart from both ends of the first conductive silicon substrate 110. It includes; and a second conductive nanowire 120 connected to. In FIG. 1, the first conductive silicon substrate 110 is illustrated as a p-type silicon substrate, and the second conductive nanowire 120 is illustrated as an n-type nanowire.
도 1에서와 같은 나노와이어를 실리콘 기판 상에 형성하는 방법으로는 실리콘 기판을 일부 제거하여 실리콘 기판의 상부 공중에 떠 있는 상태의 나노 사이즈의 구조물을 형성하여 수행할 수 있다. 상세하게는, 실리콘 기판의 적어도 일면에 산화물막을 형성하고, 나노와이어에 해당하는 영역만큼을 남기기 위하여 포토리소그래피 공정 및 실리콘 비등방 식각 공정을 통해 트랜치 구조를 형성한다. The method of forming a nanowire as shown in FIG. 1 may be performed by removing a portion of the silicon substrate to form a nano-sized structure floating in the upper air of the silicon substrate. In detail, an oxide film is formed on at least one surface of a silicon substrate, and a trench structure is formed through a photolithography process and a silicon anisotropic etching process so as to leave a region corresponding to nanowires.
이후 실리콘 비등방식각 용액을 사용하여 실리콘 기판을 습식 식각하면 실리콘 기판의 결정방향의 식각특성으로 인하여 특정한 경사를 갖는 역삼각형 구조의 실리콘 구조물이 형성된다. 이를 위하여 실리콘 기판은 결정구조가 (100)방향인 것을 사용할 수 있다. 역삼각형 구조의 실리콘 산화물은 열산화공정을 수행하면 나노와이어로 변환되고, 산화물막을 제거하면 실리콘 기판상에서 공중에 떠 있는 형태의 실리콘 나노와이어를 얻을 수 있다. 나노와이어의 두께는 열산화공정에서의 시간조절을 통해 적절히 조절할 수 있다. Subsequently, when the silicon substrate is wet-etched using the silicon boiling solution, a silicon structure having an inverted triangle structure having a specific slope is formed due to the etching characteristic of the silicon substrate. For this purpose, the silicon substrate may use a crystal structure of (100) direction. The silicon oxide having an inverted triangle structure is converted into nanowires by performing a thermal oxidation process, and when the oxide film is removed, silicon nanowires having a floating shape on the silicon substrate can be obtained. The thickness of the nanowires can be properly adjusted through time control in the thermal oxidation process.
이러한 방법으로, 도 1에서와 같이 실리콘 기판 상에 형성되어 있는 나노와이어를 얻을 수 있다. 제2도전형 나노와이어(120)는 제1도전형 실리콘 기판(110)의 상부 공중에 뜬 형태인데, 이렇게 이격된 제2도전형 나노와이어(120) 및 제1도전형 실리콘 기판(110) 사이에는 산화물막과 같은 절연층(140)이 형성되어 있어 제1도전형 실리콘 기판(110) 및 제2도전형 나노와이어(120)의 접촉 등을 방지한다. In this way, the nanowires formed on the silicon substrate can be obtained as shown in FIG. The second conductive nanowire 120 is in a form floating in the upper air of the first conductive silicon substrate 110, and is thus spaced between the second conductive nanowire 120 and the first conductive silicon substrate 110. An insulating layer 140, such as an oxide film, is formed in the second layer to prevent contact between the first conductive silicon substrate 110 and the second conductive nanowire 120.
종래에는 이러한 방법으로 제조된 나노와이어를 다른 기판으로 트랜스퍼하여 나노와이어 소자를 제조하였다. 그러나, 본 실시예에서는, 이와 달리 실리콘 기판 자체가 제1도전형 불순물로 도핑된 기판이다. 또한, 나노와이어는 제2도전형 나노와이어(120)이다. 따라서, 전술한 방법과 같이 소정의 불순물로 도핑된 실리콘 기판 상에 나노와이어를 형성한 후 실리콘 기판의 불순물과 다른 도전형의 불순물로 나노와이어를 도핑하여 실리콘 나노와이어 소자(100)를 형성한다. 이러한 방법으로, 다른 기판으로 나노와이어를 트랜스퍼할 때의 공정상 문제점을 해결할 뿐만 아니라 실리콘 기판에 흐르는 전류로 인한 소자의 오작동을 방지할 수 있다. Conventionally, a nanowire device was manufactured by transferring a nanowire manufactured by this method to another substrate. However, in this embodiment, the silicon substrate itself is otherwise a substrate doped with the first conductivity type impurity. In addition, the nanowires are second conductive nanowires 120. Thus, after forming the nanowires on the silicon substrate doped with a predetermined impurity as described above, the silicon nanowire device 100 is formed by doping the nanowires with impurities of a conductive type different from those of the silicon substrate. In this way, it is possible not only to solve the process problems when transferring nanowires to other substrates, but also to prevent device malfunction due to the current flowing through the silicon substrate.
본 실시예의 제1도전형 실리콘 기판(110)은 제2도전형 나노와이어(120)를 지지하기 위한 실리콘 나노와이어 지지부(130)를 포함한다. 실리콘 나노와이어 지지부(130)는 제2도전형 나노와이어(120)와 양단과 연결되어 있고, 상부에는 제2도전형 나노와이어(120)와 같이 제2도전형 불순물로 도핑된 제2도전형 도핑영역이 형성되어 있다. 제2도전형 도핑영역은 실리콘 나노와이어 지지부(130)의 상부 전체에 형성될 수도 있고, 도 1에서와 같이 일부에만 형성될 수 있다. The first conductive silicon substrate 110 of the present embodiment includes a silicon nanowire support 130 for supporting the second conductive nanowire 120. The silicon nanowire support unit 130 is connected to both ends of the second conductive nanowire 120, and the second conductive doping is doped with a second conductive impurity, such as the second conductive nanowire 120. The area is formed. The second conductive doped region may be formed on the entire upper portion of the silicon nanowire support 130, or may be formed only on a portion as shown in FIG. 1.
도 2는 도 1의 실리콘 나노와이어 소자(100)의 제2도전형 나노와이어(120)에서의 단면도이다. 제2도전형 나노와이어(120)는 양단이 제1도전형 실리콘 기판(110)과 연결되어 있다. 제2도전형 나노와이어(120)에 흐르는 전류를 Inw라고 하고, 제2도전형 나노와이어(120) 일단에서 제1도전형 실리콘 기판(110)을 통해 제2도전형 나노와이어(120)의 타단으로 흐르는 전류를 Isub라 하자. FIG. 2 is a cross-sectional view of the second conductive nanowire 120 of the silicon nanowire device 100 of FIG. 1. Both ends of the second conductive nanowire 120 are connected to the first conductive silicon substrate 110. The current flowing in the second conductive nanowire 120 is referred to as I nw , and one end of the second conductive nanowire 120 passes through the first conductive silicon substrate 110 at one end of the second conductive nanowire 120. Let I sub current flow to the other end.
실리콘 나노와이어 소자는 나노와이어 부분에 흐르는 전류의 변화를 측정하는 소자이므로 나노와이어에 흐르는 전류인 Inw의 측정이 중요하다. 그러나, 실리콘 나노와이어 소자에서는 나노와이어 부분에만 전류가 흐르는 것이 아니라 실리콘 기판을 통해서도 전류가 흐를 수 있다. 나노와이어는 두께가 나노 사이즈이므로 나노와이어에 흐르는 전류보다는 실리콘 기판에 흐르는 전류의 크기가 상당히 클 수 밖에 없다. 따라서, 실리콘 기판과 연결된 나노와이어의 경우, 그대로 사용하면 실리콘 기판에 흐르는 전류 Isub 때문에 나노와이어에 흐르는 전류 Inw를 측정하기가 매우 어렵다. Since the silicon nanowire device measures the change of the current flowing through the nanowire portion, it is important to measure the current I nw that flows through the nanowire. However, in the silicon nanowire device, the current may flow not only in the nanowire portion but also through the silicon substrate. Since the nanowires are nano-sized, the magnitude of the current flowing through the silicon substrate is much larger than that of the nanowire. Therefore, in the case of a nanowire connected to a silicon substrate, when used as it is, it is very difficult to measure the current I nw flowing through the nanowire because of the current I sub flowing through the silicon substrate.
그러나, 본 실시예에서는 실리콘 기판은 제1도전형 실리콘 기판(110)이고, 나노와이어는 제2도전형 나노와이어(120)로서, 서로 다른 도전형의 불순물로 도핑된다. 따라서, 제2도전형 나노와이어(120) 및 제1도전형 실리콘 기판(110) 사이에는 공핍층(150)이 형성될 수 있다. 제1도전형 실리콘 기판(110)은 p형 실리콘 기판이고, 제2도전형 나노와이어(120)는 n형 나노와이어라면, 제1도전형 실리콘 기판(110) 및 제2도전형 나노와이어(120) 사이에는 p-n접합이 형성되어 반도체에서와 같이 공핍층이 형성되는 것이다. However, in the present embodiment, the silicon substrate is the first conductive silicon substrate 110 and the nanowires are the second conductive nanowires 120 and are doped with impurities of different conductivity types. Therefore, a depletion layer 150 may be formed between the second conductive nanowire 120 and the first conductive silicon substrate 110. If the first conductive silicon substrate 110 is a p-type silicon substrate, and the second conductive nanowire 120 is an n-type nanowire, the first conductive silicon substrate 110 and the second conductive nanowire 120 may be used. The pn junction is formed between) to form a depletion layer as in a semiconductor.
즉, 제2도전형 나노와이어(120) 및 제1도전형 실리콘 기판(110) 사이에 일종의 전위장벽이 생기게 되고, 이에 따라 Isub가 Inw보다 절대적으로 우세한 것만은 아니게 된다. 이는 도 1의 실리콘 나노와이어 소자의 등가회로도를 나타낸 도 3을 참조하여 설명한다.That is, a kind of potential barrier is formed between the second conductive nanowire 120 and the first conductive silicon substrate 110, and thus, I sub is not absolutely superior to I nw . This will be described with reference to FIG. 3, which shows an equivalent circuit diagram of the silicon nanowire device of FIG. 1.
도 3의 등가회로도에서 좌측 저항은 n-n-n의 도핑구조를 갖는 일종의 저항체인 제2도전형 나노와이어(120)를 나타내고 있다. 이와 달리 제1도전형 실리콘 기판(110)을 따라 흐르는 전류는, n형인 제2도전형 나노와이어(120)의 일단에서 p형인 제1도전형 실리콘 기판(110)을 통해 다시 n형인 제2도전형 나노와이어(120)의 타단으로 흐르게 되므로, n-p-n의 n-채널 MOSFET구조라 할 수 있다. In the equivalent circuit diagram of FIG. 3, the left resistor represents the second conductive nanowire 120, which is a kind of resistor having an n-n-n doping structure. Unlike this, the current flowing along the first conductive silicon substrate 110 is n-type second conductive again through the p-type first conductive silicon substrate 110 at one end of the n-type second conductive nanowire 120. Since it flows to the other end of the nanowire 120, it can be referred to as the n-channel MOSFET structure of npn.
이 경우 제2도전형 나노와이어(120)로 흐르는 전류 Inw는 나노와이어의 도핑, 굵기, 또는 길이 등 저항의 크기에 의해 결정되며, 제1도전형 실리콘 기판(110)으로 흐르는 전류 Isub는 채널이 형성되지 않았을 때, FET에 흐르는 전류이다. 나노와이어에 흐르는 전류가 실리콘 기판에 흐르는 전류보다 우세하여야만 나노와이어의 저항변화가 전체 전류의 변화에 우세하게 기여하게 되므로, Inw >> Isub인 조건이 되도록 제1도전형 실리콘 기판(110)의 특성을 고려하면서, 제2도전형 나노와이어(120)의 조건을 조절하여야 한다. In this case, the current I nw flowing to the second conductive nanowire 120 is determined by the size of the resistance such as the doping, the thickness, or the length of the nanowire, and the current I sub flowing to the first conductive silicon substrate 110 is When no channel is formed, it is the current through the FET. Since the current flowing through the nanowires should be superior to the current flowing through the silicon substrate, since the resistance change of the nanowires contributes predominantly to the change of the total current, the first conductive silicon substrate 110 may be in the condition of I nw >> I sub . Considering the characteristics of, the conditions of the second conductive nanowires 120 should be adjusted.
도 4는 본 발명의 다른 실시예에 따른 실리콘 나노와이어 소자의 단면도이다. 본 실시예에서 실리콘 나노와이어 소자(200)는 제1도전형 실리콘 기판(210) 및 제2도전형 나노와이어(220)을 포함한다. 제1도전형 실리콘 기판(210) 및 제2도전형 나노와이어(220) 사이에는 제1공핍층(230)이 형성되어 있다. 4 is a cross-sectional view of a silicon nanowire device according to another exemplary embodiment of the present invention. In this embodiment, the silicon nanowire device 200 includes a first conductive silicon substrate 210 and a second conductive nanowire 220. The first depletion layer 230 is formed between the first conductive silicon substrate 210 and the second conductive nanowire 220.
제2도전형 나노와이어(220)는 제1도전형 실리콘 기판(210)과 이격된 영역에 제1도전형 실리콘 기판(210)의 불순물의 도전형과 동일한 제1도전형 불순물이 도핑된 제1도전형 도핑영역(240)을 포함한다. 따라서, 제2도전형 나노와이어(220)는 제1도전형 실리콘 기판(210)과 연결된 부분은 제2도전형 불순물로 도핑되어 있고, 제1도전형 실리콘 기판(210)과 이격되어 공중으로 부양된 영역의 일부는 제1도전형 불순물로 도핑된 제1도전형 도핑영역(240)이 형성되어 있다. The second conductive nanowire 220 may include a first doped first conductive dopant that is the same as a conductive type impurity of the first conductive silicon substrate 210 in a region spaced apart from the first conductive silicon substrate 210. And a conductive doped region 240. Accordingly, the portion of the second conductive nanowire 220 that is connected to the first conductive silicon substrate 210 is doped with the second conductive impurity, and is spaced apart from the first conductive silicon substrate 210 to float in the air. The first conductive doped region 240 doped with the first conductive dopant is formed in part of the doped region.
예를 들어, 제1도전형 실리콘 기판(210)이 p형 실리콘 기판이고, 제2도전형 나노와이어(220)가 n형 나노와이어라면, 제2도전형 나노와이어(220)의 제1도전형 도핑영역(240)은 p형 불순물로 도핑된다. For example, if the first conductive silicon substrate 210 is a p-type silicon substrate and the second conductive nanowire 220 is an n-type nanowire, the first conductive type of the second conductive nanowire 220 may be used. The doped region 240 is doped with p-type impurities.
이는 제2도전형 나노와이어(220)가 일단을 기준으로 하여 n-p-n 접합을 하고 있다는 것을 의미한다. 따라서, 제2도전형 나노와이어(220)의 내부에는 제2공핍층(250)이 존재한다. 이러한 구조의 실리콘 나노와이어 소자(200)는 제2도전형 나노와이어(220)가 n-p-n 접합의 트랜지스터 소자와 같은 기능을 할 수 있어 도 3에서와 같이 일종의 저항체 역할을 하는 제2도전형 나노와이어(120)와 상이한 회로를 다양하게 구현할 수 있다. This means that the second conductive nanowire 220 is n-p-n bonded based on one end. Therefore, the second depletion layer 250 is present in the second conductive nanowire 220. In the silicon nanowire device 200 having the above structure, the second conductive nanowire 220 may function as a transistor device having an npn junction, and thus, as shown in FIG. 3, the second conductive nanowire ( Various circuits different from 120 may be implemented.
도 5는 본 발명의 다른 실시예에 따른 실리콘 나노와이어 소자의 사시도이고, 도 6은 도 5의 실리콘 나노와이어 소자의 단면도이다. 본 실시예에서 실리콘 나노와이어 소자(300)는 제1도전형 실리콘 기판(310) 및 제1도전형 나노와이어(320)를 포함하고, 제1도전형 실리콘 기판(310) 및 제1도전형 나노와이어(320) 사이에는 제2도전형 우물층(340)이 형성되어 있다. 따라서, 제1도전형 실리콘 기판(310) 및 제2도전형 우물층(340) 사이에는 제1공핍층(330)이 형성되고, 제2도전형 우물층(340) 및 제1도전형 나노와이어(320) 사이에는 제2공핍층(350)이 형성된다. 5 is a perspective view of a silicon nanowire device according to another exemplary embodiment of the present invention, and FIG. 6 is a cross-sectional view of the silicon nanowire device of FIG. 5. In the present embodiment, the silicon nanowire device 300 includes a first conductive silicon substrate 310 and a first conductive nanowire 320, and includes a first conductive silicon substrate 310 and a first conductive nano. A second conductive well layer 340 is formed between the wires 320. Accordingly, a first depletion layer 330 is formed between the first conductive silicon substrate 310 and the second conductive well layer 340, and the second conductive well layer 340 and the first conductive nanowire are formed. The second depletion layer 350 is formed between the 320.
예를 들어, 도 5에서와 같이 제1도전형 실리콘 기판(310)이 p형 실리콘 기판이면, 제1도전형 나노와이어(320)는 p형 나노와이어이고, p형 실리콘 기판 및 p형 나노와이어 사이에 형성된 제2도전형 우물층(340)은 n형 층이다. 또는 제1도전형 실리콘 기판(310) n형 실리콘 기판이면, 제1도전형 나노와이어(320)는 n형 나노와이어이고, 제2도전형 우물층(340)은 p형 층일 수 있다. For example, as shown in FIG. 5, when the first conductive silicon substrate 310 is a p-type silicon substrate, the first conductive nanowire 320 is a p-type nanowire, a p-type silicon substrate and a p-type nanowire. The second conductive well layer 340 formed therebetween is an n-type layer. Alternatively, if the first conductive silicon substrate 310 is an n-type silicon substrate, the first conductive nanowire 320 may be an n-type nanowire, and the second conductive well layer 340 may be a p-type layer.
도 6을 참조하면, 실리콘 나노와이어 소자(300)는 공핍층을 제1공핍층(330) 및 제2공핍층(350)을 포함하여 총 2종류의 공핍층을 포함한다. 도 3을 참조하여 설명한 바와 같이, 제1도전형 나노와이어(320)를 따라 흐르는 전류가 제1도전형 실리콘 기판(310)을 따라 흐르는 전류에 우세하여야 한다. Referring to FIG. 6, the silicon nanowire device 300 includes two types of depletion layers including the depletion layer as the first depletion layer 330 and the second depletion layer 350. As described with reference to FIG. 3, the current flowing along the first conductive nanowire 320 should prevail over the current flowing along the first conductive silicon substrate 310.
제1도전형 나노와이어(320)를 따라 흐르는 전류는 나노와이어의 도핑, 굵기 또는 길이 등과 같이 저항체로서의 저항 크기에 따라 결정되는데, 이러한 요인을 조절하여 제1도전형 실리콘 기판(310)에 흐르는 전류보다 우세하도록 실리콘 나노와이어 소자(300)를 설계하여야 한다. 그러나, 나노와이어가 나노 사이즈를 갖는 선저항인 점에서 도핑이나 굵기, 길이 등의 요인의 변화폭은 넓지 않다. The current flowing along the first conductive nanowire 320 is determined according to the resistance as a resistor such as doping, thickness, or length of the nanowire, and the current flowing through the first conductive silicon substrate 310 is adjusted by adjusting such factors. Silicon nanowire device 300 should be designed to be more dominant. However, since the nanowire is a line resistance having a nano size, the variation of factors such as doping, thickness, and length is not wide.
따라서, 도 5에서와 같이 제1도전형 나노와이어(320) 및 제1도전형 실리콘 기판(310) 사이에 제1도전형 불순물과 다른 도전형의 제2도전형 불순물을 도핑하여 제2도전형 우물층(340)을 형성하면, 제1도전형 나노와이어(320) 양단으로부터 제1도전형 실리콘 기판(310)을 통해 흐르는 전류의 흐름을 전류 인가방향에 따라 억제할 수 있어, 제1도전형 나노와이어(320)에 흐르는 전류를 보다 효과적으로 우세하게 할 수 있다. Accordingly, as shown in FIG. 5, the second conductive type is doped between the first conductive type nanowire 320 and the first conductive type silicon substrate 310 by doping the first conductive type impurity with another conductive type second conductive impurity. When the well layer 340 is formed, the flow of current flowing from both ends of the first conductive nanowire 320 through the first conductive silicon substrate 310 can be suppressed according to the current application direction, thereby providing a first conductive type. The current flowing through the nanowires 320 can be more effectively dominated.
또한, 도면에는 도시되어 있지 않으나, 본 실시예에서 제1도전형 나노와이어가 제1도전형 실리콘 기판과 이격된 영역에 제2도전형 도핑영역을 더 포함하게 하면, 제1도전형 나노와이어의 일단을 기준으로 하여 n-p-n 접합 또는 p-n-p 접합을 형성하도록 할 수 있다. 따라서 제1도전형 나노와이어 내부에 별도의 공핍층을 더 포함한다. 이러한 구조의 실리콘 나노와이어 소자는 제1도전형 나노와이어가 n-p-n 접합(또는 p-n-p 접합)의 트랜지스터 소자와 같은 기능을 할 수 있어 도 3에서와 같이 일종의 저항체 역할을 하는 제2도전형 나노와이어(120)와 상이한 회로를 다양하게 구현할 수 있다. In addition, although not shown in the drawings, when the first conductive nanowire further includes a second conductive doped region in a region spaced apart from the first conductive silicon substrate, the first conductive nanowire may be formed. One end may be used to form an npn junction or a pnp junction. Therefore, the first conductive nanowire further includes a separate depletion layer. The silicon nanowire device having such a structure may include the second conductive nanowire 120 in which the first conductive nanowire functions as a transistor device of an npn junction (or a pnp junction), and thus acts as a kind of resistor as shown in FIG. 3. Various circuits can be implemented.
본 발명은 상술한 실시형태 및 첨부된 도면에 의해 한정되는 것이 아니라, 첨부된 청구범위에 의해 해석되어야 한다. 또한, 본 발명에 대하여 청구범위에 기재된 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 다양한 형태의 치환, 변형 및 변경이 가능하다는 것은 당해 기술분야의 통상의 지식을 가진 자에게 자명할 것이다.The invention is not to be limited by the foregoing embodiments and the accompanying drawings, but should be construed by the appended claims. In addition, it will be apparent to those skilled in the art that various forms of substitution, modification, and alteration are possible within the scope of the present invention without departing from the technical spirit of the present invention.

Claims (8)

  1. 제1도전형 실리콘 기판; 및A first conductive silicon substrate; And
    상기 제1도전형 실리콘 기판 상에 이격되어 형성되되, 양단이 상기 제1도전형 실리콘 기판과 연결된 제2도전형 나노와이어;를 포함하는 실리콘 나노와이어 소자.And a second conductive nanowire formed on the first conductive silicon substrate, the second conductive nanowire being connected to the first conductive silicon substrate at both ends thereof.
  2. 제1항에 있어서, The method of claim 1,
    상기 제1도전형 실리콘 기판은 p형 실리콘 기판이고, The first conductive silicon substrate is a p-type silicon substrate,
    상기 제2도전형 나노와이어는 n형 나노와이어인 것을 특징으로 하는 실리콘 나노와이어 소자.The second conductive nanowires are silicon nanowire devices, characterized in that the n-type nanowires.
  3. 제1항에 있어서, The method of claim 1,
    상기 제1도전형 실리콘 기판 및 상기 제2도전형 나노와이어의 이격된 사이에 형성된 절연층;을 더 포함하는 것을 특징으로 하는 실리콘 나노와이어 소자.And an insulating layer formed between the first conductive silicon substrate and the second conductive nanowire spaced apart from each other.
  4. 제1항에 있어서, The method of claim 1,
    상기 제1도전형 실리콘 기판은 상기 제2도전형 나노와이어의 양단과 연결된 실리콘 나노와이어 지지부;를 포함하고,The first conductive silicon substrate includes a silicon nanowire support portion connected to both ends of the second conductive nanowire.
    상기 실리콘 나노와이어 지지부의 상부는 제2도전형 불순물로 도핑되어 상기 제2도전형 나노와이어의 양단과 연결된 것을 특징으로 하는 실리콘 나노와이어 소자.And an upper portion of the silicon nanowire support part is doped with a second conductive impurity and connected to both ends of the second conductive nanowire.
  5. 제1항에 있어서, The method of claim 1,
    상기 제2도전형 나노와이어는,The second conductive nanowires,
    상기 제1도전형 실리콘 기판과 이격된 영역에 제1도전형 도핑영역을 포함하는 것을 특징으로 하는 실리콘 나노와이어 소자.And a first conductive doped region in a region spaced apart from the first conductive silicon substrate.
  6. 제1도전형 실리콘 기판;A first conductive silicon substrate;
    상기 제1도전형 실리콘 기판 상에 이격되어 형성되되, 양단이 상기 제1도전형 실리콘 기판과 연결된 제1도전형 나노와이어; 및 First conductive nanowires formed on the first conductive silicon substrate and spaced apart from each other and connected to both ends of the first conductive silicon substrate; And
    상기 제1도전형 실리콘 기판 및 상기 제1도전형 나노와이어 사이에 형성된 제2도전형 우물층;을 포함하는 실리콘 나노와이어 소자.And a second conductive well layer formed between the first conductive silicon substrate and the first conductive nanowire.
  7. 제6항에 있어서, The method of claim 6,
    상기 제1도전형 실리콘 기판은 p형 실리콘 기판이고,The first conductive silicon substrate is a p-type silicon substrate,
    상기 제1도전형 나노와이어는 p형 나노와이어이며, The first conductive nanowire is a p-type nanowire,
    상기 제2도전형 우물층은 n형 층인 것을 특징으로 하는 실리콘 나노와이어 소자.The second conductive well layer is a silicon nanowire device, characterized in that the n-type layer.
  8. 제6항에 있어서, The method of claim 6,
    상기 제1도전형 나노와이어는,The first conductive nanowires,
    상기 제1도전형 실리콘 기판과 이격된 영역에 제2도전형 도핑영역을 포함하는 것을 특징으로 하는 실리콘 나노와이어 소자.And a second conductive doped region in a region spaced apart from the first conductive silicon substrate.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160158998A1 (en) * 2014-12-08 2016-06-09 Canon Kabushiki Kaisha Imprint apparatus and method, and method of manufacturing article

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102395778B1 (en) 2015-09-10 2022-05-09 삼성전자주식회사 Method of forming nanostructure, method of manufacturing semiconductor device using the same and semiconductor device including nanostructure

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090003800A (en) * 2007-07-03 2009-01-12 삼성전자주식회사 Luminous device and method of manufacturing the same
JP2010505728A (en) * 2006-10-05 2010-02-25 日立化成工業株式会社 High array, high aspect ratio, high density silicon nanowires and method for producing the same
US20100297608A1 (en) * 2006-12-06 2010-11-25 Stern Eric D Systems and Methods for CMOS-Compatible Silicon Nano-Wire Sensors with Biochemical and Cellular Interfaces

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080023398A (en) * 2006-09-11 2008-03-14 전자부품연구원 Force sensor using the si nanowire and method for manufacturing the same
KR101040083B1 (en) * 2009-07-27 2011-06-09 전자부품연구원 nanowire transistor sensor, manufacturing method and nanoparticle detection apparatus using the same
KR101163202B1 (en) * 2009-12-29 2012-07-05 주식회사 아이엠헬스케어 A process for silicone nano-wire devices
KR101240294B1 (en) * 2011-03-02 2013-03-07 전자부품연구원 Biosensor module using silicon nano-wire

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010505728A (en) * 2006-10-05 2010-02-25 日立化成工業株式会社 High array, high aspect ratio, high density silicon nanowires and method for producing the same
US20100297608A1 (en) * 2006-12-06 2010-11-25 Stern Eric D Systems and Methods for CMOS-Compatible Silicon Nano-Wire Sensors with Biochemical and Cellular Interfaces
KR20090003800A (en) * 2007-07-03 2009-01-12 삼성전자주식회사 Luminous device and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160158998A1 (en) * 2014-12-08 2016-06-09 Canon Kabushiki Kaisha Imprint apparatus and method, and method of manufacturing article

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