WO2013023472A1 - 双栅极驱动的横向排列的像素结构及显示面板 - Google Patents

双栅极驱动的横向排列的像素结构及显示面板 Download PDF

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Publication number
WO2013023472A1
WO2013023472A1 PCT/CN2012/075993 CN2012075993W WO2013023472A1 WO 2013023472 A1 WO2013023472 A1 WO 2013023472A1 CN 2012075993 W CN2012075993 W CN 2012075993W WO 2013023472 A1 WO2013023472 A1 WO 2013023472A1
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Prior art keywords
gate
pixel
data line
line
thin film
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PCT/CN2012/075993
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English (en)
French (fr)
Inventor
夏志强
陈晨
黄忠守
周思思
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上海中航光电子有限公司
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Application filed by 上海中航光电子有限公司 filed Critical 上海中航光电子有限公司
Priority to KR1020137006508A priority Critical patent/KR101442713B1/ko
Priority to EP12823467.1A priority patent/EP2629281A4/en
Publication of WO2013023472A1 publication Critical patent/WO2013023472A1/zh
Priority to US14/088,287 priority patent/US9217905B2/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections

Definitions

  • Double-gate driven horizontally arranged pixel structure and display panel The present application is filed on August 12, 2011, the Chinese Patent Office, application number 201110231785.X, the invention name is "double gate drive horizontally arranged pixel structure and The priority of the Chinese Patent Application for Display Panels, the entire contents of which is hereby incorporated by reference.
  • the present invention relates to the field of display technologies, and in particular, to a dual gate driven laterally arranged pixel structure and display panel.
  • each main pixel region of the display panel is R (red), G (green), and B (blue) from left to right, wherein each main pixel region is square or Circular, each sub-pixel area is rectangular, and the short side of each sub-pixel area is substantially parallel to the gate line, as shown in FIG. 1, wherein the resolution is mxn, Gl, G2, G3 Gm-2, Gm-1 Gm is m gate lines, Dl, D2, D3 D3n-3, D3n-2, D3n-1, and D3n are 3n data lines.
  • the arrangement of such sub-pixel regions is called vertical alignment.
  • the pixel structure of the flat panel display can be mainly divided into a single-gate driven pixel arrangement, a dual-gate driven pixel arrangement, and a tri-gate (tri-gate).
  • the pixel arrangement of the driving wherein the pixel arrangement of the single gate driving is that the three color sub-pixel regions are driven together by a single gate; the pixel arrangement of the double gate driving is three color sub-pixel regions together by two Gate drive;
  • the three-gate drive pixel arrangement is that three color sub-pixel regions are respectively driven by three gates.
  • the raster lattice placed in front of the display panel needs to be vertically arranged, wherein the size of one raster lattice is similar to the size of one main pixel region;
  • the alignment error between the glass plate and the display panel assembly causes the grating grid to block a certain color, such as blocking a part of the area of the red sub-pixel area, thereby causing severe color deviation and chromatic aberration.
  • the prior art provides a lateral arrangement manner in which the sub-pixel regions of each color are arranged laterally, so that even if the glass plate where the grating grid is located has a registration error when assembled with the display panel, the sub-pixel regions of the three colors are Blocking the same area, although the amount of light transmission per sub-pixel area is reduced, the color formed by the three sub-pixel areas will not be offset.
  • the current horizontal arrangement of pixels includes the following: Single-gate driving vertical The horizontal arrangement of pixels for screen horizontal, the horizontal arrangement of pixels for dual gate driving, and the horizontal arrangement of pixels for three gate driving.
  • the principle of horizontally arranging the pixels of the single-gate-driven vertical screen is to use a screen with a resolution of mxn to be converted into a screen with a resolution of n xm.
  • This arrangement requires that a buffer be added to the driver circuit.
  • the display signal is converted horizontally and vertically, which greatly increases the cost of the system, so this arrangement is rarely used.
  • the tri-gate-driven pixel lateral arrangement is three times as large as the single-gate-driven vertical screen horizontally.
  • the number of data lines is reduced to one-third of the horizontal arrangement of the vertical screens of the single-gate driving, so the display panel using the arrangement uses more gate driving chips and less source driving. chip. Since the number of gate lines is three times that of the vertical arrangement of the vertical screens of the single-gate driving, the driving time of each gate line is shortened to three points of the horizontal arrangement of the pixels of the vertical screen of the single-gate driving.
  • TFT Thin Film Transistor
  • Embodiments of the present invention provide a dual-gate driven laterally arranged pixel structure and display panel.
  • a dual gate driven laterally arranged pixel structure comprising:
  • each main pixel region includes three sub-pixel regions vertically adjacent to each other;
  • each of the data lines is electrically connected to the sources of the two thin film transistors, wherein the thin film transistors electrically connected to different data lines are different; the gates of the two thin film transistors electrically connected to the same data line are different from each other
  • the gate lines are electrically connected.
  • a display panel includes: a first substrate, a second substrate, and a liquid crystal layer between the first substrate and the second substrate, wherein the first substrate is provided with the horizontally arranged pixel structure of the double gate driving .
  • a double gate driven laterally arranged driving method is suitable for the above-described double gate driven horizontally arranged pixel structure, comprising:
  • a first one of the two gate lines is at a high level, and a second one of the two gate lines is at a low level, electrically connected to the first gate line
  • the thin film transistor is turned on; the three data lines respectively supply power to the thin film transistor electrically connected to the self;
  • the second gate line is at a high level
  • the first gate line is at a low level
  • a thin film transistor electrically connected to the second gate line is turned on
  • the three data lines are respectively Powered by a thin film transistor that is electrically connected to itself.
  • the dual-gate driven laterally arranged pixel structure includes a double-gate driven laterally arranged pixel structure, wherein each data line is electrically connected to the sources of the two thin film transistors respectively; and the same data
  • the gates of the two thin film transistors electrically connected are electrically connected to different gate lines, respectively.
  • FIG. 1 is a schematic view of a longitudinal arrangement of pixels provided by the prior art
  • FIG. 2 is a schematic diagram of a pixel structure of a horizontally arranged double gate drive according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a pixel structure based on FIG. 2 according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram of a horizontally arranged pixel structure using dual gate driving according to an embodiment of the present invention
  • FIG. 5 is a schematic diagram of another driving manner of a horizontally arranged pixel structure using dual gate driving according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of still another driving manner of a horizontally arranged pixel structure using dual gate driving according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a pixel structure of a lateral arrangement of another double gate drive according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a pixel structure of a horizontally arranged double gate drive according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a pixel structure of a horizontally arranged double gate drive according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of a pixel structure of a lateral arrangement of a dual gate drive according to an embodiment of the present invention.
  • FIG. 11 is a schematic diagram of a pixel structure of a horizontally arranged double gate drive according to an embodiment of the present invention.
  • FIG. 12 is a schematic diagram of a pixel structure of a lateral arrangement of a dual gate drive according to an embodiment of the present invention.
  • FIG. 13 is a schematic diagram of a pixel structure of a laterally arranged double gate drive according to another embodiment of the present invention.
  • the embodiment of the invention provides a dual-gate driven horizontally arranged pixel structure, comprising: a plurality of pixel units, the pixel unit comprising:
  • the two gate lines include: a first gate line and a Two gate lines
  • the three data lines include: a first data line, a second data line, and a third data line arranged in sequence; wherein, two gate lines are disposed on the substrate and arranged in parallel along the first direction; three pieces of data The wires are disposed on the substrate and arranged in parallel along the second direction; the two gate lines intersect the three data lines, and in a specific embodiment, the first direction is perpendicular to the second direction;
  • each main pixel region includes three sub-pixel regions vertically adjacent to each other; three sub-pixel regions are R (red), G (green) and B (blue), respectively
  • the long side of each sub-pixel is substantially parallel to the first direction, and the short side of each sub-pixel is substantially parallel to the second direction.
  • each thin film transistor respectively disposed in corresponding sub-pixel regions, that is, one thin film transistor in each sub-pixel region, each thin film transistor including a source, a drain and a gate;
  • each of the data lines is electrically connected to the sources of the two thin film transistors, so that three data lines are electrically connected to the sources of the six thin film transistors, wherein the different data lines are electrically connected to the thin film transistors, that is, the first The thin film transistor electrically connected to the data line, the thin film transistor electrically connected to the second data line, and the thin film transistor electrically connected to the third data line are different, so that three data lines and six thin film transistor sources can be made. Electropolar connection; the gates of two thin film transistors electrically connected to the same data line are electrically connected to different gate lines, respectively.
  • the pixel structure may further include: a pixel electrode and a common electrode line overlapping the pixel electrode portion to form a storage capacitor, wherein the pixel electrode covers the light-transmitting region of the corresponding sub-pixel region, and each pixel electrode and the corresponding film respectively
  • the drain of the transistor is electrically connected; specifically, the method includes: two common electrode lines, that is, a first common electrode line and a second common electrode line, wherein the pixel electrode covering the sub-pixel area in the first main pixel area The first common electrode lines overlap to form three storage capacitors; the pixel electrodes covering the sub-pixel regions in the second main pixel region overlap with the second common electrode lines to form three storage capacitors, that is, the first common electrode The line and the second common electrode line are respectively parallel to the data line, and the two common electrode lines form six storage capacitors; or, the three common electrode lines, that is, the first common electrode line, the second common electrode line, and the third common electrode line The three common electrode lines are respectively parallel to the gate lines, and each of the common electrode
  • the dual-gate driven laterally arranged pixel structure includes a dual gate drive a horizontally arranged pixel structure, wherein each of the data lines is electrically connected to the sources of the two thin film transistors; the gates of the two thin film transistors electrically connected to the same data line are electrically connected to different gate lines .
  • the ordinary TFT can also meet the driving requirements, and is suitable for a wide range of applications.
  • the pixel structure provided by the embodiment of the present invention is the same as the gate line and the data line required for the vertical arrangement of the pixels of the existing dual gate drive, so that the number of the source driver chip and the gate driver chip is also Similarly, the driving time and driving mode of each gate line can be the same, and the display panel size can be the same, so the existing horizontally arranged pixel structure of the double gate driving is utilized.
  • the embodiment of the present invention provides a dual-gate driven horizontally arranged pixel structure.
  • the specific structure may be as shown in FIG. 2, which includes: a plurality of pixel units, each of which includes:
  • Two gate lines that is, a first gate line G1 and a second gate line G2; the two gate lines are disposed on the substrate and arranged in parallel along the first direction;
  • the three data lines that is, the first data line D1, the second data line D2, and the third data line D3 are sequentially arranged, and the three data lines are disposed on the substrate and arranged in parallel along the second direction; the second direction is substantially perpendicular to the first direction.
  • Two main pixel regions that is, a first main pixel region and a second main pixel region, wherein the first main pixel region respectively includes a first sub-pixel region L1, a second sub-pixel region L2 and a third sub-pixel region L3;
  • the two main pixel regions respectively include a fourth sub-pixel region L4, a fifth sub-pixel region L5, and a sixth sub-pixel region L6.
  • P1, P2, P3, P4, P5, and P6 are the first sub-pixel region L1, the second pixel region L2, the third pixel region L3, the fourth sub-pixel region L4, and the fifth sub-pixel region L5, respectively.
  • each sub-pixel region is substantially parallel to the first direction, and a short side of each sub-pixel region is substantially parallel to the second direction
  • the two main pixel regions are preferably Includes two red sub-pixel regions, two green sub-pixel regions, and two blue sub-pixels, which can have multiple combinations
  • the two main pixel regions may also include an arrangement combination of any of the color sub-pixel regions.
  • Six thin film transistors are respectively disposed in corresponding sub-pixel regions, that is, one thin film transistor in each sub-pixel region, such as a thin film transistor T1 of a first sub-pixel region, a thin film transistor T2 of a second pixel region, and a third a thin film transistor T3 of a sub-pixel region, a thin film transistor T4 of a fourth sub-pixel region, a thin film transistor T5 of a fifth sub-pixel region, and a thin film transistor T6 of a sixth sub-pixel region, each thin film transistor including a source, a drain, and a gate Extremely
  • each of the pixel electrodes covering the light-transmissive region of the corresponding sub-pixel region and electrically connected to the drain of the corresponding thin film transistor;
  • Two common electrode lines that is, a first common electrode line C1 and a second common electrode line C2, wherein the pixel electrodes electrically connected to the drains of T1, ⁇ 2, ⁇ 3 (ie, covered in LI, L2, pixel electrodes on L3) respectively overlap the first common electrode line to form three storage capacitors; pixel electrodes electrically connected to the drains of T4, ⁇ 5, ⁇ 6 (ie, pixel electrodes overlying L4, L5, L6) Each of the three common electrode lines overlaps with the second common electrode line to form three storage capacitors, wherein the first common electrode line and the second common electrode line are respectively parallel to the data line.
  • the first main pixel area is located between the first data line and the second data line; the second main pixel area is located between the second data line and the third data line;
  • the strip gate line and the three data lines intersect to form a first closed area and a second closed area; the second pixel area L2 and the fifth sub-pixel area L 5 are respectively located in the first closed area and the second closed area.
  • the first data line D1 is electrically connected to the sources of the thin film transistor T1 and the thin film transistor T2; the gate of the thin film transistor T1 is electrically connected to the first gate line G1; the gate of the thin film transistor T2 and the second gate line G2 Electrical connection; the second data line D2 is electrically connected to the sources of the thin film transistor T3 and the thin film transistor T4; the gate of the thin film transistor T3 is electrically connected to the second gate line G2; the gate of the thin film transistor T4 and the first gate line G1 is electrically connected; the third data line D3 is electrically connected to the sources of the thin film transistor T5 and the thin film transistor T6; the gate of the thin film transistor T5 is electrically connected to the first gate line G1; the gate and the second gate of the thin film transistor T6 Line G2 is electrically connected.
  • the sub-pixel region may be a rectangular region, and specifically includes: a first side and a second side, the first gate line G1 and the second gate line G2 are parallel to the first side of the sub-pixel region, and are respectively set Between three sub-pixel regions in each main pixel region or outside each sub-pixel region; a first data line D1, a second data line D2, and a third data line D3 and a second side of the sub-pixel region parallel, And respectively disposed between the two main pixel regions of the pixel unit or outside the two main pixel regions.
  • the first side is a long side of the rectangular area
  • the second side is a short side of the rectangular area.
  • the first side is a short side of the rectangular area
  • the second side is a rectangle.
  • two main pixel regions are one repeating unit, and each main pixel region includes three sub-pixel regions (a preferred one is a combination of a red sub-pixel region R, a green sub-pixel region G, and a blue sub-pixel region).
  • B that is, the smallest one repeating unit contains 6 sub-pixel regions.
  • a minimum repeating unit includes two gate lines, three data lines, six thin film transistors, and each data line drives two sub-pixel regions, and the two sub-pixel regions are respectively controlled by different gate lines.
  • a pixel structure for a screen with a resolution of mxn, the required gate line is 2m, and the required data line is 3n/2, so that the driving time of each gate line is shortened to the vertical of the single gate drive.
  • the embodiment of the present invention can be produced by using the existing double gate driving longitudinally arranged pixel structure production process.
  • the dual-gate driven laterally arranged pixel structure is provided, and the double-gate driven laterally arranged pixel structure provided by the embodiment of the present invention is more suitable for 3D display.
  • a method of driving a laterally arranged double gate drive is described as follows.
  • the method is applicable to the horizontally arranged pixel structure of the double gate drive described above, and includes:
  • a first gate line of the two gate lines is at a high level, and a second gate line of the two gate lines is a low level, and a thin film transistor electrically connected to the first gate line Open, the three data lines are respectively supplying power to the thin film transistors electrically connected to them;
  • the second gate line is at a high level
  • the first gate line is at a low level
  • a thin film transistor electrically connected to the second gate line is turned on
  • the three data lines are respectively Powered by a thin film transistor that is electrically connected to itself.
  • the following describes the driving method of the monochrome display by taking the TN normally white mode as an example.
  • the first pixel region L1 is the green sub-pixel region G1 and the second pixel region L2 is red.
  • the sub-pixel region R1 the third pixel region L3 is the blue sub-pixel region B1
  • the fourth pixel region L4 is the red sub-pixel region R2
  • the fifth pixel region L5 is the blue sub-pixel region B2
  • the sixth pixel region L6 is green.
  • the data line D provides the pixel voltage S.
  • the pixel voltage S is positive or negative with respect to the reference voltage COM
  • the sub-pixel region is in a dark state, and the pixel voltage S is positive with respect to the reference voltage COM.
  • the sub-pixel region When the level is low or negative, the sub-pixel region is in a bright state, wherein the pixel voltage S is a level at which the data line is data transmitted by the thin film transistor, wherein the pixel voltage S is positively low with respect to the reference voltage COM
  • a flat or negative low level indicates that the pixel voltage S is close to the reference voltage COM.
  • a driving method suitable for the red display of the above pixel structure is described as follows:
  • G1 is at a high level at time t1
  • other scan lines are at a low level
  • thin film transistors of G1, R2, and B2 are turned on
  • Sl, S2, and S3 respectively transmit data to G1, R2, and B2
  • Sl, S2, and S3 are the levels of data (also referred to as pixel voltages) delivered by data lines D1, D2, and D3, respectively, assuming S1 is a positive high level, S2 is a negative low level, and S3 is positive. High level, so G1 is dark, R2 is bright, and B2 is dark.
  • G2 is high, other scan lines are low, transistors of Rl, Bl, and G2 are turned on, SI, S2, and S3 are respectively supplying data to Rl, Bl, and G2, and S1 is a negative ⁇ level, and S2 is Positive high level, S3 is negative high level, R1 is on, B1 is dark, and G2 is dark. In this way, only the red sub-pixels are bright in one repeating unit, and the other sub-pixels are dark.
  • the waveform of each data line in the two main pixels repeating t1 and t2 at the next moment causes the entire repeating unit to be displayed all the time. red.
  • a driving method suitable for the green display of the above pixel structure is described as follows:
  • G1 is at a high level at time t1
  • other scan lines are at a low level
  • thin film transistors of G1, R2, and B2 are turned on, and Sl, S2, and S3 respectively transmit data to G1, R2, and B2, and SI is Positive level
  • S2 is negative high level
  • S3 is positive high level
  • G1 is bright
  • R2 is dark
  • B2 is dark.
  • G2 is high, other scan lines are low, R1, Bl, G2 thin film transistors are turned on, SI, S2, S3 are respectively transmitting data to Rl, Bl, G2, S1 is negative high level, S2 It is a positive high level, S3 is a negative low level, R1 is dark, B1 is dark, and G2 is bright. In this way, only the green sub-pixels are bright in one repeating unit, and the other sub-pixels are dark.
  • the waveform of each data line in the two main pixels repeats t1 and t2 at the next moment so that the entire repeating unit is always displayed. green.
  • a driving method suitable for the blue display of the above pixel structure is described as follows:
  • G1 is high at time t1, other scan lines are low, thin film transistors of Gl, R2, and B2 are turned on, and Sl, S2, and S3 are respectively transmitting data to Gl, R2, and B2, and SI is positive.
  • the high level S2 is a negative high level
  • S3 is a positive low level
  • G1 is dark
  • R2 is dark
  • B2 is bright.
  • G2 is high, other scan lines are low, R1, Bl, G2 thin film transistors are turned on, SI, S2, S3 are respectively transmitting data to Rl, Bl, G2, S1 is negative high level, S2 It is a positive low level, S3 is a negative high level, R1 is dark, B1 is on, and G2 is dark.
  • S1 is negative high level
  • S2 It is a positive low level
  • S3 is a negative high level
  • R1 is dark
  • B1 is on
  • G2 is dark.
  • the signal of each data line in the two main pixels repeats the waveforms of t1 and t2, so that the entire repeating unit is always Show blue.
  • the above driving method can separately control the color and brightness of each sub-pixel region, and realize display of red, green or blue. It can be seen that driving the horizontally arranged pixel structure of the double-gate driving provided by the embodiment of the present invention by using the above driving method can control the whole The screen displays the colors and patterns that the user wants.
  • FIG. 7 shows a dual-gate driven laterally arranged pixel structure according to an embodiment of the present invention, which is different from the embodiment shown in FIG. 2 in that: the first data line D1 and the thin film transistor T2 and the thin film transistor T3 are The source is electrically connected; the gate of the thin film transistor T2 is electrically connected to the first gate line G1; the gate of the thin film transistor T3 is electrically connected to the second gate line G2; the second data line D2 is connected to the thin film transistor T1 and the thin film transistor T6
  • the source of the thin film transistor T1 is electrically connected to the first gate line G1; the gate of the thin film transistor T6 is electrically connected to the second gate line G2; the third data line D3 and the thin film transistor T4 and the thin film transistor
  • the source of T5 is electrically connected; the gate of the thin film transistor T4 is electrically connected to the first gate line G1; the gate and the second gate of the thin film transistor T5
  • the pole line G2 is electrically connected.
  • FIG. 8 is a diagram showing another dual gate driving laterally arranged pixel structure according to an embodiment of the present invention, which is different from the embodiment shown in FIG. 2 in that: a first data line D1 and a thin film transistor T1 and a thin film transistor T3.
  • the source is electrically connected; the gate of the thin film transistor T1 is electrically connected to the first gate line G1; the gate of the thin film transistor T3 is electrically connected to the second gate line G2; the second data line D2 is connected to the thin film transistor T2 and the thin film transistor
  • the source of T5 is electrically connected; the gate of the thin film transistor T2 is electrically connected to the first gate line G1; the gate of the thin film transistor T5 is electrically connected to the second gate line G2; the third data line D3 and the thin film transistor T4 and the thin film
  • the source of the transistor T6 is electrically connected; the gate of the thin film transistor T4 is electrically connected to the first gate line G1; and the gate of the thin film transistor T6 is electrically connected to the second gate line G2.
  • FIG. 9 is a diagram showing another dual gate driving laterally arranged pixel structure according to an embodiment of the present invention, which is different from the embodiment shown in FIG. 2 in that: a first data line D1 and a thin film transistor T1 and a thin film transistor T3.
  • the source is electrically connected; the gate of the thin film transistor T1 is electrically connected to the first gate line G1; the gate of the thin film transistor T3 is electrically connected to the second gate line G2; the second data line D2 is connected to the thin film transistor T2 and the thin film transistor
  • the source of T5 is electrically connected; the gate of the thin film transistor T5 is electrically connected to the first gate line G1; the gate of the thin film transistor T2 is electrically connected to the second gate line G2; the third data line D3 and the thin film transistor T4 and the thin film
  • the source of the transistor T6 is electrically connected; the gate of the thin film transistor T4 is electrically connected to the first gate line G1; and the gate of the thin film transistor T6 is electrically connected to the second gate line G2.
  • FIG. 10 is a diagram showing another dual gate driving laterally arranged pixel structure according to an embodiment of the present invention, which is different from the embodiment shown in FIG. 2 in that: the first main pixel region is located at the first data line and the second Between the data lines; the second main pixel area is located between the second data line and the third data line; the two gate lines and the three data lines intersect to form the first closed area and the second closed area; the second pixel area L2 And the third sub-pixel area L3 is located in the first closed area, and the fifth sub-pixel area L5 and the sixth sub-pixel area L6 are located in the second closed area.
  • the first data line D1 is electrically connected to the sources of the thin film transistor T1 and the thin film transistor T2; the gate of the thin film transistor T1 is electrically connected to the first gate line G1; the gate of the thin film transistor T2 and the second gate line G2 is electrically connected; the second data line D2 is electrically connected to the sources of the thin film transistor T3 and the thin film transistor T4; the gate of the thin film transistor T3 is electrically connected to the second gate line G2; the gate of the thin film transistor T4 and the first gate Line G1 is electrically connected;
  • the third data line D3 is electrically connected to the sources of the thin film transistor T5 and the thin film transistor T6; the gate of the thin film transistor T5 is electrically connected to the first gate line G1; and the gate of the thin film transistor T6 is electrically connected to the second gate line G2.
  • FIG. 11 is a diagram showing another dual gate driving laterally arranged pixel structure according to an embodiment of the present invention, which is different from the embodiment shown in FIG. 2 in that: the first main pixel region is located at the first data line and the second Between the data lines; the second main pixel area is located between the second data line and the third data line; the two gate lines and the three data lines intersect to form the first closed area and the second closed area; the first pixel area L1 The second pixel area L2 and the third sub-pixel area L3 are located in the first closed area, and the fourth sub-pixel area L4, the fifth sub-pixel area L5 and the sixth sub-pixel area L6 are located in the second closed area.
  • the first data line D1 is electrically connected to the sources of the thin film transistor T1 and the thin film transistor T2; the gate of the thin film transistor T1 is electrically connected to the first gate line G1; the gate of the thin film transistor T2 and the second gate line G2 is electrically connected; the second data line D2 is electrically connected to the sources of the thin film transistor T3 and the thin film transistor T4; the gate of the thin film transistor T4 is electrically connected to the first gate line G1; the gate and the second gate of the thin film transistor T3
  • the pole line G2 is electrically connected.
  • FIG. 12 is a diagram showing another dual gate driving laterally arranged pixel structure according to an embodiment of the present invention, which is different from the embodiment shown in FIG. 2 in that: the first main pixel region is located outside the first data line, The outer side of the first data line is a side of the first data line facing away from the second data line; the second main pixel area is located between the second data line and the third data line, specifically, the first data line D1 Electrically connected to the source of the thin film transistor T1 and the thin film transistor T2; the gate of the thin film transistor T1 is electrically connected to the first gate line G1; the gate of the thin film transistor T2 is electrically connected to the second gate line G2; the second data line D2 is electrically connected to the source of the thin film transistor T3 and the thin film transistor T4; the gate of the thin film transistor T4 is electrically connected to the first gate line G1; the gate of the thin film transistor T3 is electrically connected to the second gate line G2; The line D3 is electrically connected to the sources of the
  • FIG. 13 is a diagram showing another dual gate driving laterally arranged pixel structure according to an embodiment of the present invention, which is different from the embodiment shown in FIG. 2 in that: the first main pixel region is located on the first data line.
  • the outer side of the first data line is a side of the first data line facing away from the second data line;
  • the second main pixel area is located outside the third data line, wherein the outer side of the third data line is
  • the first data line D1 is electrically connected to the source of the thin film transistor T1 and the thin film transistor T2; the gate of the thin film transistor T1 is electrically connected to the first gate line G1.
  • the gate of the thin film transistor T2 is electrically connected to the second gate line G2; the second data line D2 is electrically connected to the sources of the thin film transistor T3 and the thin film transistor T4; the gate of the thin film transistor T4 and the first gate line G1 Electrical connection; the gate of the thin film transistor T3 is electrically connected to the second gate line G2; the third data line D3 is electrically connected to the sources of the thin film transistor T5 and the thin film transistor T6; the gate of the thin film transistor T5 and the first gate line G1 is electrically connected; the gate of the thin film transistor T6 is electrically connected to the second gate line G2.
  • the sub-pixel region in the horizontally arranged pixel structure of the dual gate driving provided by the above embodiments may be a rectangular region.
  • the long side of the rectangular region is parallel to the gate line, and the rectangular region is short.
  • the side is parallel to the data line; or, the sub-pixel area is a non-rectangular area, and does not affect the implementation of the present invention.
  • the dual-gate driven laterally arranged pixel structure includes a double-gate driven laterally arranged pixel structure, wherein each data line is electrically connected to the sources of the two thin film transistors respectively;
  • the gates of the two thin film transistors electrically connected to one data line are electrically connected to different gate lines, respectively.
  • the pixel structure provided by the embodiment of the present invention is the same as the gate line and the data line required for the vertical arrangement of the pixels of the existing dual gate drive, so that the number of the source driver chip and the gate driver chip is also Similarly, the driving time and driving mode of each gate line can be the same, and the display panel size can also be the same, so the production process of the pixel structure with the longitudinal arrangement of the existing double gate driving is utilized.
  • the double-gate driven laterally arranged pixel structure provided by the embodiment of the present invention can be produced.
  • the present invention further provides a display panel, including: a first substrate, a second substrate, and a liquid crystal layer between the first substrate and the second substrate, according to the above-described dual gate driving laterally arranged pixel structure provided by the present invention,
  • the first substrate is provided with a horizontally arranged pixel structure of the double gate drive.
  • the first substrate may be a TFT substrate; the second substrate may be a color filter (CF) substrate.

Abstract

一种双栅极驱动的横向排列的像素结构及显示面板，其中双栅极驱动的横向排列的像素结构包括：水平相邻的两个主像素区，每个主像素区包括垂直相邻的三个次像素区（P1，P2，P3；P4，P5，P6）；六个薄膜晶体管（T1，T2，T3，T4，T5，T6），分别设置于对应的次像素区（Ρ1，Ρ2，Ρ3，Ρ4，Ρ5，Ρ6）内；两条栅极线（G1，G2）和三条数据线（D1，D2，D3）；其中，每条数据线（D1，D2，D3）分别与两个薄膜晶体管（T1，T2，T3，T4，T5，T6）的源级电连接，不同的数据线（D1，D2，D3）所电连接的薄膜晶体管（T1，T2，T3，T4，T5，T6）不同；与同一条数据线（D1，D2，D3）电连接的两个薄膜晶体管（T1，T2，T3，T4，T5，T6）的栅极分别与不同的栅极线（G1，G2）电连接。使用该方案，能够使当分辨率比较高时普通的TFT也可以达到驱动要求，且利用现有双栅极驱动纵向排列像素结构的生产工艺就可以生产出本发明提供的像素结构。

Description

双栅极驱动的横向排列的像素结构及显示面板 本申请要求于 2011 年 8 月 12 日提交中国专利局、 申请号为 201110231785.X,发明名称为"双栅极驱动的横向排列的像素结构及显示面 板"的中国专利申请的优先权， 其全部内容通过引用结合在本申请中。 技术领域
本发明涉及显示技术领域， 尤其是涉及一种双栅极驱动的横向排列的 像素结构及显示面板。
背景技术
现有技术中， 显示面板的一个主像素区的三个子像素区的排列从左到 右分别为 R (红）， G (绿）， B (蓝）， 其中， 每个主像素区为正方形或者 圓形，每个子像素区为长方形，且每个子像素区的短边与栅极线基本并行， 如图 1所示， 其中， 分辨率为 mxn, Gl , G2, G3 Gm-2, Gm-1 , Gm 为 m条栅极线， Dl , D2, D3 D3n-3 , D3n-2, D3n-1 , D3n为 3n条数 据线， 通常这种子像素区的排列方式称为纵向排列。
平板显示器的像素结构根据驱动模式的不同， 主要可区分为单栅极 ( single-gate )驱动的像素排列方式， 双栅极 ( dual-gate )驱动的像素排列 方式， 三栅极（tri-gate )驱动的像素排列方式， 其中， 单栅极驱动的像素 排列方式是三个颜色子像素区一起被单个栅极驱动； 双栅极驱动的像素排 列方式是三个颜色子像素区一起被两个栅极驱动； 三栅极驱动的像素排列 方式是三个颜色子像素区分别被三个栅极驱动。
通常， 在 3D显示中， 为了让人的左右眼看到不同的图像， 置于显示 面板前的光栅格子需要纵向排列， 其中， 一个光栅格子的大小与一个主像 素区的大小相近； 由于光栅格子所在的玻璃板与显示面板组装时的对位误 差， 导致光栅格子可能会遮挡住某个颜色， 比如遮挡了红色子像素区的部 分面积， 从而造成严重的颜色偏离和色差。 为了解决这个问题， 现有技术 提供了横向排列方式， 即将各颜色子像素区横向排列， 这样即使光栅格子 所在的玻璃板与显示面板组装时有对位误差， 三个颜色的子像素区都会被 挡住相同的面积， 虽然每个子像素区的透光量有所下降， 但是三个子像素 区所形成的颜色不会有偏移， 目前的像素横向排列方式包括以下几种： 单 栅极驱动的竖屏横用的像素横向排列方式、 双栅极驱动的像素横向排列方 式和三栅极驱动的像素横向排列方式。
单栅极驱动的竖屏横用的像素横向排列方式的原理是将分辨率为 mxn 的屏横过来变成分辨率为 n xm的屏来使用， 这种排列方式需要驱动电路 中加入緩存器将显示信号进行横竖的转化， 这会大大增加系统的成本， 所 以这种排列方式很少得到应用。
三栅极驱动的像素横向排列方式与单栅极驱动的竖屏横用的像素横向 排列方式相比， 其栅极线数目是单栅极驱动的竖屏横用的像素横向排列方 式的三倍， 而数据线数目缩减为单栅极驱动的竖屏横用的像素横向排列方 式的三分之一， 因此采用该排列方式的显示面板使用较多的栅极驱动芯片 与较少的源极驱动芯片。 由于栅极线数目是单栅极驱动的竖屏横用的像素 横向排列方式的三倍， 每条栅极线驱动时间缩短为单栅极驱动的竖屏横用 的像素横向排列方式的三分之一， 当分辨率比较高时普通的薄膜晶体管 ( Thin Film Transistor, TFT )制程很难达到驱动要求。 发明内容
本发明实施例提供一种双栅极驱动的横向排列的像素结构及显示面 板。
有鉴于此， 本发明实施例提供：
一种双栅极驱动的横向排列的像素结构， 包括：
水平相邻的两个主像素区， 其中， 每个主像素区分别包括垂直相邻的 三个次像素区；
六个薄膜晶体管， 分别设置于对应的次像素区内；
两条栅极线和三条数据线；
其中， 每条数据线分别与两个薄膜晶体管的源极电连接， 其中， 不同 的数据线所电连接的薄膜晶体管不同； 与同一条数据线电连接的两个薄膜 晶体管的栅极分别与不同的栅极线电连接。 一种显示面板， 包括： 第一基板、 第二基板和位于第一基板和第二基 板之间的液晶层， 其中， 所述第一基板上设置有上述双栅极驱动的横向排 列的像素结构。
一种双栅极驱动的横向排列的驱动方法， 适用于上述双栅极驱动的横 向排列的像素结构， 其包括：
在第一时刻， 两条栅极线中的第一栅极线为高电平， 两条栅极线中的 第二栅极线为低电平， 与所述第一栅极线电连接的薄膜晶体管打开； 三条 数据线分别为与自己电连接的薄膜晶体管供电；
在第二时刻， 所述第二栅极线为高电平， 所述第一栅极线为低电平， 与所述第二栅极线电连接的薄膜晶体管打开， 三条数据线分别为与自己电 连接的薄膜晶体管供电。
本发明实施例提供的双栅极驱动的横向排列的像素结构包括双栅极驱 动的横向排列的像素结构， 其中， 每条数据线分别与两个薄膜晶体管的源 极电连接； 与同一条数据线电连接的两个薄膜晶体管的栅极分别与不同的 栅极线电连接。 采用这种像素结构， 对于分辨率为 mxn的屏， 其需要的栅 极线为 2m条， 其需要的数据线为 3n/2条， 这样，每条栅极线驱动时间缩 短为单栅极驱动的竖屏横用的像素横向排列方式的二分之一， 当分辨率比 较高时普通的 TFT制程也可以达到驱动要求。
附图说明
为了更清楚地说明本发明实施例中的技术方案， 下面将对实施例描述 中所需要使用的附图作筒单地介绍， 显而易见地， 下面描述中的附图仅仅 是本发明的一些实施例， 对于本领域普通技术人员来讲， 在不付出创造性 劳动的前提下， 还可以根据这些附图获得其他的附图。
图 1是现有技术提供的像素纵向排列的示意图；
图 2是本发明实施例提供的一种双栅极驱动的横向排列的像素结构示 意图；
图 3是本发明实施例提供的基于图 2的像素结构具体示意图； 图 4是本发明实施例提供的采用双栅极驱动的横向排列的像素结构的 一种驱动方式示意图；
图 5是本发明实施例提供的采用双栅极驱动的横向排列的像素结构的 另一种驱动方式示意图；
图 6是本发明实施例提供的采用双栅极驱动的横向排列的像素结构的 又一种驱动方式示意图；
图 7是本发明实施例提供的另一种双栅极驱动的横向排列的像素结构 示意图；
图 8是本发明实施例提供的又一种双栅极驱动的横向排列的像素结构 示意图；
图 9是本发明实施例提供的又一种双栅极驱动的横向排列的像素结构 示意图；
图 10是本发明实施例提供的又一种双栅极驱动的横向排列的像素结 构示意图；
图 11 是本发明实施例提供的又一种双栅极驱动的横向排列的像素结 构示意图；
图 12是本发明实施例提供的又一种双栅极驱动的横向排列的像素结 构示意图；
图 13 是本发明实施例提供的又一种双栅极驱动的横向排列的像素结 构示意图。
具体实施方式
下面将结合本发明实施例中的附图， 对本发明实施例中的技术方案进 行清楚、 完整地描述， 显然， 所描述的实施例仅仅是本发明一部分实施例， 而不是全部的实施例。 基于本发明中的实施例， 本领域普通技术人员在没 有作出创造性劳动前提下所获得的所有其他实施例， 都属于本发明保护的 范围。
本发明实施例提供一种双栅极驱动的横向排列的像素结构， 其包括： 多个像素单元， 所述像素单元包括：
两条栅极线和三条数据线； 其中， 两条栅极线包括： 第一栅极线和第 二栅极线， 三条数据线包括： 顺序排列的第一数据线、 第二数据线和第三 数据线； 其中， 两条栅极线设置于基板上并沿着第一方向平行排列； 三条 数据线设置于基板上并沿着第二方向平行排列； 两条栅极线与三条数据线 交叉， 在一种具体的实施方式中， 第一方向与第二方向垂直；
水平相邻的两个主像素区， 其中， 每个主像素区分别包括垂直相邻的 三个次像素区； 三个次像素区分别为 R (红）， G (绿）和 B (蓝）； 每个次 像素的长边与第一方向基本平行，每个次像素的短边与第二方向基本平行。
六个薄膜晶体管， 分别设置于对应的次像素区内， 即每个次像素区内 有一个薄膜晶体管， 每个薄膜晶体管包括源极、 漏极和栅极；
其中， 每条数据线分别与两个薄膜晶体管的源极电连接， 使三条数据 线与六个薄膜晶体管的源极电连接， 其中， 不同的数据线所电连接的薄膜 晶体管不同， 即第一数据线所电连接的薄膜晶体管、 与第二数据线所电连 接的薄膜晶体管、 与第三数据线所电连接的薄膜晶体管完全不同， 这样， 就可以使三条数据线与六个薄膜晶体管的源极电连接； 与同一条数据线电 连接的两个薄膜晶体管的栅极分别与不同的栅极线电连接。
该像素结构还可以包括： 像素电极和与像素电极部分重迭构成存储电 容的公共电极线， 其中， 像素电极覆盖在对应的次像素区的透光区上， 每 个像素电极分别与对应的薄膜晶体管的漏极电连接； 具体的可以包括： 两 条公共电极线， 即第一公共电极线和第二公共电极线， 其中， 覆盖在第一 主像素区内次像素区上的像素电极与所述第一公共电极线交叠形成三个存 储电容； 覆盖在第二主像素区内次像素区上的像素电极与所述第二公共电 极线交叠形成三个存储电容， 即第一公共电极线和第二公共电极线分别与 数据线平行， 两条公共电极线形成六个存储电容； 或者， 包括三条公共电 极线， 即第一公共电极线、 第二公共电极线和第三公共电极线， 这三条公 共电极线分别平行于栅极线， 每条公共电极线分别与第一主像素区和第二 主像素区中各一个次像素区上的像素电极交叠形成存储电容， 即每条公共 电极线与两个不同主像素区的像素电极交叠形成两个存储电容， 三条公共 电极线形成六个存储电容。
本发明实施例提供的双栅极驱动的横向排列的像素结构包括双栅极驱 动的横向排列的像素结构， 其中， 每条数据线分别与两个薄膜晶体管的源 极电连接； 与同一条数据线电连接的两个薄膜晶体管的栅极分别与不同的 栅极线电连接。 采用这种像素结构， 对于分辨率为 mxn的屏， n为水平分 辨率， m为垂直分辨率，其需要的栅极线为 2m条，其需要的数据线为 3n/2 条， 这样，每条栅极线驱动时间缩短为单栅极驱动的竖屏横用的像素横向 排列方式的二分之一，当分辨率比较高时普通的 TFT也可以达到驱动要求， 适于广泛应用。 进一步的， 本发明实施例提供的像素结构与现有的双栅极 驱动的像素纵向排列方式所需要的栅极线和数据线相同， 这样， 源极驱动 芯片、 栅极驱动芯片的个数也相同， 每条栅极线的驱动时间和驱动方式也 可以相同， 显示面板尺寸也可以相同， 所以利用现有的双栅极驱动的纵向 的横向排列的像素结构。
为了使本发明实施例提供的技术方案更加清楚， 如下实施例对本发明 上述技术方案进行详细描述：
本发明实施例提供一种双栅极驱动的横向排列的像素结构， 具体结构 可如图 2所示， 其包括： 多个像素单元， 每个像素单元包括：
两条栅极线， 即第一栅极线 G1和第二栅极线 G2; 两条栅极线设置于 基板上并沿着第一方向平行排列；
三条数据线， 即顺序排列的第一数据线 D1、 第二数据线 D2和第三数 据线 D3, 三条数据线设置于基板上并沿着第二方向平行排列； 第二方向基 本垂直于第一方向。
两个主像素区， 即第一主像素区和第二主像素区， 其中， 第一主像素 区分别包括第一次像素区 L1 , 第二次像素区 L2和第三次像素区 L3; 第二 主像素区分别包括第四次像素区 L4,第五次像素区 L5和第六次像素区 L6。 其中， Pl、 P2、 P3、 P4、 P5、 P6分别为第一次像素区 Ll、 第二次像素区 L2、 第三次像素区 L3、 第四次像素区 L4、 第五次像素区 L5和第六次像素 区 L6 的透光区， 每个次像素区的长边与第一方向基本平行， 每个次像素 区的短边与第二方向基本平行， 其中， 两个主像素区优选的包括两个红色 次像素区、 两个绿色次像素区和两个蓝色次像素， 其中可以有多重组合方 式； 两个主像素区也可以包括任意种色彩次像素区的排列组合方式。
六个薄膜晶体管， 分别设置于对应的次像素区内， 即每个次像素区内 有一个薄膜晶体管， 如第一次像素区的薄膜晶体管 T1 , 第二次像素区的薄 膜晶体管 T2, 第三次像素区的薄膜晶体管 T3, 第四次像素区的薄膜晶体 管 T4, 第五次像素区的薄膜晶体管 T5, 第六次像素区的薄膜晶体管 T6, 每个薄膜晶体管包括源极、 漏极和栅极；
六个像素电极（图中未示出 ),每个像素电极覆盖在对应的次像素区的 透光区上， 分别与对应的薄膜晶体管的漏极电连接；
两条公共电极线（图中未示出）， 即第一公共电极线 C1和第二公共电 极线 C2, 其中， 与 Tl、 Τ2、 Τ3的漏极电连接的像素电极（即覆盖在 LI、 L2、 L3上的像素电极）分别与第一公共电极线交叠形成三个存储电容； 与 T4、 Τ5、 Τ6的漏极电连接的像素电极（即覆盖在 L4、 L5、 L6上的像素电 极）分别与第二公共电极线交叠形成三个存储电容， 其中， 第一公共电极 线、 第二公共电极线分别与数据线平行。
其中， 如图 2所示， 该实施例中， 第一主像素区位于第一数据线与第 二数据线之间； 第二主像素区位于第二数据线与第三数据线之间； 两条栅 极线和三条数据线交叉形成第一封闭区和第二封闭区； 第二次像素区 L2、 第五次像素区 L 5分别位于第一封闭区和第二封闭区内。
其中， 第一数据线 D1与薄膜晶体管 T1和薄膜晶体管 T2的源极电连 接； 薄膜晶体管 T1的栅极与第一栅极线 G1电连接； 薄膜晶体管 T2的栅 极与第二栅极线 G2电连接； 第二数据线 D2与薄膜晶体管 T3和薄膜晶体 管 T4的源极电连接； 薄膜晶体管 T3的栅极与第二栅极线 G2电连接； 薄 膜晶体管 T4的栅极与第一栅极线 G1电连接； 第三数据线 D3与薄膜晶体 管 T5和薄膜晶体管 T6的源极电连接； 薄膜晶体管 T5的栅极与第一栅极 线 G1电连接； 薄膜晶体管 T6的栅极与第二栅极线 G2电连接。
需要说明的是， 次像素区可以为矩形区域， 具体包括： 第一边和第二 边， 第一栅极线 G1和第二栅极线 G2与次像素区的第一边平行， 且分别设 置于每个主像素区内的三个次像素区之间或者设置于各次像素区之外； 第 一数据线 Dl、第二数据线 D2和第三数据线 D3与次像素区的第二边平行， 且分别设置于所述像素单元的两个主像素区之间或者设置于两个主像素区 之外。 在一种优选方式中， 第一边为矩形区域的长边， 第二边为矩形区域 的短边， 在另一种实施方式中， 第一边为矩形区域的短边， 第二边为矩形 区域的长边。 其中， 两条栅极线、 三条数据线的具体设置方式可参见后续 图 7至图 13所对应部分的详细描述。
本发明实施例以两个主像素区为一个重复单位， 每个主像素区包括三 个次像素区 （优选的一种组合为红色次像素区 R、 绿色次像素区 G、 蓝色 次像素区 B ), 也就是最小的一个重复单位包含 6个次像素区。 一个最小重 复单位中包括两个栅极线， 三个数据线， 六个薄膜晶体管， 且每条数据线 驱动两个次像素区， 两个次像素区分别由不同的栅极线控制， 采用这种像 素结构， 对于分辨率为 mxn的屏， 其需要的栅极线为 2m条， 其需要的数 据线为 3n/2条， 这样， 每条栅极线驱动时间缩短为单栅极驱动的竖屏横 用的像素横向排列方式的二分之一， 当分辨率比较高时普通的 TFT也可以 达到驱动要求， 适于广泛应用。 进一步的， 本发明实施例提供的像素结构 与现有的双栅极驱动的像素纵向排列方式所需要的栅极线和数据线相同， 这样， 源极驱动芯片、 栅极驱动芯片的个数也相同， 每条栅极线的驱动时 间和驱动方式也可以相同， 显示面板尺寸也可以相同， 所以利用现有的双 栅极驱动的纵向排列的像素结构的生产工艺就可以生产出本发明实施例提 供的双栅极驱动的横向排列的像素结构， 且本发明实施例提供的双栅极驱 动的横向排列的像素结构更适合于 3D显示。
如下描述一种双栅极驱动的横向排列的驱动方法， 该方法适用于上述 双栅极驱动的横向排列的像素结构， 其包括：
在第一时刻， 两条栅极线中的第一栅极线为高电平， 两条栅极线中的 第二栅极线为低电平， 与第一栅极线电连接的薄膜晶体管打开， 三条数据 线分别为与自己电连接的薄膜晶体管供电；
在第二时刻， 所述第二栅极线为高电平， 所述第一栅极线为低电平， 与所述第二栅极线电连接的薄膜晶体管打开， 三条数据线分别为与自己电 连接的薄膜晶体管供电。
即对于图 2所示的双栅极驱动的横向排列的像素结构，在 tl时刻， G1 为高电平， 薄膜晶体管 Tl、 Τ4和 Τ5同时打开，此时， D1给 L1输送数据， D2给 L4输送数据， D3给 L5输送数据。 接着在 t2时刻， G1变为低电平， G2为高电平， Tl、 Τ4、 Τ5同时关闭， 薄膜晶体管 Τ2、 Τ3、 Τ6同时打开， Dl给 L2输送数据， D2给 L3输送数据， D3给 L6输送数据， 这样就实现 了对一个像素单元的驱动。
下面以常白液晶显示屏（ TN normally white )模式为例， 描述单色显 示的驱动方法， 如图 3所示， 假定第一像素区 L1为绿色次像素区 G1 , 第 二像素区 L2为红色次像素区 R1 , 第三像素区 L3为蓝色次像素区 B1 , 第 四像素区 L4为红色次像素区 R2, 第五像素区 L5为蓝色次像素区 B2, 第 六像素区 L6为绿色次像素区 G2。 其中， 数据线 D提供像素电压 S, 像素 电压 S相对于参考电压 COM为正的高电平或者负的高电平时， 次像素区 处于暗态， 像素电压 S相对于参考电压 COM为正的低电平或者负的低电 平时， 次像素区处于亮态， 其中， 像素电压 S为数据线为薄膜晶体管所输 送的数据的电平， 其中， 像素电压 S相对于参考电压 COM为正的低电平 或者负的低电平表示像素电压 S与参考电压 COM接近。
如下描述适用于上述像素结构的红色显示的驱动方法：
如图 4所示， tl时刻 G1为高电平， 其他扫描线为低电平， Gl、 R2、 B2的薄膜晶体管打开， Sl、 S2、 S3分别给 Gl、 R2、 B2输送数据， 图中 的 Sl、 S2和 S3分别为数据线 Dl、 D2和 D3所输送的数据的电平 （也称 为像素电压）， 假定 S1为正的高电平， S2为负的低电平， S3为正的高电 平， 所以 G1暗， R2亮， B2暗。 t2时刻 G2为高电平， 其他扫描线为低电 平， Rl、 Bl、 G2的晶体管打开， SI , S2, S3分别给 Rl、 Bl、 G2输送数 据， S1 为负的氐电平， S2为正的高电平， S3为负的高电平， R1 亮， B1 暗， G2暗。 这样在一个重复单元内只有红色的次像素亮， 其他的次像素都 为暗，下一时刻两个主像素内的每条数据线的信号重复 tl和 t2时候的波形 使该整个重复单元一直显示红色。
如下描述适用于上述像素结构的绿色显示的驱动方法：
如图 5所示， tl时刻 G1为高电平， 其他扫描线为低电平， Gl、 R2、 B2的薄膜晶体管打开， Sl、 S2、 S3分别给 Gl、 R2、 B2传输数据， SI为 正的氏电平， S2为负的高电平， S3为正的高电平， G1亮， R2暗， B2暗。 t2时刻 G2为高电平， 其他扫描线为低电平， Rl、 Bl、 G2的薄膜晶体管打 开， SI , S2, S3分别给 Rl、 Bl、 G2传输数据， S1为负的高电平， S2为 正的高电平， S3为负的低电平， R1暗， B1暗， G2亮。 这样在一个重复 单元内只有绿色的次像素亮， 其他的次像素都为暗， 下一时刻两个主像素 内的每条数据线的信号重复 tl和 t2时候的波形使该整个重复单元一直显示 绿色。
如下描述适用于上述像素结构的蓝色显示的驱动方法：
如图 6所示， tl时刻 G1为高电平， 其他扫描线为低电平， Gl、 R2、 B2的薄膜晶体管打开， Sl、 S2、 S3分别给 Gl、 R2、 B2传输数据， SI为 正的高电平， S2为负的高电平， S3为正的低电平， G1暗， R2暗， B2亮。 t2时刻 G2为高电平， 其他扫描线为低电平， Rl、 Bl、 G2的薄膜晶体管打 开， SI , S2, S3分别给 Rl、 Bl、 G2传输数据， S1为负的高电平， S2为 正的低电平， S3为负的高电平， R1暗， B1 亮， G2暗。 这样在一个重复 单元内只有蓝色的次像素亮， 其他的次像素都为暗， 下一时刻两个主像素 内的每条数据线的信号重复 tl和 t2时候的波形使该整个重复单元一直显示 蓝色。
以上驱动方法可以单独控制每个次像素区的颜色和亮度， 实现显示红 色、 绿色或者蓝色， 可见采用上述驱动方法驱动本发明实施例提供的双栅 极驱动的横向排列的像素结构可以控制整个屏幕显示用户想要的颜色和图 案。
图 7示出了本发明实施例提供的一种双栅极驱动的横向排列的像素结 构， 与图 2所示实施例不同之处在于： 第一数据线 D1与薄膜晶体管 T2和 薄膜晶体管 T3的源极电连接； 薄膜晶体管 T2的栅极与第一栅极线 G1电 连接； 薄膜晶体管 T3的栅极与第二栅极线 G2电连接； 第二数据线 D2与 薄膜晶体管 T1和薄膜晶体管 T6的源极电连接； 薄膜晶体管 T1的栅极与 第一栅极线 G1电连接； 薄膜晶体管 T6的栅极与第二栅极线 G2电连接； 第三数据线 D3与薄膜晶体管 T4和薄膜晶体管 T5的源极电连接； 薄膜晶 体管 T4的栅极与第一栅极线 G1电连接； 薄膜晶体管 T5的栅极与第二栅 极线 G2电连接。
图 8示出了本发明实施例提供的另一种双栅极驱动的横向排列的像素 结构， 与图 2所示实施例不同之处在于： 第一数据线 D1与薄膜晶体管 T1 和薄膜晶体管 T3的源极电连接； 薄膜晶体管 T1的栅极与第一栅极线 G1 电连接； 薄膜晶体管 T3的栅极与第二栅极线 G2电连接； 第二数据线 D2 与薄膜晶体管 T2和薄膜晶体管 T5的源极电连接； 薄膜晶体管 T2的栅极 与第一栅极线 G1电连接；薄膜晶体管 T5的栅极与第二栅极线 G2电连接； 第三数据线 D3与薄膜晶体管 T4和薄膜晶体管 T6的源极电连接； 薄膜晶 体管 T4的栅极与第一栅极线 G1电连接； 薄膜晶体管 T6的栅极与第二栅 极线 G2电连接。
图 9示出了本发明实施例提供的另一种双栅极驱动的横向排列的像素 结构， 与图 2所示实施例不同之处在于： 第一数据线 D1与薄膜晶体管 T1 和薄膜晶体管 T3的源极电连接； 薄膜晶体管 T1的栅极与第一栅极线 G1 电连接； 薄膜晶体管 T3的栅极与第二栅极线 G2电连接； 第二数据线 D2 与薄膜晶体管 T2和薄膜晶体管 T5的源极电连接； 薄膜晶体管 T5的栅极 与第一栅极线 G1电连接；薄膜晶体管 T2的栅极与第二栅极线 G2电连接； 第三数据线 D3与薄膜晶体管 T4和薄膜晶体管 T6的源极电连接； 薄膜晶 体管 T4的栅极与第一栅极线 G1电连接； 薄膜晶体管 T6的栅极与第二栅 极线 G2电连接。
图 10 示出了本发明实施例提供的另一种双栅极驱动的横向排列的像 素结构， 与图 2所示实施例不同之处在于： 第一主像素区位于第一数据线 与第二数据线之间； 第二主像素区位于第二数据线与第三数据线之间； 两 条栅极线和三条数据线交叉形成第一封闭区和第二封闭区； 第二次像素区 L2和第三次像素区 L3位于第一封闭区内， 第五次像素区 L5和第六次像 素区 L6位于第二封闭区内。 具体的， 第一数据线 D1与薄膜晶体管 T1和 薄膜晶体管 T2的源极电连接； 薄膜晶体管 T1的栅极与第一栅极线 G1电 连接； 薄膜晶体管 T2的栅极与第二栅极线 G2电连接； 第二数据线 D2与 薄膜晶体管 T3和薄膜晶体管 T4的源极电连接； 薄膜晶体管 T3的栅极与 第二栅极线 G2电连接； 薄膜晶体管 T4的栅极与第一栅极线 G1电连接； 第三数据线 D3与薄膜晶体管 T5和薄膜晶体管 T6的源极电连接； 薄膜晶 体管 T5的栅极与第一栅极线 G1电连接； 薄膜晶体管 T6的栅极与第二栅 极线 G2电连接。
图 11 示出了本发明实施例提供的另一种双栅极驱动的横向排列的像 素结构， 与图 2所示实施例不同之处在于： 第一主像素区位于第一数据线 与第二数据线之间； 第二主像素区位于第二数据线与第三数据线之间； 两 条栅极线和三条数据线交叉形成第一封闭区和第二封闭区； 第一次像素区 Ll、 第二次像素区 L2和第三次像素区 L3位于第一封闭区内， 第四次像素 区 L4、 第五次像素区 L5和第六次像素区 L6位于第二封闭区内。 具体的， 第一数据线 D1与薄膜晶体管 T1和薄膜晶体管 T2的源极电连接； 薄膜晶 体管 T1的栅极与第一栅极线 G1电连接； 薄膜晶体管 T2的栅极与第二栅 极线 G2电连接； 第二数据线 D2与薄膜晶体管 T3和薄膜晶体管 T4的源 极电连接； 薄膜晶体管 T4 的栅极与第一栅极线 G1 电连接； 薄膜晶体管 T3的栅极与第二栅极线 G2电连接；第三数据线 D3与薄膜晶体管 T5和薄 膜晶体管 T6的源极电连接； 薄膜晶体管 T5的栅极与第一栅极线 G1电连 接； 薄膜晶体管 T6的栅极与第二栅极线 G2电连接。
图 12 示出了本发明实施例提供的另一种双栅极驱动的横向排列的像 素结构， 与图 2所示实施例不同之处在于： 第一主像素区位于第一数据线 的外侧，其中， 第一数据线的外侧为第一数据线的背向第二数据线的一侧； 第二主像素区位于第二数据线与第三数据线之间，具体的， 第一数据线 D1 与薄膜晶体管 T1和薄膜晶体管 T2的源极电连接； 薄膜晶体管 T1的栅极 与第一栅极线 G1电连接；薄膜晶体管 T2的栅极与第二栅极线 G2电连接； 第二数据线 D2与薄膜晶体管 T3和薄膜晶体管 T4的源极电连接； 薄膜晶 体管 T4的栅极与第一栅极线 G1电连接； 薄膜晶体管 T3的栅极与第二栅 极线 G2电连接； 第三数据线 D3与薄膜晶体管 T5和薄膜晶体管 T6的源 极电连接； 薄膜晶体管 T5 的栅极与第一栅极线 G1 电连接； 薄膜晶体管 T6的栅极与第二栅极线 G2电连接。
图 13 示出了本发明实施例提供的另一种双栅极驱动的横向排列的像 素结构， 与图 2所示实施例不同之处在于： 第一主像素区位于第一数据线 的外侧，其中， 第一数据线的外侧为第一数据线的背向第二数据线的一侧； 第二主像素区位于第三数据线的外侧， 其中， 第三数据线的外侧为第三数 据线的背向第二数据线的一侧； 具体的， 第一数据线 D1与薄膜晶体管 T1 和薄膜晶体管 T2的源极电连接； 薄膜晶体管 T1的栅极与第一栅极线 G1 电连接； 薄膜晶体管 T2的栅极与第二栅极线 G2电连接； 第二数据线 D2 与薄膜晶体管 T3和薄膜晶体管 T4的源极电连接； 薄膜晶体管 T4的栅极 与第一栅极线 G1电连接；薄膜晶体管 T3的栅极与第二栅极线 G2电连接； 第三数据线 D3与薄膜晶体管 T5和薄膜晶体管 T6的源极电连接； 薄膜晶 体管 T5的栅极与第一栅极线 G1电连接； 薄膜晶体管 T6的栅极与第二栅 极线 G2电连接。
需要说明的是， 上述各实施例提供的双栅极驱动的横向排列的像素结 构中的次像素区的可以为长方形区域， 此时， 长方形区域的长边与栅极线 平行， 长方形区域的短边与数据线平行； 或者， 次像素区为非长方形区域， 不影响本发明的实现。
本发明所描述的实例中栅极线、 数据线、 第一主像素区、 第二主像素 区间的位置变换及薄膜晶体管的连接关系仅为最佳实例， 对于本领域普通 技术人员来讲， 在不付出创造性劳动的前提下所获得的所有其他实施例均 属于本发明的保护范围。
本发明上述各实施例提供的双栅极驱动的横向排列的像素结构包括双 栅极驱动的横向排列的像素结构， 其中， 每条数据线分别与两个薄膜晶体 管的源极电连接； 与同一条数据线电连接的两个薄膜晶体管的栅极分别与 不同的栅极线电连接。 采用这种像素结构， 对于分辨率为 mxn的屏， 其需 要的栅极线为 2m条， 其需要的数据线为 3n/2条， 这样， 每条栅极线驱动 时间缩短为单栅极驱动的竖屏横用的像素横向排列方式的二分之一， 当分 辨率比较高时普通的 TFT也可以达到驱动要求，适于广泛应用。进一步的， 本发明实施例提供的像素结构与现有的双栅极驱动的像素纵向排列方式所 需要的栅极线和数据线相同， 这样， 源极驱动芯片、 栅极驱动芯片的个数 也相同， 每条栅极线的驱动时间和驱动方式也可以相同， 显示面板尺寸也 可以相同， 所以利用现有的双栅极驱动的纵向排列的像素结构的生产工艺 就可以生产出本发明实施例提供的双栅极驱动的横向排列的像素结构。 基于本发明提供的上述双栅极驱动的横向排列的像素结构， 本发明还 提供一种显示面板， 包括： 第一基板、 第二基板和位于第一基板和第二基 板之间的液晶层， 其中， 所述第一基板上设置有上述双栅极驱动的横向排 列的像素结构。 其中， 第一基板可以是 TFT基板； 第二基板可以是彩色滤 光片 （Color filter, CF )基板。
以上对本发明实施例所提供的双栅极驱动的横向排列的像素结构及显 式进行了阐述， 以上实施例的说明只是用于帮助理解本发明的方法及其核 心思想； 同时， 对于本领域的一般技术人员， 依据本发明的思想， 在具体 实施方式及应用范围上均会有改变之处， 综上所述， 本说明书内容不应理 解为对本发明的限制。

Claims

权 利 要 求
1、 一种双栅极驱动的横向排列的像素结构， 其特征在于， 包括： 水平相邻的两个主像素区， 其中， 每个主像素区分别包括垂直相邻的 三个次像素区；
六个薄膜晶体管， 分别设置于对应的次像素区内；
两条栅极线和三条数据线；
其中， 每条数据线分别与两个薄膜晶体管的源极电连接， 其中， 不同 的数据线所电连接的薄膜晶体管不同； 与同一条数据线电连接的两个薄膜 晶体管的栅极分别与不同的栅极线电连接。
2、根据权利要求 1所述的双栅极驱动的横向排列的像素结构，其特征 在于， 次像素区为长方形区域， 所述长方形区域的长边与栅极线平行。
3、根据权利要求 1所述的双栅极驱动的横向排列的像素结构，其特征 在于，
两条栅极线包括： 第一栅极线和第二栅极线； 三条数据线包括： 顺序 排列的第一数据线、 第二数据线和第三数据线；
次像素区包括： 第一边和第二边；
所述第一栅极线和第二栅极线与次像素区的第一边平行， 且分别设置 于每个主像素区内的三个次像素区之间或者设置于各次像素区之外。
4、根据权利要求 1所述的双栅极驱动的横向排列的像素结构，其特征 在于，
两条栅极线包括： 第一栅极线和第二栅极线； 三条数据线包括： 顺序 排列的第一数据线、 第二数据线和第三数据线；
次像素区包括： 第一边和第二边；
所述第一数据线、第二数据线和第三数据线与次像素区的第二边平行， 且分别设置于所述像素单元的两个主像素区之间或者设置于两个主像素区 之外。
5、 根据权利要求 3或者 4所述的双栅极驱动的横向排列的像素结构， 其特征在于，
水平相邻的两个主像素区包括： 第一主像素区和第二主像素区； 第一主像素区位于第一数据线与第二数据线之间；
第二主像素区位于第二数据线与第三数据线之间；
两条栅极线和三条数据线交叉形成第一封闭区和第二封闭区； 其中，
第一主像素区有一个次像素区位于第一封闭区内， 第二主像素区有一 个次像素区位于第二封闭区内；
或者，
第一主像素区中垂直相邻的二个次像素区位于第一封闭区内， 第二主 像素区中垂直相邻的二个次像素区位于第二封闭区内；
或者，
第一主像素区中垂直相邻的三个次像素区位于第一封闭区内， 第二主 像素区中垂直相邻的三个次像素区位于第二封闭区内。
6、 根据权利要求 3或者 4所述的双栅极驱动的横向排列的像素结构， 其特征在于，
水平相邻的两个主像素区包括： 第一主像素区和第二主像素区； 第二主像素区位于第二数据线与第三数据线之间；
第一主像素区位于第一数据线的外侧， 所述第一数据线的外侧是第一 数据线背向第二数据线的一侧。
7、 根据权利要求 3或者 4所述的双栅极驱动的横向排列的像素结构， 其特征在于，
水平相邻的两个主像素区包括： 第一主像素区和第二主像素区； 第一主像素区位于第一数据线的外侧， 所述第一数据线的外侧是第一 数据线背向第二数据线的一侧；
第二主像素区位于第三数据线的外侧， 所述第三数据线的外侧是第三 数据线背向第二数据线的一侧。
8、根据权利要求 1至 4任一项所述的双栅极驱动的横向排列的像素结 构， 其特征在于，
还包括： 像素电极， 和与像素电极部分重迭构成存储电容的公共电极 线， 其中， 像素电极覆盖在次像素区的透光区上。
9、根据权利要求 8所述的双栅极驱动的横向排列的像素结构，其特征 在于，
所述公共电极线包括： 分别与数据线平行的第一公共电极线和第二公 共电极线；
或者，
所述公共电极线包括： 分别与栅极线平行的第一公共电极线、 第二公 共电极线和第三公共电极线。
10、 一种显示面板， 包括： 第一基板、 第二基板和位于第一基板和第 二基板之间的液晶层， 其中， 所述第一基板上设置有权利要求 1至 9所述 的任意一个双栅极驱动的横向排列的像素结构。
11、 一种双栅极驱动的横向排列的驱动方法， 其特征在于， 适用于权 利要求 1至 9所述的任意一个双栅极驱动的横向排列的像素结构，其包括： 在第一时刻， 两条栅极线中的第一栅极线为高电平， 两条栅极线中的 第二栅极线为低电平， 与所述第一栅极线电连接的薄膜晶体管打开； 三条 数据线分别为与自己电连接的薄膜晶体管供电；
在第二时刻， 所述第二栅极线为高电平， 所述第一栅极线为低电平， 与所述第二栅极线电连接的薄膜晶体管打开， 三条数据线分别为与自己电 连接的薄膜晶体管供电。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103926766A (zh) * 2013-08-07 2014-07-16 上海中航光电子有限公司 像素阵列及液晶显示装置

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101969952B1 (ko) * 2012-06-05 2019-04-18 삼성디스플레이 주식회사 표시 장치
CN103943627B (zh) * 2013-07-30 2017-06-06 上海中航光电子有限公司 一种tft阵列基板
CN103728795A (zh) * 2013-12-26 2014-04-16 深圳市华星光电技术有限公司 一种阵列基板公共电极结构及其制造方法、阵列基板
KR20150139132A (ko) 2014-06-02 2015-12-11 삼성디스플레이 주식회사 표시 장치 및 그 구동 방법
KR20160029892A (ko) 2014-09-05 2016-03-16 삼성디스플레이 주식회사 표시 장치 및 그것의 구동 방법
US9263477B1 (en) * 2014-10-20 2016-02-16 Shenzhen China Star Optoelectronics Technology Co., Ltd. Tri-gate display panel
CN104267519B (zh) * 2014-10-22 2017-11-03 深圳市华星光电技术有限公司 Tft阵列基板
KR102255745B1 (ko) 2014-12-02 2021-05-27 삼성디스플레이 주식회사 표시 장치
KR102335113B1 (ko) * 2014-12-22 2021-12-03 삼성디스플레이 주식회사 표시 장치 및 그 구동 방법
CN104461159B (zh) * 2014-12-23 2018-10-23 上海天马微电子有限公司 阵列基板、显示面板、触控显示装置及其驱动方法
KR20160083325A (ko) 2014-12-30 2016-07-12 삼성디스플레이 주식회사 표시 장치 및 그 데이터 처리 방법
CN105047161B (zh) * 2015-08-26 2018-06-08 京东方科技集团股份有限公司 像素单元驱动装置、方法和显示装置
CN105204256B (zh) * 2015-10-29 2018-10-19 深圳市华星光电技术有限公司 一种基于数据线共用技术的阵列基板及其显示装置
KR102471113B1 (ko) * 2015-11-18 2022-11-28 삼성디스플레이 주식회사 표시장치
TWI589972B (zh) 2016-12-28 2017-07-01 友達光電股份有限公司 主動元件陣列基板及應用其之液晶面板
CN109427278B (zh) 2017-08-31 2020-07-03 昆山国显光电有限公司 显示面板及显示装置
KR102561249B1 (ko) 2018-10-10 2023-07-31 삼성디스플레이 주식회사 디스플레이 장치
CN110473489B (zh) * 2019-07-19 2023-06-27 福建华佳彩有限公司 一种双栅面板的像素排列结构
KR20220054501A (ko) * 2020-10-23 2022-05-03 삼성디스플레이 주식회사 디스플레이 장치

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101004520A (zh) * 2006-01-16 2007-07-25 三星电子株式会社 液晶显示器面板及其制造方法
CN101221337A (zh) * 2008-01-28 2008-07-16 京东方科技集团股份有限公司 液晶显示装置阵列基板及驱动方法
CN101339315A (zh) * 2004-07-15 2009-01-07 日本电气株式会社 液晶显示设备
US20090140253A1 (en) * 2007-12-03 2009-06-04 Semiconductor Energy Laboratory Co., Ltd. Tft arrangement for display device
CN101625828A (zh) * 2009-08-10 2010-01-13 友达光电股份有限公司 像素阵列

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100560401B1 (ko) * 2003-11-04 2006-03-14 엘지.필립스 엘시디 주식회사 수평 전계 인가형 박막 트랜지스터 기판 및 그 제조 방법
KR100965580B1 (ko) * 2003-08-21 2010-06-23 엘지디스플레이 주식회사 액정표시장치와 그의 구동방법
KR20070043314A (ko) * 2005-10-21 2007-04-25 삼성전자주식회사 액정 디스플레이 장치
JP5665255B2 (ja) * 2007-10-15 2015-02-04 Ｎｌｔテクノロジー株式会社 表示装置とその駆動方法、端末装置及び表示パネル
KR101547565B1 (ko) * 2008-10-08 2015-09-07 삼성디스플레이 주식회사 표시 장치 및 이의 구동 방법
CN101706633B (zh) * 2008-12-22 2011-10-26 深超光电（深圳）有限公司 液晶显示器的双闸极晶体管基板
TWI382263B (zh) * 2009-01-06 2013-01-11 Century Display Shenxhen Co Liquid crystal display of the double gate electrode crystal substrate
KR101332479B1 (ko) * 2009-08-14 2013-11-26 엘지디스플레이 주식회사 액정표시장치와 그 도트 인버젼 제어방법
KR101634744B1 (ko) * 2009-12-30 2016-07-11 삼성디스플레이 주식회사 표시 장치
CN101814278B (zh) * 2010-04-14 2013-01-09 福州华映视讯有限公司 双闸极液晶显示装置及其驱动方法
TWI431605B (zh) * 2010-11-15 2014-03-21 Au Optronics Corp 液晶顯示面板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101339315A (zh) * 2004-07-15 2009-01-07 日本电气株式会社 液晶显示设备
CN101004520A (zh) * 2006-01-16 2007-07-25 三星电子株式会社 液晶显示器面板及其制造方法
US20090140253A1 (en) * 2007-12-03 2009-06-04 Semiconductor Energy Laboratory Co., Ltd. Tft arrangement for display device
CN101221337A (zh) * 2008-01-28 2008-07-16 京东方科技集团股份有限公司 液晶显示装置阵列基板及驱动方法
CN101625828A (zh) * 2009-08-10 2010-01-13 友达光电股份有限公司 像素阵列

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103926766A (zh) * 2013-08-07 2014-07-16 上海中航光电子有限公司 像素阵列及液晶显示装置

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