WO2013013575A1 - 低压驱动电容负载的能量回收电路及其驱动方法 - Google Patents

低压驱动电容负载的能量回收电路及其驱动方法 Download PDF

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Publication number
WO2013013575A1
WO2013013575A1 PCT/CN2012/078449 CN2012078449W WO2013013575A1 WO 2013013575 A1 WO2013013575 A1 WO 2013013575A1 CN 2012078449 W CN2012078449 W CN 2012078449W WO 2013013575 A1 WO2013013575 A1 WO 2013013575A1
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Prior art keywords
switch
electrically connected
tube
node
inductor
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PCT/CN2012/078449
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English (en)
French (fr)
Inventor
陈锋
奚剑雄
Original Assignee
杭州硅星科技有限公司
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Publication of WO2013013575A1 publication Critical patent/WO2013013575A1/zh

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/34—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering
    • H02J7/345—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering using capacitors as storage or buffering devices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
    • G09G3/2965—Driving circuits for producing the waveforms applied to the driving electrodes using inductors for energy recovery

Definitions

  • the invention relates to an energy recovery circuit and a driving method thereof, in particular to an energy recovery circuit suitable for low-voltage driving capacitive load in various low-voltage environments and a driving method thereof.
  • the energy recovery circuit comprises the following components: a first switch M1 for supplying a boosted voltage VDD to the upper plate of the equivalent load capacitor CL; a second switch M2 for supplying a GND boosted voltage to the upper plate of the equivalent load capacitor CL; and a parallel storage capacitor a third switch M3 between the CST and the inductor L, a fourth switch M4; a first diode D1 and a second diode D2 for limiting the reverse current are connected in series between the third and fourth switches M3, M4; A third diode Del for reverse clamping of GND is connected to a connection point of the third switch M3 and the first diode D1, and a connection point of the fourth switch M4 and the second diode D2 is connected to the VDD The fourth diode Dc2 for positive clamping is used; the other end of the inductor L is connected to the upper plate of the equivalent load capacitance CL.
  • the working method of this technical solution is as follows (see FIG. 6):
  • the first switch M1 is implemented by a PMOS transistor, and the gate driving voltage SC1 is low level to make M1 turn on, and the high level turns M1 off;
  • the second switch M2 It is realized by NMOS transistor, its gate drive voltage SC2 is high level to make M2 turn on, low level makes M2 turn off;
  • the third switch M3 is realized by PMOS tube, and its gate drive voltage SC3 low level makes M3 lead Pass, high level makes M3 turn off;
  • fourth switch M4 is realized by NMOS tube, its gate drive voltage SC4 high level makes M4 turn on, and low level makes M4 turn off.
  • This technical solution is in one work cycle There are four working sections (see Figure 7).
  • the third switch M3 is turned on, and the first, second, and fourth switches M1, M2, and M4 are turned off, then the charge stored in the storage capacitor CST is passed through the third.
  • the switch M3 and the first diode D1 are supplied to the inductor L. Since the inductor L and the load capacitor CL form a series resonant circuit, the CL is charged with a voltage due to resonance, and the voltage VL of the upper plate can freely oscillate to VDD.
  • the current in the inductor increases from 0 to the positive direction. After reaching the peak value, the plate voltage VL oscillates to the highest point on CL, and the current in L returns to zero.
  • the current in L returns to 0, which is the end point of T1 and the starting point of T2.
  • the first switch M1 and the third switch M3 are turned on, and the second switch M2 and the fourth switch M4 are turned off.
  • the upper plate of CL is boosted to VDD via the first switch M1, and at the same time, although M3 is turned on due to the action of the first diode D1 against reverse current, no current flows through the branches of M3 and D1.
  • the first switch M1, the second switch M2, and the third switch M3 are turned off, and the fourth switch M4 is turned on.
  • the charge on the load CL is recovered via the inductor L, the second diode D2, and the fourth switch M4 by the storage capacitor CST.
  • the voltage VL on the load capacitor oscillates freely from VDD to 0, and the current in the inductor increases from 0 to the maximum point and then back to zero.
  • the second switch M2 and the fourth switch M4 are turned on, and the first switch M1 and the third switch M3 are turned off.
  • the upper plate voltage VL of CL is strengthened to GND via M1.
  • a positive on-voltage VF1 is generated across D1, in the CL During the discharge process, both ends of D2 will also generate a positive turn-on voltage VF2, which will add additional energy loss during charge and discharge.
  • the two diodes are additionally lost. Energy is negligible, but in some low-voltage environments of 3 volts, 5 volts, or even 1.8 volts, the extra energy lost by the two diodes cannot be ignored, resulting in greater energy loss.
  • the object of the present invention is to solve the above problem of the prior art energy recovery circuit which tends to have a large proportion of energy loss in low voltage applications, and to provide an energy recovery circuit suitable for a low voltage environment.
  • an energy recovery circuit for a low-voltage driving capacitive load including a load capacitor CL and a storage capacitor CST, a lower plate of the storage capacitor CST, and a lower pole of the load capacitor CL
  • the energy recovery circuit of the low-voltage driving capacitive load further includes an inductor L, a first switching transistor, a second switching transistor, and a third switching transistor, wherein the first conducting end of the first switching transistor is electrically connected to the power supply VDD Connecting, the second conductive end of the second switch is grounded, and the second conductive end of the first switch is electrically connected to the first conductive end of the second switch to the node C, the node C is electrically connected to the upper plate of the load capacitor CL, the second conductive end of the third switch is electrically connected to the first conductive end of the inductor L, and the second conductive end of the inductor L is electrically connected to the node C.
  • the first conductive end of the third switch tube is electrically connected to the upper plate of the storage capacitor CST, and the control ends of the first switch tube, the second switch tube and the third switch tube are respectively controlled by control signals .
  • the first switch tube, the second switch tube and the third switch tube can be any controllable switch tube.
  • the current flowing through the node B to the node C is in the forward current direction, and the present invention is implemented.
  • Tl, ⁇ 2, ⁇ 3 and ⁇ 4 we set the initial state of the invention to the controlled switching of the first switching tube, the controlled switching of the third switching tube, and the second switching tube.
  • the present invention starts from the T1 phase; the present invention is controlled to be turned off in the T1 phase, the second switch is controlled. A switch tube remains off, The third switch tube is controlled to be turned on; the storage capacitor CST and the inductor L and the load capacitor CL constitute an LC oscillating circuit, and the stored energy stored in the storage capacitor CST is non-destructively moved to the load capacitor CL through the LC oscillating circuit.
  • the current in the inductor L increases from 0 to the maximum forward current, and then returns to 0.
  • the switch tube the T1 interval ends; in the T2 interval, the third switch tube is controlled to be turned off, the second switch tube is kept turned off, the first switch tube is controlled to be turned on, and the power supply VDD is boosted to the load capacitor CL through the first switch tube
  • the voltage value of the upper plate of the load capacitor CL is equal to the voltage value of the power supply VDD; in the T3 interval, the first switch tube is controlled to be turned off, the second switch tube is kept turned off, and the third switch tube is controlled to be turned on.
  • load capacitance CL and electricity L and the storage capacitor CST form an LC oscillating circuit. The energy stored in the CL is transferred back to the storage capacitor CST through the LC oscillating circuit for energy recovery.
  • the current in the inductor L increases from 0 to the maximum, and then returns to 0.
  • the voltage on the storage capacitor CST is equal to the voltage on the load capacitor CL
  • the current in the inductor L reaches the reverse maximum.
  • the voltage of the inductor L reaches the lowest value of the oscillation.
  • the third switch tube is turned off, and the T3 interval ends; in the T4 interval, the third switch tube is controlled.
  • the present invention can complete the energy recovery work, and the number of components of the invention is small, the energy consumption is low, and the energy is returned. High efficiency, low pressure can be applied to a variety of environments.
  • the energy recovery circuit of the low-voltage drive capacitive load further includes a fourth switch tube, and the second conductive end of the third switch tube and the second conductive end of the fourth switch tube are electrically connected to the node B, the node B is electrically connected to the first conductive end of the inductor L, and the first conductive end of the third switch tube and the first conductive end of the fourth switch tube are electrically connected to the node A, The node A and the energy storage The upper plate of the capacitor CST is electrically connected, and the control end of the fourth switch is controlled by a control signal.
  • Such a circuit can be driven by the control signal so that the third switching tube and the fourth switching tube are synchronously opened and closed, which can fully recover the energy of the low-power driving capacitive load in a low-voltage environment, and the third switching tube and the fourth switching tube Forming a parallel conduction reduces the resistance value compared to the case where a single switch is turned on, reducing the energy loss.
  • the first switch tube is a first PMOS tube
  • the second switch tube is a first NMOS tube
  • the third switch tube is a second PMOS tube
  • the fourth switch tube is a second NMOS transistor
  • the bottom outlet of the second PMOS transistor is electrically connected to the power source VDD
  • the bottom outlet of the second NMOS transistor is grounded
  • the source of the tube is electrically connected to the node A
  • the source of the second NMOS transistor and the drain of the second PMOS transistor are electrically connected to the node B
  • the node B is electrically connected to the inductor L
  • the upper plate of the load capacitor CL is electrically connected to the node C
  • the node C is electrically connected to the drain of the first PMOS transistor and the drain of the first NMOS transistor, respectively, and the bottom lead line of the first PMOS transistor
  • the source is electrically connected to the power source VDD, and the bottom outlet and the source of
  • MOS transistors whether they are PMOS or NMOS, they are symmetrical tubes, that is, their source and drain are interchangeable, that is, when the PMOS tube's bottom outlet is connected to the power supply VDD alone, when NMOS
  • the drain and source of the MOS transistor are not biased, so as long as the voltage of the gate reaches the turn-on voltage, the forward and reverse of the drain and source of the MOS transistor can be guided.
  • the second PMOS transistor has its N-type bottom connected to the power supply VDD, which is equivalent to parasitic a parasitic diode between the node B and the power supply VDD, which can be restricted by the node B.
  • the positive voltage value is smaller than the sum of the voltage value of the power supply VDD and the parasitic diode conduction voltage value.
  • the second NMOS transistor has its P-type bottom connected to the grounding point, which is equivalent to reverse between the node B and the grounding point.
  • Parasitic a diode that limits the value of the parasitic diode turn-on voltage through the voltage at node B greater than zero. This setting saves two clamp diodes compared to the conventionally set energy recovery circuit while completing the voltage clamp. , Recovering energy in the process,
  • the second PMOS transistor and the second NMOS transistor form a form of parallel conduction, which reduces the resistance value and reduces the energy loss compared to the case where the single MOS transistor of the prior art is turned on.
  • the energy recovery circuit of the low-voltage driving capacitive load includes an inverter INV1, and an output end of the inverter INV1 is electrically connected to a gate of the second PMOS transistor, and the inverter INV1
  • the input terminal and the gate of the second NMOS transistor are electrically connected to the node D, and the node D receives the control signal SC3.
  • the second PMOS transistor is turned on when the second NMOS transistor is turned on, and the second PMOS transistor is also turned off when the second NMOS transistor is turned off, so the second PMOS transistor and the second NMOS transistor are turned off.
  • the gate control signal is inverted, so that the second conductive terminal of the inverter INV1 is electrically connected to the gate of the second PMOS transistor, and the first conductive terminal and the second NMOS of the inverter INV1
  • the gate of the tube is electrically connected, and the second PMOS transistor is turned on when the second NMOS transistor is turned on, and the second PMOS transistor is also turned off when the second NMOS transistor is turned off, saving one control signal, and only three controls are needed.
  • the signal is ready for control.
  • the capacitance value of the load capacitance CL is less than or equal to the capacitance value of the storage capacitor CST.
  • a driving method of an energy recovery circuit for driving a low-voltage capacitive load wherein the driving method of the energy recovery circuit of the low-voltage driving capacitive load is applicable to the energy recovery circuit of the low-voltage driving capacitive load according to claim 1, which is driven by a control signal
  • the switching tube of the energy recovery circuit of the low-voltage driving capacitive load changes the operating state of the circuit to achieve the purpose of energy recovery.
  • the driving method of the energy recovery circuit of the low-voltage driving capacitive load includes the following steps:
  • Step 1 One working cycle can be divided into four stages: T1, ⁇ 2, ⁇ 3, and ⁇ 4;
  • Step 2 In the T1 stage, the second switching tube is controlled to be turned off, the first switching tube is kept turned off, and the third switching tube is maintained. Controlled conduction; the storage capacitor CST and the inductor L and the load capacitor CL form an LC oscillating circuit, and the stored energy stored in the storage capacitor CST is non-destructively transferred to the load capacitor CL through the LC oscillating circuit, at the storage capacitor CST During the transfer of charge to the load capacitor CL, the current in the inductor L increases from 0 to the maximum forward current, and then returns to 0. When the voltage on the storage capacitor CST is equal to the voltage on the load capacitor CL.
  • the current in the inductor L reaches the positive maximum, when the inductor When the current in L returns from the positive maximum value to 0, the voltage of the inductor L reaches the highest value of the oscillation.
  • the control signal turns off the third switching tube, and the T1 interval ends;
  • Step 3 In the T2 interval, the third switch tube is controlled to be turned off, the second switch tube is kept turned off, the first switch tube is controlled to be turned on, and the power supply VDD is boosted to the upper plate of the load capacitor CL through the first switch tube, the load The voltage value of the upper plate of the capacitor CL is equal to the voltage value of the power supply VDD;
  • Step 4 In the T3 interval, the first switch is controlled to be turned off, the second switch is kept off, and the third switch is controlled to be turned on.
  • the load capacitor CL and the inductor L and the storage capacitor CST form an LC oscillator circuit.
  • the energy stored in the CL is transferred back to the storage capacitor CST through the LC oscillating circuit for energy recovery.
  • the current in the inductor L increases from 0 to the reverse. The maximum, and then back to 0, when the voltage on the storage capacitor CST is equal to the voltage on the load capacitor CL, the current in the inductor L reaches the reverse maximum, and the current in the inductor L returns from the reverse maximum value.
  • the voltage of the inductor L reaches the lowest value of the oscillation.
  • the third switch tube is turned off, and the T3 interval ends;
  • Step 5 In the interval T4, the third switch tube is controlled to be turned off, the first switch tube is kept turned off, the second switch tube is controlled to be turned on, and the upper plate of the load capacitor CL is grounded through the second switch tube.
  • the upper plate potential of the capacitor CL is boosted to the same potential as the ground point to complete a duty cycle.
  • the energy recovery circuit of the low-voltage drive capacitive load further includes a fourth switch tube, and the second conductive end of the third switch tube and the second conductive end of the fourth switch tube are electrically connected to the node B, the node B is electrically connected to the first conductive end of the inductor L, and the first conductive end of the third switch tube and the first conductive end of the fourth switch tube are electrically connected to the node A,
  • the node A is electrically connected to the upper plate of the storage capacitor CST, and the switch state of the fourth switch is the same as the switch state of the third switch.
  • the switch state of the fourth switch tube is the same as the switch state of the third switch tube, and only one control signal can be used to control the two switch tubes, which reduces the control difficulty and saves components.
  • the invention has the beneficial effects that: the circuit structure of the invention is simple, the invention only needs three control signals to complete the control of the invention, and saves two anti-reverse current diodes compared to the conventionally arranged energy recovery circuit, in recycling In the process of energy, the second PMOS transistor and the second NMOS transistor are connected in parallel In the form of conduction, the resistance value is reduced compared with the prior art single MOS transistor conduction, and the energy loss is reduced.
  • the present invention uses the parasitic diode to clamp, eliminating the commonly used clamping diode and reducing The loss of energy increases the energy recovery efficiency in the low-voltage energy recovery circuit.
  • Figure 1 is a circuit schematic diagram of the present invention
  • FIG. 2 is a timing diagram of a control signal of a working cycle of the present invention
  • FIG. 3 is a voltage waveform diagram of a timing diagram of a load capacitance corresponding control signal in the present invention
  • FIG. 4 is a current waveform diagram of a timing diagram of a load capacitance corresponding control signal in the present invention
  • FIG. 5 is a classic energy recovery circuit in the background art. a circuit schematic diagram
  • Fig. 7 is a diagram showing voltage and current waveforms of timing diagrams of load capacitance corresponding control signals in the classical energy recovery circuit of the background art. detailed description
  • the energy recovery circuit of the low voltage drive capacitive load includes a first PMOS transistor M1, a first NMOS transistor M2, a second PMOS transistor M3, a second NMOS transistor M4, an inductor L, an inverter INV1, and a load capacitor CL.
  • the storage capacitor CST the lower plate of the storage capacitor CST is grounded, the lower plate of the load capacitor CL is grounded, the capacitance of the storage capacitor CST is greater than the capacitance of the load capacitor CL, and the gate of the second PMOS transistor M3 is opposite
  • the output end of the phase inverter INV1 is electrically connected, the input end of the inverter INV1 and the gate of the second NMOS transistor M4 are electrically connected to the node D, and the input end of the inverter INV1 receives the control signal SC3, and the village of the second PMOS transistor M3
  • the bottom lead wire is electrically connected to the power source VDD, the second The bottom lead of the NMOS transistor M4 is grounded, the source of the second PMOS transistor M3 and the drain of the second NMOS transistor M4 are electrically connected to the node A, and the node A is electrically connected to the upper plate of the storage capacitor CST, and the second PMOS The drain of the transistor M3 and the source of the second NMOS transistor M
  • one working cycle can be divided into four stages of T1, ⁇ 2, ⁇ 3 and ⁇ 4.
  • the control signal of the first PMOS transistor M1 is the control signal SC1.
  • the control signal SC1 is at a low level, the first PMOS transistor M1 is turned on.
  • the control signal SC1 is at a high level, the first PMOS transistor M1 is turned off.
  • the control signal of the NMOS transistor M2 is the control signal SC2.
  • the control signal SC2 When the control signal SC2 is at the high level voltage, the first NMOS transistor M2 is turned on, and when the control signal SC2 is at the low level voltage, the first NMOS transistor M2 is turned off;
  • the control signal of the second PMOS transistor M3 is the control signal SC3, and the control signal of the second NMOS transistor M4 is inverted by the control signal SC3, that is, when the control signal of the second PMOS transistor M3 is at a high level, the control of the second NMOS transistor M4
  • the signal is low level, when the control signal of the second PMOS transistor M3 is low level, the control signal of the second NMOS transistor M4 is high level, so when the control signal SC3 is high level, the second PMOS transistor M3 and the The two NMOS transistors M4 are turned on, and when the control signal SC3 is at a low level, the second PMOS transistor M3 and the second NMOS transistor M4 are turned off.
  • the drain and the source of the second PMOS transistor M3 and the second NMOS transistor are not biased. Therefore, as long as the voltage of the gate reaches the turn-on voltage, the forward and reverse of the drain and the source of the second PMOS transistor M3 can be turned on, and the drain and the source of the second NMOS transistor M4 can be forward and reverse. Turn on, realize the function of the switch tube.
  • the second PMOS transistor M3, its N-type bottom is connected to the power supply VDD, which will be equivalent to the node B and the power supply VDD.
  • a parasitic diode is parasitic between the parasitic diode and the power supply VDD can limit the voltage value through the node B to be less than the voltage value of the power supply VDD plus the on-voltage value of the parasitic diode.
  • the second NMOS transistor M4 its P-type substrate Connected to the grounding point, this will be equivalent to a parasitic parasitic diode between node B and ground.
  • the parasitic diode is grounded and the negative terminal circuit is clamped to zero minus the parasitic diode turn-on voltage. Limit the diode turn-on voltage value by the voltage value of node B being greater than zero.
  • the initial state of the present invention is that the first PMOS transistor M1 is controlled to be turned off, the second PMOS transistor M3 is controlled to be turned off, the second NMOS transistor M4 is controlled to be turned off, and the first NMOS transistor M2 is controlled to be turned on.
  • the upper plate potential of capacitor CL is boosted to the same potential as the ground point, then the invention will operate from the T1 phase.
  • the first NMOS transistor M2 is controlled to be turned off, the first PMOS transistor M1 is kept turned off, and the second PMOS transistor M3 and the second NMOS transistor M4 are controlled to be turned on; the current flow direction is:
  • the current is stored by the storage capacitor CST
  • the upper plate sequentially passes through node VIII, node B and node C to the upper plate of the load capacitor CL.
  • the storage capacitor CST and the inductor L and the load capacitor CL constitute an LC oscillating circuit, and the stored energy stored in the storage capacitor CST is non-destructively transferred to the load capacitor CL through the LC oscillating circuit, and the storage capacitor CST is During the load capacitance CL moving the charge, the current in the inductor L increases from 0 to the maximum forward current, and then returns to 0. When the voltage on the storage capacitor CST is equal to the voltage on the load capacitor CL, The current in the inductor L reaches the positive maximum. When the current in the inductor L returns from the positive maximum value to 0, the voltage of the inductor L reaches the highest value of the oscillation.
  • the control signal SC3 turns off the second PMOS transistor M3 and the The two NMOS transistors M4, the T1 interval ends.
  • the second PMOS transistor M3 and the second NMOS transistor M4 are controlled to be turned off, the first NMOS transistor M2 is kept turned off, the first PMOS transistor M1 is controlled to be turned on, and the current flow direction is: The current is sequentially passed by the power supply VDD.
  • the PMOS transistor M1 and the node C reach the upper plate of the load capacitor CL.
  • the power supply VDD is boosted to the upper plate of the load capacitor CL through the first PMOS transistor M1, and the voltage value of the upper plate of the load capacitor CL is equal to the voltage value of the power supply VDD.
  • the first PMOS transistor M1 is controlled to be turned off, the first NMOS transistor M2 is kept turned off, the second PMOS transistor M3 and the second NMOS transistor M4 are controlled to be turned on, and the current flow direction is: the current is applied from the load capacitor CL
  • the plates pass through node C, node B and node A in sequence to the upper plate of the storage capacitor CST.
  • the load capacitor CL and the inductor L and the storage capacitor CST form an LC oscillating circuit.
  • the energy stored in the CL is transferred back to the storage capacitor CST through the LC oscillating circuit, and the load capacitor CL is moved to the storage capacitor CST.
  • the current in the inductor L increases from 0 to the reverse maximum, and then returns to 0.
  • the voltage on the storage capacitor CST is equal to the voltage on the load capacitor CL
  • the current in the inductor L When the current in the inductor L reaches the maximum value from the reverse maximum value, the voltage of the inductor L reaches the lowest value of the oscillation.
  • the second PMOS transistor M3 and the second NMOS transistor M4 are turned off, and the T3 interval ends. .
  • the second PMOS transistor M3 and the second NMOS transistor M4 are controlled to be turned off, the first PMOS transistor M1 is kept turned off, the first NMOS transistor M2 is controlled to be turned on, and the current flow direction is: the current is applied by the load capacitance CL
  • the plates sequentially pass through the node C and the first NMOS transistor M2 to reach the ground point.
  • the upper plate of the load capacitor CL is grounded through the first NMOS transistor M2, at which time the upper plate potential of the load capacitor CL is strengthened to the same potential as the ground point, completing energy recovery for one duty cycle.

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Abstract

一种能量回收电路及其驱动方法，能量回收电路包括负载电容(CL)和储能电容(CST)，储能电容(CST)的下极板接地，负载电容(CL)的下极板接地，还包括电感(L)、第一开关管(M1)、第二开关管(M2)、第三开关管(M3)和第四开关管(M4)，第一开关管(M1)的第一导通端与电源(VDD)电连接，第一开关管(M1)的第二导通端接地，第一开关管(M1)的第二导通端与第二开关管(M2)的第一导通端电连接于第三节点(C)，第三节点(C)与负载电容(CL)的上极板电连接，第三开关管(M3)的第二导通端与第四开关管(M4)的第二导通端电连接于第二节点(B)，第二节点(B)与电感(L)的第一导通端电连接，电感(L)的第二导通端与第三节点(C)电连接，第三开关管(M3)的第一导通端与第四开关管(M4)的第一导通端电连接于第一节点(A)，第一节点(A)与储能电容(CST)的上极板电连接，该能量回收电路能提高在低压能量回收电路中的能量回收效率。

Description

低压驱动电容负载的能量回收电路及其驱动方法 技术领域
本发明涉及一种能量回收电路及其驱动方法， 特别涉及一种适合各种低 压环境下的低压驱动电容负载的能量回收电路及其驱动方法。 背景技术
在很多应用场合需要对电容负载频繁地进行充电放电， 以传递信息。 用 直流电源通过开关直接对电容负载充电， 以及把电容负载上的电荷通过开关 直接放到地， 这将在开关上耗费大量的能量， 同时， 将引起开关元件的温度 上升， 严重时导致开关元件的损坏。 现有的一些能量回收电路可以较好的解 决这一个问题， 如 Weber在他的美国专利（编号 5081400 )中针对等离子显示 器的驱动， 提出了一种经典的能量回收电路（参见附图 5 ), 能量回收电路包 含以下元件： 向等效负载电容 CL上极板提供加强电压 VDD的第一开关 Ml ; 向等效负载电容 CL上极板提供 GND加强电压的第二开关 M2; 并联在储能 电容 CST和电感器 L之间的第三开关 M3 , 第四开关 M4; 第三和第四开关 M3、 M4之间串联着用来限制逆电流的第一二极管 Dl、 第二二极管 D2; 第 三开关 M3与第一二极管 D1的连接点连接着对 GND起反向钳位用的第三二 极管 Del , 第四开关 M4与第二二极管 D2的连接点连接着对 VDD起正向钳 位用的第四二极管 Dc2; 电感器 L的另一端连接等效负载电容 CL的上极板。 此技术方案的工作方法如下（参见附图 6 ): 第一开关 Ml用 PMOS管来实现， 其栅极驱动电压 SC1低电平令 Ml导通， 高电平令 Ml关断； 第二开关 M2 用 NMOS管来实现， 其栅极驱动电压 SC2高电平令 M2导通， 低电平令 M2 关断； 第三开关 M3用 PMOS管来实现， 其栅极驱动电压 SC3低电平令 M3 导通， 高电平令 M3关断； 第四开关 M4用 NMOS管来实现， 其栅极驱动电 压 SC4高电平令 M4导通， 低电平令 M4关断。 此技术方案在一个工作周期 内具有四个工作区间 （参见附图 7 ), 在 T1区间， 第三开关 M3开启， 第一、 二、 四开关 Ml、 M2、 M4关断， 那么储能电容 CST中储存的电荷经由第三 开关 M3、 第一二极管 D1提供给电感器 L, 由于电感器 L与负载电容 CL组 成串联共振电路， CL由于共振而充入电压， 其上极板的电压 VL可以自由振 荡到 VDD。 在 T1区间， 电感器中的电流从 0开始往正向增大， 到达峰值后， 在 CL上极板电压 VL振荡到最高点， L中电流又回到 0。 在 T2区间， L中的 电流回到 0点， 是 T1的结束点， 同时是 T2的开始点。 第一开关 Ml、 第三开 关 M3开启， 第二开关 M2、 第四开关 M4关断。 CL的上极板经由第一开关 Ml加强到 VDD, 同时由于防逆向电流的第一二极管 D1的作用， 虽然 M3开 启， 但是 M3、 D1支路没有电流流过。 在 T3区间， 第一开关 Ml、 第二开关 M2、第三开关 M3关断，第四开关 M4开启。负载 CL上的电荷经由电感器 L, 第二二极管 D2, 第四开关 M4被储能电容 CST回收。 这一过程， 负载电容上 的电压 VL从 VDD 自由振荡到 0, 电感器中的电流从 0开始反向增大到最大 点， 然后又回到 0。 在 T4区间， 第二开关 M2、 第四开关 M4开启， 第一开关 Ml、 第三开关 M3关断。 那么 CL上极板电压 VL经由 Ml加强到 GND。 此 能量回收电路中， 由于振荡时主回路中第一、 第二二极管 Dl、 D2 的存在， 在对 CL的充电过程中， D1两端将产生正向的导通电压 VF1 , 在对 CL的放 电过程， D2两端也将产生正向的导通电压 VF2, 在充放电时， 这将会额外的 损耗能量， 在诸如等离子显示器驱动的上百伏高压电路中， 此两二极管额外 损耗的能量可以忽略，但是在一些 3伏、 5伏甚至于 1.8伏的低压环境应用中， 此两二极管额外损耗的能量将无法忽略， 造成较大的能量损耗。
中国专利公告号 CN1779756A,公告日 2006年 5月 31 日，公开了一种能 量回收电路， 由以下几个部分组成： 外部电容； 等价形成于基板放电细胞上 的基板电容； 连接在上述外部电容和上述基板电容之间的感应器； 连接在上 述外部电容和上述感应器一侧之间的第 1 开关； 设置在上述感应器的另一侧 和上述基础电压源之间， 由于外部电容内被充入电压而在感应器被充电时， 与第一开关同时开启的第 2开关； 设置在上述感应器的一侧和上述基础电压 源之间借以形成电流通路的第 1二极管， 该电流通路能够把上述第 1和第 2 开关关闭时遗留在上述感应器内的第 1 逆电压提供给上述基板电容。 此技术 方案中使用了两个独立的二极管， 此两个独立的二极管除了带来额外的导通 功耗外， 还将带来寄生电容的额外功耗， 能量损耗也较多， 不适合在低压环 境下使用。 发明内容
本发明的目的在于解决上述现有技术中能量回收电路在低压应用中往往 会有较大比例能量损耗的问题， 提供一种适合低压环境下的能量回收电路。
本发明解决其技术问题所采用的技术方案是： 一种低压驱动电容负载的 能量回收电路， 包括负载电容 CL和储能电容 CST, 储能电容 CST的下极板 接地， 负载电容 CL的下极板接地， 所述的低压驱动电容负载的能量回收电路 还包括电感 L、 第一开关管、 第二开关管和第三开关管， 所述第一开关管的第 一导通端与电源 VDD电连接， 所述第二开关管的第二导通端接地， 所述第一 开关管的第二导通端与所述第二开关管的第一导通端电连接于节点 C, 所述 节点 C与负载电容 CL的上极板电连接， 所述第三开关管的第二导通端与电 感 L的第一导通端电连接， 所述电感 L的第二导通端与节点 C电连接， 所述 第三开关管的第一导通端与储能电容 CST的上极板电连接，所述第一开关管、 第二开关管和第三开关管的控制端分别受控制信号控制。 这样设置电路， 第 一开关管、 第二开关管和第三开关管可以为任何的可控开关管， 本发明中， 通过节点 B流向节点 C的电流方向为正向电流方向， 本发明在实施时一个工 作周期可分为 Tl、 Τ2、 Τ3和 Τ4四个阶段， 我们^ 设本发明的初始状态为第 一开关管受控关断， 第三开关管受控关断， 第二开关管受控导通， 此时负载 电容 CL的上极板电势被加强到与接地点电势相同， 此时本发明自 T1阶段开 始进行工作； 本发明在 T1阶段，第二开关管受控关断，第一开关管维持关断， 第三开关管受控导通；储能电容 CST与电感 L及负载电容 CL组成了一个 LC 振荡电路， 储能电容 CST上储存的电能通过 LC振荡电路无损地被搬到负载 电容 CL上来， 在储能电容 CST向负载电容 CL搬移电荷的过程中， 电感 L 中的电流从 0增大到最大正向电流， 然后又回到 0, 当储能电容 CST上极板 电压与负载电容 CL上极板电压相等时， 电感 L中的电流达到正向最大， 当电 感 L中的电流从正向最大值回到 0的同时，电感 L的电压达到振荡的最高值， 此时控制信号关断第三开关管， T1 区间结束； 在 T2区间， 第三开关管受控 关断， 第二开关管维持关断， 第一开关管受控开启， 电源 VDD通过第一开关 管加强到负载电容 CL的上极板，负载电容 CL的上极板的电压值与电源 VDD 的电压值相等； 在 T3区间， 第一开关管受控关断， 第二开关管维持关断， 第 三开关管受控导通， 负载电容 CL与电感 L及储能电容 CST组成了一个 LC 振荡电路， CL上储存的电能通过 LC振荡电路被搬回到储能电容 CST上来进 行能量回收， 在负载电容 CL向储能电容 CST搬移电荷的过程中， 电感 L中 的电流从 0增大到反向最大， 然后又回到 0, 当储能电容 CST上极板电压与 负载电容 CL上极板电压相等时， 电感 L中的电流达到反向最大， 当电感 L 中的电流从反向最大值回到 0的同时， 电感 L的电压达到振荡的最低值， 此 时关断第三开关管， T3 区间结束； 在 T4 区间， 第三开关管受控关断， 第一 开关管维持关断， 第二开关管受控导通， 负载电容 CL的上极板通过第二开关 管接地， 此时负载电容 CL的上极板电势被加强到与接地点电势相同， 完成能 量回收， 根据以上工作周期， 可以得出， 本发明能够完成能量回收的工作， 相比其他各种能量回收电路， 本发明的元件数少， 能耗低， 能量回收效率高， 能适用于各种低压环境。
作为优选， 所述的低压驱动电容负载的能量回收电路还包括第四开关管， 所述第三开关管的第二导通端与所述第四开关管的第二导通端电连接于节点 B, 所述的节点 B与电感 L的第一导通端电连接， 所述第三开关管的第一导 通端与所述第四开关管的第一导通端电连接于节点 A, 所述的节点 A与储能 电容 CST的上极板电连接， 所述第四开关管的控制端受控制信号控制。 这样 的电路， 可以由控制信号驱动使得第三开关管和第四开关管同步开闭， 完全 可以起到低压环境下的低功耗驱动电容负载的能量回收， 第三开关管和第四 开关管构成并联导通的形式， 相比单个开关管导通的情况降低电阻值， 降低 了能量的损耗。
作为优选， 所述的第一开关管为第一 PMOS管， 所述的第二开关管为第 一 NMOS管， 所述的第三开关管为第二 PMOS管， 所述的第四开关管为第二 NMOS管， 所述第二 PMOS管的村底引出线与电源 VDD电连接， 所述第二 NMOS管的村底引出线接地，所述第二 NMOS管的漏极与所述第二 PMOS管 的源极电连接于节点 A, 所述第二 NMOS管的源极与所述第二 PMOS管的漏 极电连接于节点 B, 所述的节点 B与电感 L电连接， 所述电感 L与负载电容 CL的上极板电连接于节点 C,所述节点 C分别与第一 PMOS管的漏极以及第 一 NMOS管的漏极电连接，所述第一 PMOS管的村底引出线和源极均与电源 VDD电连接，所述第一 NMOS管的村底引出线和源极均接地，所述第一 PMOS 管、 第一 NMOS管、 第二 PMOS管和第二 NMOS管的栅极分别受控制信号 控制。 对于 MOS管来说， 不论是 PMOS或者 NMOS它们都是对称的管子， 也就是说他们的源极和漏极是可以互换的， 即当 PMOS管的村底引出线单独 接电源 VDD、 当 NMOS管的村底引出线单独接地时， MOS管的漏极和源极 均没有偏置， 所以只要栅极的电压达到开启电压， 那么 MOS管的漏极与源极 之间正反向均可导通， 实现开关管的功能， 同时， 第二 PMOS管， 其 N型村 底接电源 VDD, 这将等效成在节点 B与电源 VDD之间寄生了一个正向二极 管，可以限制通过节点 B的正电压值小于电源 VDD的电压值与寄生二极管导 通电压值的和， 第二 NMOS管， 其 P型村底连接在接地点上， 这将等效成在 节点 B与接地点之间反向寄生了一个二极管， 可以限制通过节点 B的电压值 大于零减去寄生二极管导通电压值， 这样设置在完成了电压钳位的同时比常 规设置的能量回收电路节省了两个钳位二极管， 同时， 在回收能量的过程中， 第二 PMOS 管和第二 NMOS 管构成并联导通的形式， 相比现有技术的单个 MOS管导通的情况降低了电阻值， 降低了能量的损耗。
作为优选，所述的低压驱动电容负载的能量回收电路包括有反相器 INV1 , 所述反相器 INV1的输出端与所述第二 PMOS管的栅极电连接， 所述反相器 INV1的输入端与第二 NMOS管的栅极电连接于节点 D, 所述的节点 D接收 控制信号 SC3。 由于本发明中， 每个工作周期中， 第二 NMOS管导通时第二 PMOS管导通， 第二 NMOS管关断时第二 PMOS管也关断， 所以第二 PMOS 管和第二 NMOS管的栅极控制信号为反相设置， 因此反相器 INV1的第二导 通端与所述第二 PMOS管的栅极电连接， 所述反相器 INV1的第一导通端与 第二 NMOS管的栅极电连接， 可以完成第二 NMOS管导通时第二 PMOS管 导通，第二 NMOS管关断时第二 PMOS管也关断的控制，节省一个控制信号， 只需三个控制信号即可完成控制。
作为优选，所述的负载电容 CL的电容值小于或等于所述的储能电容 CST 的电容值。
一种低压驱动电容负载的能量回收电路的驱动方法， 所述的低压驱动电 容负载的能量回收电路的驱动方法适用于如权利要求 1 所述的低压驱动电容 负载的能量回收电路， 通过控制信号驱动低压驱动电容负载的能量回收电路 中各开关管， 改变电路运行状态， 达成能量回收目的， 低压驱动电容负载的 能量回收电路的驱动方法包括以下步骤：
步骤一： 一个工作周期可分为四个 Tl、 Τ2、 Τ3和 Τ4四个阶段； 步骤二： 在 T1阶段， 第二开关管受控关断， 第一开关管维持关断， 第三 开关管受控导通； 储能电容 CST与电感 L及负载电容 CL组成了一个 LC振 荡电路， 储能电容 CST上储存的电能通过 LC振荡电路无损地被搬到负载电 容 CL上来， 在储能电容 CST向负载电容 CL搬移电荷的过程中， 电感 L中 的电流从 0增大到最大正向电流， 然后又回到 0, 当储能电容 CST上极板电 压与负载电容 CL上极板电压相等时， 电感 L中的电流达到正向最大， 当电感 L中的电流从正向最大值回到 0的同时， 电感 L的电压达到振荡的最高值， 此时控制信号关断第三开关管， T1区间结束；
步骤三： 在 T2区间， 第三开关管受控关断， 第二开关管维持关断， 第一 开关管受控开启， 电源 VDD通过第一开关管加强到负载电容 CL的上极板， 负载电容 CL的上极板的电压值与电源 VDD的电压值相等；
步骤四： 在 T3区间， 第一开关管受控关断， 第二开关管维持关断， 第三 开关管受控导通， 负载电容 CL与电感 L及储能电容 CST组成了一个 LC振 荡电路， CL上储存的电能通过 LC振荡电路被搬回到储能电容 CST上来进行 能量回收， 在负载电容 CL向储能电容 CST搬移电荷的过程中， 电感 L中的 电流从 0增大到反向最大， 然后又回到 0, 当储能电容 CST上极板电压与负 载电容 CL上极板电压相等时， 电感 L中的电流达到反向最大， 当电感 L中 的电流从反向最大值回到 0的同时， 电感 L的电压达到振荡的最低值， 此时 关断第三开关管， T3区间结束；
步骤五： 在 T4区间， 第三开关管受控关断， 第一开关管维持关断， 第二 开关管受控导通， 负载电容 CL的上极板通过第二开关管接地， 此时负载电容 CL的上极板电势被加强到与接地点电势相同， 完成一个工作周期。
作为优选， 所述的低压驱动电容负载的能量回收电路还包括第四开关管， 所述第三开关管的第二导通端与所述第四开关管的第二导通端电连接于节点 B, 所述的节点 B与电感 L的第一导通端电连接， 所述第三开关管的第一导 通端与所述第四开关管的第一导通端电连接于节点 A, 所述的节点 A与储能 电容 CST的上极板电连接， 所述的第四开关管的开关状态与第三开关管的开 关状态相同。 第四开关管的开关状态与第三开关管的开关状态相同则可只采 用一个控制信号即可控制两个开关管， 降低了控制难度， 节省了元件。
本发明的有益效果是： 本发明电路结构筒单， 本发明仅需三个控制信号 即可完成本发明的控制， 还比常规设置的能量回收电路节省了两个防逆向电 流的二极管， 在回收能量的过程中， 第二 PMOS管和第二 NMOS管构成并联 导通的形式， 相比现有技术的单个 MOS管导通的情况降低了电阻值， 降低了 能量的损耗， 同时， 本发明采用寄生二极管起钳位作用， 取消了常用的钳位 二极管， 减少了能量的损耗， 提高了在低压能量回收电路中的能量回收效率。 附图说明
图 1是本发明的一种电路原理图；
图 2是本发明一个工作周期的一种控制信号时序图；
图 3是本发明中负载电容对应控制信号时序图的一种电压波形图； 图 4是本发明中负载电容对应控制信号时序图的一种电流波形图； 图 5是背景技术中经典能量回收电路的一种电路原理图；
图 6是背景技术中经典能量回收电路中各开关控制信号的一种工作时序 图；
图 7是背景技术中经典能量回收电路中负载电容对应控制信号时序图的 一种电压、 电流波形图。 具体实施方式
下面通过具体实施例， 并结合附图， 对本发明的技术方案作进一步的具 体说明。
实施例：
低压驱动电容负载的能量回收电路（参见附图 1 )包括第一 PMOS管 Ml、 第一 NMOS管 M2、 第二 PMOS管 M3、 第二 NMOS管 M4、 电感 L、 反相器 INV1、 负载电容 CL和储能电容 CST, 储能电容 CST的下极板接地， 负载电 容 CL的下极板接地，储能电容 CST的电容值大于负载电容 CL的电容值，第 二 PMOS管 M3的栅极与反相器 INV1的输出端电连接，反相器 INV1的输入 端与第二 NMOS管 M4的栅极电连接于节点 D, 反相器 INV1的输入端接收 控制信号 SC3, 第二 PMOS管 M3的村底引出线与电源 VDD电连接， 第二 NMOS管 M4的村底引出线接地， 第二 PMOS管 M3的源极与第二 NMOS管 M4的漏极电连接于节点 A, 节点 A与储能电容 CST的上极板电连接， 第二 PMOS管 M3的漏极与第二 NMOS管 M4的源极电连接于节点 B, 节点 B与 电感 L的第一导通端电连接， 电感 L的第二导通端与负载电容 CL的上极板 电连接与节点 C, 第一 PMOS管 Ml的村底引出线和源极接电源 VDD, 第一 PMOS管 Ml 的栅极接收控制信号 SC1 , 第一 PMOS管 Ml 的漏极与第一 NMOS管 M2的漏极电连接于节点 C, 第一 NMOS管 M2的栅极接收控制信 号 SC2, 第一 NMOS管 M2的村底引出线和源极接地， 本实施例中， 通过节 点 B流向节点 C的电流方向为正向电流方向。
本实施例在工作时 （参见附图 2、 附图 3、 附图 4 )一个工作周期可分为 Tl、 Τ2、 Τ3和 Τ4四个阶段。 其中， 第一 PMOS管 Ml的控制信号为控制信 号 SC1 , 当控制信号 SC1为低电平时， 第一 PMOS管 Ml导通， 当控制信号 SC1为高电平时， 第一 PMOS管 Ml关断； 第一 NMOS管 M2的控制信号为 控制信号 SC2, 当控制信号 SC2为高电平压时， 第一 NMOS管 M2导通， 当 控制信号 SC2为低电平压时， 第一 NMOS管 M2关断； 第二 PMOS管 M3的 控制信号为控制信号 SC3, 第二 NMOS管 M4的控制信号为控制信号 SC3取 反， 即当第二 PMOS管 M3的控制信号为高电平时， 第二 NMOS管 M4的控 制信号为低电平， 当第二 PMOS管 M3的控制信号为低电平时， 第二 NMOS 管 M4的控制信号为高电平， 所以当控制信号 SC3为高电平时， 第二 PMOS 管 M3和第二 NMOS管 M4导通， 当控制信号 SC3为低电平时， 第二 PMOS 管 M3和第二 NMOS管 M4关断。 由于第二 PMOS管 M3的村底引出线单独 接电源 VDD、 第二 NMOS管的村底引出线单独接地， 所以第二 PMOS管 M3 和第二 NMOS管的漏极和源极均没有偏置， 所以只要栅极的电压达到开启电 压， 那么第二 PMOS管 M3的漏极与源极之间正反向均可导通， 第二 NMOS 管 M4 的漏极与源极之间正反向均可导通， 实现开关管的功能， 同时， 第二 PMOS管 M3, 其 N型村底接电源 VDD, 这将等效成在节点 B与电源 VDD 之间寄生了一个正向二极管，寄生二极管负极接电源 VDD可以限制通过节点 B 的电压值小于电源 VDD 的电压值加上寄生二极管的导通电压值， 第二 NMOS管 M4, 其 P型村底连接在接地点上， 这将等效成在节点 B与接地点 之间反向寄生了一个二极管， 寄生二极管正极接地则负极端电路被钳位为零 减去寄生二极管导通电压的值， 可以限制通过节点 B的电压值大于零减去二 极管导通电压值。 如果本发明的初始状态为第一 PMOS管 Ml受控关断， 第 二 PMOS管 M3受控关断、 第二 NMOS管 M4受控关断， 第一 NMOS管 M2 受控导通， 此时负载电容 CL的上极板电势被加强到与接地点电势相同， 那么 本发明将从 T1阶段进行工作。 在 T1阶段， 第一 NMOS管 M2受控关断， 第 一 PMOS管 Ml维持关断，第二 PMOS管 M3和第二 NMOS管 M4受控导通； 电流流向为： 电流由储能电容 CST的上极板依次经过节点八、 节点 B和节点 C到达负载电容 CL的上极板。在 T1阶段， 储能电容 CST与电感 L及负载电 容 CL组成了一个 LC振荡电路，储能电容 CST上储存的电能通过 LC振荡电 路无损地被搬到负载电容 CL上来，在储能电容 CST向负载电容 CL搬移电荷 的过程中， 电感 L中的电流从 0增大到最大正向电流， 然后又回到 0, 当储能 电容 CST上极板电压与负载电容 CL上极板电压相等时， 电感 L中的电流达 到正向最大， 当电感 L中的电流从正向最大值回到 0时， 电感 L的电压达到 振荡的最高值， 此时控制信号 SC3关断第二 PMOS管 M3和第二 NMOS管 M4, T1区间结束。 在 T2阶段， 第二 PMOS管 M3和第二 NMOS管 M4受控 关断， 第一 NMOS管 M2维持关断， 第一 PMOS管 Ml受控开启， 电流流向 为： 电流由电源 VDD依次经过第一 PMOS管 Ml和节点 C到达负载电容 CL 的上极板。在 T2区间， 电源 VDD通过第一 PMOS管 Ml加强到负载电容 CL 的上极板， 负载电容 CL的上极板的电压值与电源 VDD的电压值相等。在 T3 阶段，第一 PMOS管 Ml受控关断，第一 NMOS管 M2维持关断，第二 PMOS 管 M3和第二 NMOS管 M4受控导通， 电流流向为： 电流由负载电容 CL的 上极板依次经过节点 C、 节点 B和节点 A到达储能电容 CST的上极板。 在 T3区间， 负载电容 CL与电感 L及储能电容 CST组成了一个 LC振荡电路， CL上储存的电能通过 LC振荡电路被搬回到储能电容 CST上来，在负载电容 CL向储能电容 CST搬移电荷的过程中， 电感 L中的电流从 0增大到反向最 大， 然后又回到 0, 当储能电容 CST上极板电压与负载电容 CL上极板电压相 等时， 电感 L中的电流达到反向最大， 当电感 L中的电流从反向最大值回到 0时， 电感 L的电压达到振荡的最低值， 此时关断第二 PMOS管 M3和第二 NMOS管 M4, T3区间结束。 在 T4阶段， 第二 PMOS管 M3和第二 NMOS 管 M4受控关断， 第一 PMOS管 Ml维持关断， 第一 NMOS管 M2受控导通， 电流流向为： 电流由负载电容 CL的上极板依次经过节点 C和第一 NMOS管 M2到达接地点。 在 T4区间， 负载电容 CL的上极板通过第一 NMOS管 M2 接地， 此时负载电容 CL的上极板电势被加强到与接地点电势相同， 完成一个 工作周期的能量回收。
以上所述的实施例只是本发明的一种较佳的方案， 并非对本发明作任何 形式上的限制， 在不超出权利要求所记载的技术方案的前提下还有其它的变 体及改型。

Claims

权利要求
1.一种低压驱动电容负载的能量回收电路， 包括负载电容 CL和储能电容 CST, 储能电容 CST的下极板接地， 负载电容 CL的下极板接地， 其特征在 于： 所述的低压驱动电容负载的能量回收电路还包括电感 L、 第一开关管、 第 二开关管和第三开关管， 所述第一开关管的第一导通端与电源 VDD电连接， 所述第二开关管的第二导通端接地， 所述第一开关管的第二导通端与所述第 二开关管的第一导通端电连接于节点 C,所述节点 C与负载电容 CL的上极板 电连接， 所述第三开关管的第二导通端与电感 L的第一导通端电连接， 所述 电感 L的第二导通端与节点 C电连接， 所述第三开关管的第一导通端与储能 电容 CST的上极板电连接， 所述第一开关管、 第二开关管和第三开关管的控 制端分别受控制信号控制。
2. 根据权利要求 1所述的低压驱动电容负载的能量回收电路， 其特征在 于： 所述的低压驱动电容负载的能量回收电路还包括第四开关管， 所述第三 开关管的第二导通端与所述第四开关管的第二导通端电连接于节点 B , 所述 的节点 B与电感 L的第一导通端电连接， 所述第三开关管的第一导通端与所 述第四开关管的第一导通端电连接于节点 A, 所述的节点 A与储能电容 CST 的上极板电连接， 所述第四开关管的控制端受控制信号控制。
3. 根据权利要求 2所述的低压驱动电容负载的能量回收电路， 其特征在 于：所述的第一开关管为第一 PMOS管，所述的第二开关管为第一 NMOS管， 所述的第三开关管为第二 PMOS管， 所述的第四开关管为第二 NMOS管， 所 述第二 PMOS管的村底引出线与电源 VDD电连接， 所述第二 NMOS管的村 底引出线接地， 所述第二 NMOS管的漏极与所述第二 PMOS管的源极电连接 于节点 A, 所述第二 NMOS管的源极与所述第二 PMOS管的漏极电连接于节 点 B, 所述的节点 B与电感 L电连接， 所述电感 L与负载电容 CL的上极板 电连接于节点 C,所述节点 C分别与第一 PMOS管的漏极以及第一 NMOS管 的漏极电连接，所述第一 PM0S管的村底引出线和源极均与电源 VDD电连接， 所述第一 NMOS 管的村底引出线和源极均接地， 所述第一 PMOS 管、 第一 NM0S管、 第二 PM0S管和第二 NMOS管的栅极分别受控制信号控制。
4. 根据权利要求 3所述的低压驱动电容负载的能量回收电路， 其特征在 于： 所述的低压驱动电容负载的能量回收电路包括有反相器 INV1 , 所述反相 器 INV1的输出端与所述第二 PMOS管的栅极电连接，所述反相器 INV1的输 入端与第二 NMOS管的栅极电连接于节点 D, 所述的节点 D接收控制信号 SC3。
5. 根据权利要求 1或 2或 3或 4所述的低压驱动电容负载的能量回收电 路， 其特征在于： 所述的负载电容 CL 的电容值小于或等于所述的储能电容 CST的电容值。
6. 一种低压驱动电容负载的能量回收电路的驱动方法， 所述的低压驱动 电容负载的能量回收电路的驱动方法适用于如权利要求 1 所述的低压驱动电 容负载的能量回收电路， 通过控制信号驱动低压驱动电容负载的能量回收电 路中各开关管， 改变电路运行状态， 达成能量回收目的， 其特征在于： 低压 驱动电容负载的能量回收电路的驱动方法包括以下步骤：
步骤一： 一个工作周期可分为四个 Tl、 Τ2、 Τ3和 Τ4四个阶段； 步骤二： 在 T1阶段， 第二开关管受控关断， 第一开关管维持关断， 第三 开关管受控导通； 储能电容 CST与电感 L及负载电容 CL组成了一个 LC振 荡电路， 储能电容 CST上储存的电能通过 LC振荡电路无损地被搬到负载电 容 CL上来， 在储能电容 CST向负载电容 CL搬移电荷的过程中， 电感 L中 的电流从 0增大到最大正向电流， 然后又回到 0, 当储能电容 CST上极板电 压与负载电容 CL上极板电压相等时， 电感 L中的电流达到正向最大， 当电感 L中的电流从正向最大值回到 0的同时， 电感 L的电压达到振荡的最高值， 此时控制信号关断第三开关管， T1区间结束；
步骤三： 在 Τ2区间， 第三开关管受控关断， 第二开关管维持关断， 第一 开关管受控开启， 电源 VDD通过第一开关管加强到负载电容 CL的上极板， 负载电容 CL的上极板的电压值与电源 VDD的电压值相等；
步骤四： 在 T3区间， 第一开关管受控关断， 第二开关管维持关断， 第三 开关管受控导通， 负载电容 CL与电感 L及储能电容 CST组成了一个 LC振 荡电路， CL上储存的电能通过 LC振荡电路被搬回到储能电容 CST上来进行 能量回收， 在负载电容 CL向储能电容 CST搬移电荷的过程中， 电感 L中的 电流从 0增大到反向最大， 然后又回到 0, 当储能电容 CST上极板电压与负 载电容 CL上极板电压相等时， 电感 L中的电流达到反向最大， 当电感 L中 的电流从反向最大值回到 0的同时， 电感 L的电压达到振荡的最低值， 此时 关断第三开关管， T3区间结束；
步骤五： 在 T4区间， 第三开关管受控关断， 第一开关管维持关断， 第二 开关管受控导通， 负载电容 CL的上极板通过第二开关管接地， 此时负载电容 CL的上极板电势被加强到与接地点电势相同， 完成一个工作周期。
7. 根据权利要求 6 所述的低压驱动电容负载的能量回收电路的驱动方 法， 其特征在于： 所述的低压驱动电容负载的能量回收电路还包括第四开关 管， 所述第三开关管的第二导通端与所述第四开关管的第二导通端电连接于 节点 B, 所述的节点 B与电感 L的第一导通端电连接， 所述第三开关管的第 一导通端与所述第四开关管的第一导通端电连接于节点 A, 所述的节点 A与 储能电容 CST的上极板电连接， 所述的第四开关管的开关状态与第三开关管 的开关状态相同。
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