WO2013011649A1 - Demultiplexer - Google Patents

Demultiplexer Download PDF

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Publication number
WO2013011649A1
WO2013011649A1 PCT/JP2012/004401 JP2012004401W WO2013011649A1 WO 2013011649 A1 WO2013011649 A1 WO 2013011649A1 JP 2012004401 W JP2012004401 W JP 2012004401W WO 2013011649 A1 WO2013011649 A1 WO 2013011649A1
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WO
WIPO (PCT)
Prior art keywords
electrode
filter element
ground
transmission
terminal
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Application number
PCT/JP2012/004401
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French (fr)
Japanese (ja)
Inventor
竹村 忠治
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株式会社村田製作所
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Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Publication of WO2013011649A1 publication Critical patent/WO2013011649A1/en

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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/70Multiple-port networks for connecting several sources or loads, working on different frequencies or frequency bands, to a common load or source
    • H03H9/72Networks using surface acoustic waves
    • H03H9/725Duplexers
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02Details
    • H03H9/05Holders; Supports
    • H03H9/0538Constructional combinations of supports or holders with electromechanical or other electronic elements
    • H03H9/0566Constructional combinations of supports or holders with electromechanical or other electronic elements for duplexers
    • H03H9/0576Constructional combinations of supports or holders with electromechanical or other electronic elements for duplexers including surface acoustic wave [SAW] devices

Definitions

  • the present invention relates to a duplexer including a first filter element and a second filter element having different pass bands.
  • the conventional branching circuit 500 shown in FIG. 10 described in Patent Document 1 includes a low-frequency filter 501 and a high-frequency filter 502.
  • the low-frequency filter 501 is formed by a transmission line Lf1 connected to the common terminal 503, a series resonance circuit including a transmission line Lf2 connected between the low-frequency terminal 504 and the ground, and a capacitor Cf1.
  • the high frequency filter 502 includes a capacitor Cf2 connected to the common terminal 503, a capacitor Cf3 connected between the capacitor Cf2 and the high frequency terminal 505, and a connection point between the capacitors Cf2 and Cf3 and the ground. It is formed by a direct resonance circuit composed of a connected transmission line Lf3 and a capacitor Cf4.
  • the transmission lines Lf1 to Lf3 and the capacitors Cf1 to Cf4 forming the low frequency filter 501 and the high frequency filter 502 are built in the laminated substrate as electrode patterns, but the duplexer 500 is further downsized. Therefore, the following problems may occur when the electrode patterns are arranged close to each other and incorporated in the multilayer substrate. That is, the circuit pattern (transmission line Lf3, capacitors Cf2 to Cf4) forming the circuit element (transmission line Lf3, capacitors Cf2 to Cf4) forming the high frequency filter 502 is configured. If the electrode patterns to be arranged are opposed to each other with the dielectric layer of the laminated substrate interposed therebetween, parasitic capacitance may be generated between the two electrode patterns, and the two electrode patterns may be coupled electromagnetically.
  • the electrode pattern constituting the transmission line Lf1 forming the low frequency filter 501 and the electrode pattern constituting the capacitor Cf2 forming the high frequency filter 501 are electromagnetic It arrange
  • the electrode patterns that form both filters 501 and 502 are arranged so as not to overlap in the stacking direction of the stacked substrate, the generation of parasitic capacitance between the two electrode patterns is suppressed. It is possible to prevent the two electrode patterns from being electromagnetically coupled, to reduce the size of the duplexer 500, and to improve the isolation characteristics between the filters 501 and 502.
  • a transmission filter element 601 and a reception filter element 602 having different pass bands are mounted on a mounting substrate 603, and the transmission filter element 601 and the reception filter element 602 are mounted.
  • a duplexer 600 formed by being protected by a resin mold layer 604 is also known.
  • the wiring electrode 606 connected to the transmission terminal 605 that is the input side of the transmission filter element 601 the wiring electrode 608 that is connected to the common terminal 607 that is the output side, and the output side of the reception filter element 602.
  • a wiring electrode 610 connected to the receiving terminal 609, a ground electrode 612 connected to the ground terminal 611 of the receiving filter element 602, and the like are built in the mounting substrate 603.
  • the duplexer 600 As described above, parasitic capacitance is generated between the wiring electrodes 606, 608, 610, and the wiring electrodes 606, 608, 610 are electromagnetically coupled, thereby transmitting the filter element 601.
  • the wiring electrodes 606, 608, and 610 for signal transmission are arranged so as not to overlap in the stacking direction of the stacked substrate 603.
  • a part of the configuration such as the wiring electrode is omitted for easy explanation.
  • a grounding ground electrode having a large-area flat pattern shape is provided on the multilayer substrate or the mounting substrate 603. ing.
  • a ground electrode for grounding having a large-area flat pattern shape in a laminated substrate or a mounting substrate, the following problems may occur.
  • the ground electrode 612 having a flat pattern shape with a large area is arranged on the mounting substrate 603 so as to overlap the signal transmission wiring electrodes 608 and 610 in plan view. . Therefore, as shown in a region surrounded by a dotted line in FIG. 11, parasitic capacitance is generated between the wiring electrode 608 and the ground electrode 612 facing each other with the dielectric layer of the mounting substrate 603 interposed therebetween, and the wiring electrode 608 is formed.
  • the ground electrode 612 is electromagnetically coupled, a signal transmitted by the wiring electrode 608 may leak to the ground electrode 612.
  • the ground electrode 612 is ideal due to a parasitic inductance generated in the via conductor 612a connected to the ground electrode 612 and the like. There is a possibility that it is not grounded. In this case, a signal leaking from the wiring electrode 608 to the ground electrode 612 is transmitted to the wiring electrode 610 connected to the reception terminal 609 of the reception filter element 602 via the ground electrode 612, whereby the transmission filter element 601 and the reception filter 601 are received. There is a possibility that the isolation characteristics between the filter elements 602 may be deteriorated, and improvement of the technique has been demanded.
  • the present invention has been made in view of the above-described problems, and an object thereof is to provide a technique capable of improving the isolation characteristics between the first and second filter elements included in the duplexer. .
  • a duplexer includes a first filter element and a second filter element having different pass bands, and a mounting substrate on which the first and second filter elements are mounted. And first and second wiring electrodes for signal transmission and first and second ground electrodes for grounding provided respectively for the first and second filter elements on the mounting substrate, The first ground electrode connected to the ground terminal of the first filter element and the second wiring electrode connected to the signal terminal of the second filter element do not overlap in a plan view. It is characterized by being arranged (Claim 1).
  • first ground electrode and the second ground electrode connected to the ground terminal of the second filter element are disposed in an electrically insulated state ( Claim 2).
  • the second filter element includes a transmission filter for a transmission signal, and the second filter element includes a transmission terminal connected to the input side of the transmission filter and a common terminal connected to the output side.
  • the second wiring electrode is a transmission electrode connected to the transmission terminal and a common electrode connected to the common terminal of the second filter element (Claim 3).
  • the second wiring electrode further includes a pattern electrode that forms a filter circuit connected to the transmission terminal (claim 4).
  • the first wiring electrode is connected to a signal terminal of the first filter element, the first filter element includes a reception signal reception filter, and the first filter element includes: A common terminal connected to the input side of the reception filter and a reception terminal connected to the output side are provided as the signal terminals of the first filter element, and the first wiring electrode is the first wiring electrode A common electrode connected to a common terminal of the filter element and a reception electrode connected to the reception terminal, wherein the common electrode of the first wiring electrode and the common electrode of the second wiring electrode are electrically And the first ground electrode is disposed between the transmission electrode and the common electrode of each of the first and second wiring electrodes and the reception electrode in plan view.
  • the first ground electrode leaks a transmission signal for communication with a large output that transmits the common electrode of each of the transmission electrode and the first and second wiring electrodes to the reception electrode. Therefore, the isolation characteristic between the first and second filter elements can be further improved.
  • the first filter element is provided with a plurality of ground terminals, and the first ground electrode is a flat plate disposed so as to overlap the ground terminals of the first filter element in plan view. It has the pattern shape of (6).
  • the mounting board further includes a plurality of mounting electrodes provided on the back surface of the mounting substrate, and some of the mounting electrodes connected to the first ground electrode are larger than the other mounting electrodes.
  • the first ground electrode and the part of the mounting electrodes have an area and are electrically connected by a plurality of via conductors (Claim 7). For example, by disposing a part of the mounting electrode having a large area between the plurality of other mounting electrodes connected to the first and second wiring electrodes, the electric power between the plurality of other mounting electrodes can be reduced. Interference can be suppressed.
  • the first ground electrode connected to the ground terminal of the first filter element and the second wiring electrode connected to the signal terminal of the second filter element overlap in plan view. Therefore, the generation of parasitic capacitance between the first ground electrode and the second wiring electrode is suppressed, and the first ground electrode and the second wiring electrode are electromagnetically coupled. Can be prevented. Therefore, the signal transmitted through the second wiring electrode is prevented from leaking to the first ground electrode, and the signal transmitted through the second wiring electrode is transmitted to the first wiring electrode via the first ground electrode. Since transmission can be prevented, the isolation characteristics between the first and second filter elements provided in the duplexer can be improved.
  • FIG. 1st Embodiment of the splitter of this invention It is a block diagram which shows the internal structure of the splitter of FIG. It is a top view which shows an example of the electrode shape of the board
  • FIG. 1 is a diagram showing a first embodiment of a duplexer according to the present invention.
  • FIG. 2 is a block diagram showing the internal configuration of the duplexer of FIG.
  • FIG. 3 is a plan view showing an example of the electrode shape of the mounting substrate.
  • FIGS. 3A to 3C show the electrode shapes of the dielectric layers of the mounting substrate, respectively.
  • FIG. 4 is a view showing a state in which the electrode shapes in the respective dielectric layers of the mounting substrate shown in FIG.
  • the duplexer 1 is used to separate a transmission signal and a reception signal having different frequencies, and a circuit such as a high-frequency antenna switch module mounted on a mother board or the like included in a communication portable terminal such as a mobile phone or a portable information terminal. Implemented in the module. Then, by mounting the circuit module on which the duplexer 1 is mounted on a mother board or the like, various signal lines such as an antenna line ANT, a ground line GND, a reception signal line Rx, and a transmission signal line Tx provided on the mother board or the like. The power supply line and the duplexer 1 are connected, and transmission / reception signals are input / output between the mother board and the duplexer 1.
  • the duplexer 1 includes a reception filter element 2 (corresponding to a “first filter element” of the present invention) and a transmission filter element 3 (corresponding to the present invention) having different high-frequency signal passbands.
  • a reception filter element 2 corresponds to a “first filter element” of the present invention
  • a transmission filter element 3 correspond to the present invention having different high-frequency signal passbands.
  • LPF low-pass filter
  • the reception filter element 2 and the transmission filter element 3 include a reception filter for reception signals and a transmission filter for transmission signals, respectively.
  • the reception filter element 2 and the transmission filter element 3 are each formed by a SAW (surface acoustic wave) filter element.
  • the reception filter element 2 has a balanced output type reception filter. .
  • the reception filter element 2 is provided with a common terminal 21 (antenna terminal) connected to the input side of the reception filter and a reception terminal 22 connected to the output side as signal terminals, and the ground terminal 23 is a ground terminal. It is provided as.
  • the transmission filter element 3 is provided with a transmission terminal 31 connected to the input side of the transmission filter and a common terminal 32 (antenna terminal) connected to the output side as a signal terminal, and a ground terminal 33 is a ground terminal. It is provided as.
  • the reception filter element 2 and the transmission filter element 3 included in the duplexer 1 are formed by SAW filter elements.
  • SAW filter elements a plurality of resonators and coils are connected.
  • the reception filter and the transmission filter may be formed, and if the transmission signal and the reception signal having different frequencies can be reliably demultiplexed, the reception filter element 2 and the transmission filter element 3 may be a dielectric filter, Any device such as a BAW filter element may be used.
  • the LPF 4 is connected to the transmission terminal 31 of the transmission filter element 3 and filters the transmission signal input from the transmission signal line Tx. That is, the output of the transmission signal input to the transmission filter element 3 via the transmission signal line Tx is amplified by a power amplifier for communication, and second-order or higher harmonic components included in the transmission signal are also amplified by the power amplifier. It is amplified by. Accordingly, the LPF 4 attenuates second-order or higher harmonic components included in the transmission signal amplified by the power amplifier.
  • the mounting substrate 5 is integrally formed as a ceramic laminate by laminating and firing a plurality of dielectric layers 51 to 53 formed of ceramic green sheets.
  • the ceramic green sheets forming the respective dielectric layers 51 to 53 are obtained by forming a sheet in which a slurry in which a mixed powder such as alumina and glass is mixed with an organic binder and a solvent is formed by a molding machine. It is formed so that it can be fired at a low temperature of about 1000 ° C. at a so-called low temperature. Then, via holes are formed in the ceramic green sheet cut into a predetermined shape by laser processing or the like, and the formed via holes are filled with a conductive paste containing Ag, Cu, etc. Via conductors are formed, and various electrode patterns are formed by printing with a conductor paste to form the dielectric layers 51 to 53.
  • via conductors and electrode patterns are appropriately formed in each of the dielectric layers 51 to 53, so that a signal transmission second layer provided for the reception filter element 2 and the transmission filter element 3 respectively on the mounting substrate 5 is provided.
  • the first and second wiring electrodes 7 and 8 and the first and second ground electrodes 9 and 10 are built in, and a plurality of mounting electrodes 11 are formed on the back surface of the mounting substrate 5.
  • electrode patterns and via conductors are appropriately provided in the dielectric layers 51 to 53, and the first and second wiring electrodes 7, 8, the first and second ground electrodes 9, 10 and the mounting electrode 11 are provided.
  • the reception filter element 2 and the transmission filter element 3 mounted on the mounting substrate 5 and the mounting electrode 11 are electrically connected to each other.
  • circuit elements such as capacitors and coils are formed by the electrode patterns and via conductors formed in the respective dielectric layers 51 to 53, and LPF 4 and the like are formed by the formed circuit elements such as capacitors and coils.
  • a filter circuit, a matching circuit, or the like may be formed.
  • the first wiring electrode 7 for signal transmission of the reception filter element 2 has a common electrode 71 connected to the common terminal 21 of the reception filter element 2 and a reception electrode 72 connected to the reception terminal 22.
  • the second wiring electrode 8 for signal transmission of the transmission filter element 3 is connected to the transmission electrode 81 connected to the transmission terminal 31 of the transmission filter element 3, the common electrode 82 connected to the common terminal 32, and the transmission terminal 31.
  • the pattern electrode 83 for forming the LPF 4 is provided.
  • a coil is formed by the pattern electrode 83, and the LPF 4 is formed by a capacitor (not shown) built in the transmission filter element 3 and a coil formed by the pattern electrode 83.
  • the common electrode 71 of the first wiring electrode 7 and the common electrode 82 of the second wiring electrode 7 formed on the dielectric layer 51 are electrically formed by being formed with the same electrode pattern. (See FIG. 3A).
  • the reception filter element 2 and the transmission filter element 3 are provided with a plurality of ground terminals 23 and 33, respectively.
  • the ground terminals 23 and 33 are respectively connected to the first and second ground electrodes 9 and 10, respectively. Grounded.
  • the mounting electrode 11 includes a mounting common electrode 11a, a mounting receiving electrode 11b, a mounting transmitting electrode 11c, mounting ground electrodes 11d and 11e, and a mounting unconnected electrode 11f (see FIG. 3 (c)).
  • the mounting common electrode 11a is connected to the common terminals 21 and 32 of the reception filter element 2 and the transmission filter element 3 via the common electrodes 71 and 82, respectively.
  • the mounting receiving electrode 11 b is connected to the receiving terminal 22 of the receiving filter element 2 via the receiving electrode 72.
  • the mounting transmission electrode 11 c is connected to the transmission terminal 31 of the transmission filter element 3 via the transmission electrode 81 and the pattern electrode 83.
  • the mounting ground electrode 11d is connected to the ground terminal 23 of the reception filter element 2 via the first ground electrode 9, and the mounting ground electrode 11e is connected to the ground terminal 33 of the transmission filter element 3 and the second ground. It is connected via the electrode 10. Further, the mounting unconnected electrode 11f is provided on the back surface of the mounting substrate 5 in order to improve mounting strength when the duplexer 1 is mounted on the module substrate of the circuit module.
  • the pattern electrode 84 that connects the second ground electrode 10 to which the ground terminal 33 of the transmission filter element 3 is connected and the mounting ground electrode 11 e is the second wiring electrode 8. It is provided on the dielectric layer 52 (see FIG. 3B).
  • a coil is formed by forming a coil with the pattern electrode 84, and an attenuation pole that improves the attenuation characteristic of the transmission filter of the transmission filter element 3 is formed by the resonator configured with the pattern electrode 84.
  • the electrodes formed by the same electrode pattern formed in each of the dielectric layers 51 to 53 are a plurality of electrodes corresponding to the respective electrodes formed by the same electrode pattern. Reference numerals are assigned to the same electrode pattern. Further, in FIG. 3, only the first and second wiring electrodes 7 and 8, the first and second ground electrodes 9 and 10 and the mounting electrode 11 and main via conductors are shown for easy explanation. The other electrodes and via conductors are not shown. Further, only the arrangement position of the via conductor is indicated by a circle.
  • the mounting electrode 11 is actually provided on the back surface of the dielectric layer 53, but in FIG. 3C, it is provided on the dielectric layer 53.
  • the mounting positions of the mounting electrodes 11 in plan view are indicated by solid lines. Note that FIGS. 5 to 8 used in the following description are also illustrated in the same manner as in FIG.
  • the first dielectric layer 51 which is the mounting surface of the mounting substrate 5, is connected to the common terminal 21 when the reception filter element 2 is mounted.
  • a common electrode 71, a receiving electrode 72 to which the receiving terminal 22 is connected, and a first ground electrode 9 to which the ground terminal 23 is connected are formed.
  • the first ground electrode 9 has a flat pattern shape formed by cutting out the center portion of the substantially convex base portion, and the convex portion on the right side of the dielectric layer 51 in FIG. Are arranged so as to overlap each ground terminal 23 of the reception filter element 2 in plan view.
  • the plurality of ground terminals 23 of the reception filter element 2 are connected to the position G1 of the first ground electrode 9, respectively.
  • the common electrode 71 has a crank-shaped pattern shape, and is disposed substantially below the center of the dielectric layer 51 of FIG. 3A. In a plan view, the crank-shaped piece portion is a first ground electrode. It is arrange
  • the common terminal 21 of the reception filter element 2 is connected to the position A1 of the common electrode 71.
  • the receiving electrode 72 has a rectangular shape with a tongue-shaped portion, and two receiving electrodes 72 are arranged on the right side of the dielectric layer 51 in FIG. It is arrange
  • the two reception terminals 22 of the reception filter element 2 are connected to the position R1 of the reception electrode 72, respectively.
  • a second ground electrode 10 to which 82 and the ground terminal 33 are connected is formed.
  • Three second ground electrodes 10 are disposed on the dielectric layer 51 in FIG. 3A, and one second ground electrode 10 is disposed on the upper side of the approximate center of the dielectric layer 51 in FIG. A ground electrode 10 is disposed, and two second ground electrodes 10 are disposed vertically on the left side of the dielectric layer 51.
  • the plurality of ground terminals 33 of the transmission filter element 3 are connected to the position G2 of the second ground electrode 10, respectively. Further, an unconnected terminal (not shown) of the transmission filter element 3 is connected to the position NC2 of the second ground electrode 10.
  • the transmission electrode 81 has a shape in which a rectangular line-shaped extending portion is provided, and is disposed in the upper left portion of the dielectric layer 51 in FIG. 3A.
  • the transmission terminal 31 of the transmission filter element 3 is , Connected to the position T2 of the transmission electrode 81.
  • the common electrode 81 is formed by the same electrode pattern as the common electrode 71, and the common terminal 32 of the transmission filter element 3 is connected to the position A ⁇ b> 2 of the common electrode 81.
  • the dielectric layer 52 disposed below the dielectric layer 51 has the same electrode pattern having a substantially L-shaped flat pattern arranged on the right side.
  • First and second ground electrodes 9 and 10 are formed.
  • the first and second ground electrodes 9 and 10 of the dielectric layer 52 are arranged so as to substantially overlap with the first and second ground electrodes 9 and 10 to which the dielectric layer 51 is hatched. ing.
  • the first and second ground electrodes 9, 10 of the dielectric layer 52 and the first and second ground electrodes 9, 10 to which the dielectric layer 51 is hatched are electrically connected by via conductors. ing.
  • the first and second ground electrodes 9 and 10 disposed on the dielectric layers 51 and 52 are formed as large as possible to be connected to the first and second ground electrodes 9 and 10.
  • the ground state of the ground terminal 23 of the second filter element 2 can be made favorable.
  • two rod-shaped receiving electrodes 72 are arranged vertically on the right side of the dielectric layer 52, and the two receiving electrodes 72 and via conductors arranged on the right side of the dielectric layer 51, respectively. Are electrically connected.
  • common electrodes 71 and 82 are formed by the same rod-shaped electrode pattern disposed substantially below the center of the dielectric layer 52, and the common electrodes 71 and 82 of the dielectric layer 51 and via conductors are used. Electrically connected. As shown in FIG.
  • the common electrodes 71 and 82 and the first and second ground electrodes 9 and 10 are arranged as far apart as possible, so that the dielectric layer
  • the transmission signal transmitted through the 52 common electrodes 71 and 82 is prevented from leaking to the first and second ground electrodes 9 and 10 of the dielectric layer 52.
  • a spiral pattern electrode 83 is disposed in the upper left portion of the dielectric layer 52 and is electrically connected to the transmission electrode 81 of the dielectric layer 51 by a via conductor.
  • a substantially U-shaped pattern electrode 84 is disposed in the lower left portion of the dielectric layer 52, and is electrically connected to the second ground electrode 10 disposed in the lower left portion of the dielectric layer 51 and via conductors.
  • a rod-shaped second ground electrode 10 is disposed on the left side of the dielectric layer 52, and the ground electrode 10 is disposed on the left side of the dielectric layer 51 and is not connected to the transmission filter element 3. The second ground electrode 10 connected to the terminal is electrically connected to the via conductor.
  • a plurality of mounting ground electrodes 11d and 11e are disposed on the back surface of the dielectric layer 53 disposed below the dielectric layer 52.
  • some of the mounting ground electrodes 11d and 11e that are disposed near the upper and lower right portions of the center of the dielectric layer 53 and are hatched are dielectric
  • the first and second ground electrodes 9 and 10 to which the layer 52 is hatched are electrically connected by via conductors.
  • the center The mounting ground electrodes 11d and 11e provided on the upper side have a larger area than the other mounting electrodes 11, and the first and second dielectric layers 52 are hatched by a plurality of via conductors.
  • the two ground electrodes 9 and 10 are electrically connected. If comprised in this way, the grounding state of the 1st, 2nd ground electrodes 9 and 10 provided in the dielectrics 51 and 52 connected to the said mounting electrodes 11d and 11e can be made favorable. .
  • the mounting ground electrode 11e provided in the lower left portion of the dielectric layer 53 is electrically connected to the pattern electrode 84 of the dielectric layer 52 by a via conductor.
  • a mounting common electrode 11a is disposed substantially below the center of the dielectric layer 53, and is electrically connected to the common electrodes 71 and 82 of the dielectric layer 52 by via conductors.
  • two mounting receiving electrodes 11b are arranged one above the other in the upper right portion of the dielectric layer 53, and the two receiving electrodes 72 and via conductors provided in the upper right portion of the dielectric layer 52, respectively. Are electrically connected.
  • a mounting transmission electrode 11c is disposed on the upper left portion of the dielectric layer 53, and is electrically connected to the pattern electrode 83 of the dielectric layer 52 by a via conductor. Further, the mounting unconnected electrode 11f is disposed on the left side of the approximate center of the dielectric layer 53, and is formed by the second ground electrode 10 and the via conductor disposed on the left side of the approximate center of the dielectric layer 52. Electrically connected.
  • each hatched electrode is a first ground. It is electrically connected to the electrode 9.
  • the transmission electrode 81, the pattern electrode 83, and the mounting transmission electrode 11c filled with dots transmit the transmission signal before being subjected to the filtering process by the transmission filter, and the common electrodes 71 and 82 filled with dots and In the mounting common electrode 11a, the transmission signal after being subjected to the filter processing by the transmission filter is transmitted.
  • each electrode electrically connected to the first ground electrode 9 and hatched, common electrodes 71 and 82 filled with a point where a transmission signal is transmitted, and transmission electrodes 81, the pattern electrode 83, the mounting common electrode 11a, and the mounting transmitting electrode 11c are arranged without overlapping in a plan view (see a region ⁇ surrounded by a dotted line in FIG. 1).
  • each hatched electrode electrically connected to the first ground electrode 9 has a common electrode 71, 82, a transmission electrode 81, a pattern filled with a transmission signal in a plan view.
  • the electrode 83, the mounting common electrode 11a, the mounting transmission electrode 11c, and the reception electrode 72 are disposed.
  • a via hole is formed in a ceramic green sheet formed in a predetermined shape with a laser or the like, and a via conductor for interlayer connection is formed by filling the inside with a conductive paste or by performing via fill plating.
  • Electrode patterns such as the two wiring electrodes 7 and 8, the first and second ground electrodes 9 and 10 and the mounting electrode 11 are printed with a conductive paste, and the dielectric layers 51 to 53 constituting the mounting substrate 5 are printed.
  • a ceramic green sheet for forming the is prepared. Each ceramic green sheet has via conductors, first and second wiring electrodes 7 and 8, first and second ground electrodes 9, so that a large number of mounting substrates 5 can be formed at one time.
  • a plurality of electrode patterns such as 10 and mounting electrodes 11 are provided.
  • the dielectric layers 51 to 53 are laminated to form a laminated body. And the groove
  • the reception filter element 2 and the reception filter element 3 are mounted on the mounting surface of the assembly of the mounting substrates 5, and the reception filter element 2 and the reception filter element 3 are
  • the mounting surface of the assembly of the mounted mounting substrates 5 is filled with mold resin, and this is heated and cured, whereby the mold layer 6 is provided on each mounting substrate 5 to form an assembly of the duplexer 1. Is done.
  • the aggregate of the duplexers 1 is individually divided, and the duplexer 1 is completed.
  • the transmission signal output from the transmission signal line Tx of the mother board to the transmission terminal 31 of the transmission filter element 3 via the LPF 4 and the transmission electrode 81 is input to the transmission filter. Then, a predetermined filtering process is performed, the signal is output from the common terminal 32 to the mounting substrate 5 side, and is output to the antenna line ANT of the mother substrate via the common electrode 82. Further, the reception signal input from the antenna line ANT of the mother board to the common terminal 21 of the reception filter element 2 via the common electrode 71 is input to the reception filter and subjected to a predetermined filtering process. Is output to the mounting substrate 5 side and is output to the reception signal line Rx of the mother substrate via the reception electrode 72 and the mounting reception electrode 11b.
  • the duplexer 1 is not limited to the above-described manufacturing method, and may be formed by a known general manufacturing method.
  • the mounting substrate 5 is a printed circuit board, LTCC using resin, ceramic, polymer material, or the like.
  • the substrate 5 can be formed of an alumina substrate, a glass substrate, a composite material substrate, a multilayer substrate, etc., and the mounting substrate 5 may be formed by selecting an optimal material according to the purpose of use of the duplexer 1. .
  • the mounting substrate 5 on which the reception filter element 2 and the transmission filter element 3 having different pass bands are mounted has a signal transmission first for the reception filter element 2 and the transmission filter element 3.
  • first wiring electrodes 7 and 8 and first and second ground electrodes 9 and 10 for grounding are provided, respectively.
  • the first ground electrode 9 connected to the ground terminal 23 of the reception filter element 2 and the second wiring electrode 8 connected to the transmission terminal 31 and the common terminal 32 of the transmission filter element 3 are in plan view. Since they are arranged without overlapping, the generation of parasitic capacitance between the first ground electrode 9 and the second wiring electrode 8 is suppressed, and the first ground electrode 9 and the second wiring electrode 8 are Electromagnetic coupling can be prevented.
  • the transmission filter element 3 is provided with a transmission terminal 31 connected to the input side of the transmission filter and a common terminal 32 connected to the output side as signal terminals.
  • the second wiring electrode 8 has a transmission electrode 81 connected to the transmission terminal 31 and a common electrode 82 connected to the common terminal 32, and the transmission electrode 81 and the common electrode 82 provide power for communication.
  • the first ground electrode 9, the transmission electrode 81, and the common electrode 82 are arranged so as not to overlap each other in plan view, so that the first ground electrode 9 is transmitted. 9 is prevented from being generated between the transmission electrode 81 and the common electrode 82, and the first ground electrode 9, the transmission electrode 81, and the common electrode 82 are prevented from being electromagnetically coupled. be able to.
  • a transmission signal input to the transmission filter of the transmission filter element 3 is provided. Filter processing by various filter circuits can be performed.
  • the pattern electrode 83 forming the filter circuit is arranged so as not to overlap the first ground electrode 9 in plan view, a parasitic capacitance is generated between the first ground electrode 9 and the pattern electrode 83. Therefore, the first ground electrode 9 and the pattern electrode 83 can be prevented from being electromagnetically coupled.
  • the first ground electrode 9 is disposed between the transmission electrode 81 and the common electrodes 71 and 82 and the reception electrode 72 in plan view, the first ground electrode 9 that is grounded transmits the first ground electrode 9. Since the transmission signal for communication having a large output transmitted through the electrode 31 and the common electrodes 71 and 82 is prevented from leaking to the reception electrode 72, further isolation characteristics between the reception filter element 2 and the transmission filter element 3 are obtained. Can be improved.
  • the reception filter element 2 is provided with a plurality of ground terminals 23, and has a large area of the first area having a flat pattern shape that is arranged so as to overlap each ground terminal 23 of the reception filter element 2 in plan view. Since each ground terminal 23 of the reception filter element 2 is grounded by the ground electrode 9, the grounding state of the reception filter element 2 can be improved, so that the reception filter element 2 and the transmission filter element 3 are connected to each other. Isolation characteristics can be improved.
  • some of the mounting electrodes 11 e connected to the first ground electrode 9 are larger than the other mounting electrodes 11. Since it has an area, for example, a part of the mounting electrode 11e having a large area is arranged between a plurality of other mounting electrodes 11 connected to the first and second wiring electrodes 7 and 8. Thus, electrical interference between the plurality of other mounting electrodes 11 can be suppressed.
  • first ground electrode 9 and a part of the mounting electrode 11e having a large area are electrically connected by a plurality of via conductors, so that the parasitic inductance generated in the plurality of via conductors can be reduced.
  • the first ground electrode 9 can be grounded in an ideal state.
  • FIG. 5 is a plan view showing an example of the electrode shape of the mounting substrate in the second embodiment of the present invention
  • FIGS. 5A to 5C show the electrode shapes in the respective dielectric layers of the mounting substrate.
  • FIG. 6 is a plan view showing a modification of the electrode shape of the mounting substrate.
  • this embodiment is different from the first embodiment described above in that the shape of each electrode provided on each dielectric layer 51 to 53 of the mounting substrate and a part of the arrangement position are different. Since the other configuration is the same as that of the first embodiment, description of the configuration is omitted by giving the same reference numerals.
  • the second ground electrode 10 disposed substantially above the center of the dielectric layer 51 is divided into two parts and disposed on the upper side.
  • the ground terminal 33 of the transmission filter element 3 is connected to the position G2 of the second ground electrode 10, and the unconnected terminal of the transmission filter element 3 is connected to the position NC2 of the second ground electrode 10 arranged on the lower side.
  • the second ground electrode 10 is disposed in the lower left portion of the dielectric layer 51 with an electrode pattern formed so as to be long in the vertical direction.
  • a ground terminal 33 is connected.
  • the mounting electrodes 11 arranged on the back surface of the dielectric layer 53 are arranged point-symmetrically with the center of gravity of the duplexer 1 as the rotation center in plan view. Yes.
  • each mounting electrode 11 is arranged point-symmetrically with the center of gravity of the duplexer 11 as the center of rotation. Therefore, when the duplexer 1 is mounted on the module substrate of the circuit module, the duplexer 1 is prevented from tilting. Therefore, mountability such as mounting accuracy and mounting strength when the duplexer 1 is mounted on the module substrate of the circuit module can be improved.
  • each mounting electrode 11 formed on the back surface of the dielectric layer 53 may be formed identically. If it does in this way, when mounting the splitter 1, the design of the mask for solder printing used when printing a solder paste can be made easy. Further, when the duplexer 1 is mounted on the module substrate of the circuit module, the stress applied to the mounting surface between the duplexer 1 and the module substrate due to impact caused by dropping or expansion / contraction of the substrate accompanying heating and cooling, It can be uniformly dispersed in each mounting electrode 11.
  • a notch 11 g may be provided in a part of the mounting electrodes 11 formed on the back surface of the dielectric layer 53, or a recognition mark 11 h may be provided on the back surface of the dielectric layer 53.
  • the mounting electrodes 11 are formed in the same shape and the same size on the back surface of the duplexer 1 (dielectric layer 53), and the mounting electrodes 11 are point-symmetric. Even if it is arranged, it is possible to recognize the vertical direction in plan view of the duplexer 1 by recognizing the notch 11g or the recognition mark 11h, so each mounting electrode formed on the back surface of the duplexer 1 11 electrode characteristics can be recognized without error.
  • FIG. 7 is a plan view showing an example of the electrode shape of the mounting substrate according to the third embodiment of the present invention.
  • FIGS. 7A to 7C show the electrode shapes in the respective dielectric layers of the mounting substrate.
  • This embodiment is different from the second embodiment described above in that, as shown in FIG. 7, the shape of each electrode provided on each dielectric layer 51 to 53 of the mounting substrate and a part of the arrangement position are different. Since other configurations are the same as those in the first and second embodiments described above, description of the configuration is omitted by giving the same reference numerals.
  • 11d and 11e and the mounting common electrode 11a disposed on the lower side are formed to be larger than the areas of the other mounting electrodes 11.
  • the mounting ground electrodes 11d and 11e which are disposed substantially above the center of the dielectric layer 51, in a large area, the mounting ground electrodes 11d and 11e and the dielectric layer 52 are disposed. Since the first and second ground electrodes 9 and 10 can be electrically connected by a plurality of via electrodes, the same effects as those of the first embodiment described above can be obtained.
  • the common electrodes 71 and 82 of the dielectric layer 51 and the mounting of the dielectric layer 53 are mounted. As shown in FIG. 7B, the common electrode 11a can be electrically connected by the common electrodes 71 and 82 of the dielectric layer 52 formed by via conductors. Therefore, the influence of electromagnetic noise can be reduced by electrically connecting the common electrodes 71 and 82 of the dielectric layer 51 and the mounting common electrode 11a of the dielectric layer 53 through the shortest path. .
  • FIG. 8 is a plan view showing an example of the electrode shape of the mounting substrate in the fourth embodiment of the present invention
  • FIGS. 8A to 8C show the electrode shapes in the respective dielectric layers of the mounting substrate.
  • This embodiment is different from the first embodiment described above in that, as shown in FIG. 8, the shape of each electrode provided on each dielectric layer 51 to 53 of the mounting substrate and a part of the arrangement position are different. Since the other configuration is the same as that of the first embodiment, description of the configuration is omitted by giving the same reference numerals.
  • common electrodes 71 and 82 are disposed at substantially the center of the dielectric layer 51, and the common terminal 21 of the reception filter element 2 and the transmission filter element 3 are common.
  • the terminal 32 is connected to the positions A1 and A2 of the common electrodes 71 and 82, respectively.
  • the mounting common electrode 11a is disposed at substantially the center of the dielectric layer 53 in correspondence with the positions of the common electrodes 71 and 82 of the dielectric layer 51.
  • the common electrodes 71 and 82 of the body layer 51 and the mounting common electrode 11 of the dielectric layer 53 include the common electrodes 71 and 82 disposed substantially at the center of the dielectric layer 52 as shown in FIG. Electrically connected.
  • FIG. 9 is a plan view showing an example of the electrode shape of the mounting substrate according to the fifth embodiment of the present invention.
  • FIGS. 9A to 9C show the electrode shapes in the respective dielectric layers of the mounting substrate.
  • This embodiment differs from the first embodiment described above in that, as shown in FIG. 9, the shape of each electrode provided on each dielectric layer 51 to 53 of the mounting substrate and a part of the arrangement position are different. Since the other configuration is the same as that of the first embodiment, description of the configuration is omitted by giving the same reference numerals.
  • the second ground electrode 10 disposed substantially above the center of the dielectric layer 51 is divided into two parts and is disposed on the upper side.
  • the ground terminal 33 of the transmission filter element 3 is connected to the position G2 of the second ground electrode 10, and the unconnected terminal of the transmission filter element 3 is connected to the position NC2 of the second ground electrode 10 arranged on the lower side.
  • the ground terminal 33 of the transmission filter element 3 is connected to the position G2 of the second ground electrode 10 disposed on the left side of the approximate center of the dielectric layer 51.
  • two second ground electrodes 10 are arranged vertically above the approximate center of the dielectric layer 52. Then, the second ground electrode 10 disposed on the upper side of the two second ground electrodes 10 disposed substantially above the center of the dielectric layer 51 by the upper second ground electrode 10. Are electrically connected to the mounting ground electrode 11e disposed substantially above the center of the dielectric layer 53. In addition, the second ground electrode 10 disposed on the lower side of the two second ground electrodes 10 disposed substantially above the center of the dielectric layer 51 by the second ground electrode 10 on the lower side. The electrode 10 is electrically connected to the mounting unconnected electrode 11f disposed substantially at the center of the dielectric layer 53.
  • the first ground electrode 9 and the second ground electrode 10 are arranged in an electrically insulated state. Therefore, even if signals transmitted through the first and second wiring electrodes 7 and 8 leak to the first and second ground electrodes 9 and 10, respectively, the first and second ground electrodes 9 and 10 are electrically connected. Since the first and second ground electrodes 9 and 10 are prevented from being transmitted to the other ground electrodes, the first and second ground electrodes 9 and 10 are prevented from being transmitted to each other. The isolation characteristics between the filter elements 2 and 3 can be further improved.
  • the ground terminal 33 and the unconnected terminal of the transmission filter element 3 are electrically insulated from each other, and the mounting ground electrode 11e and the mounting ground electrode provided on the back surface of the dielectric layer 53, respectively. It is electrically connected to the unconnected electrode 11f. Therefore, the common terminals 21 and 32, the reception terminal 22, the transmission terminal 31, the ground terminal 23 of the reception filter element 2, and the ground terminal 33 of the transmission filter element 3 are electrically insulated from each other. Since the respective electrodes 11 are electrically connected to the mounting electrodes 11 provided on the back surface of the dielectric layer 53, respectively, electrical mutual interference between the terminals can be reduced. The isolation characteristics between the filter elements 2 and 3 can be further improved.
  • the present invention is not limited to the above-described embodiment, and various modifications other than those described above can be made without departing from the spirit of the present invention.
  • the first filter element of the present invention is formed by the reception filter element 2
  • the second filter element of the present invention is formed by the transmission filter element 3
  • the first and second filters The elements may be formed by the transmission filter element 3 and the reception filter element 2, respectively.
  • the present invention can be widely applied to a duplexer including a first filter element and a second filter element having different pass bands.

Abstract

Provided is a technology enabling improved isolation characteristics between a first and a second filter element provided to a demultiplexer. A first ground electrode (9) connected to a grounding terminal (23) of a reception filter element (2), and a second wiring electrode (8) connected to a transmission element (31) and common terminal (32) of a transmission filter element (3), are arranged without overlapping in plan view, and thus the occurrence of parasitic capacitance between the first ground electrode (9) and the second wiring electrode (8) is suppressed; magnetic combination of the first ground electrode (9) and second wiring electrode (8) can be prevented; and a transmission signal transmitted through the second wiring electrode (8) can be prevented from be transmitted via the first ground electrode (9) to a first wiring electrode (7). This makes it possible to improve isolation characteristics between the reception filter element (2) and the transmission filter element (3) provided to the demultiplexer (1).

Description

分波器Duplexer
 本発明は、通過帯域が異なる第1のフィルタ素子および第2のフィルタ素子を備える分波器に関する。 The present invention relates to a duplexer including a first filter element and a second filter element having different pass bands.
 近年、GSM(Global System for Mobile Communications)規格やCDMA(Code Division Multiple Access)規格などの複数の通信規格による通信をサポートする携帯電話や携帯情報端末などの通信携帯端末が急速に普及しており、これらの通信携帯端末では、共通のアンテナを用いて異なる周波数帯域の信号の送受信が行われる。したがって、周波数の異なる送信信号および受信信号を分波する分波器の更なる高性能化および小型化の要求が高まっている。 In recent years, mobile communication terminals such as mobile phones and personal digital assistants that support communication based on multiple communication standards such as the GSM (Global System for Mobile Communications) standard and the CDMA (Code Division Multiple Access) standard are rapidly spreading. In these communication portable terminals, signals in different frequency bands are transmitted and received using a common antenna. Therefore, there is an increasing demand for further enhancement in performance and size of the duplexer that demultiplexes transmission signals and reception signals having different frequencies.
 例えば、特許文献1に記載された図10に示す従来の分波回路500は、低周波側フィルタ501および高周波側フィルタ502を備えている。また、低周波側フィルタ501は、共通端子503に接続された伝送線路Lf1と、低周波側端子504とグランドとの間に接続された伝送線路Lf2とコンデンサCf1とからなる直列共振回路とにより形成されている。また、高周波側フィルタ502は、共通端子503に接続されたコンデンサCf2と、コンデンサCf2と高周波側端子505との間に接続されたコンデンサCf3と、コンデンサCf2,Cf3の接続点とグランドとの間に接続された伝送線路Lf3とコンデンサCf4とからなる直接共振回路とにより形成されている。 For example, the conventional branching circuit 500 shown in FIG. 10 described in Patent Document 1 includes a low-frequency filter 501 and a high-frequency filter 502. The low-frequency filter 501 is formed by a transmission line Lf1 connected to the common terminal 503, a series resonance circuit including a transmission line Lf2 connected between the low-frequency terminal 504 and the ground, and a capacitor Cf1. Has been. The high frequency filter 502 includes a capacitor Cf2 connected to the common terminal 503, a capacitor Cf3 connected between the capacitor Cf2 and the high frequency terminal 505, and a connection point between the capacitors Cf2 and Cf3 and the ground. It is formed by a direct resonance circuit composed of a connected transmission line Lf3 and a capacitor Cf4.
 そして、低周波側フィルタ501および高周波側フィルタ502を形成する、伝送線路Lf1~Lf3およびコンデンサCf1~Cf4は、電極パターンとして積層基板に内蔵されるが、分波器500の更なる小型化を図るため、各電極パターンが近接配置されて積層基板に内蔵されることで、次のような問題が生じるおそれがある。すなわち、低周波側フィルタ501を形成する回路素子(伝送線路Lf1,Lf2、コンデンサCf1)を構成する電極パターンと、高周波側フィルタ502を形成する回路素子(伝送線路Lf3、コンデンサCf2~Cf4)を構成する電極パターンとが、積層基板の誘電体層を挟んで対向して配置されると、両電極パターン間に寄生容量が発生して両電極パターンが電磁界的に結合するおそれがある。 The transmission lines Lf1 to Lf3 and the capacitors Cf1 to Cf4 forming the low frequency filter 501 and the high frequency filter 502 are built in the laminated substrate as electrode patterns, but the duplexer 500 is further downsized. Therefore, the following problems may occur when the electrode patterns are arranged close to each other and incorporated in the multilayer substrate. That is, the circuit pattern (transmission line Lf3, capacitors Cf2 to Cf4) forming the circuit element (transmission line Lf3, capacitors Cf2 to Cf4) forming the high frequency filter 502 is configured. If the electrode patterns to be arranged are opposed to each other with the dielectric layer of the laminated substrate interposed therebetween, parasitic capacitance may be generated between the two electrode patterns, and the two electrode patterns may be coupled electromagnetically.
 低周波側フィルタ501および高周波側フィルタ502をそれぞれ形成する両電極パターン間に寄生容量が生じて両電極パターンが電磁界的に結合すると、両フィルタ501,502間で信号の漏れが生じ、両フィルタ501,502間のアイソレーション特性が劣化する。そこで、図10に示す従来の分波器500では、低周波側フィルタ501を形成する伝送線路Lf1を構成する電極パターンと、高周波側フィルタ501を形成するコンデンサCf2を構成する電極パターンとが、電磁界的に結合しないように、積層基板の積層方向に実質的に重畳しないように配置されている。 When parasitic capacitance is generated between both electrode patterns forming the low-frequency filter 501 and the high-frequency filter 502, and both electrode patterns are electromagnetically coupled, signal leakage occurs between the filters 501 and 502. The isolation characteristic between 501 and 502 deteriorates. Therefore, in the conventional duplexer 500 shown in FIG. 10, the electrode pattern constituting the transmission line Lf1 forming the low frequency filter 501 and the electrode pattern constituting the capacitor Cf2 forming the high frequency filter 501 are electromagnetic It arrange | positions so that it may not overlap substantially in the lamination direction of a laminated substrate so that it may not couple | bond together.
 このように、両フィルタ501,502をそれぞれ形成する電極パターンが、積層基板の積層方向に重ならないように配置されることで、両電極パターン間に寄生容量が発生するのが抑制されるため、両電極パターンが電磁界的に結合することを防止でき、分波器500の小型化を図ると共に、両フィルタ501,502間のアイソレーション特性の向上を図ることができる。 In this way, since the electrode patterns that form both filters 501 and 502 are arranged so as not to overlap in the stacking direction of the stacked substrate, the generation of parasitic capacitance between the two electrode patterns is suppressed. It is possible to prevent the two electrode patterns from being electromagnetically coupled, to reduce the size of the duplexer 500, and to improve the isolation characteristics between the filters 501 and 502.
 また、図11の従来の分波器600の断面図に示すように、通過帯域の異なる送信フィルタ素子601および受信フィルタ素子602が実装用基板603に実装され、送信フィルタ素子601および受信フィルタ素子602が樹脂モールド層604により保護されて形成された分波器600も知られている。また、分波器600では、送信フィルタ素子601の入力側である送信端子605に接続される配線電極606や出力側である共通端子607に接続される配線電極608、受信フィルタ素子602の出力側である受信端子609に接続される配線電極610、受信フィルタ素子602の接地端子611に接続されるグランド電極612などが実装用基板603に内蔵されている。 Further, as shown in the cross-sectional view of the conventional duplexer 600 in FIG. 11, a transmission filter element 601 and a reception filter element 602 having different pass bands are mounted on a mounting substrate 603, and the transmission filter element 601 and the reception filter element 602 are mounted. A duplexer 600 formed by being protected by a resin mold layer 604 is also known. In the duplexer 600, the wiring electrode 606 connected to the transmission terminal 605 that is the input side of the transmission filter element 601, the wiring electrode 608 that is connected to the common terminal 607 that is the output side, and the output side of the reception filter element 602. A wiring electrode 610 connected to the receiving terminal 609, a ground electrode 612 connected to the ground terminal 611 of the receiving filter element 602, and the like are built in the mounting substrate 603.
 そして、分波器600では、上記したように、各配線電極606,608,610間に寄生容量が生じて各配線電極606,608,610が電磁界的に結合することにより、送信フィルタ素子601および受信フィルタ素子602間のアイソレーション特性が劣化することを防止するために、信号伝達用の各配線電極606,608,610は積層基板603の積層方向に重ならないように配置されている。なお、図11に示す分波器600の断面図では、説明を容易にするために、配線電極などの構成が一部図示省略されている。 In the duplexer 600, as described above, parasitic capacitance is generated between the wiring electrodes 606, 608, 610, and the wiring electrodes 606, 608, 610 are electromagnetically coupled, thereby transmitting the filter element 601. In order to prevent the isolation characteristics between the reception filter elements 602 from deteriorating, the wiring electrodes 606, 608, and 610 for signal transmission are arranged so as not to overlap in the stacking direction of the stacked substrate 603. In addition, in the cross-sectional view of the duplexer 600 shown in FIG. 11, a part of the configuration such as the wiring electrode is omitted for easy explanation.
特開2005-210607号公報(段落0010,0017~0022、図1,5、要約書など)Japanese Patent Laying-Open No. 2005-210607 (paragraphs 0010, 0017 to 0022, FIG. 1, 5, abstract, etc.)
 ところで、従来の分波器500,600では、上記したアイソレーション特性の向上を図るために、大面積の平板状のパターン形状を有する接地用のグランド電極が積層基板や実装用基板603に設けられている。ところが、積層基板や実装用基板内に、大面積の平板状のパターン形状を有する接地用のグランド電極を設けることにより、次のような問題が生じるおそれがある。 By the way, in the conventional duplexers 500 and 600, in order to improve the isolation characteristics described above, a grounding ground electrode having a large-area flat pattern shape is provided on the multilayer substrate or the mounting substrate 603. ing. However, by providing a ground electrode for grounding having a large-area flat pattern shape in a laminated substrate or a mounting substrate, the following problems may occur.
 すなわち、例えば図11に示すように、大面積の平板状のパターン形状を有するグランド電極612は、平面視において、信号伝達用の配線電極608,610と重なるように実装用基板603に配置される。したがって、図11中の点線で囲まれた領域に示すように、実装用基板603の誘電体層を挟んで対向する配線電極608とグランド電極612との間に寄生容量が発生し、配線電極608およびグランド電極612が電磁界的に結合することにより、配線電極608により伝達される信号がグランド電極612に漏洩するおそれがある。 That is, for example, as shown in FIG. 11, the ground electrode 612 having a flat pattern shape with a large area is arranged on the mounting substrate 603 so as to overlap the signal transmission wiring electrodes 608 and 610 in plan view. . Therefore, as shown in a region surrounded by a dotted line in FIG. 11, parasitic capacitance is generated between the wiring electrode 608 and the ground electrode 612 facing each other with the dielectric layer of the mounting substrate 603 interposed therebetween, and the wiring electrode 608 is formed. When the ground electrode 612 is electromagnetically coupled, a signal transmitted by the wiring electrode 608 may leak to the ground electrode 612.
 このとき、特に、分波器600が数GHzの高周波帯域で使用される場合には、グランド電極612に接続されたビア導体612aなどに生じる寄生インダクタンスなどに起因して、グランド電極612が理想的な状態で接地されていないおそれがある。この場合、配線電極608からグランド電極612に漏れた信号が、受信フィルタ素子602の受信端子609に接続される配線電極610にグランド電極612を介して伝達されることにより、送信フィルタ素子601および受信フィルタ素子602間のアイソレーション特性が劣化するおそれがあり、技術の改善が求められていた。 At this time, in particular, when the duplexer 600 is used in a high frequency band of several GHz, the ground electrode 612 is ideal due to a parasitic inductance generated in the via conductor 612a connected to the ground electrode 612 and the like. There is a possibility that it is not grounded. In this case, a signal leaking from the wiring electrode 608 to the ground electrode 612 is transmitted to the wiring electrode 610 connected to the reception terminal 609 of the reception filter element 602 via the ground electrode 612, whereby the transmission filter element 601 and the reception filter 601 are received. There is a possibility that the isolation characteristics between the filter elements 602 may be deteriorated, and improvement of the technique has been demanded.
 この発明は、上記した課題に鑑みてなされたものであり、分波器が備える第1、第2のフィルタ素子間のアイソレーション特性の向上を図ることができる技術を提供することを目的とする。 The present invention has been made in view of the above-described problems, and an object thereof is to provide a technique capable of improving the isolation characteristics between the first and second filter elements included in the duplexer. .
 上記した目的を達成するために、本発明の分波器は、通過帯域が異なる第1のフィルタ素子および第2のフィルタ素子と、前記第1、第2のフィルタ素子が実装される実装用基板と、前記実装用基板に前記第1、第2のフィルタ素子用としてそれぞれ設けられた信号伝達用の第1、第2の配線電極および接地用の第1、第2のグランド電極とを備え、前記第1のフィルタ素子の接地端子に接続された前記第1のグランド電極と、前記第2のフィルタ素子の信号用端子に接続された前記第2の配線電極とが、平面視において重なることなく配置されていることを特徴としている(請求項1)。 In order to achieve the above-described object, a duplexer according to the present invention includes a first filter element and a second filter element having different pass bands, and a mounting substrate on which the first and second filter elements are mounted. And first and second wiring electrodes for signal transmission and first and second ground electrodes for grounding provided respectively for the first and second filter elements on the mounting substrate, The first ground electrode connected to the ground terminal of the first filter element and the second wiring electrode connected to the signal terminal of the second filter element do not overlap in a plan view. It is characterized by being arranged (Claim 1).
 また、前記第1のグランド電極と、前記第2のフィルタ素子の接地端子に接続された前記第2のグランド電極とが、電気的に絶縁された状態で配置されていることを特徴としている(請求項2)。このような構造にすることにより、第1、第2のグランド電極に漏洩した信号が、互いに他方のグランド電極に伝達するのが防止されるので、第1、第2のフィルタ素子間のアイソレーション特性の向上をさらに図ることができる。 Further, the first ground electrode and the second ground electrode connected to the ground terminal of the second filter element are disposed in an electrically insulated state ( Claim 2). With this structure, signals leaking to the first and second ground electrodes are prevented from being transmitted to the other ground electrode, so that the isolation between the first and second filter elements is achieved. The characteristics can be further improved.
 また、前記第2のフィルタ素子は送信信号用の送信フィルタを有し、前記第2のフィルタ素子には、前記送信フィルタの入力側に接続される送信端子と出力側に接続される共通端子とが前記第2のフィルタ素子の前記信号用端子として設けられ、前記第2の配線電極は、前記送信端子と接続された送信電極および前記第2のフィルタ素子の前記共通端子と接続された共通電極を有することを特徴としている(請求項3)。このような構造にすることにより、第1のグランド電極と、第2の配線電極の送信電極および共通電極と間に寄生容量が発生するのが抑制されて、第1のグランド電極と第2の配線電極の送信電極および共通電極とが電磁界的に結合することを防止することができる。 The second filter element includes a transmission filter for a transmission signal, and the second filter element includes a transmission terminal connected to the input side of the transmission filter and a common terminal connected to the output side. Is provided as the signal terminal of the second filter element, and the second wiring electrode is a transmission electrode connected to the transmission terminal and a common electrode connected to the common terminal of the second filter element (Claim 3). With such a structure, generation of parasitic capacitance between the first ground electrode and the transmission electrode and the common electrode of the second wiring electrode is suppressed, and the first ground electrode and the second ground electrode are suppressed. It is possible to prevent the transmission electrode and the common electrode of the wiring electrode from being electromagnetically coupled.
 また、前記第2の配線電極は、前記送信端子に接続されるフィルタ回路を形成するパターン電極をさらに有することを特徴としている(請求項4)。このような構造にすることにより、第2のフィルタ素子の送信フィルタに入力される送信信号に種々のフィルタ回路によるフィルタ処理を施すことができる。 Further, the second wiring electrode further includes a pattern electrode that forms a filter circuit connected to the transmission terminal (claim 4). By adopting such a structure, it is possible to perform filter processing by various filter circuits on the transmission signal input to the transmission filter of the second filter element.
 また、前記第1の配線電極は、前記第1のフィルタ素子の信号用端子に接続され、前記第1のフィルタ素子は受信信号用の受信フィルタを有し、前記第1のフィルタ素子には、前記受信フィルタの入力側に接続される共通端子と出力側に接続される受信端子とが前記第1のフィルタ素子の前記信号用端子として設けられ、前記第1の配線電極は、前記第1のフィルタ素子の共通端子と接続された共通電極および前記受信端子と接続された受信電極とを有し、前記第1の配線電極の前記共通電極および前記第2の配線電極の前記共通電極が電気的に接続されると共に、前記第1のグランド電極は、平面視において、前記送信電極および前記第1、第2の配線電極それぞれの前記共通電極と、前記受信電極との間に配置されていることを特徴としている(請求項5)。このような構造にすることにより、第1のグランド電極により、送信電極および第1、第2の配線電極それぞれの共通電極を伝達する出力の大きな通信用の送信信号が受信電極に漏洩するのが防止されるので、第1、第2のフィルタ素子間のより一層のアイソレーション特性の向上を図ることができる。 The first wiring electrode is connected to a signal terminal of the first filter element, the first filter element includes a reception signal reception filter, and the first filter element includes: A common terminal connected to the input side of the reception filter and a reception terminal connected to the output side are provided as the signal terminals of the first filter element, and the first wiring electrode is the first wiring electrode A common electrode connected to a common terminal of the filter element and a reception electrode connected to the reception terminal, wherein the common electrode of the first wiring electrode and the common electrode of the second wiring electrode are electrically And the first ground electrode is disposed between the transmission electrode and the common electrode of each of the first and second wiring electrodes and the reception electrode in plan view. With features And that (claim 5). With this structure, the first ground electrode leaks a transmission signal for communication with a large output that transmits the common electrode of each of the transmission electrode and the first and second wiring electrodes to the reception electrode. Therefore, the isolation characteristic between the first and second filter elements can be further improved.
 また、前記第1のフィルタ素子には接地端子が複数設けられており、前記第1のグランド電極は、平面視において、前記第1のフィルタ素子の前記各接地端子と重なって配置される平板状のパターン形状を有することを特徴としている(請求項6)。このような構造にすることにより、第1のフィルタ素子の接地状態を良好なものとすることができるので、第1、第2のフィルタ素子間のアイソレーション特性の向上を図ることができる。 The first filter element is provided with a plurality of ground terminals, and the first ground electrode is a flat plate disposed so as to overlap the ground terminals of the first filter element in plan view. It has the pattern shape of (6). By adopting such a structure, the grounding state of the first filter element can be improved, so that the isolation characteristics between the first and second filter elements can be improved.
 また、前記実装用基板の裏面に設けられた複数の実装用電極をさらに備え、前記第1のグランド電極に接続される一部の前記実装用電極は、他の前記実装用電極よりも大なる面積を有し、前記第1のグランド電極および前記一部の実装用電極は、複数のビア導体により電気的に接続されていることを特徴としている(請求項7)。例えば、大面積の一部の実装用電極を、第1、第2の配線電極と接続される複数の他の実装用電極間に配置することにより、複数の他の実装用電極間での電気的な干渉を抑制することができる。 The mounting board further includes a plurality of mounting electrodes provided on the back surface of the mounting substrate, and some of the mounting electrodes connected to the first ground electrode are larger than the other mounting electrodes. The first ground electrode and the part of the mounting electrodes have an area and are electrically connected by a plurality of via conductors (Claim 7). For example, by disposing a part of the mounting electrode having a large area between the plurality of other mounting electrodes connected to the first and second wiring electrodes, the electric power between the plurality of other mounting electrodes can be reduced. Interference can be suppressed.
 本発明によれば、第1のフィルタ素子の接地端子に接続された第1のグランド電極と、第2のフィルタ素子の信号用端子に接続された第2の配線電極とが、平面視において重なることなく配置されているため、第1のグランド電極と第2の配線電極と間に寄生容量が発生するのが抑制されて、第1のグランド電極および第2の配線電極が電磁界的に結合することを防止することができる。したがって、第2の配線電極を伝達する信号が第1のグランド電極に漏洩することが防止され、第2の配線電極を伝達する信号が、第1のグランド電極を介して第1の配線電極に伝達するのを防止することができるので、分波器が備える第1、第2のフィルタ素子間のアイソレーション特性の向上を図ることができる。 According to the present invention, the first ground electrode connected to the ground terminal of the first filter element and the second wiring electrode connected to the signal terminal of the second filter element overlap in plan view. Therefore, the generation of parasitic capacitance between the first ground electrode and the second wiring electrode is suppressed, and the first ground electrode and the second wiring electrode are electromagnetically coupled. Can be prevented. Therefore, the signal transmitted through the second wiring electrode is prevented from leaking to the first ground electrode, and the signal transmitted through the second wiring electrode is transmitted to the first wiring electrode via the first ground electrode. Since transmission can be prevented, the isolation characteristics between the first and second filter elements provided in the duplexer can be improved.
本発明の分波器の第1実施形態を示す図である。It is a figure which shows 1st Embodiment of the splitter of this invention. 図1の分波器の内部構成を示すブロック図である。It is a block diagram which shows the internal structure of the splitter of FIG. 実装用基板の電極形状の一例を示す平面図である。It is a top view which shows an example of the electrode shape of the board | substrate for mounting. 図3に示す実装用基板の各誘電体層における電極形状を平面視において重ね合わせた状態を示す図である。It is a figure which shows the state which overlapped in the planar view the electrode shape in each dielectric material layer of the mounting board | substrate shown in FIG. 本発明の第2実施形態における実装用基板の電極形状の一例を示す平面図である。It is a top view which shows an example of the electrode shape of the board | substrate for mounting in 2nd Embodiment of this invention. 実装用基板の電極形状の変形例を示す平面図である。It is a top view which shows the modification of the electrode shape of the board | substrate for mounting. 本発明の第3実施形態における実装用基板の電極形状の一例を示す平面図である。It is a top view which shows an example of the electrode shape of the board | substrate for mounting in 3rd Embodiment of this invention. 本発明の第4実施形態における実装用基板の電極形状の一例を示す平面図である。It is a top view which shows an example of the electrode shape of the board | substrate for mounting in 4th Embodiment of this invention. 本発明の第5実施形態における実装用基板の電極形状の一例を示す平面図である。It is a top view which shows an example of the electrode shape of the board | substrate for mounting in 5th Embodiment of this invention. 従来の分波回路の一例を示す図である。It is a figure which shows an example of the conventional branching circuit. 従来の分波器の一例を示す断面図である。It is sectional drawing which shows an example of the conventional splitter.
 <第1実施形態>
 本発明の分波器(デュプレクサ)の第1実施形態について、図1~図4を参照して説明する。図1は本発明の分波器の第1実施形態を示す図である。図2は図1の分波器の内部構成を示すブロック図である。図3は実装用基板の電極形状の一例を示す平面図であり、(a)~(c)はそれぞれ実装用基板の各誘電体層における電極形状を示す。図4は図3に示す実装用基板の各誘電体層における電極形状を平面視において重ね合わせた状態を示す図である。
<First Embodiment>
A first embodiment of a duplexer according to the present invention will be described with reference to FIGS. FIG. 1 is a diagram showing a first embodiment of a duplexer according to the present invention. FIG. 2 is a block diagram showing the internal configuration of the duplexer of FIG. FIG. 3 is a plan view showing an example of the electrode shape of the mounting substrate. FIGS. 3A to 3C show the electrode shapes of the dielectric layers of the mounting substrate, respectively. FIG. 4 is a view showing a state in which the electrode shapes in the respective dielectric layers of the mounting substrate shown in FIG.
 (分波器)
 分波器1は、周波数の異なる送信信号と受信信号とを分離するために用いられ、携帯電話や携帯情報端末などの通信携帯端末が備えるマザー基板等に搭載される高周波アンテナスイッチモジュールなどの回路モジュールに実装される。そして、分波器1が実装された回路モジュールがマザー基板等に実装されることにより、マザー基板等が備えるアンテナラインANTやグランドラインGND、受信信号ラインRx、送信信号ラインTxなどの各種信号ラインおよび電源ラインと分波器1とが接続されて、マザー基板等と分波器1との間で送受信信号の入出力が行われる。
(Demultiplexer)
The duplexer 1 is used to separate a transmission signal and a reception signal having different frequencies, and a circuit such as a high-frequency antenna switch module mounted on a mother board or the like included in a communication portable terminal such as a mobile phone or a portable information terminal. Implemented in the module. Then, by mounting the circuit module on which the duplexer 1 is mounted on a mother board or the like, various signal lines such as an antenna line ANT, a ground line GND, a reception signal line Rx, and a transmission signal line Tx provided on the mother board or the like. The power supply line and the duplexer 1 are connected, and transmission / reception signals are input / output between the mother board and the duplexer 1.
 図1および図2に示すように、分波器1は、高周波信号の通過帯域が異なる受信フィルタ素子2(本発明の「第1のフィルタ素子」に相当)および送信フィルタ素子3(本発明の「第2のフィルタ」に相当)と、送信フィルタ素子3の送信端子31に接続されるローパスフィルタ(LPF)4(本発明の「フィルタ回路」に相当)と、受信フィルタ素子2および送信フィルタ素子3が実装される実装用基板5と、受信フィルタ素子2および送信フィルタ素子3が実装された実装用基板5の実装面をモールドして保護するモールド樹脂層6とを備えている。 As shown in FIGS. 1 and 2, the duplexer 1 includes a reception filter element 2 (corresponding to a “first filter element” of the present invention) and a transmission filter element 3 (corresponding to the present invention) having different high-frequency signal passbands. "Corresponding to a" second filter "), a low-pass filter (LPF) 4 (corresponding to the" filter circuit "of the present invention) connected to the transmission terminal 31 of the transmission filter element 3, the reception filter element 2 and the transmission filter element 3 and a mold resin layer 6 that molds and protects the mounting surface of the mounting substrate 5 on which the reception filter element 2 and the transmission filter element 3 are mounted.
 受信フィルタ素子2および送信フィルタ素子3は、それぞれ受信信号用の受信フィルタおよび送信信号用の送信フィルタを備えている。また、受信フィルタ素子2および送信フィルタ素子3は、それぞれSAW(表面弾性波)フィルタ素子により形成されており、この実施形態では、受信フィルタ素子2は、平衡出力型の受信フィルタを有している。 The reception filter element 2 and the transmission filter element 3 include a reception filter for reception signals and a transmission filter for transmission signals, respectively. The reception filter element 2 and the transmission filter element 3 are each formed by a SAW (surface acoustic wave) filter element. In this embodiment, the reception filter element 2 has a balanced output type reception filter. .
 また、受信フィルタ素子2には、受信フィルタの入力側に接続される共通端子21(アンテナ端子)および出力側に接続される受信端子22が信号用端子として設けられ、接地端子23が接地用端子として設けられている。また、送信フィルタ素子3には、送信フィルタの入力側に接続される送信端子31および出力側に接続される共通端子32(アンテナ端子)が信号用端子として設けられ、接地端子33が接地用端子として設けられている。 The reception filter element 2 is provided with a common terminal 21 (antenna terminal) connected to the input side of the reception filter and a reception terminal 22 connected to the output side as signal terminals, and the ground terminal 23 is a ground terminal. It is provided as. The transmission filter element 3 is provided with a transmission terminal 31 connected to the input side of the transmission filter and a common terminal 32 (antenna terminal) connected to the output side as a signal terminal, and a ground terminal 33 is a ground terminal. It is provided as.
 なお、この実施形態では、分波器1が備える受信フィルタ素子2および送信フィルタ素子3はSAWフィルタ素子により形成されているが、SAWフィルタ素子の他に、複数の共振器およびコイルなどが接続されることにより受信フィルタおよび送信フィルタが形成されていてもよく、周波数の異なる送信信号と受信信号とを確実に分波することができれば、受信フィルタ素子2および送信フィルタ素子3は、誘電体フィルタやBAWフィルタ素子など、どのようなものであってもよい。 In this embodiment, the reception filter element 2 and the transmission filter element 3 included in the duplexer 1 are formed by SAW filter elements. However, in addition to the SAW filter elements, a plurality of resonators and coils are connected. Thus, the reception filter and the transmission filter may be formed, and if the transmission signal and the reception signal having different frequencies can be reliably demultiplexed, the reception filter element 2 and the transmission filter element 3 may be a dielectric filter, Any device such as a BAW filter element may be used.
 LPF4は、送信フィルタ素子3の送信端子31に接続されるものであり、送信信号ラインTxから入力された送信信号をフィルタ処理する。すなわち、送信信号ラインTxを介して送信フィルタ素子3に入力される送信信号は、通信用にその出力がパワーアンプにより増幅されており、送信信号に含まれる2次以上の高調波成分もパワーアンプにより増幅されている。したがって、LPF4は、パワーアンプにより増幅された送信信号に含まれる2次以上の高調波成分を減衰する。 The LPF 4 is connected to the transmission terminal 31 of the transmission filter element 3 and filters the transmission signal input from the transmission signal line Tx. That is, the output of the transmission signal input to the transmission filter element 3 via the transmission signal line Tx is amplified by a power amplifier for communication, and second-order or higher harmonic components included in the transmission signal are also amplified by the power amplifier. It is amplified by. Accordingly, the LPF 4 attenuates second-order or higher harmonic components included in the transmission signal amplified by the power amplifier.
 実装用基板5は、この実施形態では、セラミックグリーンシートにより形成された複数の誘電体層51~53が積層されて焼成されることで一体的にセラミック積層体として形成される。 In this embodiment, the mounting substrate 5 is integrally formed as a ceramic laminate by laminating and firing a plurality of dielectric layers 51 to 53 formed of ceramic green sheets.
 すなわち、各誘電体層51~53を形成するセラミックグリーンシートは、アルミナおよびガラスなどの混合粉末が有機バインダおよび溶剤などと一緒に混合されたスラリーが成型器によりシート化されたものであり、約1000℃前後の低い温度で、所謂、低温焼成できるように形成されている。そして、所定形状に切り取られたセラミックグリーンシートに、レーザー加工などによりビアホールが形成され、形成されたビアホールにAgやCuなどを含む導体ペーストが充填されたり、ビアフィルめっきが施されることにより層間接続用のビア導体が形成され、導体ペーストによる印刷により種々の電極パターンが形成されて、各誘電体層51~53が形成される。 That is, the ceramic green sheets forming the respective dielectric layers 51 to 53 are obtained by forming a sheet in which a slurry in which a mixed powder such as alumina and glass is mixed with an organic binder and a solvent is formed by a molding machine. It is formed so that it can be fired at a low temperature of about 1000 ° C. at a so-called low temperature. Then, via holes are formed in the ceramic green sheet cut into a predetermined shape by laser processing or the like, and the formed via holes are filled with a conductive paste containing Ag, Cu, etc. Via conductors are formed, and various electrode patterns are formed by printing with a conductor paste to form the dielectric layers 51 to 53.
 また、各誘電体層51~53に、ビア導体および電極パターンが適宜形成されることで、実装用基板5に、受信フィルタ素子2および送信フィルタ素子3用としてそれぞれ設けられた信号伝達用の第1、第2の配線電極7,8および第1、第2のグランド電極9,10が内蔵され、実装用基板5の裏面に複数の実装用電極11が形成される。 In addition, via conductors and electrode patterns are appropriately formed in each of the dielectric layers 51 to 53, so that a signal transmission second layer provided for the reception filter element 2 and the transmission filter element 3 respectively on the mounting substrate 5 is provided. The first and second wiring electrodes 7 and 8 and the first and second ground electrodes 9 and 10 are built in, and a plurality of mounting electrodes 11 are formed on the back surface of the mounting substrate 5.
 すなわち、電極パターンおよびビア導体が各誘電体層51~53に適宜設けられて、第1、第2の配線電極7,8、第1、第2のグランド電極9,10および実装用電極11が形成されることで、実装用基板5に実装される受信フィルタ素子2および送信フィルタ素子3と、実装用電極11とが相互に電気的に接続される。このとき、後述するように、各誘電体層51~53に形成される電極パターンおよびビア導体によりコンデンサやコイルなどの回路素子を形成したり、形成されたコンデンサやコイルなどの回路素子によりLPF4等のフィルタ回路や整合回路などを形成してもよい。 That is, electrode patterns and via conductors are appropriately provided in the dielectric layers 51 to 53, and the first and second wiring electrodes 7, 8, the first and second ground electrodes 9, 10 and the mounting electrode 11 are provided. By being formed, the reception filter element 2 and the transmission filter element 3 mounted on the mounting substrate 5 and the mounting electrode 11 are electrically connected to each other. At this time, as will be described later, circuit elements such as capacitors and coils are formed by the electrode patterns and via conductors formed in the respective dielectric layers 51 to 53, and LPF 4 and the like are formed by the formed circuit elements such as capacitors and coils. A filter circuit, a matching circuit, or the like may be formed.
 受信フィルタ素子2の信号伝達用の第1の配線電極7は、受信フィルタ素子2の共通端子21と接続された共通電極71および受信端子22と接続された受信電極72を有している。送信フィルタ素子3の信号伝達用の第2の配線電極8は、送信フィルタ素子3の送信端子31と接続された送信電極81、共通端子32と接続された共通電極82および送信端子31に接続されるLPF4を形成するパターン電極83を有している。 The first wiring electrode 7 for signal transmission of the reception filter element 2 has a common electrode 71 connected to the common terminal 21 of the reception filter element 2 and a reception electrode 72 connected to the reception terminal 22. The second wiring electrode 8 for signal transmission of the transmission filter element 3 is connected to the transmission electrode 81 connected to the transmission terminal 31 of the transmission filter element 3, the common electrode 82 connected to the common terminal 32, and the transmission terminal 31. The pattern electrode 83 for forming the LPF 4 is provided.
 なお、この実施形態では、パターン電極83によりコイルが形成されており、送信フィルタ素子3に内蔵されたコンデンサ(図示省略)と、パターン電極83により形成されるコイルとによりLPF4が形成される。また、この実施形態では、誘電体層51に形成された第1の配線電極7の共通電極71および第2の配線電極7の共通電極82は、同一の電極パターンにより形成されることにより電気的に接続されている(図3(a)参照)。 In this embodiment, a coil is formed by the pattern electrode 83, and the LPF 4 is formed by a capacitor (not shown) built in the transmission filter element 3 and a coil formed by the pattern electrode 83. In this embodiment, the common electrode 71 of the first wiring electrode 7 and the common electrode 82 of the second wiring electrode 7 formed on the dielectric layer 51 are electrically formed by being formed with the same electrode pattern. (See FIG. 3A).
 また、受信フィルタ素子2および送信フィルタ素子3には、それぞれ複数の接地端子23,33が設けられており、各接地端子23,33は、それぞれ第1、第2のグランド電極9,10を介して接地される。 The reception filter element 2 and the transmission filter element 3 are provided with a plurality of ground terminals 23 and 33, respectively. The ground terminals 23 and 33 are respectively connected to the first and second ground electrodes 9 and 10, respectively. Grounded.
 実装用電極11は、実装用共通電極11aと、実装用受信電極11bと、実装用送信電極11cと、実装用接地電極11d,11eと、実装用未接続電極11fとを有している(図3(c)参照)。 The mounting electrode 11 includes a mounting common electrode 11a, a mounting receiving electrode 11b, a mounting transmitting electrode 11c, mounting ground electrodes 11d and 11e, and a mounting unconnected electrode 11f (see FIG. 3 (c)).
 なお、実装用共通電極11aは、受信フィルタ素子2および送信フィルタ素子3それぞれの共通端子21,32と共通電極71,82を介して接続される。実装用受信電極11bは、受信フィルタ素子2の受信端子22と受信電極72を介して接続される。実装用送信電極11cは、送信フィルタ素子3の送信端子31と送信電極81およびパターン電極83を介して接続される。 The mounting common electrode 11a is connected to the common terminals 21 and 32 of the reception filter element 2 and the transmission filter element 3 via the common electrodes 71 and 82, respectively. The mounting receiving electrode 11 b is connected to the receiving terminal 22 of the receiving filter element 2 via the receiving electrode 72. The mounting transmission electrode 11 c is connected to the transmission terminal 31 of the transmission filter element 3 via the transmission electrode 81 and the pattern electrode 83.
 また、実装用接地電極11dは、受信フィルタ素子2の接地端子23と第1のグランド電極9を介して接続され、実装用接地電極11eは、送信フィルタ素子3の接地端子33と第2のグランド電極10を介して接続される。また、実装用未接続電極11fは、分波器1を回路モジュールのモジュール基板に実装したときの実装強度を向上するために実装用基板5の裏面に設けられている。 The mounting ground electrode 11d is connected to the ground terminal 23 of the reception filter element 2 via the first ground electrode 9, and the mounting ground electrode 11e is connected to the ground terminal 33 of the transmission filter element 3 and the second ground. It is connected via the electrode 10. Further, the mounting unconnected electrode 11f is provided on the back surface of the mounting substrate 5 in order to improve mounting strength when the duplexer 1 is mounted on the module substrate of the circuit module.
 また、この実施形態では、送信フィルタ素子3の接地端子33が接続される第2のグランド電極10と、実装用接地電極11eとを接続するパターン電極84が、第2の配線電極8として第2誘電体層52に設けられている(図3(b)参照)。そして、パターン電極84によりコイルが形成されてコイルが構成されており、パターン電極84により構成された共振器により、送信フィルタ素子3の送信フィルタの減衰特性を向上させる減衰極が形成される。 In this embodiment, the pattern electrode 84 that connects the second ground electrode 10 to which the ground terminal 33 of the transmission filter element 3 is connected and the mounting ground electrode 11 e is the second wiring electrode 8. It is provided on the dielectric layer 52 (see FIG. 3B). A coil is formed by forming a coil with the pattern electrode 84, and an attenuation pole that improves the attenuation characteristic of the transmission filter of the transmission filter element 3 is formed by the resonator configured with the pattern electrode 84.
 (実装用基板の電極形状)
 次に、図3および図4を参照して、実装用基板5の各誘電体層51~53に設けられた第1、第2の配線電極7,8、第1、第2のグランド電極9,10および実装用電極11の電極形状の一例について具体的に説明する。
(Electrode shape of mounting board)
Next, referring to FIG. 3 and FIG. 4, first and second wiring electrodes 7 and 8, first and second ground electrodes 9 provided on the dielectric layers 51 to 53 of the mounting substrate 5, respectively. , 10 and an example of the electrode shape of the mounting electrode 11 will be specifically described.
 なお、上記した各電極のうち、各誘電体層51~53に形成された同一の電極パターンにより形成されている電極については、当該同一の電極パターンにより形成される各電極にそれぞれ対応した複数の符号が、当該同一の電極パターンに付されている。また、図3では、説明が容易となるように、第1、第2の配線電極7,8、第1、第2のグランド電極9,10および実装用電極11、並びに、主要なビア導体のみが図示されており、その他の電極およびビア導体は図示省略されている。また、ビア導体については、その配置位置のみが○印により図示されている。 Of the electrodes described above, the electrodes formed by the same electrode pattern formed in each of the dielectric layers 51 to 53 are a plurality of electrodes corresponding to the respective electrodes formed by the same electrode pattern. Reference numerals are assigned to the same electrode pattern. Further, in FIG. 3, only the first and second wiring electrodes 7 and 8, the first and second ground electrodes 9 and 10 and the mounting electrode 11 and main via conductors are shown for easy explanation. The other electrodes and via conductors are not shown. Further, only the arrangement position of the via conductor is indicated by a circle.
 また、図3(c)に示す誘電体層53では、実装用電極11は実際には誘電体層53の裏面に設けられているが、同図(c)では、誘電体層53に設けられた各実装用電極11の平面視における配置位置が実線で示されている。なお、後の説明で用いられる図5~図8についても図3と同様に図示されているため、以下ではその説明は省略する。 Further, in the dielectric layer 53 shown in FIG. 3C, the mounting electrode 11 is actually provided on the back surface of the dielectric layer 53, but in FIG. 3C, it is provided on the dielectric layer 53. The mounting positions of the mounting electrodes 11 in plan view are indicated by solid lines. Note that FIGS. 5 to 8 used in the following description are also illustrated in the same manner as in FIG.
 図3(a)に示すように、実装用基板5の実装面となる最上層の誘電体層51には、受信フィルタ素子2が実装される際に、共通端子21が接続される第1の共通電極71、受信端子22が接続される受信電極72および接地端子23が接続される第1のグランド電極9が形成されている。 As shown in FIG. 3A, the first dielectric layer 51, which is the mounting surface of the mounting substrate 5, is connected to the common terminal 21 when the reception filter element 2 is mounted. A common electrode 71, a receiving electrode 72 to which the receiving terminal 22 is connected, and a first ground electrode 9 to which the ground terminal 23 is connected are formed.
 第1のグランド電極9は、略凸形状の基部の中央部分が切り欠かれて形成された平板状のパターン形状を有し、同図(a)の誘電体層51の右寄りに凸部を右側に向けて配設されており、平面視において、受信フィルタ素子2の各接地端子23と重なって配置される。そして、受信フィルタ素子2の複数の接地端子23は、第1のグランド電極9の位置G1にそれぞれ接続される。 The first ground electrode 9 has a flat pattern shape formed by cutting out the center portion of the substantially convex base portion, and the convex portion on the right side of the dielectric layer 51 in FIG. Are arranged so as to overlap each ground terminal 23 of the reception filter element 2 in plan view. The plurality of ground terminals 23 of the reception filter element 2 are connected to the position G1 of the first ground electrode 9, respectively.
 共通電極71はクランク状のパターン形状を有し、図3(a)の誘電体層51の略中央の下寄りに配設されて、平面視において、クランク状の一片部分が第1のグランド電極9の切欠き部分に配置される。そして、受信フィルタ素子2の共通端子21は、共通電極71の位置A1に接続される。受信電極72は、矩形に舌状部が設けられた形状を有し、同図(a)の誘電体層51の右寄りに2個配設されており、平面視において、第1のグランド電極9の凸部の上下にそれぞれ配置されている。そして、受信フィルタ素子2の2個の受信端子22は、受信電極72の位置R1にそれぞれ接続される。 The common electrode 71 has a crank-shaped pattern shape, and is disposed substantially below the center of the dielectric layer 51 of FIG. 3A. In a plan view, the crank-shaped piece portion is a first ground electrode. It is arrange | positioned in 9 notch parts. The common terminal 21 of the reception filter element 2 is connected to the position A1 of the common electrode 71. The receiving electrode 72 has a rectangular shape with a tongue-shaped portion, and two receiving electrodes 72 are arranged on the right side of the dielectric layer 51 in FIG. It is arrange | positioned at the upper and lower sides of the convex part, respectively. The two reception terminals 22 of the reception filter element 2 are connected to the position R1 of the reception electrode 72, respectively.
 また、図3(a)に示すように、誘電体層51には、送信フィルタ素子3が実装される際に、送信端子31が接続される送信電極81、共通端子32が接続される共通電極82および接地端子33が接続される第2のグランド電極10が形成されている。 As shown in FIG. 3A, when the transmission filter element 3 is mounted on the dielectric layer 51, the transmission electrode 81 to which the transmission terminal 31 is connected and the common electrode to which the common terminal 32 is connected. A second ground electrode 10 to which 82 and the ground terminal 33 are connected is formed.
 第2のグランド電極10は、図3(a)の誘電体層51に3個配設されており、同図(a)の誘電体層51の略中央の上寄りに1個の第2のグランド電極10が配設され、誘電体層51の左寄りに上下に並べて2個の第2のグランド電極10が配設される。そして、送信フィルタ素子3の複数の接地端子33は、第2のグランド電極10の位置G2にそれぞれ接続される。また、送信フィルタ素子3の未接続端子(図資省略)が、第2のグランド電極10の位置NC2に接続される。 Three second ground electrodes 10 are disposed on the dielectric layer 51 in FIG. 3A, and one second ground electrode 10 is disposed on the upper side of the approximate center of the dielectric layer 51 in FIG. A ground electrode 10 is disposed, and two second ground electrodes 10 are disposed vertically on the left side of the dielectric layer 51. The plurality of ground terminals 33 of the transmission filter element 3 are connected to the position G2 of the second ground electrode 10, respectively. Further, an unconnected terminal (not shown) of the transmission filter element 3 is connected to the position NC2 of the second ground electrode 10.
 送信電極81は、矩形にライン状の延伸部が設けられた形状を有し、図3(a)の誘電体層51の左上部分に配設されており、送信フィルタ素子3の送信端子31は、送信電極81の位置T2に接続される。共通電極81は、共通電極71と同一の電極パターンにより形成されており、送信フィルタ素子3の共通端子32は、共通電極81の位置A2に接続される。 The transmission electrode 81 has a shape in which a rectangular line-shaped extending portion is provided, and is disposed in the upper left portion of the dielectric layer 51 in FIG. 3A. The transmission terminal 31 of the transmission filter element 3 is , Connected to the position T2 of the transmission electrode 81. The common electrode 81 is formed by the same electrode pattern as the common electrode 71, and the common terminal 32 of the transmission filter element 3 is connected to the position A <b> 2 of the common electrode 81.
 図3(b)に示すように、誘電体層51の下層に配置される誘電体層52には、右寄りに配設された略L字状の平板状のパターン形状を有する同一の電極パターンにより、第1、第2のグランド電極9,10が形成されている。誘電体層52の第1、第2のグランド電極9,10は、誘電体層51のハッチングが施された第1、第2のグランド電極9,10と、平面視においてほぼ重なるように配置されている。そして、誘電体層52の第1、第2のグランド電極9,10および誘電体層51のハッチングが施された第1、第2のグランド電極9,10は、ビア導体により電気的に接続されている。このように、誘電体層51,52に配設された第1、第2のグランド電極9,10をできるだけ大面積で形成することにより、第1、第2のグランド電極9,10に接続される第2のフィルタ素子2の接地端子23の接地状態を良好なものとすることができる。 As shown in FIG. 3B, the dielectric layer 52 disposed below the dielectric layer 51 has the same electrode pattern having a substantially L-shaped flat pattern arranged on the right side. First and second ground electrodes 9 and 10 are formed. The first and second ground electrodes 9 and 10 of the dielectric layer 52 are arranged so as to substantially overlap with the first and second ground electrodes 9 and 10 to which the dielectric layer 51 is hatched. ing. The first and second ground electrodes 9, 10 of the dielectric layer 52 and the first and second ground electrodes 9, 10 to which the dielectric layer 51 is hatched are electrically connected by via conductors. ing. In this way, the first and second ground electrodes 9 and 10 disposed on the dielectric layers 51 and 52 are formed as large as possible to be connected to the first and second ground electrodes 9 and 10. The ground state of the ground terminal 23 of the second filter element 2 can be made favorable.
 また、誘電体層52の右寄りには棒状の2個の受信電極72が上下に並べて配設されており、それぞれ、誘電体層51の右寄りに配設された2個の受信電極72とビア導体により電気的に接続される。また、誘電体層52の略中央の下寄りに配設された棒状の同一の電極パターンにより、共通電極71,82が形成されており、誘電体層51の共通電極71,82とビア導体により電気的に接続される。なお、図3(b)に示すように、誘電体層52において、共通電極71,82および第1、第2のグランド電極9,10はできるだけ離間した状態で配置されることにより、誘電体層52の共通電極71,82を伝達する送信信号が誘電体層52の第1、第2のグランド電極9,10に漏洩するのが防止されている。 Further, two rod-shaped receiving electrodes 72 are arranged vertically on the right side of the dielectric layer 52, and the two receiving electrodes 72 and via conductors arranged on the right side of the dielectric layer 51, respectively. Are electrically connected. Further, common electrodes 71 and 82 are formed by the same rod-shaped electrode pattern disposed substantially below the center of the dielectric layer 52, and the common electrodes 71 and 82 of the dielectric layer 51 and via conductors are used. Electrically connected. As shown in FIG. 3B, in the dielectric layer 52, the common electrodes 71 and 82 and the first and second ground electrodes 9 and 10 are arranged as far apart as possible, so that the dielectric layer The transmission signal transmitted through the 52 common electrodes 71 and 82 is prevented from leaking to the first and second ground electrodes 9 and 10 of the dielectric layer 52.
 また、誘電体層52の左上部分には、渦巻状のパターン電極83が配設されており、誘電体層51の送信電極81とビア導体により電気的に接続される。また、誘電体層52の左下部分には、略コ字状のパターン電極84が配設されており、誘電体層51の左下部分に配設された第2のグランド電極10とビア導体により電気的に接続される。また、誘電体層52の左寄りには、棒状の第2のグランド電極10が配設されており、該グランド電極10は、誘電体層51の左寄りに配設されて送信フィルタ素子3の未接続端子と接続された第2のグランド電極10とビア導体により電気的に接続される。 In addition, a spiral pattern electrode 83 is disposed in the upper left portion of the dielectric layer 52 and is electrically connected to the transmission electrode 81 of the dielectric layer 51 by a via conductor. In addition, a substantially U-shaped pattern electrode 84 is disposed in the lower left portion of the dielectric layer 52, and is electrically connected to the second ground electrode 10 disposed in the lower left portion of the dielectric layer 51 and via conductors. Connected. Further, a rod-shaped second ground electrode 10 is disposed on the left side of the dielectric layer 52, and the ground electrode 10 is disposed on the left side of the dielectric layer 51 and is not connected to the transmission filter element 3. The second ground electrode 10 connected to the terminal is electrically connected to the via conductor.
 図3(c)に示すように、誘電体層52の1つ下に配置される誘電体層53の裏面には、複数の実装用接地電極11d,11eが配設されている。複数の実装用接地電極11d,11eのうち、誘電体層53の略中央の上寄りと右下部分に配設されてハッチングが施された一部の実装用接地電極11d,11eは、誘電体層52のハッチングが施された第1、第2のグランド電極9,10とビア導体により電気的に接続される。 As shown in FIG. 3 (c), a plurality of mounting ground electrodes 11d and 11e are disposed on the back surface of the dielectric layer 53 disposed below the dielectric layer 52. Among the plurality of mounting ground electrodes 11d and 11e, some of the mounting ground electrodes 11d and 11e that are disposed near the upper and lower right portions of the center of the dielectric layer 53 and are hatched are dielectric The first and second ground electrodes 9 and 10 to which the layer 52 is hatched are electrically connected by via conductors.
 また、誘電体層52のハッチングが施された第1、第2のグランド電極9,10とビア導体により電気的に接続される誘電体層53の実装用接地電極11d,11eのうち、略中央の上寄りに設けられた実装用接地電極11d,11eは、他の実装用電極11よりも大なる面積を有し、複数のビア導体により誘電体層52のハッチングが施された第1、第2のグランド電極9,10と電気的に接続される。このように構成すると、当該実装用電極11d,11eに接続される、誘電体51,52に設けられた第1、第2のグランド電極9,10の接地状態を良好なものとすることができる。 Of the mounting ground electrodes 11d and 11e of the dielectric layer 53 electrically connected to the first and second ground electrodes 9 and 10 to which the dielectric layer 52 is hatched by via conductors, the center The mounting ground electrodes 11d and 11e provided on the upper side have a larger area than the other mounting electrodes 11, and the first and second dielectric layers 52 are hatched by a plurality of via conductors. The two ground electrodes 9 and 10 are electrically connected. If comprised in this way, the grounding state of the 1st, 2nd ground electrodes 9 and 10 provided in the dielectrics 51 and 52 connected to the said mounting electrodes 11d and 11e can be made favorable. .
 なお、誘電体層53の左下部分に設けられた実装用接地電極11eは、誘電体層52のパターン電極84とビア導体により電気的に接続される。 Note that the mounting ground electrode 11e provided in the lower left portion of the dielectric layer 53 is electrically connected to the pattern electrode 84 of the dielectric layer 52 by a via conductor.
 また、誘電体層53の略中央の下寄りには実装用共通電極11aが配設されており、誘電体層52の共通電極71,82とビア導体により電気的に接続される。また、誘電体層53の右上部分には2個の実装用受信電極11bが上下に並べて配設されており、それぞれ誘電体層52の右上部分に設けられた2個の受信電極72とビア導体により電気的に接続される。 In addition, a mounting common electrode 11a is disposed substantially below the center of the dielectric layer 53, and is electrically connected to the common electrodes 71 and 82 of the dielectric layer 52 by via conductors. In addition, two mounting receiving electrodes 11b are arranged one above the other in the upper right portion of the dielectric layer 53, and the two receiving electrodes 72 and via conductors provided in the upper right portion of the dielectric layer 52, respectively. Are electrically connected.
 また、誘電体層53の左上部分には実装用送信電極11cが配設されており、誘電体層52のパターン電極83とビア導体により電気的に接続される。また、誘電体層53の略中央の左寄りには実装用未接続電極11fが配設されており、誘電体層52の略中央の左寄りに配設された第2のグランド電極10とビア導体により電気的に接続される。 Further, a mounting transmission electrode 11c is disposed on the upper left portion of the dielectric layer 53, and is electrically connected to the pattern electrode 83 of the dielectric layer 52 by a via conductor. Further, the mounting unconnected electrode 11f is disposed on the left side of the approximate center of the dielectric layer 53, and is formed by the second ground electrode 10 and the via conductor disposed on the left side of the approximate center of the dielectric layer 52. Electrically connected.
 なお、図3(a)~(c)に示された、第1、第2のグランド電極9,10および実装用電極11e,11dのうち、ハッチングが施された各電極は、第1のグランド電極9に電気的に接続される。また、点で塗りつぶされた送信電極81、パターン電極83および実装用送信電極11cでは、送信フィルタによるフィルタ処理が施される前の送信信号が伝達され、点で塗りつぶされた共通電極71,82および実装用共通電極11aでは、送信フィルタによるフィルタ処理が施された後の送信信号が伝達される。 Of the first and second ground electrodes 9 and 10 and the mounting electrodes 11e and 11d shown in FIGS. 3A to 3C, each hatched electrode is a first ground. It is electrically connected to the electrode 9. In addition, the transmission electrode 81, the pattern electrode 83, and the mounting transmission electrode 11c filled with dots transmit the transmission signal before being subjected to the filtering process by the transmission filter, and the common electrodes 71 and 82 filled with dots and In the mounting common electrode 11a, the transmission signal after being subjected to the filter processing by the transmission filter is transmitted.
 また、図4に示すように、第1のグランド電極9に電気的に接続されてハッチングが施された各電極と、送信信号が伝達される点で塗りつぶされた共通電極71,82、送信電極81、パターン電極83、実装用共通電極11aおよび実装用送信電極11cとは、平面視において、重なることなく配置されている(図1の点線で囲まれた領域α参照)。 Further, as shown in FIG. 4, each electrode electrically connected to the first ground electrode 9 and hatched, common electrodes 71 and 82 filled with a point where a transmission signal is transmitted, and transmission electrodes 81, the pattern electrode 83, the mounting common electrode 11a, and the mounting transmitting electrode 11c are arranged without overlapping in a plan view (see a region α surrounded by a dotted line in FIG. 1).
 また、第1のグランド電極9に電気的に接続されてハッチングが施された各電極は、平面視において、送信信号が伝達される点で塗りつぶされた共通電極71,82、送信電極81、パターン電極83、実装用共通電極11aおよび実装用送信電極11cと、受信電極72との間に配置されている。 In addition, each hatched electrode electrically connected to the first ground electrode 9 has a common electrode 71, 82, a transmission electrode 81, a pattern filled with a transmission signal in a plan view. The electrode 83, the mounting common electrode 11a, the mounting transmission electrode 11c, and the reception electrode 72 are disposed.
 (製造方法)
 次に、図1の分波器1の製造方法の一例についてその概略を説明する。
(Production method)
Next, an outline of an example of a method for manufacturing the duplexer 1 of FIG. 1 will be described.
 まず、所定形状に形成されたセラミックグリーンシートに、レーザーなどでビアホールを形成し、内部に導体ペーストを充填したり、ビアフィルめっきを施すことにより層間接続用のビア導体が形成され、第1、第2の配線電極7,8、第1、第2のグランド電極9,10および実装用電極11などの電極パターンが導体ペーストにより印刷されて、実装用基板5を構成する各誘電体層51~53を形成するためのセラミックグリーンシートが準備される。なお、それぞれのセラミックグリーンシートには、一度に大量の実装用基板5を形成できるように、ビア導体や、第1、第2の配線電極7,8、第1、第2のグランド電極9,10および実装用電極11などの電極パターンが複数設けられている。 First, a via hole is formed in a ceramic green sheet formed in a predetermined shape with a laser or the like, and a via conductor for interlayer connection is formed by filling the inside with a conductive paste or by performing via fill plating. Electrode patterns such as the two wiring electrodes 7 and 8, the first and second ground electrodes 9 and 10 and the mounting electrode 11 are printed with a conductive paste, and the dielectric layers 51 to 53 constituting the mounting substrate 5 are printed. A ceramic green sheet for forming the is prepared. Each ceramic green sheet has via conductors, first and second wiring electrodes 7 and 8, first and second ground electrodes 9, so that a large number of mounting substrates 5 can be formed at one time. A plurality of electrode patterns such as 10 and mounting electrodes 11 are provided.
 次に、各誘電体層51~53が積層されて積層体が形成される。そして、焼成後に個々の実装用基板5に分割するための溝が、各実装用基板5の領域を囲むように形成される。続いて、積層体が低温焼成されることにより実装用基板5の集合体が形成される。 Next, the dielectric layers 51 to 53 are laminated to form a laminated body. And the groove | channel for dividing | segmenting into each mounting board | substrate 5 after baking is formed so that the area | region of each mounting board | substrate 5 may be enclosed. Subsequently, the assembly of the mounting substrate 5 is formed by firing the laminated body at a low temperature.
 次に、個々の実装用基板5に分割される前に、実装用基板5の集合体の実装面に受信フィルタ素子2および受信フィルタ素子3が実装され、受信フィルタ素子2および受信フィルタ素子3が実装された実装用基板5の集合体の実装面にモールド樹脂が充填されて、これが加熱硬化されることによりモールド層6が各実装用基板5に設けられて分波器1の集合体が形成される。そして、分波器1の集合体は個々に分割されて、分波器1が完成する。 Next, before being divided into individual mounting substrates 5, the reception filter element 2 and the reception filter element 3 are mounted on the mounting surface of the assembly of the mounting substrates 5, and the reception filter element 2 and the reception filter element 3 are The mounting surface of the assembly of the mounted mounting substrates 5 is filled with mold resin, and this is heated and cured, whereby the mold layer 6 is provided on each mounting substrate 5 to form an assembly of the duplexer 1. Is done. Then, the aggregate of the duplexers 1 is individually divided, and the duplexer 1 is completed.
 このように形成された分波器1では、マザー基板の送信信号ラインTxから、LPF4および送信電極81を介して送信フィルタ素子3の送信端子31に出力された送信信号は、送信フィルタに入力されて所定のフィルタ処理が施されて、共通端子32から実装用基板5側に出力され、共通電極82を介してマザー基板のアンテナラインANTに出力される。また、マザー基板のアンテナラインANTから、共通電極71を介して受信フィルタ素子2の共通端子21に入力された受信信号は、受信フィルタに入力されて所定のフィルタ処理が施されて、受信端子22から実装用基板5側に出力され、受信電極72および実装用受信電極11bを介してマザー基板の受信信号ラインRxに出力される。 In the duplexer 1 formed in this way, the transmission signal output from the transmission signal line Tx of the mother board to the transmission terminal 31 of the transmission filter element 3 via the LPF 4 and the transmission electrode 81 is input to the transmission filter. Then, a predetermined filtering process is performed, the signal is output from the common terminal 32 to the mounting substrate 5 side, and is output to the antenna line ANT of the mother substrate via the common electrode 82. Further, the reception signal input from the antenna line ANT of the mother board to the common terminal 21 of the reception filter element 2 via the common electrode 71 is input to the reception filter and subjected to a predetermined filtering process. Is output to the mounting substrate 5 side and is output to the reception signal line Rx of the mother substrate via the reception electrode 72 and the mounting reception electrode 11b.
 なお、分波器1は、上記した製造方法に限らず、周知の一般的な製造方法により形成すればよく、実装用基板5は、樹脂やセラミック、ポリマー材料などを用いた、プリント基板、LTCC、アルミナ系基板、ガラス基板、複合材料基板、多層基板などで形成することができ、分波器1の使用目的に応じて、適宜最適な材質を選択して実装用基板5を形成すればよい。 The duplexer 1 is not limited to the above-described manufacturing method, and may be formed by a known general manufacturing method. The mounting substrate 5 is a printed circuit board, LTCC using resin, ceramic, polymer material, or the like. The substrate 5 can be formed of an alumina substrate, a glass substrate, a composite material substrate, a multilayer substrate, etc., and the mounting substrate 5 may be formed by selecting an optimal material according to the purpose of use of the duplexer 1. .
 以上のように、この実施形態では、通過帯域が異なる受信フィルタ素子2および送信フィルタ素子3が実装された実装用基板5には、受信フィルタ素子2および送信フィルタ素子3用として信号伝達用の第1、第2の配線電極7,8および接地用の第1、第2のグランド電極9,10がそれぞれ設けられている。そして、受信フィルタ素子2の接地端子23に接続された第1のグランド電極9と、送信フィルタ素子3の送信端子31および共通端子32に接続された第2の配線電極8とが、平面視において重なることなく配置されているため、第1のグランド電極9と第2の配線電極8と間に寄生容量が発生するのが抑制されて、第1のグランド電極9および第2の配線電極8が電磁界的に結合することを防止することができる。 As described above, in this embodiment, the mounting substrate 5 on which the reception filter element 2 and the transmission filter element 3 having different pass bands are mounted has a signal transmission first for the reception filter element 2 and the transmission filter element 3. 1, first wiring electrodes 7 and 8 and first and second ground electrodes 9 and 10 for grounding are provided, respectively. The first ground electrode 9 connected to the ground terminal 23 of the reception filter element 2 and the second wiring electrode 8 connected to the transmission terminal 31 and the common terminal 32 of the transmission filter element 3 are in plan view. Since they are arranged without overlapping, the generation of parasitic capacitance between the first ground electrode 9 and the second wiring electrode 8 is suppressed, and the first ground electrode 9 and the second wiring electrode 8 are Electromagnetic coupling can be prevented.
 したがって、第1のグランド電極9と第2の配線電極8との間に寄生容量が発生するのが抑制されるため、第2の配線電極8を伝達する送信信号が第1のグランド電極9に漏洩することが防止され、第2の配線電極8を伝達する送信信号が、第1のグランド電極9を介して第1の配線電極7に伝達するのを防止することができるので、分波器1が備える受信フィルタ素子2および送信フィルタ素子3間のアイソレーション特性の向上を図ることができる。 Therefore, since the generation of parasitic capacitance between the first ground electrode 9 and the second wiring electrode 8 is suppressed, a transmission signal transmitted through the second wiring electrode 8 is transmitted to the first ground electrode 9. Leakage can be prevented and transmission signals transmitted through the second wiring electrode 8 can be prevented from being transmitted to the first wiring electrode 7 via the first ground electrode 9. The isolation characteristic between the reception filter element 2 and the transmission filter element 3 included in 1 can be improved.
 すなわち、送信フィルタ素子3には、送信フィルタの入力側に接続される送信端子31と出力側に接続される共通端子32とが信号用端子として設けられている。そして、第2の配線電極8は、送信端子31と接続された送信電極81および共通端子32と接続された共通電極82を有しており、送信電極81および共通電極82により、通信用に電力が増幅されて出力の大きい送信信号が伝達されるが、第1のグランド電極9と、送信電極81および共通電極82とが、平面視において重なることなく配置されているため、第1のグランド電極9と、送信電極81および共通電極82と間に寄生容量が発生するのが抑制されて、第1のグランド電極9と送信電極81および共通電極82とが電磁界的に結合することを防止することができる。 That is, the transmission filter element 3 is provided with a transmission terminal 31 connected to the input side of the transmission filter and a common terminal 32 connected to the output side as signal terminals. The second wiring electrode 8 has a transmission electrode 81 connected to the transmission terminal 31 and a common electrode 82 connected to the common terminal 32, and the transmission electrode 81 and the common electrode 82 provide power for communication. The first ground electrode 9, the transmission electrode 81, and the common electrode 82 are arranged so as not to overlap each other in plan view, so that the first ground electrode 9 is transmitted. 9 is prevented from being generated between the transmission electrode 81 and the common electrode 82, and the first ground electrode 9, the transmission electrode 81, and the common electrode 82 are prevented from being electromagnetically coupled. be able to.
 したがって、第1のグランド電極9と送信電極81および共通電極82との間に寄生容量が発生するのが抑制されるため、送信電極81および共通電極82を伝達する出力の大きな通信用の送信信号が、第1のグランド電極9に漏洩することが防止されて、送信信号が第1のグランド電極9を介して第1の配線電極7に伝達するのを防止することができるので、非常に実用的である。 Therefore, since the generation of parasitic capacitance between the first ground electrode 9 and the transmission electrode 81 and the common electrode 82 is suppressed, a transmission signal for communication having a large output that transmits the transmission electrode 81 and the common electrode 82. However, since leakage to the first ground electrode 9 is prevented and transmission signals can be prevented from being transmitted to the first wiring electrode 7 through the first ground electrode 9, it is very practical. Is.
 また、第2の配線電極8として、送信フィルタ素子3の送信端子81に接続されるフィルタ回路を形成するパターン電極83をさらに設けることにより、送信フィルタ素子3の送信フィルタに入力される送信信号に種々のフィルタ回路によるフィルタ処理を施すことができる。 Further, by providing a pattern electrode 83 that forms a filter circuit connected to the transmission terminal 81 of the transmission filter element 3 as the second wiring electrode 8, a transmission signal input to the transmission filter of the transmission filter element 3 is provided. Filter processing by various filter circuits can be performed.
 また、フィルタ回路を形成するパターン電極83は、第1のグランド電極9と平面視において重なることなく配置されているため、第1のグランド電極9とパターン電極83との間に寄生容量が発生するのが抑制されて、第1のグランド電極9とパターン電極83とが電磁界的に結合することを防止することができる。 Further, since the pattern electrode 83 forming the filter circuit is arranged so as not to overlap the first ground electrode 9 in plan view, a parasitic capacitance is generated between the first ground electrode 9 and the pattern electrode 83. Therefore, the first ground electrode 9 and the pattern electrode 83 can be prevented from being electromagnetically coupled.
 したがって、第1のグランド電極9とパターン電極83との間に寄生容量が発生するのが抑制されるため、パターン電極83を伝達する出力の大きな通信用の送信信号が、第1のグランド電極9に漏洩することが防止されて、送信信号が第1のグランド電極9を介して第1の配線電極7に伝達するのを防止することができる。 Therefore, since the generation of parasitic capacitance between the first ground electrode 9 and the pattern electrode 83 is suppressed, a transmission signal for communication having a large output that transmits the pattern electrode 83 is transmitted to the first ground electrode 9. It is possible to prevent the transmission signal from being transmitted to the first wiring electrode 7 through the first ground electrode 9.
 また、第1のグランド電極9は、平面視において、送信電極81および共通電極71,82と、受信電極72との間に配置されているため、接地された第1のグランド電極9により、送信電極31および共通電極71,82を伝達する出力の大きな通信用の送信信号が受信電極72に漏洩するのが防止されるので、受信フィルタ素子2および送信フィルタ素子3間のより一層のアイソレーション特性の向上を図ることができる。 Further, since the first ground electrode 9 is disposed between the transmission electrode 81 and the common electrodes 71 and 82 and the reception electrode 72 in plan view, the first ground electrode 9 that is grounded transmits the first ground electrode 9. Since the transmission signal for communication having a large output transmitted through the electrode 31 and the common electrodes 71 and 82 is prevented from leaking to the reception electrode 72, further isolation characteristics between the reception filter element 2 and the transmission filter element 3 are obtained. Can be improved.
 また、受信フィルタ素子2には接地端子23が複数設けられており、平面視において、受信フィルタ素子2の各接地端子23と重なって配置される平板状のパターン形状を有する大面積の第1のグランド電極9により、受信フィルタ素子2の各接地端子23が接地されることで、受信フィルタ素子2の接地状態を良好なものとすることができるので、受信フィルタ素子2および送信フィルタ素子3間のアイソレーション特性の向上を図ることができる。 The reception filter element 2 is provided with a plurality of ground terminals 23, and has a large area of the first area having a flat pattern shape that is arranged so as to overlap each ground terminal 23 of the reception filter element 2 in plan view. Since each ground terminal 23 of the reception filter element 2 is grounded by the ground electrode 9, the grounding state of the reception filter element 2 can be improved, so that the reception filter element 2 and the transmission filter element 3 are connected to each other. Isolation characteristics can be improved.
 また、実装用基板5の裏面に設けられた複数の実装用電極11のうち、第1のグランド電極9に接続される一部の実装用電極11eは、他の実装用電極11よりも大なる面積を有しているため、例えば、大面積の一部の実装用電極11eを、第1、第2の配線電極7,8と接続される複数の他の実装用電極11間に配置することにより、複数の他の実装用電極11間での電気的な干渉を抑制することができる。 Among the plurality of mounting electrodes 11 provided on the back surface of the mounting substrate 5, some of the mounting electrodes 11 e connected to the first ground electrode 9 are larger than the other mounting electrodes 11. Since it has an area, for example, a part of the mounting electrode 11e having a large area is arranged between a plurality of other mounting electrodes 11 connected to the first and second wiring electrodes 7 and 8. Thus, electrical interference between the plurality of other mounting electrodes 11 can be suppressed.
 また、第1のグランド電極9および大面積の一部の実装用電極11eが、複数のビア導体により電気的に接続されることにより、複数のビア導体に生じる寄生インダクタンスを低減することができ、第1のグランド電極9を理想的な状態で接地することができる。 Further, the first ground electrode 9 and a part of the mounting electrode 11e having a large area are electrically connected by a plurality of via conductors, so that the parasitic inductance generated in the plurality of via conductors can be reduced. The first ground electrode 9 can be grounded in an ideal state.
 <第2実施形態>
 次に、図5を参照して本発明の第2実施形態について説明する。図5は本発明の第2実施形態における実装用基板の電極形状の一例を示す平面図であり、(a)~(c)はそれぞれ実装用基板の各誘電体層における電極形状を示す。図6は実装用基板の電極形状の変形例を示す平面図である。
<Second Embodiment>
Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 5 is a plan view showing an example of the electrode shape of the mounting substrate in the second embodiment of the present invention, and FIGS. 5A to 5C show the electrode shapes in the respective dielectric layers of the mounting substrate. FIG. 6 is a plan view showing a modification of the electrode shape of the mounting substrate.
 この実施形態が上記した第1実施形態と異なるのは、図5に示すように、実装用基板の各誘電体層51~53に設けられた各電極の形状および配置位置の一部が異なる点であり、その他の構成は上記した第1実施形態と同様の構成であるため、同一符号を付すことによりその構成の説明は省略する。 As shown in FIG. 5, this embodiment is different from the first embodiment described above in that the shape of each electrode provided on each dielectric layer 51 to 53 of the mounting substrate and a part of the arrangement position are different. Since the other configuration is the same as that of the first embodiment, description of the configuration is omitted by giving the same reference numerals.
 この実施形態では、図5(a)に示すように、誘電体層51の略中央の上寄りに配設された第2のグランド電極10が2個に分割されており、上側に配置された第2のグランド電極10の位置G2に送信フィルタ素子3の接地端子33が接続され、下側に配置された第2のグランド電極10の位置NC2に送信フィルタ素子3の未接続端子が接続される。また、誘電体層51の左下部分に、上下に長く形成された電極パターンにより第2のグランド電極10が配設されており、その上端側および下端側の位置G2に、それぞれ送信フィルタ素子3の接地端子33が接続される。 In this embodiment, as shown in FIG. 5 (a), the second ground electrode 10 disposed substantially above the center of the dielectric layer 51 is divided into two parts and disposed on the upper side. The ground terminal 33 of the transmission filter element 3 is connected to the position G2 of the second ground electrode 10, and the unconnected terminal of the transmission filter element 3 is connected to the position NC2 of the second ground electrode 10 arranged on the lower side. . In addition, the second ground electrode 10 is disposed in the lower left portion of the dielectric layer 51 with an electrode pattern formed so as to be long in the vertical direction. A ground terminal 33 is connected.
 また、図5(c)に示すように、誘電体層53の裏面に配設された各実装用電極11が、平面視において、分波器1の重心を回転中心として点対称に配置されている。このように構成すると、各実装用電極11が分波器11の重心を回転中心として点対称に配置されているため、分波器1を回路モジュールのモジュール基板に実装するときに、分波器1が傾くことが防止される。したがって、分波器1を回路モジュールのモジュール基板に実装するときの、実装精度や実装強度などの実装性を向上することができる。 Further, as shown in FIG. 5C, the mounting electrodes 11 arranged on the back surface of the dielectric layer 53 are arranged point-symmetrically with the center of gravity of the duplexer 1 as the rotation center in plan view. Yes. With this configuration, each mounting electrode 11 is arranged point-symmetrically with the center of gravity of the duplexer 11 as the center of rotation. Therefore, when the duplexer 1 is mounted on the module substrate of the circuit module, the duplexer 1 is prevented from tilting. Therefore, mountability such as mounting accuracy and mounting strength when the duplexer 1 is mounted on the module substrate of the circuit module can be improved.
 また、図6の実装用基板の電極形状の変形例に示すように、誘電体層53の裏面に形成された各実装用電極11の大きさおよび形状を同一に形成してもよい。このようにすると、分波器1を実装するときに、はんだペーストを印刷する際に使用されるはんだ印刷用マスクの設計を容易なものとすることができる。また、分波器1が回路モジュールのモジュール基板に実装されたときに、落下による衝撃や、加熱、冷却に伴う基板の伸縮などにより分波器1とモジュール基板との実装面に加わる応力を、各実装用電極11に均一に分散することができる。 Further, as shown in the modification of the electrode shape of the mounting substrate in FIG. 6, the size and shape of each mounting electrode 11 formed on the back surface of the dielectric layer 53 may be formed identically. If it does in this way, when mounting the splitter 1, the design of the mask for solder printing used when printing a solder paste can be made easy. Further, when the duplexer 1 is mounted on the module substrate of the circuit module, the stress applied to the mounting surface between the duplexer 1 and the module substrate due to impact caused by dropping or expansion / contraction of the substrate accompanying heating and cooling, It can be uniformly dispersed in each mounting electrode 11.
 また、このとき、図6に示すように、誘電体層53の裏面に形成された一部の実装用電極11に切欠11gを設けたり、誘電体層53の裏面に認識マーク11hを設けるとよい。このように構成すると、分波器1(誘電体層53)の裏面に、各実装用電極11が、同一形状および同一の大きさで形成されると共に、各実装用電極11が、点対称に配置されていても、切欠11gまたは認識マーク11hを認識することにより、分波器1の平面視における上下方向を認識することができるので、分波器1の裏面に形成された各実装用電極11の電極特性を誤りなく認識することができる。 Further, at this time, as shown in FIG. 6, a notch 11 g may be provided in a part of the mounting electrodes 11 formed on the back surface of the dielectric layer 53, or a recognition mark 11 h may be provided on the back surface of the dielectric layer 53. . With this configuration, the mounting electrodes 11 are formed in the same shape and the same size on the back surface of the duplexer 1 (dielectric layer 53), and the mounting electrodes 11 are point-symmetric. Even if it is arranged, it is possible to recognize the vertical direction in plan view of the duplexer 1 by recognizing the notch 11g or the recognition mark 11h, so each mounting electrode formed on the back surface of the duplexer 1 11 electrode characteristics can be recognized without error.
 <第3実施形態>
 次に、図7を参照して本発明の第3実施形態について説明する。図7は本発明の第3実施形態における実装用基板の電極形状の一例を示す平面図であり、(a)~(c)はそれぞれ実装用基板の各誘電体層における電極形状を示す。
<Third Embodiment>
Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 7 is a plan view showing an example of the electrode shape of the mounting substrate according to the third embodiment of the present invention. FIGS. 7A to 7C show the electrode shapes in the respective dielectric layers of the mounting substrate.
 この実施形態が上記した第2実施形態と異なるのは、図7に示すように、実装用基板の各誘電体層51~53に設けられた各電極の形状および配置位置の一部が異なる点であり、その他の構成は上記した第1および第2実施形態と同様の構成であるため、同一符号を付すことによりその構成の説明は省略する。 This embodiment is different from the second embodiment described above in that, as shown in FIG. 7, the shape of each electrode provided on each dielectric layer 51 to 53 of the mounting substrate and a part of the arrangement position are different. Since other configurations are the same as those in the first and second embodiments described above, description of the configuration is omitted by giving the same reference numerals.
 この実施形態では、図7(c)に示すように、誘電体層53の裏面に形成された実装用電極のうち、誘電体層51の略中央の上寄りに配設された実装用接地電極11d,11eおよび下寄りに配設された実装用共通電極11aの面積が、他の実装用電極11の面積よりも大きく形成されている。 In this embodiment, as shown in FIG. 7 (c), among the mounting electrodes formed on the back surface of the dielectric layer 53, the mounting ground electrode disposed substantially above the center of the dielectric layer 51. 11d and 11e and the mounting common electrode 11a disposed on the lower side are formed to be larger than the areas of the other mounting electrodes 11.
 したがって、誘電体層51の略中央の上寄りに配設された実装用接地電極11d,11eの面積を大きく形成することにより、当該実装用接地電極11d,11eと、誘電体層52に配設された第1、第2のグランド電極9,10とを複数のビア電極で電気的に接続することができるため、上記した第1実施形態と同様の効果を奏することができる。 Therefore, by forming the mounting ground electrodes 11d and 11e, which are disposed substantially above the center of the dielectric layer 51, in a large area, the mounting ground electrodes 11d and 11e and the dielectric layer 52 are disposed. Since the first and second ground electrodes 9 and 10 can be electrically connected by a plurality of via electrodes, the same effects as those of the first embodiment described above can be obtained.
 また、誘電体層51の略中央の下寄りに配設された実装用共通電極11aの面積を大きく形成することにより、誘電体層51の共通電極71,82と、誘電体層53の実装用共通電極11aとを、図7(b)に示すように、ビア導体により形成された誘電体層52の共通電極71,82により電気的に接続することができる。したがって、誘電体層51の共通電極71,82と、誘電体層53の実装用共通電極11aとを最短の経路で電気的に接続することにより、電磁的なノイズの影響を低減することができる。 Further, by increasing the area of the mounting common electrode 11 a disposed substantially below the center of the dielectric layer 51, the common electrodes 71 and 82 of the dielectric layer 51 and the mounting of the dielectric layer 53 are mounted. As shown in FIG. 7B, the common electrode 11a can be electrically connected by the common electrodes 71 and 82 of the dielectric layer 52 formed by via conductors. Therefore, the influence of electromagnetic noise can be reduced by electrically connecting the common electrodes 71 and 82 of the dielectric layer 51 and the mounting common electrode 11a of the dielectric layer 53 through the shortest path. .
 <第4実施形態>
 次に、図8を参照して本発明の第4実施形態について説明する。図8は本発明の第4実施形態における実装用基板の電極形状の一例を示す平面図であり、(a)~(c)はそれぞれ実装用基板の各誘電体層における電極形状を示す。
<Fourth embodiment>
Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 8 is a plan view showing an example of the electrode shape of the mounting substrate in the fourth embodiment of the present invention, and FIGS. 8A to 8C show the electrode shapes in the respective dielectric layers of the mounting substrate.
 この実施形態が上記した第1実施形態と異なるのは、図8に示すように、実装用基板の各誘電体層51~53に設けられた各電極の形状および配置位置の一部が異なる点であり、その他の構成は上記した第1実施形態と同様の構成であるため、同一符号を付すことによりその構成の説明は省略する。 This embodiment is different from the first embodiment described above in that, as shown in FIG. 8, the shape of each electrode provided on each dielectric layer 51 to 53 of the mounting substrate and a part of the arrangement position are different. Since the other configuration is the same as that of the first embodiment, description of the configuration is omitted by giving the same reference numerals.
 この実施形態では、図8(a)に示すように、誘電体層51の略中央に共通電極71,82が配設されており、受信フィルタ素子2の共通端子21および送信フィルタ素子3の共通端子32が、それぞれ共通電極71,82の位置A1,A2に接続される。また、誘電体層51の共通電極71,82の位置に対応して、図8(c)に示すように、誘電体層53の略中央に実装用共通電極11aが配設されており、誘電体層51の共通電極71,82および誘電体層53の実装用共通電極11は、図8(b)に示すように、誘電体層52の略中央に配設された共通電極71,82を介して電気的に接続される。 In this embodiment, as shown in FIG. 8A, common electrodes 71 and 82 are disposed at substantially the center of the dielectric layer 51, and the common terminal 21 of the reception filter element 2 and the transmission filter element 3 are common. The terminal 32 is connected to the positions A1 and A2 of the common electrodes 71 and 82, respectively. Further, as shown in FIG. 8C, the mounting common electrode 11a is disposed at substantially the center of the dielectric layer 53 in correspondence with the positions of the common electrodes 71 and 82 of the dielectric layer 51. The common electrodes 71 and 82 of the body layer 51 and the mounting common electrode 11 of the dielectric layer 53 include the common electrodes 71 and 82 disposed substantially at the center of the dielectric layer 52 as shown in FIG. Electrically connected.
 この実施形態においても、上記した第1実施形態と同様の効果を奏することができる。 Also in this embodiment, the same effects as those of the first embodiment described above can be obtained.
 <第5実施形態>
 次に、図9を参照して本発明の第5実施形態について説明する。図9は本発明の第5実施形態における実装用基板の電極形状の一例を示す平面図であり、(a)~(c)はそれぞれ実装用基板の各誘電体層における電極形状を示す。
<Fifth Embodiment>
Next, a fifth embodiment of the present invention will be described with reference to FIG. FIG. 9 is a plan view showing an example of the electrode shape of the mounting substrate according to the fifth embodiment of the present invention. FIGS. 9A to 9C show the electrode shapes in the respective dielectric layers of the mounting substrate.
 この実施形態が上記した第1実施形態と異なるのは、図9に示すように、実装用基板の各誘電体層51~53に設けられた各電極の形状および配置位置の一部が異なる点であり、その他の構成は上記した第1実施形態と同様の構成であるため、同一符号を付すことによりその構成の説明は省略する。 This embodiment differs from the first embodiment described above in that, as shown in FIG. 9, the shape of each electrode provided on each dielectric layer 51 to 53 of the mounting substrate and a part of the arrangement position are different. Since the other configuration is the same as that of the first embodiment, description of the configuration is omitted by giving the same reference numerals.
 この実施形態では、図9(a)に示すように、誘電体層51の略中央の上寄りに配設された第2のグランド電極10が2個に分割されており、上側に配置された第2のグランド電極10の位置G2に送信フィルタ素子3の接地端子33が接続され、下側に配置された第2のグランド電極10の位置NC2に送信フィルタ素子3の未接続端子が接続される。また、誘電体層51の略中央の左寄りに配設された第2のグランド電極10の位置G2に、送信フィルタ素子3の接地端子33が接続される。 In this embodiment, as shown in FIG. 9A, the second ground electrode 10 disposed substantially above the center of the dielectric layer 51 is divided into two parts and is disposed on the upper side. The ground terminal 33 of the transmission filter element 3 is connected to the position G2 of the second ground electrode 10, and the unconnected terminal of the transmission filter element 3 is connected to the position NC2 of the second ground electrode 10 arranged on the lower side. . Further, the ground terminal 33 of the transmission filter element 3 is connected to the position G2 of the second ground electrode 10 disposed on the left side of the approximate center of the dielectric layer 51.
 また、図9(b)に示すように、誘電体層52の略中央の上寄りに、第2のグランド電極10が2個上下に並べて配設されている。そして、上側の第2のグランド電極10により、誘電体層51の略中央の上寄りに配設された2個の第2のグランド電極10のうち、上側に配置された第2のグランド電極10と、誘電体層53の略中央の上寄りに配設された実装用接地電極11eとが電気的に接続される。また、下側の第2のグランド電極10により、誘電体層51の略中央の上寄りに配設された2個の第2のグランド電極10のうち、下側に配置された第2のグランド電極10と、誘電体層53の略中央に配設された実装用未接続電極11fとが電気的に接続される。 Further, as shown in FIG. 9B, two second ground electrodes 10 are arranged vertically above the approximate center of the dielectric layer 52. Then, the second ground electrode 10 disposed on the upper side of the two second ground electrodes 10 disposed substantially above the center of the dielectric layer 51 by the upper second ground electrode 10. Are electrically connected to the mounting ground electrode 11e disposed substantially above the center of the dielectric layer 53. In addition, the second ground electrode 10 disposed on the lower side of the two second ground electrodes 10 disposed substantially above the center of the dielectric layer 51 by the second ground electrode 10 on the lower side. The electrode 10 is electrically connected to the mounting unconnected electrode 11f disposed substantially at the center of the dielectric layer 53.
 以上のように、この実施形態では、上記した実施形態と異なり、第1のグランド電極9および第2のグランド電極10が、電気的に絶縁された状態で配置されている。したがって、第1、第2の配線電極7,8を伝達する信号が、それぞれ第1、第2のグランド電極9,10に漏洩しても、第1、第2のグランド電極9,10が電気的に絶縁された状態で配置されているため、第1、第2のグランド電極9,10に漏洩した信号が、互いに他方のグランド電極に伝達するのが防止されるので、第1、第2のフィルタ素子2,3間のアイソレーション特性の向上をさらに図ることができる。 As described above, in this embodiment, unlike the above-described embodiment, the first ground electrode 9 and the second ground electrode 10 are arranged in an electrically insulated state. Therefore, even if signals transmitted through the first and second wiring electrodes 7 and 8 leak to the first and second ground electrodes 9 and 10, respectively, the first and second ground electrodes 9 and 10 are electrically connected. Since the first and second ground electrodes 9 and 10 are prevented from being transmitted to the other ground electrodes, the first and second ground electrodes 9 and 10 are prevented from being transmitted to each other. The isolation characteristics between the filter elements 2 and 3 can be further improved.
 また、この実施形態では、送信フィルタ素子3の接地端子33および未接続端子が、互いに電気的に絶縁された状態で、それぞれ誘電体層53の裏面に設けられた実装用接地電極11eおよび実装用未接続電極11fと電気的に接続される。したがって、共通端子21,32と、受信端子22と、送信端子31と、受信フィルタ素子2の接地端子23と、送信フィルタ素子3の接地端子33とが、互いに電気的に絶縁された状態で、それぞれ、それぞれ誘電体層53の裏面に設けられた各実装用電極11に電気的に接続されるため、各端子間の電気的な相互干渉を低減することができるので、第1、第2のフィルタ素子2,3間のアイソレーション特性の向上をさらに図ることができる。 In this embodiment, the ground terminal 33 and the unconnected terminal of the transmission filter element 3 are electrically insulated from each other, and the mounting ground electrode 11e and the mounting ground electrode provided on the back surface of the dielectric layer 53, respectively. It is electrically connected to the unconnected electrode 11f. Therefore, the common terminals 21 and 32, the reception terminal 22, the transmission terminal 31, the ground terminal 23 of the reception filter element 2, and the ground terminal 33 of the transmission filter element 3 are electrically insulated from each other. Since the respective electrodes 11 are electrically connected to the mounting electrodes 11 provided on the back surface of the dielectric layer 53, respectively, electrical mutual interference between the terminals can be reduced. The isolation characteristics between the filter elements 2 and 3 can be further improved.
 なお、本発明は上記した実施形態に限定されるものではなく、その趣旨を逸脱しない限りにおいて、上記したもの以外に種々の変更を行なうことが可能である。例えば、上記した実施形態では、本発明の第1のフィルタ素子を受信フィルタ素子2により形成し、本発明の第2のフィルタ素子を送信フィルタ素子3により形成したが、第1、第2のフィルタ素子を、それぞれ送信フィルタ素子3および受信フィルタ素子2により形成してもよい。 Note that the present invention is not limited to the above-described embodiment, and various modifications other than those described above can be made without departing from the spirit of the present invention. For example, in the above-described embodiment, the first filter element of the present invention is formed by the reception filter element 2, and the second filter element of the present invention is formed by the transmission filter element 3, but the first and second filters The elements may be formed by the transmission filter element 3 and the reception filter element 2, respectively.
 本発明は、通過帯域が異なる第1のフィルタ素子および第2のフィルタ素子を備える分波器に広く適用することができる。 The present invention can be widely applied to a duplexer including a first filter element and a second filter element having different pass bands.
 1  分波器
 2  受信フィルタ素子(第1のフィルタ素子)
 21  共通端子
 22  受信端子
 23  接地端子
 3  送信フィルタ素子(第2のフィルタ素子)
 31  送信端子
 32  共通端子
 33  接地端子
 4  ローパスフィルタ(フィルタ回路)
 5  実装用基板
 7  第1の配線電極
 71  共通電極
 72  受信電極
 8  第2の配線電極
 81  送信電極
 82  共通電極
 83  パターン電極
 9  第1のグランド電極
 10  第2のグランド電極
 11  実装用電極
1 demultiplexer 2 reception filter element (first filter element)
21 Common terminal 22 Reception terminal 23 Ground terminal 3 Transmission filter element (second filter element)
31 Transmission terminal 32 Common terminal 33 Ground terminal 4 Low-pass filter (filter circuit)
5 mounting substrate 7 first wiring electrode 71 common electrode 72 reception electrode 8 second wiring electrode 81 transmission electrode 82 common electrode 83 pattern electrode 9 first ground electrode 10 second ground electrode 11 mounting electrode

Claims (7)

  1.  通過帯域が異なる第1のフィルタ素子および第2のフィルタ素子と、
     前記第1、第2のフィルタ素子が実装される実装用基板と、
     前記実装用基板に前記第1、第2のフィルタ素子用としてそれぞれ設けられた信号伝達用の第1、第2の配線電極および接地用の第1、第2のグランド電極とを備え、
     前記第1のフィルタ素子の接地端子に接続された前記第1のグランド電極と、前記第2のフィルタ素子の信号用端子に接続された前記第2の配線電極とが、平面視において重なることなく配置されている
     ことを特徴とする分波器。
    A first filter element and a second filter element having different passbands;
    A mounting substrate on which the first and second filter elements are mounted;
    The mounting board includes first and second wiring electrodes for signal transmission and first and second ground electrodes for grounding, which are provided for the first and second filter elements, respectively.
    The first ground electrode connected to the ground terminal of the first filter element and the second wiring electrode connected to the signal terminal of the second filter element do not overlap in a plan view. A duplexer characterized by being arranged.
  2.  前記第1のグランド電極と、前記第2のフィルタ素子の接地端子に接続された前記第2のグランド電極とが、電気的に絶縁された状態で配置されていることを特徴とする請求項1に記載の分波器。 2. The first ground electrode and the second ground electrode connected to a ground terminal of the second filter element are disposed in an electrically insulated state. The duplexer described in 1.
  3.  前記第2のフィルタ素子は送信信号用の送信フィルタを有し、
     前記第2のフィルタ素子には、前記送信フィルタの入力側に接続される送信端子と出力側に接続される共通端子とが前記第2のフィルタ素子の前記信号用端子として設けられ、
     前記第2の配線電極は、前記送信端子と接続された送信電極および前記第2のフィルタ素子の前記共通端子と接続された共通電極を有することを特徴とする請求項1または2に記載の分波器。
    The second filter element includes a transmission filter for a transmission signal;
    In the second filter element, a transmission terminal connected to the input side of the transmission filter and a common terminal connected to the output side are provided as the signal terminals of the second filter element,
    The component according to claim 1, wherein the second wiring electrode includes a transmission electrode connected to the transmission terminal and a common electrode connected to the common terminal of the second filter element. Waver.
  4.  前記第2の配線電極は、前記送信端子に接続されるフィルタ回路を形成するパターン電極をさらに有することを特徴とする請求項3に記載の分波器。 The duplexer according to claim 3, wherein the second wiring electrode further includes a pattern electrode forming a filter circuit connected to the transmission terminal.
  5.  前記第1の配線電極は、前記第1のフィルタ素子の信号用端子に接続され、
     前記第1のフィルタ素子は受信信号用の受信フィルタを有し、
     前記第1のフィルタ素子には、前記受信フィルタの入力側に接続される共通端子と出力側に接続される受信端子とが前記第1のフィルタ素子の前記信号用端子として設けられ、
     前記第1の配線電極は、前記第1のフィルタ素子の共通端子と接続された共通電極および前記受信端子と接続された受信電極とを有し、
     前記第1の配線電極の前記共通電極および前記第2の配線電極の前記共通電極が電気的に接続されると共に、
     前記第1のグランド電極は、平面視において、前記送信電極および前記第1、第2の配線電極それぞれの前記共通電極と、前記受信電極との間に配置されていることを特徴とする請求項3または4に記載の分波器。
    The first wiring electrode is connected to a signal terminal of the first filter element;
    The first filter element includes a reception filter for a reception signal;
    In the first filter element, a common terminal connected to the input side of the reception filter and a reception terminal connected to the output side are provided as the signal terminals of the first filter element,
    The first wiring electrode has a common electrode connected to a common terminal of the first filter element and a receiving electrode connected to the receiving terminal,
    The common electrode of the first wiring electrode and the common electrode of the second wiring electrode are electrically connected;
    The first ground electrode is arranged between the transmission electrode and the common electrode of each of the first and second wiring electrodes and the reception electrode in plan view. The duplexer according to 3 or 4.
  6.  前記第1のフィルタ素子には接地端子が複数設けられており、
     前記第1のグランド電極は、平面視において、前記第1のフィルタ素子の前記各接地端子と重なって配置される平板状のパターン形状を有することを特徴とする請求項1ないし5のいずれかに記載の分波器。
    The first filter element is provided with a plurality of ground terminals,
    The first ground electrode has a flat pattern shape arranged so as to overlap the ground terminals of the first filter element in plan view. The duplexer described.
  7.  前記実装用基板の裏面に設けられた複数の実装用電極をさらに備え、
     前記第1のグランド電極に接続される一部の前記実装用電極は、他の前記実装用電極よりも大なる面積を有し、
     前記第1のグランド電極および前記一部の実装用電極は、複数のビア導体により電気的に接続されていることを特徴とする請求項1ないし6のいずれかに記載の分波器。
    A plurality of mounting electrodes provided on the back surface of the mounting substrate;
    Some of the mounting electrodes connected to the first ground electrode have a larger area than the other mounting electrodes,
    7. The duplexer according to claim 1, wherein the first ground electrode and the part of the mounting electrodes are electrically connected by a plurality of via conductors.
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