WO2008029641A1 - Circuit board for wave separator device, wave separator, and communication device - Google Patents

Circuit board for wave separator device, wave separator, and communication device Download PDF

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Publication number
WO2008029641A1
WO2008029641A1 PCT/JP2007/066451 JP2007066451W WO2008029641A1 WO 2008029641 A1 WO2008029641 A1 WO 2008029641A1 JP 2007066451 W JP2007066451 W JP 2007066451W WO 2008029641 A1 WO2008029641 A1 WO 2008029641A1
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WO
WIPO (PCT)
Prior art keywords
circuit board
duplexer
dielectric layers
signal
conductor
Prior art date
Application number
PCT/JP2007/066451
Other languages
French (fr)
Japanese (ja)
Inventor
Takeshi Takenoshita
Takanori Ikuta
Wataru Koga
Original Assignee
Kyocera Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corporation filed Critical Kyocera Corporation
Priority to JP2008533096A priority Critical patent/JP4926179B2/en
Publication of WO2008029641A1 publication Critical patent/WO2008029641A1/en

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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02Transmitters
    • H04B1/04Circuits
    • H04B1/0458Arrangements for matching and coupling between power amplifier and antenna or between amplifying stages
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02Details
    • H03H9/05Holders; Supports
    • H03H9/0538Constructional combinations of supports or holders with electromechanical or other electronic elements
    • H03H9/0566Constructional combinations of supports or holders with electromechanical or other electronic elements for duplexers
    • H03H9/0576Constructional combinations of supports or holders with electromechanical or other electronic elements for duplexers including surface acoustic wave [SAW] devices
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/70Multiple-port networks for connecting several sources or loads, working on different frequencies or frequency bands, to a common load or source
    • H03H9/72Networks using surface acoustic waves
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/70Multiple-port networks for connecting several sources or loads, working on different frequencies or frequency bands, to a common load or source
    • H03H9/72Networks using surface acoustic waves
    • H03H9/725Duplexers

Definitions

  • the present invention relates to a circuit board for mounting a duplexer, a duplexer, and a communication device using the same.
  • a duplexer installed in a portable communication terminal such as a cellular phone has a surface acoustic wave filter (SAW filter) in which comb-like electrodes are formed on a piezoelectric substrate,
  • SAW filter surface acoustic wave filter
  • FBAR Fin Bulk Acoustic Resonator
  • duplexers have the advantage that they can be made very compact compared to the duplexers using dielectric filters that have been used in the past, and are portable devices. For communication terminals that require the installation of multiple high-functionality applications for a certain size, this is an essential component.
  • the duplexer transmits the transmission signal input from the transmission circuit connected to the signal terminal 701 to the antenna terminal 703 via the signal line 707 and the signal line 709.
  • a transmission filter 704, and a reception filter 705 that transmits a reception signal input from the antenna terminal 703 to a reception circuit connected to the signal terminal 702 via the signal line 710 and the signal line 708.
  • This duplexer includes an antenna terminal (common terminal) 703 to which the transmission filter 704 and the reception filter 705 are connected in order to share the antenna for transmission and reception.
  • a matching circuit 706 is provided for adjustment.
  • This matching circuit 706 is usually composed of one or more inductors and other components. In order to meet the demand for miniaturization of circuits and components used in portable communication terminals, the matching circuit 706 is also a duplexer. Therefore, there is a need for a matching circuit-integrated duplexer that is housed in the element.
  • the inductance value required in the matching circuit 706 is a force that depends on the frequency band using the demultiplexer.
  • the frequency band near 2 GHz is about 1 to 6 ⁇
  • the frequency band near 900 MHz is several nH to About a dozen nH.
  • Examples of a method for placing such a matching circuit 706 in the duplexer include a circuit board on which a board on which a filter element is formed is mounted, and an inductor using a line inside the package.
  • the present invention has been made in view of the above problems, and a circuit board for a duplexer device capable of improving the isolation characteristics inside the circuit board and the isolation characteristics between the outside of the circuit board.
  • a circuit board for a duplexer device capable of improving the isolation characteristics inside the circuit board and the isolation characteristics between the outside of the circuit board.
  • the duplexer device circuit board includes a plurality of dielectric layers stacked on each other and surrounded by the plurality of dielectric layers. And a matching circuit line for adjusting the impedance between the first and second filter elements having different pass frequency bands and the plurality of dielectric layers, and the plurality of dielectric layers And a first signal transmission line for electrically connecting the first filter element and the first signal transmission terminal, and the second signal transmission line.
  • a second signal transmission line for electrically connecting the filter element and the second signal transmission terminal; and between the first signal transmission line and the matching circuit line; and Between the first signal transmission line and the second signal transmission line. Setting vignetting, and it was set to and a first grounding conductor surrounding the first signal electrical transmission for lines to.
  • a duplexer device circuit board is the duplexer device circuit board according to the first aspect, wherein the second signal transmission line includes the plurality of dielectrics.
  • the duplexer device circuit board is surrounded by a body layer and formed from an uppermost layer to a lowermost layer of the plurality of dielectric layers, and the duplexer device circuit board includes the second signal transmission line and the A second grounding line provided between the matching circuit line and between the second signal transmission line and the first signal transmission line and surrounding the second signal transmission line.
  • the conductor was further equipped.
  • both the transmission and reception signal transmission lines are electrically shielded between the lines inside the circuit board and are also electrically shielded from the outside of the circuit board. Between the isolation characteristics inside the circuit board and the outside of the circuit board Isolation characteristics can be further improved.
  • a circuit board for a duplexer device is the circuit board for a duplexer device according to the first aspect, wherein the first grounding conductor is the plurality of dielectrics.
  • the conductor pattern formed between the layers of one or more dielectric layers adjacent to each other among the layers was included.
  • grounding conductor surrounding the circumference of the signal transmission line is configured by the conductor pattern formed between the dielectric layers, the grounding conductor can be easily formed.
  • a circuit board for a duplexer device is the circuit board for a duplexer device according to the third aspect, wherein the first grounding conductor is the plurality of dielectrics.
  • a plurality of conductor pattern regions respectively formed between layers of a plurality of dielectric layers adjacent to each other, and a plurality of the dielectric layers sandwiched between the plurality of conductor pattern regions, And one or more conductors that are electrically connected to each other.
  • a duplexer device circuit board is the duplexer device circuit board according to the fourth aspect, wherein the one or more conductors are used for the first signal transmission.
  • a plurality of conductors provided so as to surround the track were included.
  • a circuit board for a duplexer device is the circuit board for a duplexer device according to the first aspect, wherein each of the first and second filter elements is a ladder type. It was made to be a finala element.
  • a circuit board for a duplexer device is the circuit board for a duplexer device according to the fourth aspect, and is a relative of the first and second filter elements.
  • a filter element having a very high pass frequency band has a resonator in a parallel arm, and the resonator is electrically connected to the first grounding conductor.
  • a circuit board for a duplexer device is the circuit board for a duplexer device according to the second aspect, wherein the first and second grounding conductors are the plurality.
  • Each of the dielectric layers includes a conductor pattern formed between one or more dielectric layers adjacent to each other.
  • the grounding conductor is formed by surrounding the periphery of the signal transmission line with the conductor pattern formed between the dielectric layers, so that the grounding conductor can be easily formed.
  • a circuit board for a duplexer device is the circuit board for a duplexer device according to the eighth aspect, wherein the first grounding conductor is the plurality of dielectrics.
  • a plurality of first conductor pattern regions respectively formed between a plurality of sets of dielectric layers adjacent to each other, and a dielectric layer sandwiched between the plurality of first conductor pattern regions.
  • One or more conductors that pass through and electrically connect the plurality of first conductor pattern regions to each other, and the second grounding conductor is mutually connected among the plurality of dielectric layers.
  • a plurality of second conductor pattern regions respectively formed between layers of a plurality of adjacent dielectric layers and a dielectric layer sandwiched between the plurality of second conductor pattern regions, and the plurality One or more conductors electrically connected to each other in the second conductor pattern area of the I included it.
  • a circuit board for a duplexer device is the circuit board for a duplexer device according to the ninth aspect, wherein the plurality of first conductor pattern regions are electrically connected to each other. And a plurality of conductors provided so as to surround the first signal transmission line.
  • the isolation characteristics inside the circuit board and the outside of the circuit board can be obtained.
  • the isolation characteristics in can be further improved.
  • a circuit board for a duplexer device is the circuit board for a duplexer device according to the ninth aspect, wherein the plurality of second conductor pattern regions are electrically connected to each other. And a plurality of conductors provided so as to surround the second signal transmission line.
  • a circuit board for a duplexer device is the circuit board for a duplexer device according to the ninth aspect, wherein each of the first and second filter elements is a ladder type It was made to be a finala element.
  • a circuit board for a duplexer device is the circuit board for a duplexer device according to the ninth aspect, and is a relative of the first and second filter elements.
  • a filter element having a very high pass frequency band has a resonator in a parallel arm, and the resonator is electrically connected to the first and second grounding conductors.
  • a circuit board for a duplexer device is the circuit board for a duplexer device according to the first aspect, wherein the first filter element is a filter element for transmission.
  • the second filter element force is a receiving filter element.
  • a duplexer according to the fifteenth aspect is mounted on the duplexer device circuit board according to any one of the first to fourteenth aspects, and the duplexer device circuit board.
  • the first and second filter elements are provided.
  • a duplexer is the duplexer according to the fifteenth aspect, wherein the first filter The filter element is a transmission filter element, the second filter element is a reception filter element, and the first and second filter element forces and a common terminal electrically connected to the antenna And one end of the matching circuit is electrically connected to the common terminal, and the other end of the matching circuit that is different from one end of the matching circuit is grounded. I did it.
  • a duplexer is the duplexer according to the sixteenth aspect, wherein the matching circuit power and a signal in a predetermined frequency band for reception are transmitted from the common terminal to the transmission circuit.
  • the impedance is almost infinite, and the impedance from the transmitting circuit to the receiving circuit is made almost infinite for a signal in a predetermined frequency band for transmission.
  • a duplexer according to an eighteenth aspect is the duplexer according to the seventeenth aspect, wherein the frequency band for reception is 869 to 894 MHz, and the frequency band for transmission is 824. -849 MHz.
  • a duplexer according to a nineteenth aspect is the duplexer according to the fifteenth aspect, wherein the first and second filter element forces S are each surrounded by an annular electrode portion. did.
  • the communication device is mounted with the duplexer according to any of the fifteenth to nineteenth aspects.
  • FIG. 1 is a block diagram showing a functional configuration of a communication apparatus according to a first embodiment of the present invention.
  • FIG. 2 is a diagram illustrating a circuit configuration of a duplexer according to the first embodiment of the present invention.
  • FIG. 3 is a schematic cross-sectional view illustrating the schematic configuration of the circuit board according to the first embodiment of the invention.
  • FIG. 4 is a diagram illustrating an example of the arrangement of conductor patterns and vias on the circuit board according to the first embodiment of the present invention.
  • FIG. 5 is a diagram showing an example of the arrangement of conductor patterns and vias on the circuit board according to the first embodiment of the present invention.
  • FIG. 6 is a top view illustrating the configuration of the surface acoustic wave element according to the first embodiment of the invention.
  • FIG. 7 shows an example of the arrangement of conductor patterns and vias on the circuit board according to the second embodiment of the present invention.
  • FIG. 8 is a diagram illustrating an example of the arrangement of conductor patterns and vias on a circuit board according to a second embodiment of the present invention.
  • FIG. 9 is a diagram showing an equivalent circuit of the duplexer according to the second embodiment of the present invention.
  • FIG. 10 is a diagram showing an arrangement of conductor patterns and vias on a circuit board according to a comparative example.
  • FIG. 11 is a diagram showing an arrangement of conductor patterns and vias of a circuit board according to a comparative example.
  • FIG. 12 is a graph showing the isolation characteristics of Examples 1 and 2 and a comparative example.
  • FIG. 13 is a graph showing the isolation characteristics of Examples 1 and 2 and a comparative example.
  • FIG. 14 is a graph showing the isolation characteristics of Examples 1 and 2 and a comparative example.
  • FIG. 15 is a diagram illustrating a circuit configuration of a conventional duplexer.
  • FIG. 1 is a block diagram showing a functional configuration of the communication apparatus 100 according to the first embodiment of the present invention.
  • the communication device 100 is configured by, for example, a mobile phone or a portable wireless terminal.
  • the communication device 100 mainly includes a control unit 200, a transceiver 300, an antenna 400, an operation unit 600, a microphone MP, and a speaker SP.
  • the control unit 200 is a part that performs overall control of various operations of the communication device 100.
  • the control unit 200 includes a CPU, a RAM, a ROM, and the like, and various controls and functions of the communication apparatus 100 are realized by the CPU reading and executing a program stored in the ROM or the like.
  • the antenna 400 is a part that transmits a radio wave based on a transmission signal from the transceiver 300, and receives a radio wave from the outside of the communication apparatus 100 and transfers a reception signal to the transceiver 300. is there.
  • the speaker SP is a part that emits a sound in response to the sound signal from the transceiver 300, and the microphone MP generates a sound signal in response to the reception of the sound and transmits the transceiver via the control unit 200. This is a part that outputs an audio signal to 300.
  • the operation unit 600 is a part that accepts various inputs from the user to the communication device 100, and includes, for example, various buttons.
  • the transceiver 300 converts an audio signal input from the microphone MP through the control unit 200 into a transmission signal and outputs the transmission signal to the antenna 400, while converting a reception signal from the antenna 400 into an audio signal and a speaker. This is the part that outputs to SP.
  • an analog audio signal input via the microphone MP force and the control unit 200 is A / D converted (converted from an analog signal to a digital signal) by a DSP (Digital Signal Pr OCeSSO r) 301. ), The signal is modulated by the modulator 302 and further frequency-converted by the mixer 303 using the oscillation signal of the local oscillator 320. The output of the mixer 303 passes through the transmission band-pass filter 304 and the power amplifier 305, passes through the duplexer 306, and is output as a transmission signal to the antenna 400.
  • DSP Digital Signal Pr OCeSSO r
  • a received signal from antenna 400 is input to mixer 309 through demultiplexer 306, low noise amplifier 307, and reception bandpass filter 308.
  • the mixer 309 converts the frequency of the received signal using the oscillation signal of the local oscillator 320, the converted signal passes through the low-pass filter 310, is demodulated by the demodulator 311, and is further D / A converted (digital) by the DSP 301. After the signal is converted into an analog signal, it is output as an analog audio signal to the speaker SP via the control unit 200.
  • the transmitter / receiver 300 of the communication device 100 is equipped with the duplexer 310 having excellent isolation characteristics, so that a call with less noise is possible.
  • the duplexer 306 will be described in detail.
  • FIG. 2 is a diagram illustrating a circuit configuration of the duplexer 306 according to the first embodiment of the present invention.
  • the duplexer 306 includes signal terminals 1 and 2, a common terminal 3, and a transmission filter element.
  • transmission filter (Hereinafter simply referred to as “transmission filter”) 4, a reception filter element (hereinafter simply referred to as “reception filter”) 5, a matching circuit 6, and signal lines 7 to 10 are provided.
  • the signal terminal 1 is a terminal (transmission side signal terminal) that is electrically connected (conducting connection) to the power amplifier 305 included in the transmission side circuit (transmission circuit).
  • ,Receiver This is a terminal (signal terminal on the receiving side) that is electrically connected to the low noise amplifier 307 included in this circuit (receiving circuit).
  • the common terminal 3 is a terminal that is electrically connected to the antenna 400.
  • the transmission filter 4 is different from the reception filter 5 in the frequency band (pass frequency band) of the signal that is selectively passed therethrough, and is provided between the common terminal 3 and the transmission-side signal terminal 1. Yes. Specifically, the transmission filter 4 is electrically connected to the transmission-side signal terminal 1 and the common terminal 3 by signal lines 7 and 9. The transmission filter 4 selectively passes a signal in a predetermined transmission frequency band (for example, 824 to 849 MHz) among signals input from the transmission-side signal terminal 1 via the signal line 7, Output to the common terminal 3 via the signal line 9.
  • a predetermined transmission frequency band for example, 824 to 849 MHz
  • the reception filter 5 is provided between the common terminal 3 and the reception-side signal terminal 2. Specifically, the reception filter 5 is electrically connected to the reception-side signal terminal 2 and the common terminal 3 by signal lines 8 and 10. The reception filter 5 selectively selects a signal in a predetermined reception frequency band (for example, 869 to 894 MHz) from signals input from the antenna 400 side, that is, the common terminal 3 through the signal line 10. Pass through and output to the signal terminal 2 on the receiving side via the signal line 8.
  • a predetermined reception frequency band for example, 869 to 894 MHz
  • the matching circuit 6 is a circuit in which one end is electrically connected to the common terminal 3 and the other end is grounded. A signal in a predetermined reception frequency band is transmitted from the common terminal 3 to the transmission circuit. This is a part that adjusts so that the impedance from the transmitting circuit to the receiving circuit becomes almost infinite while the impedance to the signal becomes almost infinite.
  • a matching circuit 6 when transmitting a transmission signal, a matching circuit 6 is provided in front of the common terminal 3 when viewed from the transmission filter 4, and when transmitting a reception signal, it is viewed from the common terminal 3. Thus, a matching circuit 6 is provided in front of the reception filter 5.
  • the transmission filter 4 and the reception filter 5 are flip-chip mounted, for example, on a circuit board formed by laminating a plurality of thin dielectric layers. Configured.
  • the matching line constituting the matching circuit 6 is a spiral conductor pattern (helical pattern) formed in a plurality of dielectric layers or a meandering conductor. It consists of a body pattern (meandering pattern) or both a spiral pattern and a serpentine pattern, and the end is grounded.
  • the transmission filter 4 and the reception filter 5 may be surface acoustic wave filters (SAW filters), so-called FBAR filters, or other types of filters.
  • SAW filters surface acoustic wave filters
  • FBAR filters acoustic wave filters
  • the transmission filter 4 and the reception filter 5 are manufactured on the same substrate (for example, a piezoelectric substrate for the SAW fintoror and various substrates for the FBAR filter), but each is manufactured on a separate substrate. However, it is preferable that they are produced on the same substrate for the following reasons.
  • the transmission filter 4 and the reception filter 5 that have various manufacturing variations are combined.
  • the optimum inductance value S of the conductor pattern (line pattern) of the line of the matching circuit 6 and a problem that varies depending on the combination of the transmission filter 4 and the reception filter 5 are likely to occur.
  • the filters 4 and 5 are fabricated on the same substrate, similar variations occur between filters fabricated at substantially the same location on the wafer.
  • the optimum inductance value is almost the same for the 5 combinations. Therefore, the transmission filter 4 and the reception filter 5 must be fabricated on the same substrate from the viewpoint that there is no need to worry about characteristic variations due to the combination of the transmission filter 4 and the reception filter 5. Is preferred.
  • FIG. 3 shows an outline of a substrate 800 on which a circuit for mounting the transmission filter 4 and the reception filter 5 in the duplexer 306 is disposed (hereinafter also referred to as “demultiplexer device circuit substrate”) 800. It is a cross-sectional schematic diagram which illustrates a structure. Note that in Fig. 3 and Fig. 3 and subsequent figures, three XYZ orthogonal axes are attached to clarify the orientation relationship.
  • a circuit board for duplexer devices (hereinafter simply referred to as "circuit board”) 800 has a predetermined shape.
  • dielectric thin film (dielectric layer) Lb, Ld, Lf and the surface of the dielectric layer Lb, Ld, Lf and between the layers A layer (conductor wiring pattern layer) provided with a wiring pattern of four layers of conductors provided La, Lc, Le, and Lg Yes. That is, three dielectric layers Lb, Ld, and Lf are stacked on top of each other, and two conductor wiring pattern layers Lc and Le sandwiched between the plurality of dielectric layers Lb, Ld, and Lf are formed. ing.
  • the conductor wiring pattern layer La is the upper surface (the surface in the + Z direction) of the dielectric layer Lb, that is, the circuit board.
  • the conductor wiring pattern layer Lc is provided on the lower surface (one Z-direction surface) of the dielectric layer Lb and on the upper surface (+ Z-direction surface) of the dielectric layer Ld. That is, the conductor wiring pattern layer Lc is
  • the dielectric layer Lb is provided between the dielectric layer Ld and the dielectric layer Ld.
  • the conductor wiring pattern layer Le is provided on the lower surface (one Z direction surface) of the dielectric layer Ld and on the upper surface (+ Z direction surface) of the dielectric layer Lf. In other words, the conductor wiring pattern layer Le is
  • the dielectric layer Ld and the dielectric layer Lf are provided between the layers.
  • the conductor wiring pattern layer Lg is a lower surface (one Z-direction surface) of the dielectric layer Lf, that is, a circuit board.
  • the circuit board 800 includes, in order from the top in FIG. 3, the conductor wiring pattern layer La, the dielectric layer Lb, the conductor wiring pattern layer Lc, the dielectric layer Ld, the conductor wiring pattern layer Le, The dielectric layer Lf and the conductor wiring pattern layer Lg are laminated.
  • Examples of the dielectric material constituting the dielectric layers Lb, Ld, and Lf include ceramics mainly composed of alumina, glass ceramics that can be sintered at low temperature, or glass epoxy mainly composed of organic materials. Resin or the like is used.
  • a slurry in which a metal oxide such as ceramics and an organic binder are homogeneously kneaded with an organic solvent or the like is first molded into a sheet shape. This produces a plurality of green sheets.
  • a desired conductor pattern (conductor pattern) and a conductor portion (hereinafter simply referred to as “via”) filled with a conductor in a via hole penetrating from the front surface to the back surface are formed on a plurality of green sheets.
  • the circuit board 800 is manufactured by laminating a plurality of green sheets and press-bonding them together and firing them.
  • the spiral pattern and the meandering pattern constituting the matching circuit 6 are a plurality of conductor pattern forces produced by a conductor on the surface of each dielectric layer (here, the dielectric layers Ld and Lf). It is formed by being electrically connected by a via provided through the body layer.
  • silver an alloy obtained by adding palladium to silver, tungsten, copper, gold, or the like can be used as the conductor constituting the conductor pattern.
  • the conductor pattern is formed by screen printing using a metal conductor or a combination of a film forming method such as vapor deposition or sputtering and etching.
  • circuit board 800 Hereinafter, a specific example of the circuit board 800 will be described.
  • FIGS. 4 and 5 are diagrams illustrating the arrangement of conductor patterns and vias in each layer La to Lg constituting the circuit board 800.
  • FIG. 4 and 5 the position of the outer edge of the circuit board 800 is indicated by a broken line in order to clarify the positional relationship with the outer edge of the circuit board 800, that is, the outer edges of the dielectric layers Lb, Ld, and Lf. RU
  • the multilayer substrate constituting the circuit board 800 has a structure in which three dielectric layers are laminated (three-layer laminated structure), and a conductor pattern (Fig. 4 (a)) formed on the surface of the multilayer substrate.
  • Conductor pattern formed on the back side of the multilayer substrate (Fig. 5 (c)), Conductor pattern formed between the dielectric layer Lb and dielectric layer Ld (Fig. 4 (c)), dielectric layer Ld and dielectric layer
  • a conductor pattern (Fig. 5 (a)) formed between the layer Lf and a plurality of layers penetrating through the dielectric layer Lb for electrically connecting the conductor patterns provided across the dielectric layer Lb.
  • Vias (FIG. 4 (b)), a plurality of vias (FIG.
  • the transmission and reception filters 4 and 5 are not shown, but the upper surface (the surface in the + Z direction) of the circuit board 800 is the transmission and reception filters 4 and 5.
  • the right side of Fig. 4 (a) is the filter mounting surface of the transmission filter 4
  • the left side of Fig. 4 (a) is the filter of the reception filter 5. It becomes a mounting surface!
  • the matching circuit 6 has a transmission frequency band different from each other. Lines for adjusting the impedance between the trusted and receiving filters 4 and 5 (hereinafter also referred to as “matching circuit lines”).
  • Each of the signal lines 7 to 10 is a line for transmitting a signal (hereinafter referred to as “line for matching circuit”). Further, the signal terminals 1 and 2 and the common terminal 3 are terminals for transmitting signals (hereinafter also referred to as “signal transmission terminals”).
  • connection state of the conductor pattern and the via in the circuit board 800 and the transmission and reception filters 4 and 5 are mounted on the circuit board 800 to transmit and A flow of transmission / reception signals when the reception circuit is connected will be described.
  • the signal line 7 composed of the conductor patterns 14, 27, 41 and the vias 19, 32, 46 is electrically connected to the transmission-side signal terminal 1, and the conductor pattern 14 is used for transmission.
  • Filter 4 functions as a terminal to be electrically connected. More specifically, the signal line 7 is surrounded by a plurality of dielectric layers Lb, Ld, Lf except in the vertical direction (the direction along the Y axis), and the plurality of dielectric layers Lb, Ld, Lf A plurality of dielectric layers Lb, Ld, and Lf are formed from the uppermost layer to the lowermost layer so as to penetrate the plurality of dielectric layers Lb, Ld, and Lf in the multilayer substrate thus configured.
  • the transmission signal input from the transmission side signal terminal 1 is input to the transmission filter 4 via the signal line 7.
  • the signal line 9 constituted by the conductor patterns 12, 25, 40 and the vias 17, 31, 45 is electrically connected to the common terminal 3, and the conductor pattern 12 is used for transmission.
  • Filter 4 functions as a terminal to be electrically connected. More specifically, the signal line 9 is surrounded by a plurality of dielectric layers Lb, Ld, Lf except in the vertical direction (the direction along the Y axis), and the plurality of dielectric layers Lb, Ld, Lf The uppermost layer force of the plurality of dielectric layers Lb, Ld, and Lf and the lowermost layer are formed so as to penetrate the plurality of dielectric layers Lb, Ld, and Lf inside the multilayer substrate.
  • the transmission signal output from the transmission filter 4 is output to the antenna 400 (FIG. 1) via the signal line 9 and the common terminal 3.
  • the signal line 10 is electrically connected, and the conductor pattern 15 functions as a terminal to which the reception filter 5 is electrically connected. More specifically, the signal line 10 is surrounded by a plurality of dielectric layers Lb, Ld, Lf except for the upper and lower directions (directions along the Y axis), and the plurality of dielectric layers Lb, Ld, Lf Is formed from the uppermost layer to the lowermost layer of the plurality of dielectric layers Lb, Ld, Lf so as to penetrate through the plurality of dielectric layers Lb, Ld, Lf.
  • the reception signal input from the antenna 400 is input to the reception filter 5 through the common terminal 3 and the signal line 10.
  • the signal line 8 constituted by the conductor patterns 16, 29, 43 and the vias 21, 36, 48 is electrically connected to the reception side signal terminal 2, and the conductor pattern 16 is
  • the reception filter 5 functions as a terminal to be electrically connected. More specifically, the signal line 8 is surrounded by a plurality of dielectric layers Lb, Ld, Lf except in the vertical direction (the direction along the Y axis), and the plurality of dielectric layers Lb, Ld, Lf Is formed from the top layer to the bottom layer of the plurality of dielectric layers Lb, Ld, and Lf so as to penetrate the plurality of dielectric layers Lb, Ld, and Lf.
  • the signal output from the reception filter 5 is output from the reception-side signal terminal 2 via the signal line 8.
  • the matching circuit 6 electrically connected to the common terminal 3 is a line including conductor patterns 28 and 40 and vias 34 that are electrically connected to the common terminal 3 by vias 45 (matching lines). It is constituted by.
  • the conductor patterns 28 and 40 constituting the matching circuit 6 are constituted by a spiral pattern. More specifically, the matching circuit 6 is surrounded by a plurality of dielectric layers Lb, Ld, and Lf, and the dielectric layer Ld is formed inside the multilayer substrate constituted by the plurality of dielectric layers Lb, Ld, and Lf. It is formed through.
  • One end of the conductor pattern 28 (the end opposite to the side connected by the spiral pattern 40 and the via 34) is connected to the ground conductor pattern (ground pattern) 44 by the via 35. Electrically connected.
  • grounding conductor means “a conductor to which a constant voltage or a reference voltage is applied”.
  • the annular electrode pattern 11 included in the conductor spring pattern layer La constituting the uppermost part of the circuit board 800 is composed of a conductor pattern for grounding (grounding) by via groups 22 to 24 each including a plurality of vias. Pattern) 30 is electrically connected. Grounding pattern 30 is formed between a pair of dielectric layers Lb and Ld and is surrounded by two dielectric layers Lb and Ld, and is electrically connected to the grounding pattern 44 by the via groups 37 to 39. Connected. Furthermore, the grounding pattern 44 is formed between a pair of dielectric layers Ld and Lf and is surrounded by two dielectric layers Ld and Lf.
  • the circuit board 800 is formed by via groups 49 to 51. It is electrically connected to a grounding terminal (grounding terminal) 52 provided on the back surface of the.
  • the line constituted by the conductor patterns 13, 26, 42 and the vias 18, 33, 47 is a line for electrically connecting the transmission filter 4 to the grounding terminal 52.
  • the transmission-side signal terminal 1 is arranged on the lower right side in the figure, and the reception-side signal terminal 2 is Arranged at the lower left, the common terminal 3 is arranged at the approximate center in the upper part of the figure.
  • the three terminals 1 to 3 are arranged as far as possible from each other.
  • Such a line arrangement includes a signal line 7 (configured by conductor patterns 14, 27, 41 and vias 19, 32, 46) and a matching circuit 6 (configured by conductor patterns 28, 40 and via 34). Between signal line 8 (consisting of conductor patterns 16, 29, 43 and vias 21, 36, 48) and matching circuit 6, signal line 7 and signal line 8 This is to ensure isolation between and. In other words, in a limited space, the distance between the three lines of the matching circuit 6, the signal line 7, and the signal line 8 is devised so that the respective distances are set appropriately.
  • the signal line 7 and the signal line 8 are surrounded by the grounding patterns 30, 44 from the side.
  • the grounding pattern 30 is composed of the conductor pattern 27 constituting the signal line 7 and the conductor constituting the signal line 8. It is provided so as to pass through both the space area between the pattern 29 and the space area between the conductor pattern 27 and the conductor pattern 28 constituting the matching circuit 6, and the conductor pattern 27 from the side. A space area between the conductor pattern 29 and the conductor pattern 27, and a space area between the conductor pattern 29 and the conductor pattern 28, as well as the surrounding annular conductor pattern area (ground pattern area) 30a. Provided to pass through both spatial areas And an annular grounding conductor pattern region (grounding pattern region) 30b surrounding the conductor pattern 29 from the side.
  • the conductor pattern region 30 a is preferably uniform over the entire circumference of the conductor pattern 27. In this case, stray capacitance can be prevented from occurring between the conductor pattern region 30a and the conductor pattern 27.
  • the same configuration is preferable for the relationship between the conductor pattern region 30b and the conductor pattern 29.
  • the grounding pattern 44 includes a conductor pattern 41 constituting the signal line 7 and a conductor pattern 43 constituting the signal line 8.
  • a conductor pattern 41 constituting the signal line 7
  • a conductor pattern 43 constituting the signal line 8.
  • Conductor pattern region (ground pattern region) 44a and a spatial region between the conductor pattern 43 and the conductor pattern 41 and a spatial region between the conductor pattern 43 and the conductor pattern 40.
  • An annular grounding conductor pattern region (grounding pattern region) 44b is provided so as to pass through the space region and surrounds the conductor pattern 43 from the side.
  • FIG. 6 is a top view illustrating the configuration of the surface acoustic wave element 900 mounted on the filter mounting surface shown in FIG. 4 (a).
  • the surface acoustic wave element 900 is formed by forming the transmission filter 4 and the reception filter 5 on the same substrate.
  • the inertial surface acoustic wave element 900 shown in FIG. 6 includes a so-called ladder-type filter element.
  • the surface acoustic wave device 900 mainly includes a transmission filter (Tx filter) 4 and a reception filter (Rx filter) 5 on one main surface of the piezoelectric substrate 902! /
  • the elastic surface wave device 900 is provided with an annular electrode portion (annular conductor) 930 that individually surrounds the Tx filter 4 and the Rx filter 5.
  • annular electrode portion 930 annular conductor 930 that individually surrounds the Tx filter 4 and the Rx filter 5.
  • the Tx finoleta 4 has a plurality of excitation electrodes composed of six series-arm resonators (series resonators) 914a to 914f and two parallel-arm resonators (parallel resonators) 915a and 915b. Setting Each excitation electrode is electrically connected by a connection electrode 917.
  • the TX filter 4 includes an input pad portion 911, an output pad portion 912 that is electrically connected to the antenna 400, and a ground electrode portion 913.
  • the parallel resonators 915a and 915b are electrically connected to the ground electrode portion 913, respectively.
  • the Rx filter 5 is provided with a plurality of excitation electrodes composed of four direct IJ resonators 924a to 924d and four parallel IJ resonators 925a to 925d, and between the excitation electrodes. Are electrically connected by connecting electrode 927.
  • the Rx finoleta 5 is provided with an input pad portion 921, an output pad portion 922, and a grounding electrode 923.
  • the parallel resonators 925a to 925d are electrically connected to the grounding electrode 923, respectively.
  • the ground electrode 923 is electrically connected to the annular electrode portion 930.
  • the surface acoustic wave element 900 having such a configuration is mounted on the circuit board 800 by face-down mounting, whereby the duplexer 306 is formed.
  • the annular electrode portion 930 is associated with the annular electrode pattern 11
  • the conductor pattern 14 is associated with the input pad portion 911
  • the conductor pattern 12 is associated with the output pad portion 912
  • the ground electrode portion 913 is associated with.
  • the conductor pattern 13 is electrically connected to the input pad portion 921 via the solder pattern 15 and the conductor pattern 15 is electrically connected to the output pad portion 922 via the solder bump.
  • the parallel resonators 925a to 925d are the grounding electrode 923, the annular electrode portion 930, the solder bump, the annular electrode pattern 11, the via group 22 to 24, the grounding pattern 30, the via group 37 to 39, and the grounding pattern. Are electrically connected (conductively connected) to the grounding terminal 52 through the via 44 and the via groups 49 to 51 sequentially.
  • the matching circuit 6 is disposed inside the multilayer board surrounded by the plurality of dielectric layers Lb, Ld, and Lf.
  • Each of the signal line 7 and the signal line 8 is disposed inside the multilayer substrate surrounded by the plurality of dielectric layers Lb, Ld, and Lf, and between the other signal lines 7 and 8 and the matching circuit 6.
  • a grounding conductor here, grounding pattern areas 30a, 30b, 44a, 44b is provided that passes through and surrounds the periphery.
  • the outside of the plate 800 is also electrically shielded. Therefore, electrical interference inside the circuit board 800 and electrical interference between the outside of the circuit board 800 can be reduced. That is, the isolation characteristics inside the circuit board 800 and the isolation characteristics between the outside of the circuit board 800 can be improved.
  • grounding conductor surrounding the signal lines 7 and 8 is formed by the conductor pattern formed between the dielectric layers, the grounding conductor can be easily formed. Touch with force S.
  • the duplexer 306 on which the circuit board 800 is mounted has excellent isolation characteristics, the communication device 100 on which the duplexer 306 is mounted can perform good communication.
  • the signal lines 7 and 8 are surrounded by the grounding patterns 30 and 44.
  • further isolation is provided by providing a via for electrically connecting the grounding patterns 30 and 44 at positions surrounding the signal lines 7 and 8. The characteristics are improved.
  • the communication device 100A according to the second embodiment has the same configuration as the communication device 100 according to the first embodiment except that vias are additionally arranged as appropriate.
  • the same parts as those of the communication device 100 according to the first embodiment are denoted by the same reference numerals and the description thereof is omitted, while the communication according to the first embodiment is performed.
  • the configuration of the circuit board 800A different from the device 100 will be mainly described.
  • FIGS. 7 and 8 are diagrams illustrating the arrangement of conductor patterns and vias in the respective layers La to Lg constituting the circuit board 800A according to the second embodiment.
  • a plurality of vias for grounding are provided around the signal line 7 constituted by the conductor patterns 14, 27, 41 and the vias 19, 32, 46.
  • via groups 54a and 54b including a plurality of grounding vias are provided around the signal line 8 constituted by the conductor patterns 16, 29, 43 and the vias 21, 36, 48.
  • two annular loops are provided so as to pass between the signal line 7, the signal line 8, and the matching circuit 6, and surround the signal line 7.
  • Grounding pattern Grounding via groups 53a and 53b for electrically connecting the regions 30a and 44a are provided.
  • two annular grounding pattern regions 30b and 44b that are provided so as to pass between the signal line 8, the signal line 7, and the matching circuit 6 and that surround the signal line 8 are electrically connected.
  • Grounding via groups 54a and 54b are provided.
  • a grounding via group 53a, 53b is provided.
  • the via 36 constituting the signal line 8, the via 32 constituting the signal line 7 and the via 34 constituting the matching circuit 6 are constituted by a plurality of vias arranged in a ring shape.
  • Grounding via groups 54a and 54b are provided.
  • the circuit board 800A is newly provided with the ground pattern areas 30a, 30b, 44a, and 44b so as to surround the signal lines 7 and 8 with the ground conductors.
  • the ground vias 53a, 53b, 54a and 54b surrounding the signal lines 7 and 8 are newly provided by utilizing the fact that the area where the ground via can be provided is increased.
  • via groups 55b which electrically connect the annular electrode pattern 11 (FIG. 7 (a)) and the conductor pattern 30 (FIG. 7 (c)), 56b (Fig. 7 (b)) Newly installed.
  • FIG. 9 is a diagram showing an equivalent circuit of the duplexer 306A according to the second embodiment.
  • the ground via group 53a, 53b, 54a, 54b is newly provided, and as shown in FIG. 9, the wiring path (that is, the parallel resonators 925a to 925d of the reception filter 5 are grounded)
  • the wiring path that is, the parallel resonators 925a to 925d of the reception filter 5 are grounded
  • the number of wiring paths that are electrically connected in parallel increases. For this reason, the inductance of the wiring path (circuit) from the grounding electrode 923 to the grounding terminal 52 decreases.
  • the periphery of the signal lines 7 and 8 includes a plurality of ground pattern regions 30a, 30b, 44a, which are formed between a plurality of sets of dielectric layers. 44 b and a plurality of ground pattern regions 30a, 30b, 44a, 44b are passed through the dielectric layer Ld sandwiched between them, and the plurality of ground pattern regions 30a, 30b, 44a, 44b are electrically connected. It is surrounded by conductors (here, via groups 53a, 53b, 54a, 54b).
  • the circuit board 800A is electrically shielded between the lines inside the circuit board 800A (between the matching circuit 6, the signal line 7 and the signal line 8). And the signal lines 7 and 8 surrounded by the grounding conductor (here, grounding pattern areas 30a, 30b, 44a and 44b, and via groups 53a, 53b, 54a and 54b) are also electrically shielded.
  • the grounding conductor here, grounding pattern areas 30a, 30b, 44a and 44b, and via groups 53a, 53b, 54a and 54b
  • the force S can further improve the isolation characteristics inside the circuit board and the isolation characteristics with the outside of the circuit board.
  • the dielectric is provided between the plurality of ground pattern areas 30b and 44b around the signal line 8.
  • the area (position) where a via that is a conductor penetrating the layer Ld can be arranged is increased.
  • a line that electrically connects between the parallel resonator of the filter having a relatively high pass frequency band generally, the reception filter
  • the ground terminal In other words, if the inductance value generated in the conductor pattern of the circuit board and vias penetrating the dielectric layer is reduced, the filter having a relatively high pass frequency band in the duplexer is reduced. It is known that there is a property of increasing the out-of-band attenuation on the frequency side.
  • vias that are conductors that electrically connect the ground patterns 30 and 44 electrically connected to the parallel resonators through the dielectric layer.
  • Group 53a, 53b, 54a, 54b) and by forming a grounding line for via group 53a, 53b, 54a, 54b force parallel lj, parallel resonators 925a-925d and The inductance value with respect to the grounding terminal 52 decreases. For this reason, it is possible to increase the out-of-band attenuation amount of the reception filter 5. That is, it can be said that the fact that the via groups 53a, 53b, 54a, 54b can be newly provided contributes to the reduction of the inductance value.
  • the isolation filter is further improved and the reception filter 5 is provided.
  • the communication characteristics of communication apparatus 100A can be further improved by increasing the out-of-band attenuation.
  • the signal lines 7 and 8 are both surrounded by the ground pattern areas 30a, 30b, 44a, and 44b. Peripheral force of at least one signal line of lines 7 and 8
  • One or more grounding conductors for example, conductor pattern regions 30a, 30b) provided between one or more dielectric layers adjacent to each other , 44a, 44b, etc.
  • the periphery of both of the signal lines 7 and 8 is a plurality of multiple dielectric layers formed between the layers of the adjacent dielectric layers. It is preferable to be surrounded by a grounding conductor (for example, conductor pattern regions 30a, 30b, 44a, 44b).
  • the ground pattern areas 30a and 44a are electrically connected by the ground via groups 53a and 53b, and the ground pattern areas 30b and 44b are grounded vias. Forces electrically connected by the groups 54a and 54b Not limited to this, so that at least one of the ground pattern areas 30a and 44a and the ground pattern areas 30b and 44b is electrically connected by the via group. Even so, the same effect as in the second embodiment can be obtained.
  • the signal lines 7 and 8 are surrounded by the annular ground pattern areas 30a, 30b, 44a, and 44b.
  • the annular ground pattern areas 30a, 30b, 44a, and 44b As long as electrical connection for grounding can be secured, slits etc. are provided as appropriate. It does not matter.
  • the shape of the conductor pattern regions 30a, 30b, 44a, 44b surrounding the signal lines 7, 8 is not necessarily circular, and surrounds the signal line 7 and the signal line 8 and the other signal line 7, As long as the conductor pattern for grounding is provided so as to pass between 8 and the matching circuit 6, those of various shapes can be adopted.
  • the conductor surrounding the periphery of the signal lines 7 and 8 is constituted by the grounding conductor pattern and via formed between the dielectric layers.
  • the present invention is not limited to this. Any grounding conductor that penetrates the dielectric multilayer film may be used.
  • the matching circuit 6 is not limited to the force S formed by the two layers of the spiral conductor patterns 28, 40.
  • a desired size or inductance value can be obtained. May be composed of one or three or more layers of conductor patterns, etc.
  • the reception filter 5 has a relatively high pass frequency band.
  • the transmission filter 4 may have a relatively high pass frequency band in accordance with various different standards.
  • the inductance of the line for electrically connecting the parallel resonator of the transmission filter 4 to the grounding terminal 52 is further reduced. Increase the out-of-band attenuation of the transmission filter 4 with the force S.
  • a filter having a resonator in a parallel arm such as providing a parallel resonator in a so-called DMS filter, that is, a parallel arm resonator (parallel
  • the out-of-band attenuation of the filter can be increased by reducing the inductance of the line that electrically connects the parallel resonator to the ground terminal.
  • Example 1 there are two types having the same configuration as the duplexer 306 using the circuit board 800 according to the first embodiment and the duplexer 306A using the circuit board 800A according to the second embodiment.
  • a duplexer was prepared.
  • a device corresponding to the duplexer 306 was designated as Example 1
  • a device corresponding to the duplexer 306A was designated as Example 2.
  • the matching circuit 6 is disposed inside the multilayer film surrounded by the plurality of dielectric layers, and both the signal lines 7 and 8 are Arranged inside the multilayer film surrounded by a plurality of dielectric layers and surrounded by ground pattern areas 30a, 30b, 44a, 44b passing between the other signal lines 7, 8 and the matching circuit 6. A thing was used.
  • the matching circuit 6 is disposed inside the multilayer film surrounded by the plurality of dielectric layers, and both of the signal lines 7 and 8 are Ground pattern areas 30a, 30b, 44a, 44b, which are arranged inside a multilayer film surrounded by a plurality of dielectric layers and pass between the other signal lines 7, 8 and the matching circuit 6, and the ground What was surrounded by ground via groups 53a, 53b, 54a, 54b that electrically connect the pattern areas 30a, 30b, 44a, 44b for use was used.
  • a resonator including an IDT (Inter Digital Transducer) electrode and a reflector electrode on a piezoelectric substrate, a wiring electrode connecting the resonators, and a circuit substrate
  • IDT Inter Digital Transducer
  • a circuit substrate A surface acoustic wave filter (surface acoustic wave element) 900 (Fig. 6) in which a connection terminal for connection to the substrate was formed was used.
  • a piezoelectric thin film made of lithium tantalate (LiTaO) was used, and a Ti thin film having a thickness of 6 nm was formed on the main surface of the piezoelectric substrate.
  • An A1-Cu thin film with a thickness of 125 nm was formed on this, and this Ti thin film and A1-Cu thin film were alternately laminated in three layers to form a total of six Ti / Al-Cu laminated films.
  • a photoresist having a thickness of about 0.5 m was applied by a resist coating apparatus. Then, using a reduction projection exposure apparatus (stepper) or the like, the photoresist pattern to be the resonator, signal line, pad electrode, etc. shown in FIG. 6 was formed. In the filter for reception The photoresist pattern is also formed in this process for the parallel resonator closest to the antenna. Furthermore, unnecessary portions of the photoresist were dissolved with an alkali developer by a developing device.
  • the electrode pattern shown in Fig. 6 was formed by a RIE (Reactive Ion Etching) apparatus. And the protective film was produced on the predetermined area
  • an SiO film having a thickness of about 15 nm was formed on the electrode pattern and the main surface of the piezoelectric substrate by a CVD (Chemical Vapor D-marked osition) apparatus.
  • the photoresist is patterned by photolithography, and the flip chip electrode portion (input / output electrode, ground electrode and pad electrode) is covered with an RIE apparatus or the like! /, And the S film is etched. went. Then, using a sputtering apparatus, a laminated electrode was formed by laminating a Cr layer, a Ni layer, and an Au layer on the portion from which the SiO film was removed. At this time, the thickness of the laminated electrode was about 1 ⁇ m, and the thicknesses of the Cr layer, the Ni layer, and the Au layer were set to 0.01 m, 1 m, and 0.2 m, respectively.
  • the surface acoustic wave element 900 was divided into chips.
  • circuit boards 800 and 800A first, green sheets were produced by molding a slurry in which a metal oxide such as ceramics and an organic binder were homogeneously kneaded with an organic solvent or the like into a sheet. Then, after forming desired conductor patterns and vias on a plurality of green sheets, a plurality of green sheets are laminated and pressure-bonded to produce a multilayer film, and fired to produce a plurality of circuit boards 800. , 800A gathered circuit board (integrated circuit board).
  • the material used for the conductor pattern, etc. provided on the collective circuit board is composed mainly of silver and glass, and has a total of three dielectric layers, conductor patterns formed on the front and back surfaces, and between the layers. An assembled circuit board was prepared.
  • the conductor patterns 11 to 16 of the conductor wiring pattern layer La (Figs. 4 (a) and 7 (a)); A conductive material (conductive material) was printed on top. Solder was used as the conductive material.
  • the surface acoustic wave element 900 was temporarily bonded to the collective circuit board by a flip chip mounting apparatus with the electrode forming surface of the surface acoustic wave element 900 as the bottom surface. This temporary bonding was performed in an N gas atmosphere. Further, by performing reflow in an N gas atmosphere and melting the solder, the surface acoustic wave element 900 and the collective circuit board were bonded and hermetically sealed.
  • the circuit board on which a plurality of surface acoustic wave elements 900 can be mounted is used, the circuit board is divided into individual pieces of the circuit boards 800 and 800A by performing dicing along the dicing lines of the collective circuit board.
  • a plurality of duplexers 306 and 306A were obtained in one step.
  • the dimensions (finished dimensions) of the completed duplexers 306 and 306A were set to a mounting area of 2.5 mm X 2. Omm X height of 0.9 mm.
  • FIG. 10 and FIG. 11 are diagrams showing the arrangement of conductor patterns and vias in each layer La to Lg constituting the circuit board included in the duplexer according to the comparative example.
  • the signal lines 7 and 8 are respectively surrounded from the conductor pattern of the conductor wiring pattern layer Lc according to the first embodiment.
  • the grounding pattern areas 30a and 30b are removed, and the grounding conductor pattern 30 is separated into three grounding conductor patterns 55 to 57.
  • the signal lines 7 and 8 are respectively surrounded by the conductor pattern of the conductor wiring pattern layer Le according to the first embodiment.
  • the ring-shaped grounding pattern areas 44a and 44b were removed, and the grounding conductor pattern 44 is separated into three grounding conductor patterns 58-60.
  • the circuit board according to the modified example has the same configuration as the circuit board 800 according to the first embodiment. Therefore, in FIGS. Parts similar to those of the circuit board 800 according to FIG.
  • duplexer according to the modification is similar to the duplexer according to the first and second embodiments.
  • the duplexer according to the modified example manufactured in this way is transmitted from the measured value (S parameter) using the network analyzer.
  • the transmission coefficient (ie isolation) from the side signal terminal 1 to the reception side signal terminal 2 was obtained.
  • FIGS. 12 to 14 Transmission coefficients from the transmission-side signal terminal 1 to the reception-side signal terminal 2 for the two types of duplexers according to Examples 1 and 2 and the duplexer according to the comparative example obtained as described above.
  • isolation is shown in FIGS. 12 to 14 and Table 1 below. 12 to 14, the horizontal axis represents frequency (unit: MHz), and the vertical axis represents isolation (unit: dB).
  • the isolation of Example 1 is indicated by a solid line R1
  • the isolation of Example 2 is indicated by a thick line R2
  • the isolation of the comparative example is indicated by a broken line R3.
  • Fig. 12 shows the isolation in a wide frequency band (760 to 960MHz).
  • FIG. 13 shows the isolation focused on the transmission frequency band (824 to 849 MHz) required in the US-CDMA system, that is, the isolation focused on the area surrounded by the thick broken line A1 in Fig. 12.
  • Fig. 14 shows the isolation focused on the reception frequency band (869 to 894 MHz) required in the US-CDMA system, that is, the isolation focused on the area surrounded by the thick broken line A2 in Fig. 12.
  • Table 1 below, the maximum value of isolation in the transmission frequency band (824 to 849 MHz) and the reception frequency band (869 to 894 MHz) for Examples 1, 2 and Comparative Example are shown. The maximum isolation values are shown respectively.
  • the demultiplexing of the second embodiment in which grounding via groups 53a, 53b, 54a, and 54b surrounding both the signal lines 7 and 8 are further provided.
  • the maximum isolation value in the receiving frequency band (869 to 894 MHz) is a force that does not change as much as -42 dB, and the combined force is the isolation in the transmitting frequency band (824 to 849 MHz). The maximum value of was reduced to 57dB.
  • both the transmission frequency band (824 to 849 MHz) and the reception frequency band (869 to 894 MHz) are! / The maximum value tended to decrease slightly.
  • both signal lines 7 and 8 are arranged inside a plurality of dielectric layers, and the periphery of both signal lines 7 and 8 is connected to the other signal lines 7 and 8 and matching circuit 6. It was confirmed that a duplexer with improved isolation characteristics can be obtained by surrounding it with a grounding conductor that passes between them. Further, the isolation characteristics tend to be further improved by surrounding the signal lines 7 and 8 with grounding via groups rather than surrounding them with grounding patterns provided between the dielectric layers. I confirmed it.

Abstract

It is an object to improve an isolation characteristic in the inside of a circuit board and an isolation characteristic between the circuit board and its outside. In order to achieve the object, the circuit board is comprised of a plurality of mutually stacked dielectric layers (Lb, Ld, Lf), a matching circuit line (6) surrounded with a plurality of the dielectric layers for adjusting an impedance between first and second filter elements provided with mutually different passing frequency bands, a first signal transmitting line (7) formed on a plurality of the dielectric layers ranging from the top to the bottom for electrically connecting the first filter elements with a first signal transmitting terminal, a second signal transmitting line (8) for electrically connecting the second filter elements with a second signal transmitting terminal, and first grounding conductors (30, 44) arranged between the first signal transmitting line and the matching circuit line, also arranged between the first and second signal transmitting lines and further arranged to surround the first signal transmitting line.

Description

明 細 書  Specification
分波器デバイス用回路基板、分波器、及び通信装置  Circuit board for duplexer device, duplexer, and communication apparatus
技術分野  Technical field
[0001] 本発明は、分波器を実装するための回路基板、分波器及びこれを用いた通信装置 に関する。  The present invention relates to a circuit board for mounting a duplexer, a duplexer, and a communication device using the same.
背景技術  Background art
[0002] 近年、携帯電話機等の携帯式の通信端末に搭載されて!/、る分波器には、圧電基 板に櫛歯状電極が形成された弾性表面波フィルタ(SAWフィルタ)や、圧電薄膜に 対して上下から挟むように電極が設けられた薄膜共振器を用いた所謂 FBAR (Film Bulk Acoustic Resonator)フィルタが採用されている。  [0002] In recent years, a duplexer installed in a portable communication terminal such as a cellular phone has a surface acoustic wave filter (SAW filter) in which comb-like electrodes are formed on a piezoelectric substrate, A so-called FBAR (Film Bulk Acoustic Resonator) filter using a thin film resonator in which electrodes are provided so as to be sandwiched from above and below the piezoelectric thin film is employed.
[0003] これらの分波器は、従来使用されていた誘電体フィルタを用いた分波器と比較して 、非常に小型化を図ることが可能であるという利点を有し、携帯可能な機器のサイズ に対して複数の高機能を有するアプリケーションの搭載が求められる通信端末にお いては、無くてはならな!/、部品となってレ、る。  [0003] These duplexers have the advantage that they can be made very compact compared to the duplexers using dielectric filters that have been used in the past, and are portable devices. For communication terminals that require the installation of multiple high-functionality applications for a certain size, this is an essential component.
[0004] 図 15に示すように、分波器は、信号端子 701に接続される送信回路から入力され た送信信号を信号線路 707と信号線路 709とを介してアンテナ端子 703へと透過さ せる送信用フィルタ 704と、アンテナ端子 703から入力される受信信号を信号線路 7 10と信号線路 708とを介して信号端子 702に接続された受信回路へと透過させる受 信用フィルタ 705とを備えている。この分波器では、アンテナを送受信で共用するた め、送信用フィルタ 704及び受信用フィルタ 705が共に接続されるアンテナ端子(共 通端子) 703を備えている。  As shown in FIG. 15, the duplexer transmits the transmission signal input from the transmission circuit connected to the signal terminal 701 to the antenna terminal 703 via the signal line 707 and the signal line 709. A transmission filter 704, and a reception filter 705 that transmits a reception signal input from the antenna terminal 703 to a reception circuit connected to the signal terminal 702 via the signal line 710 and the signal line 708. . This duplexer includes an antenna terminal (common terminal) 703 to which the transmission filter 704 and the reception filter 705 are connected in order to share the antenna for transmission and reception.
[0005] これらの信号端子 701 , 702、共通端子 703、送信用フィルタ 704、受信用フィルタ  [0005] These signal terminals 701 and 702, common terminal 703, transmission filter 704, reception filter
705、及び信号線路 707〜710を単純に接続すると、送信回路から入力され送信用 フィルタ 704を透過した信号が受信用フィルタ 705に漏洩してしまう。このため、受信 用の周波数帯域についてはアンテナから送信回路へのインピーダンスがほぼ無限大 となる一方で、送信用の周波数帯域については送信回路から受信回路へのインピー ダンスがほぼ無限大となるように調整する整合回路 706が設けられている。 [0006] この整合回路 706は、通常 1点以上のインダクタなどの部品からなる力 携帯式の 通信端末に用いられる回路や部品に対する小型化の要求に応えるために、整合回 路 706も分波器の素子内に納められた整合回路一体型の分波器が求められている 。そして、整合回路一体型の分波器の小型化を図るためには、整合回路 706自体に 用いられる素子数をできる限り削減する必要があり、整合回路 706の部品点数を最 少とした構成は、共通端子 703と接地端子との間にインダクタを設けた構成である。 When the 705 and the signal lines 707 to 710 are simply connected, a signal input from the transmission circuit and transmitted through the transmission filter 704 leaks to the reception filter 705. For this reason, the impedance from the antenna to the transmission circuit is almost infinite for the frequency band for reception, while the impedance from the transmission circuit to the reception circuit is almost infinite for the frequency band for transmission. A matching circuit 706 is provided for adjustment. [0006] This matching circuit 706 is usually composed of one or more inductors and other components. In order to meet the demand for miniaturization of circuits and components used in portable communication terminals, the matching circuit 706 is also a duplexer. Therefore, there is a need for a matching circuit-integrated duplexer that is housed in the element. In order to reduce the size of the matching circuit integrated duplexer, it is necessary to reduce the number of elements used in the matching circuit 706 itself as much as possible, and the configuration in which the number of parts of the matching circuit 706 is minimized is as follows. In this configuration, an inductor is provided between the common terminal 703 and the ground terminal.
[0007] ところで、整合回路 706において必要なインダクタンスの値は、分波器を用いる周 波数帯域によって左右される力 2GHz近辺の周波数帯域では 1〜6ηΗ程度、 900 MHz近辺の周波数帯域では数 nH〜十数 nH程度である。そして、このような整合回 路 706を分波器内に収める方法としては、フィルタ素子を形成した基板を実装する回 路基板やパッケージの内部に線路を用いたインダクタを設ける方法が挙げられる。  [0007] By the way, the inductance value required in the matching circuit 706 is a force that depends on the frequency band using the demultiplexer. The frequency band near 2 GHz is about 1 to 6 ηΗ, and the frequency band near 900 MHz is several nH to About a dozen nH. Examples of a method for placing such a matching circuit 706 in the duplexer include a circuit board on which a board on which a filter element is formed is mounted, and an inductor using a line inside the package.
[0008] 但し、このような方法で整合回路一体型の分波器の小型化を図ると、整合回路 706 と送受信用の信号線路との間、及び送信用の信号線路と受信用の信号線路との間 における電気的な干渉によりアイソレーションが悪化するといつた問題が生じる。  However, when the matching circuit integrated duplexer is reduced in size by such a method, between the matching circuit 706 and the signal line for transmission / reception, and between the signal line for transmission and the signal line for reception When the isolation deteriorates due to electrical interference between the two, problems arise.
[0009] そこで、整合回路 706と送受信用の信号線路との間、及び送信用の信号線路と受 信用の信号線路との間における電気的な干渉を低減して、良好なアイソレーション特 性を得るために、送受信用の信号線路と整合回路間、及び送信用の信号線路と受 信用の信号線路との間に接地パターンを設ける技術が提案されている(例えば、特 開 2003— 298462号公報参照)。  [0009] Therefore, it is possible to reduce electrical interference between the matching circuit 706 and the transmission / reception signal line, and between the transmission signal line and the reception signal line, and to achieve good isolation characteristics. In order to achieve this, a technique for providing a ground pattern between a transmission / reception signal line and a matching circuit, and between a transmission signal line and a reception signal line has been proposed (for example, Japanese Patent Application Laid-Open No. 2003-298462). reference).
[0010] しかしながら、特開 2003— 298462号公報に記載の技術では、送受信用の信号 線路が回路基板の外周部に形成されているため、回路基板の外部空間において、 信号線路間で電磁界の結合が起こり、アイソレーションが十分に得られない問題があ つた。また、回路基板外部へ信号が放射されるために他の部品に悪影響を与えるとと もに、外部の部品からの信号 (ノイズ)の影響を受け易いといった問題があった。 発明の開示  [0010] However, in the technique described in Japanese Patent Application Laid-Open No. 2003-298462, since the transmission / reception signal line is formed on the outer periphery of the circuit board, an electromagnetic field is generated between the signal lines in the external space of the circuit board. There was a problem that bonding occurred and sufficient isolation was not obtained. In addition, since the signal is radiated to the outside of the circuit board, other components are adversely affected, and the signal (noise) from the external components is easily affected. Disclosure of the invention
[0011] 本発明は上記課題に鑑みてなされたものであり、回路基板内部におけるアイソレー シヨン特性、並びに回路基板外部との間におけるアイソレーション特性を向上させる ことが可能な分波器デバイス用回路基板、分波器及びこれを用いた通信装置を提供 することを目白勺とする。 The present invention has been made in view of the above problems, and a circuit board for a duplexer device capable of improving the isolation characteristics inside the circuit board and the isolation characteristics between the outside of the circuit board. Provides a duplexer and a communication device using the duplexer Doing that is to do.
[0012] 上記課題を解決するため、第 1の態様に係る分波器デバイス用回路基板は、相互 に積層された複数の誘電体層と、前記複数の誘電体層によって包囲されているととも に、相互に通過周波数帯域が異なる第 1及び第 2のフィルタ素子間のインピーダンス を調整するための整合回路用線路と、前記複数の誘電体層によって包囲されている とともに、前記複数の誘電体層の最上層から最下層に渡って形成され、かつ前記第 1のフィルタ素子と第 1の信号電送用端子とを電気的に接続するための第 1の信号電 送用線路と、前記第 2のフィルタ素子と第 2の信号電送用端子とを電気的に接続する ための第 2の信号電送用線路と、前記第 1の信号電送用線路と前記整合回路用線 路との間、及び前記第 1の信号電送用線路と前記第 2の信号電送用線路との間に設 けられ、かつ前記第 1の信号電送用線路を囲む第 1の接地用導体と、を備えるように した。  [0012] In order to solve the above problem, the duplexer device circuit board according to the first aspect includes a plurality of dielectric layers stacked on each other and surrounded by the plurality of dielectric layers. And a matching circuit line for adjusting the impedance between the first and second filter elements having different pass frequency bands and the plurality of dielectric layers, and the plurality of dielectric layers And a first signal transmission line for electrically connecting the first filter element and the first signal transmission terminal, and the second signal transmission line. A second signal transmission line for electrically connecting the filter element and the second signal transmission terminal; and between the first signal transmission line and the matching circuit line; and Between the first signal transmission line and the second signal transmission line. Setting vignetting, and it was set to and a first grounding conductor surrounding the first signal electrical transmission for lines to.
[0013] これにより、回路基板内部の線路間が電気的に遮蔽されるとともに、接地用の導体 によって囲まれた信号電送用線路と回路基板外部との間も電気的に遮蔽されるため 、回路基板内部における電気的な干渉及び回路基板外部との間における電気的な 干渉を低減することができ、その結果として、回路基板内部におけるアイソレーション 特性、並びに回路基板外部との間におけるアイソレーション特性を向上させることが できる。  [0013] Thereby, between the lines inside the circuit board is electrically shielded, and between the signal transmission line surrounded by the grounding conductor and the outside of the circuit board is also electrically shielded. It is possible to reduce electrical interference inside the board and outside the circuit board. As a result, the isolation characteristics inside the circuit board and the isolation characteristics inside the circuit board can be reduced. It can be improved.
[0014] 第 2の態様に係る分波器デバイス用回路基板は、第 1の態様に係る分波器デバイ ス用回路基板であって、前記第 2の信号電送用線路が、前記複数の誘電体層によつ て包囲されているとともに、前記複数の誘電体層の最上層から最下層に渡って形成 され、前記分波器デバイス用回路基板が、前記第 2の信号電送用線路と前記整合回 路用線路との間、及び前記第 2の信号電送用線路と前記第 1の信号電送用線路との 間に設けられ、かつ前記第 2の信号電送用線路を囲む第 2の接地用導体、を更に備 えるよつにした。  [0014] A duplexer device circuit board according to a second aspect is the duplexer device circuit board according to the first aspect, wherein the second signal transmission line includes the plurality of dielectrics. The duplexer device circuit board is surrounded by a body layer and formed from an uppermost layer to a lowermost layer of the plurality of dielectric layers, and the duplexer device circuit board includes the second signal transmission line and the A second grounding line provided between the matching circuit line and between the second signal transmission line and the first signal transmission line and surrounding the second signal transmission line. The conductor was further equipped.
[0015] これにより、送信用及び受信用の信号電送用線路の双方について、回路基板内部 の線路間が電気的に遮蔽されるとともに、回路基板外部との間も電気的に遮蔽され るため、回路基板内部におけるアイソレーション特性、並びに回路基板外部との間に おけるアイソレーション特性をより向上させることができる。 [0015] With this, both the transmission and reception signal transmission lines are electrically shielded between the lines inside the circuit board and are also electrically shielded from the outside of the circuit board. Between the isolation characteristics inside the circuit board and the outside of the circuit board Isolation characteristics can be further improved.
[0016] 第 3の態様に係る分波器デバイス用回路基板は、第 1の態様に係る分波器デバイ ス用回路基板であって、前記第 1の接地用導体が、前記複数の誘電体層のうちの相 互に隣接した 1組以上の誘電体層の層間に形成された導体パターンを含むようにし た。 [0016] A circuit board for a duplexer device according to a third aspect is the circuit board for a duplexer device according to the first aspect, wherein the first grounding conductor is the plurality of dielectrics. The conductor pattern formed between the layers of one or more dielectric layers adjacent to each other among the layers was included.
[0017] これにより、誘電体層間に形成された導体パターンによって信号電送用線路の周 囲を囲む接地用の導体を構成するため、容易に接地用の導体を形成することができ  [0017] Accordingly, since the grounding conductor surrounding the circumference of the signal transmission line is configured by the conductor pattern formed between the dielectric layers, the grounding conductor can be easily formed.
[0018] 第 4の態様に係る分波器デバイス用回路基板は、第 3の態様に係る分波器デバイ ス用回路基板であって、前記第 1の接地用導体が、前記複数の誘電体層のうちの相 互に隣接した複数組の誘電体層の層間にそれぞれ形成された複数の導体パターン 領域と、当該複数の導体パターン領域によって挟まれた誘電体層を貫通し、かつ前 記複数の導体パターン領域を相互に電気的に接続した 1以上の導体と、を含むよう にした。 [0018] A circuit board for a duplexer device according to a fourth aspect is the circuit board for a duplexer device according to the third aspect, wherein the first grounding conductor is the plurality of dielectrics. A plurality of conductor pattern regions respectively formed between layers of a plurality of dielectric layers adjacent to each other, and a plurality of the dielectric layers sandwiched between the plurality of conductor pattern regions, And one or more conductors that are electrically connected to each other.
[0019] 第 5の態様に係る分波器デバイス用回路基板は、第 4の態様に係る分波器デバイ ス用回路基板であって、前記 1以上の導体が、前記第 1の信号電送用線路を囲むよ うに設けられた複数の導体を含むようにした。  [0019] A duplexer device circuit board according to a fifth aspect is the duplexer device circuit board according to the fourth aspect, wherein the one or more conductors are used for the first signal transmission. A plurality of conductors provided so as to surround the track were included.
[0020] これにより、信号電送用線路を更に誘電体層を貫通する複数の接地用の導体で囲 むことで、回路基板内部におけるアイソレーション特性、並びに回路基板外部との間 におけるアイソレーション特性を更に向上させることができる。  [0020] Thus, by surrounding the signal transmission line with a plurality of grounding conductors that further penetrate the dielectric layer, the isolation characteristic inside the circuit board and the isolation characteristic between the outside of the circuit board can be obtained. Further improvement can be achieved.
[0021] 第 6の態様に係る分波器デバイス用回路基板は、第 1の態様に係る分波器デバイ ス用回路基板であって、前記第 1及び第 2のフィルタ素子が、それぞれラダー型のフ イノレタ素子であるようにした。  [0021] A circuit board for a duplexer device according to a sixth aspect is the circuit board for a duplexer device according to the first aspect, wherein each of the first and second filter elements is a ladder type. It was made to be a finala element.
[0022] 第 7の態様に係る分波器デバイス用回路基板は、第 4の態様に係る分波器デバイ ス用回路基板であって、前記第 1及び第 2のフィルタ素子のうちの相対的に高い通過 周波数帯域を有するフィルタ素子が、並列腕に共振子を有し、前記共振子が、前記 第 1の接地用導体に対して電気的に接続されているようにした。  [0022] A circuit board for a duplexer device according to a seventh aspect is the circuit board for a duplexer device according to the fourth aspect, and is a relative of the first and second filter elements. A filter element having a very high pass frequency band has a resonator in a parallel arm, and the resonator is electrically connected to the first grounding conductor.
[0023] これにより、信号電送用線路の周囲に接地用の導体パターンが設けられたことで、 接地用の導体パターン間に誘電体層を貫通する導体をより多く配置する事ができ、 その結果として、相対的に高い通過周波数帯域を有するフィルタ素子の並列共振子 と接地用の端子との間を電気的に接続する導体のインダクタンスが小さくなるため、 相対的に高い通過周波数帯域を有するフィルタ素子の低周波側の帯域外減衰量が 増大する。 [0023] Thereby, by providing a grounding conductor pattern around the signal transmission line, More conductors penetrating the dielectric layer can be arranged between the grounding conductor patterns, and as a result, between the parallel resonator of the filter element having a relatively high pass frequency band and the grounding terminal. Since the inductance of the conductor that electrically connects to the filter element becomes small, the out-of-band attenuation on the low frequency side of the filter element having a relatively high pass frequency band increases.
[0024] 第 8の態様に係る分波器デバイス用回路基板は、第 2の態様に係る分波器デバイ ス用回路基板であって、前記第 1及び第 2の接地用導体が、前記複数の誘電体層の うちの相互に隣接した 1組以上の誘電体層の層間に形成された導体パターンをそれ ぞれ含むようにした。  [0024] A circuit board for a duplexer device according to an eighth aspect is the circuit board for a duplexer device according to the second aspect, wherein the first and second grounding conductors are the plurality. Each of the dielectric layers includes a conductor pattern formed between one or more dielectric layers adjacent to each other.
[0025] これにより、誘電体層間に形成された導体パターンによって信号電送用線路の周 囲を囲む接地用の導体を構成するため、容易に接地用の導体を形成することができ  [0025] With this, the grounding conductor is formed by surrounding the periphery of the signal transmission line with the conductor pattern formed between the dielectric layers, so that the grounding conductor can be easily formed.
[0026] 第 9の態様に係る分波器デバイス用回路基板は、第 8の態様に係る分波器デバイ ス用回路基板であって、前記第 1の接地用導体が、前記複数の誘電体層のうちの相 互に隣接した複数組の誘電体層の層間にそれぞれ形成された複数の第 1の導体パ ターン領域と、当該複数の第 1の導体パターン領域によって挟まれた誘電体層を貫 通し、かつ前記複数の第 1の導体パターン領域を相互に電気的に接続した 1以上の 導体と、を含み、前記第 2の接地用導体が、前記複数の誘電体層のうちの相互に隣 接した複数組の誘電体層の層間にそれぞれ形成された複数の第 2の導体パターン 領域と、当該複数の第 2の導体パターン領域によって挟まれた誘電体層を貫通し、か つ前記複数の第 2の導体パターン領域を相互に電気的に接続した 1以上の導体と、 を含むようにした。 [0026] A circuit board for a duplexer device according to a ninth aspect is the circuit board for a duplexer device according to the eighth aspect, wherein the first grounding conductor is the plurality of dielectrics. A plurality of first conductor pattern regions respectively formed between a plurality of sets of dielectric layers adjacent to each other, and a dielectric layer sandwiched between the plurality of first conductor pattern regions. One or more conductors that pass through and electrically connect the plurality of first conductor pattern regions to each other, and the second grounding conductor is mutually connected among the plurality of dielectric layers. A plurality of second conductor pattern regions respectively formed between layers of a plurality of adjacent dielectric layers and a dielectric layer sandwiched between the plurality of second conductor pattern regions, and the plurality One or more conductors electrically connected to each other in the second conductor pattern area of the I included it.
[0027] 第 10の態様に係る分波器デバイス用回路基板は、第 9の態様に係る分波器デバイ ス用回路基板であって、前記複数の第 1の導体パターン領域を相互に電気的に接続 した 1以上の導体力 S、前記第 1の信号電送用線路を囲むように設けられた複数の導 体を含むようにした。  [0027] A circuit board for a duplexer device according to a tenth aspect is the circuit board for a duplexer device according to the ninth aspect, wherein the plurality of first conductor pattern regions are electrically connected to each other. And a plurality of conductors provided so as to surround the first signal transmission line.
[0028] これにより、信号電送用線路を更に誘電体層を貫通する複数の接地用の導体で囲 むことで、回路基板内部におけるアイソレーション特性、並びに回路基板外部との間 におけるアイソレーション特性を更に向上させることができる。 [0028] Thus, by surrounding the signal transmission line with a plurality of grounding conductors that further penetrate the dielectric layer, the isolation characteristics inside the circuit board and the outside of the circuit board can be obtained. The isolation characteristics in can be further improved.
[0029] 第 11の態様に係る分波器デバイス用回路基板は、第 9の態様に係る分波器デバイ ス用回路基板であって、前記複数の第 2の導体パターン領域を相互に電気的に接続 した 1以上の導体力 S、前記第 2の信号電送用線路を囲むように設けられた複数の導 体を含むようにした。 [0029] A circuit board for a duplexer device according to an eleventh aspect is the circuit board for a duplexer device according to the ninth aspect, wherein the plurality of second conductor pattern regions are electrically connected to each other. And a plurality of conductors provided so as to surround the second signal transmission line.
[0030] これにより、信号電送用線路を更に誘電体層を貫通する複数の接地用の導体で囲 むことで、回路基板内部におけるアイソレーション特性、並びに回路基板外部との間 におけるアイソレーション特性を更に向上させることができる。  [0030] Thus, by surrounding the signal transmission line with a plurality of grounding conductors that further penetrate the dielectric layer, the isolation characteristic inside the circuit board and the isolation characteristic between the outside of the circuit board can be obtained. Further improvement can be achieved.
[0031] 第 12の態様に係る分波器デバイス用回路基板は、第 9の態様に係る分波器デバイ ス用回路基板であって、前記第 1及び第 2のフィルタ素子が、それぞれラダー型のフ イノレタ素子であるようにした。  [0031] A circuit board for a duplexer device according to a twelfth aspect is the circuit board for a duplexer device according to the ninth aspect, wherein each of the first and second filter elements is a ladder type It was made to be a finala element.
[0032] 第 13の態様に係る分波器デバイス用回路基板は、第 9の態様に係る分波器デバイ ス用回路基板であって、前記第 1及び第 2のフィルタ素子のうちの相対的に高い通過 周波数帯域を有するフィルタ素子が、並列腕に共振子を有し、前記共振子が、前記 第 1及び第 2の接地用導体に対して電気的に接続されているようにした。  [0032] A circuit board for a duplexer device according to a thirteenth aspect is the circuit board for a duplexer device according to the ninth aspect, and is a relative of the first and second filter elements. A filter element having a very high pass frequency band has a resonator in a parallel arm, and the resonator is electrically connected to the first and second grounding conductors.
[0033] これにより、信号電送用線路の周囲に接地用の導体パターンが設けられたことで、 接地用の導体パターン間に誘電体層を貫通する導体をより多く配置する事ができ、 その結果として、相対的に高い通過周波数帯域を有するフィルタ素子の並列共振子 と接地用の端子との間を電気的に接続する導体のインダクタンスが小さくなるため、 相対的に高い通過周波数帯域を有するフィルタ素子の低周波側の帯域外減衰量が 増大する。  [0033] Thereby, since the grounding conductor pattern is provided around the signal transmission line, more conductors penetrating the dielectric layer can be arranged between the grounding conductor patterns. Filter element having a relatively high pass frequency band because the inductance of the conductor electrically connecting between the parallel resonator of the filter element having a relatively high pass frequency band and the grounding terminal is reduced. The out-of-band attenuation on the low frequency side increases.
[0034] 第 14の態様に係る分波器デバイス用回路基板は、第 1の態様に係る分波器デバイ ス用回路基板であって、前記第 1のフィルタ素子が、送信用フィルタ素子であり、前記 第 2のフィルタ素子力 受信用フィルタ素子であるようにした。  [0034] A circuit board for a duplexer device according to a fourteenth aspect is the circuit board for a duplexer device according to the first aspect, wherein the first filter element is a filter element for transmission. The second filter element force is a receiving filter element.
[0035] 第 15の態様に係る分波器は、第 1から第 14の態様のいずれかの態様に係る分波 器デバイス用回路基板と、前記分波器デバイス用回路基板に対して実装された前記 第 1及び第 2のフィルタ素子と、を備えるようにした。 [0035] A duplexer according to the fifteenth aspect is mounted on the duplexer device circuit board according to any one of the first to fourteenth aspects, and the duplexer device circuit board. The first and second filter elements are provided.
[0036] 第 16の態様に係る分波器は、第 15の態様に係る分波器であって、前記第 1のフィ ルタ素子が、送信用フィルタ素子であり、前記第 2のフィルタ素子が、受信用フィルタ 素子であり、前記第 1及び第 2のフィルタ素子力、アンテナに対して電気的に接続さ れた共通端子に共通して電気的に接続され、前記整合回路の一端が、前記共通端 子に対して電気的に接合され、前記整合回路の一端とは異なる前記整合回路の他 端が、接地されているようにした。 [0036] A duplexer according to a sixteenth aspect is the duplexer according to the fifteenth aspect, wherein the first filter The filter element is a transmission filter element, the second filter element is a reception filter element, and the first and second filter element forces and a common terminal electrically connected to the antenna And one end of the matching circuit is electrically connected to the common terminal, and the other end of the matching circuit that is different from one end of the matching circuit is grounded. I did it.
[0037] 第 17の態様に係る分波器は、第 16の態様に係る分波器であって、前記整合回路 力、所定の受信用の周波数帯域の信号について前記共通端子から送信回路へのィ ンピーダンスがほぼ無限大となり、所定の送信用の周波数帯域の信号について前記 送信回路から受信回路へのインピーダンスがほぼ無限大となるようにした。  [0037] A duplexer according to a seventeenth aspect is the duplexer according to the sixteenth aspect, wherein the matching circuit power and a signal in a predetermined frequency band for reception are transmitted from the common terminal to the transmission circuit. The impedance is almost infinite, and the impedance from the transmitting circuit to the receiving circuit is made almost infinite for a signal in a predetermined frequency band for transmission.
[0038] 第 18の態様に係る分波器は、第 17の態様に係る分波器であって、前記受信用の 周波数帯域が、 869〜894MHzであり、前記送信用の周波数帯域が、 824-849 MHzであるようにした。  [0038] A duplexer according to an eighteenth aspect is the duplexer according to the seventeenth aspect, wherein the frequency band for reception is 869 to 894 MHz, and the frequency band for transmission is 824. -849 MHz.
[0039] 第 19の態様に係る分波器は、第 15の態様に係る分波器であって、前記第 1及び 第 2のフィルタ素子力 S、それぞれ環状電極部によって取り囲まれているようにした。  [0039] A duplexer according to a nineteenth aspect is the duplexer according to the fifteenth aspect, wherein the first and second filter element forces S are each surrounded by an annular electrode portion. did.
[0040] 第 20の態様に係る通信装置は、第 15から第 19の態様のいずれかの態様に係る分 波器が搭載されたものとした。  [0040] The communication device according to the twentieth aspect is mounted with the duplexer according to any of the fifteenth to nineteenth aspects.
図面の簡単な説明  Brief Description of Drawings
[0041] [図 1]本発明の第 1実施形態に係る通信装置の機能構成を示すブロック図である。  FIG. 1 is a block diagram showing a functional configuration of a communication apparatus according to a first embodiment of the present invention.
[図 2]本発明の第 1実施形態に係る分波器の回路構成を例示する図である。  FIG. 2 is a diagram illustrating a circuit configuration of a duplexer according to the first embodiment of the present invention.
[図 3]本発明の第 1実施形態に係る回路基板の概略構成を例示する断面模式図であ  FIG. 3 is a schematic cross-sectional view illustrating the schematic configuration of the circuit board according to the first embodiment of the invention.
[図 4]本発明の第 1実施形態に係る回路基板の導体パターンとビアの配置を例示す る図である。 FIG. 4 is a diagram illustrating an example of the arrangement of conductor patterns and vias on the circuit board according to the first embodiment of the present invention.
[図 5]本発明の第 1実施形態に係る回路基板の導体パターンとビアの配置を例示す る図である。  FIG. 5 is a diagram showing an example of the arrangement of conductor patterns and vias on the circuit board according to the first embodiment of the present invention.
[図 6]本発明の第 1実施形態に係る弾性表面波素子の構成を例示する上面図である FIG. 6 is a top view illustrating the configuration of the surface acoustic wave element according to the first embodiment of the invention.
Yes
[図 7]本発明の第 2実施形態に係る回路基板の導体パターンとビアの配置を例示す る図である。 FIG. 7 shows an example of the arrangement of conductor patterns and vias on the circuit board according to the second embodiment of the present invention. FIG.
[図 8]本発明の第 2実施形態に係る回路基板の導体パターンとビアの配置を例示す る図である。  FIG. 8 is a diagram illustrating an example of the arrangement of conductor patterns and vias on a circuit board according to a second embodiment of the present invention.
[図 9]本発明の第 2実施形態に係る分波器の等価回路を示す図である。  FIG. 9 is a diagram showing an equivalent circuit of the duplexer according to the second embodiment of the present invention.
[図 10]比較例に係る回路基板の導体パターンとビアの配置を示す図である。  FIG. 10 is a diagram showing an arrangement of conductor patterns and vias on a circuit board according to a comparative example.
[図 11]比較例に係る回路基板の導体パターンとビアの配置を示す図である。  FIG. 11 is a diagram showing an arrangement of conductor patterns and vias of a circuit board according to a comparative example.
[図 12]実施例 1 , 2及び比較例のアイソレーション特性を示す図である。  FIG. 12 is a graph showing the isolation characteristics of Examples 1 and 2 and a comparative example.
[図 13]実施例 1 , 2及び比較例のアイソレーション特性を示す図である。  FIG. 13 is a graph showing the isolation characteristics of Examples 1 and 2 and a comparative example.
[図 14]実施例 1 , 2及び比較例のアイソレーション特性を示す図である。  FIG. 14 is a graph showing the isolation characteristics of Examples 1 and 2 and a comparative example.
[図 15]従来の分波器の回路構成を例示する図である。  FIG. 15 is a diagram illustrating a circuit configuration of a conventional duplexer.
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0042] 以下、本発明の実施形態を図面に基づいて説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0043] <第 1実施形態〉 [0043] <First embodiment>
<通信装置〉  <Communication device>
図 1は、本発明の第 1実施形態に係る通信装置 100の機能構成を示すブロック図 である。通信装置 100は、例えば、携帯電話機や携帯式の無線端末等によって構成 される。  FIG. 1 is a block diagram showing a functional configuration of the communication apparatus 100 according to the first embodiment of the present invention. The communication device 100 is configured by, for example, a mobile phone or a portable wireless terminal.
[0044] 図 1に示すように、通信装置 100は、主に制御部 200、送受信機 300、アンテナ 40 0、操作部 600、マイクロフォン MP、及びスピーカ SPを備えている。  As shown in FIG. 1, the communication device 100 mainly includes a control unit 200, a transceiver 300, an antenna 400, an operation unit 600, a microphone MP, and a speaker SP.
[0045] 制御部 200は、通信装置 100の各種動作を統括制御する部位である。この制御部 200は、 CPU, RAM,及び ROM等を備え、 ROM内等に格納されたプログラムを C PUが読み込んで実行することで、通信装置 100の各種制御や機能が実現される。  The control unit 200 is a part that performs overall control of various operations of the communication device 100. The control unit 200 includes a CPU, a RAM, a ROM, and the like, and various controls and functions of the communication apparatus 100 are realized by the CPU reading and executing a program stored in the ROM or the like.
[0046] アンテナ 400は、送受信機 300からの送信信号に基づいて無線電波を発信する一 方、通信装置 100の外部からの無線電波を受け付けて送受信機 300に対して受信 信号を転送する部位である。  [0046] The antenna 400 is a part that transmits a radio wave based on a transmission signal from the transceiver 300, and receives a radio wave from the outside of the communication apparatus 100 and transfers a reception signal to the transceiver 300. is there.
[0047] スピーカ SPは、送受信機 300からの音声信号に応答して音声を発する部位であり 、マイクロフォン MPは、音声の受け付けに応答して音声信号を生成して制御部 200 を介して送受信機 300に対して音声信号を出力する部位である。 [0048] 操作部 600は、ユーザーによる通信装置 100への各種入力を受け付ける部位であ り、例えば、各種ボタン等によって構成される。 The speaker SP is a part that emits a sound in response to the sound signal from the transceiver 300, and the microphone MP generates a sound signal in response to the reception of the sound and transmits the transceiver via the control unit 200. This is a part that outputs an audio signal to 300. [0048] The operation unit 600 is a part that accepts various inputs from the user to the communication device 100, and includes, for example, various buttons.
[0049] 送受信機 300は、マイクロフォン MPから制御部 200を介して入力された音声信号 を送信信号に変換してアンテナ 400に出力する一方、アンテナ 400からの受信信号 を音声信号に変換してスピーカ SPに対して出力する部位である。  [0049] The transceiver 300 converts an audio signal input from the microphone MP through the control unit 200 into a transmission signal and outputs the transmission signal to the antenna 400, while converting a reception signal from the antenna 400 into an audio signal and a speaker. This is the part that outputs to SP.
[0050] この送受信機 300では、マイクロフォン MP力、ら制御部 200を介して入力されたアナ ログ音声信号が DSP(Digital Signal PrOCeSSOr)301で A/D変換 (アナログ信号から デジタル信号へ変換)された後、変調器 302で変調され、更に局部発振器 320の発 振信号を用いてミキサ 303で周波数変換される。ミキサ 303の出力は送信用バンドパ スフィルタ 304およびパワーアンプ 305を通り、分波器 306を通ってアンテナ 400に 対して送信信号として出力される。 [0050] In the transceiver 300, an analog audio signal input via the microphone MP force and the control unit 200 is A / D converted (converted from an analog signal to a digital signal) by a DSP (Digital Signal Pr OCeSSO r) 301. ), The signal is modulated by the modulator 302 and further frequency-converted by the mixer 303 using the oscillation signal of the local oscillator 320. The output of the mixer 303 passes through the transmission band-pass filter 304 and the power amplifier 305, passes through the duplexer 306, and is output as a transmission signal to the antenna 400.
[0051] また、アンテナ 400からの受信信号は分波器 306を通ってローノイズアンプ 307、 受信用バンドパスフィルタ 308を経てミキサ 309へ入力される。ミキサ 309は局部発 振器 320の発振信号を用いて受信信号の周波数を変換し、当該変換された信号は ローパスフィルタ 310を通って復調器 311で復調され、更に DSP301で D/A変換( デジタル信号からアナログ信号へ変換)された後、制御部 200を介してスピーカ SP に対してアナログ音声信号として出力される。  In addition, a received signal from antenna 400 is input to mixer 309 through demultiplexer 306, low noise amplifier 307, and reception bandpass filter 308. The mixer 309 converts the frequency of the received signal using the oscillation signal of the local oscillator 320, the converted signal passes through the low-pass filter 310, is demodulated by the demodulator 311, and is further D / A converted (digital) by the DSP 301. After the signal is converted into an analog signal, it is output as an analog audio signal to the speaker SP via the control unit 200.
[0052] なお、通信装置 100の送受信機 300では、アイソレーション特性に優れた分波器 3 06が搭載されているため、ノイズの少ない通話が可能である。以下、分波器 306に ついて詳述する。  [0052] Note that the transmitter / receiver 300 of the communication device 100 is equipped with the duplexer 310 having excellent isolation characteristics, so that a call with less noise is possible. Hereinafter, the duplexer 306 will be described in detail.
[0053] <分波器〉  [0053] <Demultiplexer>
図 2は、本発明の第 1実施形態に係る分波器 306の回路構成を例示する図である FIG. 2 is a diagram illustrating a circuit configuration of the duplexer 306 according to the first embodiment of the present invention.
Yes
[0054] 図 2に示すように、分波器 306は、信号端子 1 , 2、共通端子 3、送信用フィルタ素子  As shown in FIG. 2, the duplexer 306 includes signal terminals 1 and 2, a common terminal 3, and a transmission filter element.
(以下、単に「送信用フィルタ」と略称する) 4、受信用フィルタ素子(以下、単に「受信 用フィルタ」と略称する) 5、整合回路 6、及び信号線路 7〜; 10を備えている。  (Hereinafter simply referred to as “transmission filter”) 4, a reception filter element (hereinafter simply referred to as “reception filter”) 5, a matching circuit 6, and signal lines 7 to 10 are provided.
[0055] 信号端子 1は、送信側の回路(送信回路)に含まれるパワーアンプ 305に対して電 気的に接続 (導通接続)される端子(送信側信号端子)であり、信号端子 2は、受信側 の回路(受信回路)に含まれるローノイズアンプ 307に対して電気的に接続される端 子(受信側信号端子)である。共通端子 3は、アンテナ 400に対して電気的に接続さ れる端子である。 [0055] The signal terminal 1 is a terminal (transmission side signal terminal) that is electrically connected (conducting connection) to the power amplifier 305 included in the transmission side circuit (transmission circuit). ,Receiver This is a terminal (signal terminal on the receiving side) that is electrically connected to the low noise amplifier 307 included in this circuit (receiving circuit). The common terminal 3 is a terminal that is electrically connected to the antenna 400.
[0056] 送信用フィルタ 4は、受信用フィルタ 5とは選択的に通過させる信号の周波数帯域( 通過周波数帯域)が相互に異なり、共通端子 3と送信側信号端子 1との間に設けられ ている。具体的には、送信用フィルタ 4は、送信側信号端子 1及び共通端子 3に対し て信号線路 7, 9によって電気的に接続されている。この送信用フィルタ 4は、送信側 信号端子 1から信号線路 7を介して入力された信号のうち、所定の送信用の周波数 帯域(例えば、 824〜849MHz)の信号を選択的に通過させて、信号線路 9を介して 共通端子 3に対して出力する。  The transmission filter 4 is different from the reception filter 5 in the frequency band (pass frequency band) of the signal that is selectively passed therethrough, and is provided between the common terminal 3 and the transmission-side signal terminal 1. Yes. Specifically, the transmission filter 4 is electrically connected to the transmission-side signal terminal 1 and the common terminal 3 by signal lines 7 and 9. The transmission filter 4 selectively passes a signal in a predetermined transmission frequency band (for example, 824 to 849 MHz) among signals input from the transmission-side signal terminal 1 via the signal line 7, Output to the common terminal 3 via the signal line 9.
[0057] 受信用フィルタ 5は、共通端子 3と受信側信号端子 2との間に設けられている。具体 的には、受信用フィルタ 5は、受信側信号端子 2及び共通端子 3に対して信号線路 8 , 10によって電気的に接続されている。この受信用フィルタ 5は、アンテナ 400側す なわち共通端子 3から信号線路 10を介して入力された信号のうち、所定の受信用の 周波数帯域(例えば、 869〜894MHz)の信号を選択的に通過させて、信号線路 8 を介して受信側信号端子 2に対して出力する。  The reception filter 5 is provided between the common terminal 3 and the reception-side signal terminal 2. Specifically, the reception filter 5 is electrically connected to the reception-side signal terminal 2 and the common terminal 3 by signal lines 8 and 10. The reception filter 5 selectively selects a signal in a predetermined reception frequency band (for example, 869 to 894 MHz) from signals input from the antenna 400 side, that is, the common terminal 3 through the signal line 10. Pass through and output to the signal terminal 2 on the receiving side via the signal line 8.
[0058] 整合回路 6は、一端が共通端子 3に対して電気的に接続され、他端が接地された 回路であり、所定の受信用の周波数帯域の信号については共通端子 3から送信回 路へのインピーダンスがほぼ無限大となる一方で、所定の送信用の周波数帯域の信 号については送信回路から受信回路へのインピーダンスがほぼ無限大となるように 調整する部位である。  The matching circuit 6 is a circuit in which one end is electrically connected to the common terminal 3 and the other end is grounded. A signal in a predetermined reception frequency band is transmitted from the common terminal 3 to the transmission circuit. This is a part that adjusts so that the impedance from the transmitting circuit to the receiving circuit becomes almost infinite while the impedance to the signal becomes almost infinite.
[0059] ここでは、送信信号を電送する場合には、送信用フィルタ 4から見て、共通端子 3の 前段に整合回路 6が設けられ、受信信号を電送する場合には、共通端子 3から見て 、受信用フィルタ 5の前段に整合回路 6が設けられている。  [0059] Here, when transmitting a transmission signal, a matching circuit 6 is provided in front of the common terminal 3 when viewed from the transmission filter 4, and when transmitting a reception signal, it is viewed from the common terminal 3. Thus, a matching circuit 6 is provided in front of the reception filter 5.
[0060] このような回路構成を有する分波器 306は、薄い誘電体の層が複数積層されて形 成された回路基板上に送信用フィルタ 4と受信用フィルタ 5とが例えばフリップチップ 実装されて構成される。また、整合回路 6を構成する整合用線路は、複数の誘電体 層にわたって構成された螺旋状の導体パターン (螺旋状パターン)又は蛇行状の導 体パターン (蛇行状パターン)若しくは螺旋状パターン及び蛇行状パターンの両方で 構成され、端部が接地される。 In the duplexer 306 having such a circuit configuration, the transmission filter 4 and the reception filter 5 are flip-chip mounted, for example, on a circuit board formed by laminating a plurality of thin dielectric layers. Configured. In addition, the matching line constituting the matching circuit 6 is a spiral conductor pattern (helical pattern) formed in a plurality of dielectric layers or a meandering conductor. It consists of a body pattern (meandering pattern) or both a spiral pattern and a serpentine pattern, and the end is grounded.
[0061] ここで、送信用フィルタ 4及び受信用フィルタ 5は、弾性表面波フィルタ(SAWフィル タ)であっても、所謂 FBARフィルタであっても、その他の方式のフィルタであっても良 い。また、送信用フィルタ 4及び受信用フィルタ 5は、同一基板(例えば、 SAWフィノレ タでは圧電基板、 FBARフィルタでは種々の基板)上に作製されていても、各々別個 の基板上に作製されていても構わないが、以下の理由により同一基板上に作製され ている方が好ましい。 Here, the transmission filter 4 and the reception filter 5 may be surface acoustic wave filters (SAW filters), so-called FBAR filters, or other types of filters. . Further, the transmission filter 4 and the reception filter 5 are manufactured on the same substrate (for example, a piezoelectric substrate for the SAW fintoror and various substrates for the FBAR filter), but each is manufactured on a separate substrate. However, it is preferable that they are produced on the same substrate for the following reasons.
[0062] 送信用フィルタ 4及び受信用フィルタ 5の各々には製造上のばらつきが発生する。  [0062] Manufacturing variations occur in each of the transmission filter 4 and the reception filter 5.
このため、各フィルタ 4, 5が別個の基板上に作製されている場合には、別個に様々 な製造上のばらつきが生じた送信用フィルタ 4と受信用フィルタ 5とが組み合わされる 事となる。その結果、整合回路 6の線路の導体パターン (線路パターン)の最適なイン ダクタンスの値力 S、送信用フィルタ 4と受信用フィルタ 5との組合せによって異なってし まう不具合が生じ易い。これに対して、各フィルタ 4, 5が同一基板上に作製されてい る場合には、ウェハーのほぼ同じ場所に作製されたフィルタ間では同様なばらつきが 生じるため、ウェハーから切り出したどのフィルタ 4, 5の組合せに対しても最適なイン ダクタンスの値が略同一となる。したがって、送信用フィルタ 4と受信用フィルタ 5との 組合せによる特性のばらつきを気にする必要性が無くなるといった点から、送信用フ ィルタ 4及び受信用フィルタ 5が同一基板上に作製されていることが好ましい。  For this reason, when the filters 4 and 5 are manufactured on separate substrates, the transmission filter 4 and the reception filter 5 that have various manufacturing variations are combined. As a result, the optimum inductance value S of the conductor pattern (line pattern) of the line of the matching circuit 6 and a problem that varies depending on the combination of the transmission filter 4 and the reception filter 5 are likely to occur. On the other hand, when the filters 4 and 5 are fabricated on the same substrate, similar variations occur between filters fabricated at substantially the same location on the wafer. The optimum inductance value is almost the same for the 5 combinations. Therefore, the transmission filter 4 and the reception filter 5 must be fabricated on the same substrate from the viewpoint that there is no need to worry about characteristic variations due to the combination of the transmission filter 4 and the reception filter 5. Is preferred.
[0063] <分波器デバイス用回路基板〉  [0063] <Circuit board for duplexer device>
図 3は、分波器 306のうちの送信用フィルタ 4及び受信用フィルタ 5を実装するため の回路が配設された基板(以下「分波器デバイス用回路基板」とも称する) 800の概 略構成を例示する断面模式図である。なお、図 3及び図 3以降の図では、方位関係 を明確化するために XYZの直交する 3軸が付されている。  FIG. 3 shows an outline of a substrate 800 on which a circuit for mounting the transmission filter 4 and the reception filter 5 in the duplexer 306 is disposed (hereinafter also referred to as “demultiplexer device circuit substrate”) 800. It is a cross-sectional schematic diagram which illustrates a structure. Note that in Fig. 3 and Fig. 3 and subsequent figures, three XYZ orthogonal axes are attached to clarify the orientation relationship.
[0064] 分波器デバイス用回路基板(以下、単に「回路基板」と略称する) 800は、所定形状  [0064] A circuit board for duplexer devices (hereinafter simply referred to as "circuit board") 800 has a predetermined shape.
(ここでは略矩形状)の外形を有する複数層(ここでは 3層)の誘電体の薄膜 (誘電体 層) Lb, Ld, Lfと、当該誘電体層 Lb, Ld, Lfの表面及び層間に設けられた 4層の導 体の配線パターンが設けられた層(導体配線パターン層) La, Lc, Le, Lgとを備えて いる。すなわち、 3層の誘電体層 Lb, Ld, Lfが相互に積層され、その層間に複数の 誘電体層 Lb, Ld, Lfによって挟まれた 2層の導体配線パターン層 Lc, Leが形成さ れている。 (Three layers here) dielectric thin film (dielectric layer) Lb, Ld, Lf and the surface of the dielectric layer Lb, Ld, Lf and between the layers A layer (conductor wiring pattern layer) provided with a wiring pattern of four layers of conductors provided La, Lc, Le, and Lg Yes. That is, three dielectric layers Lb, Ld, and Lf are stacked on top of each other, and two conductor wiring pattern layers Lc and Le sandwiched between the plurality of dielectric layers Lb, Ld, and Lf are formed. ing.
[0065] 導体配線パターン層 Laは、誘電体層 Lbの上面(+ Z方向の面)すなわち回路基板 [0065] The conductor wiring pattern layer La is the upper surface (the surface in the + Z direction) of the dielectric layer Lb, that is, the circuit board.
800を構成する多層基板の一方主面(ここでは、表面)に設けられて!/、る。 It is provided on one main surface (here, the surface) of the multi-layer substrate constituting the 800! /.
[0066] 導体配線パターン層 Lcは、誘電体層 Lbの下面(一 Z方向の面)であり、かつ誘電 体層 Ldの上面(+ Z方向の面)に設けられている。つまり、導体配線パターン層 Lcは[0066] The conductor wiring pattern layer Lc is provided on the lower surface (one Z-direction surface) of the dielectric layer Lb and on the upper surface (+ Z-direction surface) of the dielectric layer Ld. That is, the conductor wiring pattern layer Lc is
、誘電体層 Lbと誘電体層 Ldとの層間に設けられている。 The dielectric layer Lb is provided between the dielectric layer Ld and the dielectric layer Ld.
[0067] 導体配線パターン層 Leは、誘電体層 Ldの下面(一 Z方向の面)であり、かつ誘電 体層 Lfの上面(+ Z方向の面)に設けられている。つまり、導体配線パターン層 LeはThe conductor wiring pattern layer Le is provided on the lower surface (one Z direction surface) of the dielectric layer Ld and on the upper surface (+ Z direction surface) of the dielectric layer Lf. In other words, the conductor wiring pattern layer Le is
、誘電体層 Ldと誘電体層 Lfとの層間に設けられている。 The dielectric layer Ld and the dielectric layer Lf are provided between the layers.
[0068] 導体配線パターン層 Lgは、誘電体層 Lfの下面(一 Z方向の面)すなわち回路基板[0068] The conductor wiring pattern layer Lg is a lower surface (one Z-direction surface) of the dielectric layer Lf, that is, a circuit board.
800を構成する多層基板の他方主面(ここでは、裏面)に設けられている。 It is provided on the other main surface (here, the back surface) of the multilayer substrate constituting 800.
[0069] このように、回路基板 800は、図 3中の上から順番に、導体配線パターン層 La、誘 電体層 Lb、導体配線パターン層 Lc、誘電体層 Ld、導体配線パターン層 Le、誘電体 層 Lf、及び導体配線パターン層 Lgが積層されて構成されて!/、る。 [0069] Thus, the circuit board 800 includes, in order from the top in FIG. 3, the conductor wiring pattern layer La, the dielectric layer Lb, the conductor wiring pattern layer Lc, the dielectric layer Ld, the conductor wiring pattern layer Le, The dielectric layer Lf and the conductor wiring pattern layer Lg are laminated.
[0070] 誘電体層 Lb, Ld, Lfを構成する誘電体の材料としては、例えばアルミナを主成分 とするセラミックスや、低温で焼結可能なガラスセラミックス、又は有機材料を主成分と するガラスエポキシ樹脂等が用いられる。  [0070] Examples of the dielectric material constituting the dielectric layers Lb, Ld, and Lf include ceramics mainly composed of alumina, glass ceramics that can be sintered at low temperature, or glass epoxy mainly composed of organic materials. Resin or the like is used.
[0071] なお、誘電体の材料として、セラミックスやガラスセラミックスを用いる場合には、まず 、セラミックス等の金属酸化物と有機バインダとが有機溶剤等で均質に混練されたス ラリーをシート状に成型することでグリーンシートを複数枚作製する。次に、複数枚の グリーンシートに対して所望の導体のパターン (導体パターン)や表面から裏面へと 貫通するビアホールに導体を充填した導体部分(以下、単に「ビア」と略称する)を形 成した後に、複数枚のグリーンシートを積層して圧着することで一体形成して焼成す ることにより、回路基板 800が作製される。  [0071] When ceramics or glass ceramics is used as the dielectric material, a slurry in which a metal oxide such as ceramics and an organic binder are homogeneously kneaded with an organic solvent or the like is first molded into a sheet shape. This produces a plurality of green sheets. Next, a desired conductor pattern (conductor pattern) and a conductor portion (hereinafter simply referred to as “via”) filled with a conductor in a via hole penetrating from the front surface to the back surface are formed on a plurality of green sheets. After that, the circuit board 800 is manufactured by laminating a plurality of green sheets and press-bonding them together and firing them.
[0072] 整合回路 6を構成する螺旋状パターンや蛇行状パターンは、各誘電体層(ここでは 、誘電体層 Ld, Lf)の表面に導体によって作製された複数の導体パターン力 誘電 体層を貫通して設けられたビアによって電気的に接続されることで形成されている。 [0072] The spiral pattern and the meandering pattern constituting the matching circuit 6 are a plurality of conductor pattern forces produced by a conductor on the surface of each dielectric layer (here, the dielectric layers Ld and Lf). It is formed by being electrically connected by a via provided through the body layer.
[0073] ここで、導体パターンを構成する導体としては、銀、銀にパラジウムを添加した合金 、タングステン、銅、及び金などを採用することができる。当該導体パターンは、金属 導体を用いたスクリーン印刷、或いは蒸着やスパッタリング等の成膜法とエッチングと の組合せ等によって形成される。 Here, silver, an alloy obtained by adding palladium to silver, tungsten, copper, gold, or the like can be used as the conductor constituting the conductor pattern. The conductor pattern is formed by screen printing using a metal conductor or a combination of a film forming method such as vapor deposition or sputtering and etching.
[0074] また、送信用フィルタ 4及び受信用フィルタ 5に対して直接接続される導体パターン や、 PCB等の外部回路に分波器を搭載する際に接続するための導体パターン (端 子)については、送信用フィルタ 4及び受信用フィルタ 5等の接続端子との接合性の 向上に必要であれば、適宜導体パターンの表面に Ni或いは Au等のめっきを施して も良い。 [0074] Conductor patterns that are directly connected to the transmission filter 4 and the reception filter 5 and conductor patterns (terminals) that are connected when a duplexer is mounted on an external circuit such as a PCB. If necessary for improving the bondability with the connection terminals such as the transmission filter 4 and the reception filter 5, the surface of the conductor pattern may be appropriately plated with Ni or Au.
[0075] 以下、回路基板 800の具体的な例について説明する。  Hereinafter, a specific example of the circuit board 800 will be described.
[0076] 図 4及び図 5は、回路基板 800を構成する各層 La〜Lgにおける導体パターン及び ビアの配置を例示する図である。図 4及び図 5では、回路基板 800の外縁すなわち 誘電体層 Lb, Ld, Lfの外縁との位置関係を明確化するために、回路基板 800の外 縁の位置が破線で示されて!/、る。  FIGS. 4 and 5 are diagrams illustrating the arrangement of conductor patterns and vias in each layer La to Lg constituting the circuit board 800. FIG. 4 and 5, the position of the outer edge of the circuit board 800 is indicated by a broken line in order to clarify the positional relationship with the outer edge of the circuit board 800, that is, the outer edges of the dielectric layers Lb, Ld, and Lf. RU
[0077] 回路基板 800を構成する多層基板は、 3層の誘電体層が積層した構造(3層積層 構造)を有し、多層基板表面に形成された導体パターン(図 4(a))、多層基板裏面に 形成された導体パターン(図 5(c))、誘電体層 Lbと誘電体層 Ldとの層間に形成され た導体パターン(図 4(c))、誘電体層 Ldと誘電体層 Lfとの層間に形成された導体パ ターン(図 5(a))、誘電体層 Lbを挟んで設けられた導体パターン間を電気的に接続 するための誘電体層 Lbを貫通する複数のビア(図 4(b))、誘電体層 Ldを挟んで設け られた導体パターン間を電気的に接続するための誘電体層 Ldを貫通する複数のビ ァ(図 4(d))、及び誘電体層 Lfを挟んで設けられた導体パターン間を電気的に接続 するための誘電体層 Lfを貫通する複数のビア(図 5(b))を備えて!/、る。  [0077] The multilayer substrate constituting the circuit board 800 has a structure in which three dielectric layers are laminated (three-layer laminated structure), and a conductor pattern (Fig. 4 (a)) formed on the surface of the multilayer substrate. Conductor pattern formed on the back side of the multilayer substrate (Fig. 5 (c)), Conductor pattern formed between the dielectric layer Lb and dielectric layer Ld (Fig. 4 (c)), dielectric layer Ld and dielectric layer A conductor pattern (Fig. 5 (a)) formed between the layer Lf and a plurality of layers penetrating through the dielectric layer Lb for electrically connecting the conductor patterns provided across the dielectric layer Lb. Vias (FIG. 4 (b)), a plurality of vias (FIG. 4 (d)) penetrating through the dielectric layer Ld for electrically connecting conductor patterns provided across the dielectric layer Ld, and A plurality of vias (FIG. 5 (b)) penetrating through the dielectric layer Lf for electrically connecting between the conductor patterns provided across the dielectric layer Lf are provided.
[0078] なお、図 4及び図 5では、送信用及び受信用フィルタ 4, 5は図示されていないが、 回路基板 800の上面(+ Z方向の面)が、送信用及び受信用フィルタ 4, 5を搭載する ための面(フィルタ搭載面)となっており、図 4(a)の右方が送信用フィルタ 4のフィルタ 搭載面、図 4(a)の左方が受信用フィルタ 5のフィルタ搭載面となって!/、る。 [0079] なお、送信用及び受信用フィルタ 4, 5が実装されて送信及び受信回路が接続され る前段階の回路基板 800単体の状態では、整合回路 6は、相互に通過周波数帯域 が異なる送信用及び受信用フィルタ 4, 5間のインピーダンスを調整するための線路( 以下「整合回路用線路」とも称する)であり、各信号線路 7〜; 10は、信号を伝送するた めの線路(以下「信号電送用線路」とも称する)であり、更に、信号端子 1 , 2、及び共 通端子 3は、信号を伝送するための端子(以下「信号電送用端子」とも称する)である 4 and FIG. 5, the transmission and reception filters 4 and 5 are not shown, but the upper surface (the surface in the + Z direction) of the circuit board 800 is the transmission and reception filters 4 and 5. The right side of Fig. 4 (a) is the filter mounting surface of the transmission filter 4, and the left side of Fig. 4 (a) is the filter of the reception filter 5. It becomes a mounting surface! [0079] It should be noted that, in the state of the circuit board 800 alone at the stage before the transmission and reception filters 4 and 5 are mounted and the transmission and reception circuits are connected, the matching circuit 6 has a transmission frequency band different from each other. Lines for adjusting the impedance between the trusted and receiving filters 4 and 5 (hereinafter also referred to as “matching circuit lines”). Each of the signal lines 7 to 10 is a line for transmitting a signal (hereinafter referred to as “line for matching circuit”). Further, the signal terminals 1 and 2 and the common terminal 3 are terminals for transmitting signals (hereinafter also referred to as “signal transmission terminals”).
[0080] ここで、図 4及び図 5を参照しつつ、回路基板 800における導体パターン及びビア の接続状態と、回路基板 800に対して送信用及び受信用フィルタ 4, 5が実装されて 送信及び受信回路が接続された際の送信/受信信号の流れについて説明する。 Here, referring to FIG. 4 and FIG. 5, the connection state of the conductor pattern and the via in the circuit board 800 and the transmission and reception filters 4 and 5 are mounted on the circuit board 800 to transmit and A flow of transmission / reception signals when the reception circuit is connected will be described.
[0081] 送信側信号端子 1に対して、導体パターン 14, 27, 41とビア 19, 32, 46とによって 構成される信号線路 7が電気的に接続されており、導体パターン 14は、送信用フィ ルタ 4が電気的に接続される端子として機能する。より詳細には、信号線路 7が、上下 方向(Y軸に沿った方向)を除いて複数の誘電体層 Lb, Ld, Lfによって包囲されて おり、複数の誘電体層 Lb, Ld, Lfによって構成された多層基板の内部において当 該複数の誘電体層 Lb, Ld, Lfを貫通するように複数の誘電体層 Lb, Ld, Lfの最上 層から最下層に渡って形成されている。そして、送信側信号端子 1から入力される送 信用の信号は、信号線路 7を介して送信用フィルタ 4に入力されることになる。  [0081] The signal line 7 composed of the conductor patterns 14, 27, 41 and the vias 19, 32, 46 is electrically connected to the transmission-side signal terminal 1, and the conductor pattern 14 is used for transmission. Filter 4 functions as a terminal to be electrically connected. More specifically, the signal line 7 is surrounded by a plurality of dielectric layers Lb, Ld, Lf except in the vertical direction (the direction along the Y axis), and the plurality of dielectric layers Lb, Ld, Lf A plurality of dielectric layers Lb, Ld, and Lf are formed from the uppermost layer to the lowermost layer so as to penetrate the plurality of dielectric layers Lb, Ld, and Lf in the multilayer substrate thus configured. The transmission signal input from the transmission side signal terminal 1 is input to the transmission filter 4 via the signal line 7.
[0082] また、共通端子 3に対して、導体パターン 12, 25, 40とビア 17, 31 , 45とによって 構成される信号線路 9が電気的に接続されており、導体パターン 12は、送信用フィ ルタ 4が電気的に接続される端子として機能する。より詳細には、信号線路 9が、上下 方向(Y軸に沿った方向)を除いて複数の誘電体層 Lb, Ld, Lfによって包囲されて おり、複数の誘電体層 Lb, Ld, Lfによって構成される多層基板の内部において当該 複数の誘電体層 Lb, Ld, Lfを貫通するように複数の誘電体層 Lb, Ld, Lfの最上層 力、ら最下層に渡って形成されている。そして、送信用フィルタ 4から出力される送信信 号は、信号線路 9と共通端子 3とを介して、アンテナ 400 (図 1)に出力されることにな  [0082] Further, the signal line 9 constituted by the conductor patterns 12, 25, 40 and the vias 17, 31, 45 is electrically connected to the common terminal 3, and the conductor pattern 12 is used for transmission. Filter 4 functions as a terminal to be electrically connected. More specifically, the signal line 9 is surrounded by a plurality of dielectric layers Lb, Ld, Lf except in the vertical direction (the direction along the Y axis), and the plurality of dielectric layers Lb, Ld, Lf The uppermost layer force of the plurality of dielectric layers Lb, Ld, and Lf and the lowermost layer are formed so as to penetrate the plurality of dielectric layers Lb, Ld, and Lf inside the multilayer substrate. The transmission signal output from the transmission filter 4 is output to the antenna 400 (FIG. 1) via the signal line 9 and the common terminal 3.
[0083] 一方、共通端子 3に対して、導体パターン 15, 25, 40とビア 20, 31 , 45とによって 構成される信号線路 10が電気的に接続されており、導体パターン 15は、受信用フィ ルタ 5が電気的に接続される端子として機能する。より詳細には、信号線路 10が、上 下方向(Y軸に沿った方向)を除いて複数の誘電体層 Lb, Ld, Lfによって包囲され ており、複数の誘電体層 Lb, Ld, Lfによって構成される多層基板の内部において当 該複数の誘電体層 Lb, Ld, Lfを貫通するように複数の誘電体層 Lb, Ld, Lfの最上 層から最下層に渡って形成されている。そして、アンテナ 400から入力される受信信 号は共通端子 3と信号線路 10とを介して受信用フィルタ 5に入力されることになる。 [0083] On the other hand, for the common terminal 3, conductor patterns 15, 25, 40 and vias 20, 31, 45 The configured signal line 10 is electrically connected, and the conductor pattern 15 functions as a terminal to which the reception filter 5 is electrically connected. More specifically, the signal line 10 is surrounded by a plurality of dielectric layers Lb, Ld, Lf except for the upper and lower directions (directions along the Y axis), and the plurality of dielectric layers Lb, Ld, Lf Is formed from the uppermost layer to the lowermost layer of the plurality of dielectric layers Lb, Ld, Lf so as to penetrate through the plurality of dielectric layers Lb, Ld, Lf. The reception signal input from the antenna 400 is input to the reception filter 5 through the common terminal 3 and the signal line 10.
[0084] また、受信側信号端子 2に対して、導体パターン 16, 29, 43とビア 21 , 36, 48とに よって構成される信号線路 8が電気的に接続されており、導体パターン 16は、受信 用フィルタ 5が電気的に接続される端子として機能する。より詳細には、信号線路 8が 、上下方向(Y軸に沿った方向)を除いて複数の誘電体層 Lb, Ld, Lfによって包囲さ れており、複数の誘電体層 Lb, Ld, Lfによって構成される多層基板の内部において 当該複数の誘電体層 Lb, Ld, Lfを貫通するように複数の誘電体層 Lb, Ld, Lfの最 上層から最下層に渡って形成されている。そして、受信用フィルタ 5から出力される信 号は、信号線路 8を介して受信側信号端子 2から出力されることになる。  Further, the signal line 8 constituted by the conductor patterns 16, 29, 43 and the vias 21, 36, 48 is electrically connected to the reception side signal terminal 2, and the conductor pattern 16 is The reception filter 5 functions as a terminal to be electrically connected. More specifically, the signal line 8 is surrounded by a plurality of dielectric layers Lb, Ld, Lf except in the vertical direction (the direction along the Y axis), and the plurality of dielectric layers Lb, Ld, Lf Is formed from the top layer to the bottom layer of the plurality of dielectric layers Lb, Ld, and Lf so as to penetrate the plurality of dielectric layers Lb, Ld, and Lf. The signal output from the reception filter 5 is output from the reception-side signal terminal 2 via the signal line 8.
[0085] 共通端子 3に電気的に接続されている整合回路 6は、共通端子 3に対してビア 45 によって電気的に接続される導体パターン 28, 40及びビア 34を含む線路 (整合用 線路)によって構成されている。整合回路 6を構成する導体パターン 28, 40は螺旋 状パターンによって構成されている。より詳細には、整合回路 6が、複数の誘電体層 Lb, Ld, Lfによって包囲されており、複数の誘電体層 Lb, Ld, Lfによって構成され る多層基板の内部において誘電体層 Ldを貫通して形成されている。また、導体バタ ーン 28の一端(螺旋状パターン 40とビア 34によって接続されている側とは反対側の 端部)は、ビア 35によって接地用の導体パターン (接地用パターン) 44に対して電気 的に接続されている。ここで、「接地用の導体」とは「定電圧あるいは基準電圧が与え られる導体」と!/ヽうことあでさる。  The matching circuit 6 electrically connected to the common terminal 3 is a line including conductor patterns 28 and 40 and vias 34 that are electrically connected to the common terminal 3 by vias 45 (matching lines). It is constituted by. The conductor patterns 28 and 40 constituting the matching circuit 6 are constituted by a spiral pattern. More specifically, the matching circuit 6 is surrounded by a plurality of dielectric layers Lb, Ld, and Lf, and the dielectric layer Ld is formed inside the multilayer substrate constituted by the plurality of dielectric layers Lb, Ld, and Lf. It is formed through. One end of the conductor pattern 28 (the end opposite to the side connected by the spiral pattern 40 and the via 34) is connected to the ground conductor pattern (ground pattern) 44 by the via 35. Electrically connected. Here, “grounding conductor” means “a conductor to which a constant voltage or a reference voltage is applied”.
[0086] 回路基板 800の最上部を構成する導体配泉パターン層 Laに含まれる環状電極パ ターン 11は、各々複数のビアによって構成されるビア群 22〜24によって接地用の導 体パターン (接地用パターン) 30に対して電気的に接続されている。接地用パターン 30は、 1組の誘電体層 Lb, Ldの層間に形成され、かつ 2層の誘電体層 Lb, Ldによ つて包囲されており、ビア群 37〜39によって接地用パターン 44に対して電気的に接 続されている。更に、接地用パターン 44は、 1組の誘電体層 Ld, Lfの層間に形成さ れ、かつ 2層の誘電体層 Ld, Lfによって包囲されており、ビア群 49〜51によって回 路基板 800の裏面に設けられた接地用の端子 (接地用端子) 52に対して電気的に 接続されている。 [0086] The annular electrode pattern 11 included in the conductor spring pattern layer La constituting the uppermost part of the circuit board 800 is composed of a conductor pattern for grounding (grounding) by via groups 22 to 24 each including a plurality of vias. Pattern) 30 is electrically connected. Grounding pattern 30 is formed between a pair of dielectric layers Lb and Ld and is surrounded by two dielectric layers Lb and Ld, and is electrically connected to the grounding pattern 44 by the via groups 37 to 39. Connected. Furthermore, the grounding pattern 44 is formed between a pair of dielectric layers Ld and Lf and is surrounded by two dielectric layers Ld and Lf. The circuit board 800 is formed by via groups 49 to 51. It is electrically connected to a grounding terminal (grounding terminal) 52 provided on the back surface of the.
[0087] なお、導体パターン 13, 26, 42とビア 18, 33, 47によって構成される線路は、送 信用フィルタ 4を接地用端子 52に対して電気的に接続するための線路である。  Note that the line constituted by the conductor patterns 13, 26, 42 and the vias 18, 33, 47 is a line for electrically connecting the transmission filter 4 to the grounding terminal 52.
[0088] 回路基板 800の裏面では、図 5 (c)で示すように、導体配線パターン層 Lgのうち、 送信側信号端子 1が図中右下方に配置され、受信側信号端子 2が図中左下方に配 置され、共通端子 3が図中上方の略中央に配置されている。このように回路基板 800 の裏面では、 3つの端子 1〜3が相互に極力離隔されて配置されている。  [0088] On the back surface of the circuit board 800, as shown in FIG. 5 (c), in the conductor wiring pattern layer Lg, the transmission-side signal terminal 1 is arranged on the lower right side in the figure, and the reception-side signal terminal 2 is Arranged at the lower left, the common terminal 3 is arranged at the approximate center in the upper part of the figure. Thus, on the back surface of the circuit board 800, the three terminals 1 to 3 are arranged as far as possible from each other.
[0089] このような線路配置は、信号線路 7 (導体パターン 14, 27, 41とビア 19, 32, 46と によって構成)と整合回路 6 (導体パターン 28, 40とビア 34とによって構成)との間に おけるアイソレーション、信号泉路 8 (導体ノ ターン 16, 29, 43とビア 21 , 36, 48とに よって構成)と整合回路 6との間におけるアイソレーション、信号線路 7と信号線路 8と の間におけるアイソレーションを確保するためのものである。つまり、限られた空間内 において、整合回路 6、信号線路 7、及び信号線路 8の 3つの線路間の距離が、それ ぞれ適正な距離設定となるように工夫されて!/、る。  [0089] Such a line arrangement includes a signal line 7 (configured by conductor patterns 14, 27, 41 and vias 19, 32, 46) and a matching circuit 6 (configured by conductor patterns 28, 40 and via 34). Between signal line 8 (consisting of conductor patterns 16, 29, 43 and vias 21, 36, 48) and matching circuit 6, signal line 7 and signal line 8 This is to ensure isolation between and. In other words, in a limited space, the distance between the three lines of the matching circuit 6, the signal line 7, and the signal line 8 is devised so that the respective distances are set appropriately.
[0090] 更に、回路基板 800では、信号線路 7及び信号線路 8の周囲が、それぞれ、側方よ り接地用パターン 30, 44によって囲まれている。  Further, in the circuit board 800, the signal line 7 and the signal line 8 are surrounded by the grounding patterns 30, 44 from the side.
[0091] より具体的には、導体配線パターン層 Lc (図 4(c))の面内において、接地用パター ン 30が、信号線路 7を構成する導体パターン 27と信号線路 8を構成する導体パター ン 29との間の空間領域、及び導体パターン 27と整合回路 6を構成する導体パターン 28との間の空間領域の双方の空間領域を通るように設けられ、かつ導体パターン 27 を側方より囲む環状の接地用の導体パターンの領域 (接地用パターン領域) 30aを 有するとともに、導体パターン 29と導体パターン 27との間の空間領域、及び導体パ ターン 29と導体パターン 28との間の空間領域の双方の空間領域を通るように設けら れ、かつ導体パターン 29を側方より囲む環状の接地用の導体パターンの領域 (接地 用パターン領域) 30bを有する。なお、導体パターンの領域 30aは、その内縁と導体 パターン 27との間隔力 導体パターン 27の全周にわたって均一であることがよい。こ の場合、導体パターンの領域 30aと導体パターン 27との間に、浮遊容量が発生する のを抑えることができる。導体パターンの領域 30bと導体パターン 29との関係におい ても同様の構成がよい。 More specifically, in the plane of the conductor wiring pattern layer Lc (FIG. 4 (c)), the grounding pattern 30 is composed of the conductor pattern 27 constituting the signal line 7 and the conductor constituting the signal line 8. It is provided so as to pass through both the space area between the pattern 29 and the space area between the conductor pattern 27 and the conductor pattern 28 constituting the matching circuit 6, and the conductor pattern 27 from the side. A space area between the conductor pattern 29 and the conductor pattern 27, and a space area between the conductor pattern 29 and the conductor pattern 28, as well as the surrounding annular conductor pattern area (ground pattern area) 30a. Provided to pass through both spatial areas And an annular grounding conductor pattern region (grounding pattern region) 30b surrounding the conductor pattern 29 from the side. Note that the conductor pattern region 30 a is preferably uniform over the entire circumference of the conductor pattern 27. In this case, stray capacitance can be prevented from occurring between the conductor pattern region 30a and the conductor pattern 27. The same configuration is preferable for the relationship between the conductor pattern region 30b and the conductor pattern 29.
[0092] また、導体配線パターン層 Le (図 5(a))の面内において、接地用パターン 44が、信 号線路 7を構成する導体パターン 41と信号線路 8を構成する導体パターン 43との間 の空間領域、及び導体パターン 41と整合回路 6を構成する導体パターン 40との間の 空間領域の双方の空間領域を通るように設けられ、かつ導体パターン 41を側方より 囲む環状の接地用の導体パターンの領域 (接地用パターン領域) 44aを有するととも に、導体パターン 43と導体パターン 41との間の空間領域、及び導体パターン 43と導 体パターン 40との間の空間領域の双方の空間領域を通るように設けられ、かつ導体 パターン 43を側方より囲む環状の接地用の導体パターンの領域 (接地用パターン領 域) 44bを有する。 [0092] Further, in the plane of the conductor wiring pattern layer Le (Fig. 5 (a)), the grounding pattern 44 includes a conductor pattern 41 constituting the signal line 7 and a conductor pattern 43 constituting the signal line 8. For the grounding of the ring, which is provided so as to pass through both the space area between the space area between the conductor pattern 41 and the conductor pattern 40 constituting the matching circuit 6 and surrounds the conductor pattern 41 from the side. Conductor pattern region (ground pattern region) 44a, and a spatial region between the conductor pattern 43 and the conductor pattern 41 and a spatial region between the conductor pattern 43 and the conductor pattern 40. An annular grounding conductor pattern region (grounding pattern region) 44b is provided so as to pass through the space region and surrounds the conductor pattern 43 from the side.
[0093] 図 6は、図 4 (a)で示したフィルタ搭載面上に実装される弾性表面波素子 900の構 成を例示する上面図である。ここでは、送信用フィルタ 4及び受信用フィルタ 5が同一 基板上に形成されることで弾性表面波素子 900が形成されている。なお、図 6で示さ れる弹性表面波素子 900は、いわゆるラダー型のフィルタ素子によって構成されてい  FIG. 6 is a top view illustrating the configuration of the surface acoustic wave element 900 mounted on the filter mounting surface shown in FIG. 4 (a). Here, the surface acoustic wave element 900 is formed by forming the transmission filter 4 and the reception filter 5 on the same substrate. Note that the inertial surface acoustic wave element 900 shown in FIG. 6 includes a so-called ladder-type filter element.
[0094] 図 6に示すように、弾性表面波素子 900は、主に圧電基板 902の一方主面上に送 信用フィルタ(Txフィルタ) 4と受信用フィルタ(Rxフィルタ) 5とを備えて!/、る。弾性表 面波素子 900では、 Txフィルタ 4と Rxフィルタ 5とを個別に取り囲む環状電極部(環 状導体) 930が設けられている。図 6では、環状電極部 930で囲まれた 2つの領域の うち上方の領域力Txフィルタ 4が設けられた領域、下方の領域が Rxフィルタ 5が設け られた領域を示している。 As shown in FIG. 6, the surface acoustic wave device 900 mainly includes a transmission filter (Tx filter) 4 and a reception filter (Rx filter) 5 on one main surface of the piezoelectric substrate 902! / The elastic surface wave device 900 is provided with an annular electrode portion (annular conductor) 930 that individually surrounds the Tx filter 4 and the Rx filter 5. In FIG. 6, of the two regions surrounded by the annular electrode portion 930, the region where the upper region force Tx filter 4 is provided and the region below the region where the Rx filter 5 is provided are shown.
[0095] Txフィノレタ 4には、 6つの直列腕の共振子(直列共振子) 914a〜914fと 2つの並列 腕の共振子(並列共振子) 915a, 915bとによって構成される複数の励振電極が設 けられ、各励振電極間が接続電極 917によって電気的に接続されている。そして、 T Xフィルタ 4には、入力パッド部 911、アンテナ 400と電気的に接続される出力パッド 部 912、及び接地電極部 913が設けられている。そして、並列共振子 915a, 915b は、それぞれ接地電極部 913に対して電気的に接続されている。 [0095] The Tx finoleta 4 has a plurality of excitation electrodes composed of six series-arm resonators (series resonators) 914a to 914f and two parallel-arm resonators (parallel resonators) 915a and 915b. Setting Each excitation electrode is electrically connected by a connection electrode 917. The TX filter 4 includes an input pad portion 911, an output pad portion 912 that is electrically connected to the antenna 400, and a ground electrode portion 913. The parallel resonators 915a and 915b are electrically connected to the ground electrode portion 913, respectively.
[0096] 一方、 Rxフィルタ 5には、 4つの直歹 IJ共振子 924a〜924dと 4つの並歹 IJ共振子 925 a〜925dとによって構成される複数の励振電極が設けられ、各励振電極間が接続電 極 927によって電気的に接続されている。そして、 Rxフィノレタ 5には、入力パッド部 9 21、出力パッド部 922、及び接地用電極 923が設けられており、並列共振子 925a〜 925dは、それぞれ接地用電極 923に対して電気的に接続されている。更に、接地 用電極 923が、環状電極部 930に対して電気的に接続されている。  [0096] On the other hand, the Rx filter 5 is provided with a plurality of excitation electrodes composed of four direct IJ resonators 924a to 924d and four parallel IJ resonators 925a to 925d, and between the excitation electrodes. Are electrically connected by connecting electrode 927. The Rx finoleta 5 is provided with an input pad portion 921, an output pad portion 922, and a grounding electrode 923. The parallel resonators 925a to 925d are electrically connected to the grounding electrode 923, respectively. Has been. Further, the ground electrode 923 is electrically connected to the annular electrode portion 930.
[0097] このような構成を有する弾性表面波素子 900が、回路基板 800上にフェイスダウン 実装によって搭載されることで、分波器 306が形成される。具体的には、環状電極パ ターン 11に対して環状電極部 930が、入力パッド部 911に対して導体パターン 14が 、出力パッド部 912に対して導体パターン 12が、接地電極部 913に対して導体パタ ーン 13が、入力パッド部 921に対して導体パターン 15が、出力パッド部 922に対し て導体パターン 16が、それぞれ半田バンプを介して電気的に接続される。ここでは、 並列共振子 925a〜925dが、接地用電極 923、環状電極部 930、半田バンプ、環状 電極パターン 11、ビア群 22〜24、接地用パターン 30、ビア群 37〜39、接地用パタ ーン 44、ビア群 49〜51を順次介して接地用端子 52に対して電気的に接続(導通接 続)される。  The surface acoustic wave element 900 having such a configuration is mounted on the circuit board 800 by face-down mounting, whereby the duplexer 306 is formed. Specifically, the annular electrode portion 930 is associated with the annular electrode pattern 11, the conductor pattern 14 is associated with the input pad portion 911, the conductor pattern 12 is associated with the output pad portion 912, and the ground electrode portion 913 is associated with. The conductor pattern 13 is electrically connected to the input pad portion 921 via the solder pattern 15 and the conductor pattern 15 is electrically connected to the output pad portion 922 via the solder bump. Here, the parallel resonators 925a to 925d are the grounding electrode 923, the annular electrode portion 930, the solder bump, the annular electrode pattern 11, the via group 22 to 24, the grounding pattern 30, the via group 37 to 39, and the grounding pattern. Are electrically connected (conductively connected) to the grounding terminal 52 through the via 44 and the via groups 49 to 51 sequentially.
[0098] 以上のように、第 1実施形態に係る回路基板 800では、整合回路 6が、複数の誘電 体層 Lb, Ld, Lfによって包囲された多層基板内部に配置される。そして、信号線路 7及び信号線路 8のそれぞれが、複数の誘電体層 Lb, Ld, Lfによって包囲された多 層基板内部に配置され、かつ他方の信号線路 7, 8ならびに整合回路 6との間を通り かつ周囲を囲む接地用の導体(ここでは、接地用パターン領域 30a, 30b, 44a, 44 b)が設けられている。  As described above, in the circuit board 800 according to the first embodiment, the matching circuit 6 is disposed inside the multilayer board surrounded by the plurality of dielectric layers Lb, Ld, and Lf. Each of the signal line 7 and the signal line 8 is disposed inside the multilayer substrate surrounded by the plurality of dielectric layers Lb, Ld, and Lf, and between the other signal lines 7 and 8 and the matching circuit 6. A grounding conductor (here, grounding pattern areas 30a, 30b, 44a, 44b) is provided that passes through and surrounds the periphery.
[0099] このため、回路基板 800内部の各線路間(整合回路 6、信号線路 7、及び信号線路  [0099] Therefore, between each line in the circuit board 800 (matching circuit 6, signal line 7, and signal line
8の各線路間)が電気的に遮蔽されるとともに、信号線路 7及び信号線路 8と回路基 板 800の外部との間も電気的に遮蔽される。したがって、回路基板 800内部における 電気的な干渉及び回路基板 800の外部との間における電気的な干渉を低減するこ とができる。すなわち、回路基板 800内部におけるアイソレーション特性、並びに回 路基板 800外部との間におけるアイソレーション特性を向上させることができる。 8 between each line) and the signal lines 7 and 8 and the circuit board. The outside of the plate 800 is also electrically shielded. Therefore, electrical interference inside the circuit board 800 and electrical interference between the outside of the circuit board 800 can be reduced. That is, the isolation characteristics inside the circuit board 800 and the isolation characteristics between the outside of the circuit board 800 can be improved.
[0100] また、信号線路 7, 8の周囲を囲む接地用の導体を、誘電体層間に形成された導体 ノ ターンによって形成するような構成を採用すると、容易に接地用の導体を形成する こと力 Sでさる。 [0100] If a configuration in which the grounding conductor surrounding the signal lines 7 and 8 is formed by the conductor pattern formed between the dielectric layers, the grounding conductor can be easily formed. Touch with force S.
[0101] 更に、回路基板 800を搭載した分波器 306はアイソレーション特性に優れるため、 当該分波器 306を搭載した通信装置 100では、良好な通信を行うことができる。  Furthermore, since the duplexer 306 on which the circuit board 800 is mounted has excellent isolation characteristics, the communication device 100 on which the duplexer 306 is mounted can perform good communication.
[0102] <第 2実施形態〉  [0102] <Second Embodiment>
上述した第 1実施形態に係る回路基板 800では、信号線路 7, 8が、接地用パター ン 30, 44によって囲まれた。これに対して、第 2実施形態に係る回路基板 800Aでは 、信号線路 7, 8を囲むような位置に接地用パターン 30, 44間を電気的に接続するビ ァを設けることで、更にアイソレーション特性の向上を図っている。  In the circuit board 800 according to the first embodiment described above, the signal lines 7 and 8 are surrounded by the grounding patterns 30 and 44. On the other hand, in the circuit board 800A according to the second embodiment, further isolation is provided by providing a via for electrically connecting the grounding patterns 30 and 44 at positions surrounding the signal lines 7 and 8. The characteristics are improved.
[0103] 第 2実施形態に係る通信装置 100Aは、適宜ビアを追加配置した以外は、第 1実施 形態に係る通信装置 100と同様な構成を有する。以下、第 2実施形態に係る通信装 置 100Aのうち、第 1実施形態に係る通信装置 100と同様な部分については同じ符 号を付して説明を省略しつつ、第 1実施形態に係る通信装置 100と異なる回路基板 800Aの構成につ!/、て主に説明する。  [0103] The communication device 100A according to the second embodiment has the same configuration as the communication device 100 according to the first embodiment except that vias are additionally arranged as appropriate. Hereinafter, in the communication device 100A according to the second embodiment, the same parts as those of the communication device 100 according to the first embodiment are denoted by the same reference numerals and the description thereof is omitted, while the communication according to the first embodiment is performed. The configuration of the circuit board 800A different from the device 100 will be mainly described.
[0104] 図 7及び図 8は、第 2実施形態に係る回路基板 800Aを構成する各層 La〜Lgにお ける導体パターン及びビアの配置を例示する図である。  FIGS. 7 and 8 are diagrams illustrating the arrangement of conductor patterns and vias in the respective layers La to Lg constituting the circuit board 800A according to the second embodiment.
[0105] 図 7及び図 8に示すように、回路基板 800Aでは、導体パターン 14, 27, 41とビア 1 9, 32, 46とによって構成される信号線路 7の周囲に接地用の複数のビアからなるビ ァ群 53a, 53bカ設けられている。また、導体ノ ターン 16, 29, 43とビア 21 , 36, 48 とによって構成される信号線路 8の周囲に接地用の複数のビアからなるビア群 54a, 54bが設けられている。  As shown in FIGS. 7 and 8, in the circuit board 800A, a plurality of vias for grounding are provided around the signal line 7 constituted by the conductor patterns 14, 27, 41 and the vias 19, 32, 46. There are 53a and 53b via groups. In addition, via groups 54a and 54b including a plurality of grounding vias are provided around the signal line 8 constituted by the conductor patterns 16, 29, 43 and the vias 21, 36, 48.
[0106] 具体的には、図 7 (d)に示すように、信号線路 7と信号線路 8並びに整合回路 6との 間を通るように設けられ、かつ信号線路 7の周囲を囲む 2つの環状の接地用パターン 領域 30a, 44aの間を電気的に接続する接地用のビア群 53a, 53bが設けられている 。また、信号線路 8と信号線路 7並びに整合回路 6との間を通るように設けられ、かつ 信号線路 8の周囲を囲む 2つの環状の接地用パターン領域 30b, 44bの間を電気的 に接続する接地用のビア群 54a, 54bが設けられている。 Specifically, as shown in FIG. 7 (d), two annular loops are provided so as to pass between the signal line 7, the signal line 8, and the matching circuit 6, and surround the signal line 7. Grounding pattern Grounding via groups 53a and 53b for electrically connecting the regions 30a and 44a are provided. In addition, two annular grounding pattern regions 30b and 44b that are provided so as to pass between the signal line 8, the signal line 7, and the matching circuit 6 and that surround the signal line 8 are electrically connected. Grounding via groups 54a and 54b are provided.
[0107] より詳細には、信号線路 7を構成するビア 32と、信号線路 8を構成するビア 36なら びに整合回路 6を構成するビア 34との間の空間領域において環状に配置された複 数のビアによって構成される接地用のビア群 53a, 53bが設けられている。また、信 号線路 8を構成するビア 36と、信号線路 7を構成するビア 32ならびに整合回路 6を 構成するビア 34との間の空間領域において環状に配置された複数のビアによって構 成された接地用のビア群 54a, 54bが設けられている。  More specifically, a plurality of annularly arranged in a spatial region between the via 32 constituting the signal line 7 and the via 36 constituting the signal line 8 and the via 34 constituting the matching circuit 6. A grounding via group 53a, 53b is provided. In addition, the via 36 constituting the signal line 8, the via 32 constituting the signal line 7 and the via 34 constituting the matching circuit 6 are constituted by a plurality of vias arranged in a ring shape. Grounding via groups 54a and 54b are provided.
[0108] このように、回路基板 800Aでは、信号線路 7, 8の周囲をそれぞれ接地用の導体 で囲むために新たに接地用パターン領域 30a, 30b, 44a, 44bを設けたことで、新 たに接地用のビアを設けることができる領域が増加したことを利用して、信号線路 7, 8の周囲をそれぞれ囲む接地用のビア群 53a, 53b, 54a, 54bが新たに設けられて いる。また、接地用パターン領域 30a, 30bを設けたことで、環状電極パターン 11 (図 7(a))と導体パターン 30 (図 7(c))との間を電気的に接続するビア群 55b, 56b (図 7(b ))あ新たに設けることカでさた。  As described above, the circuit board 800A is newly provided with the ground pattern areas 30a, 30b, 44a, and 44b so as to surround the signal lines 7 and 8 with the ground conductors. The ground vias 53a, 53b, 54a and 54b surrounding the signal lines 7 and 8 are newly provided by utilizing the fact that the area where the ground via can be provided is increased. In addition, by providing the ground pattern areas 30a and 30b, via groups 55b, which electrically connect the annular electrode pattern 11 (FIG. 7 (a)) and the conductor pattern 30 (FIG. 7 (c)), 56b (Fig. 7 (b)) Newly installed.
[0109] 図 9は、第 2実施形態に係る分波器 306Aの等価回路を示す図である。ここでは、 接地用のビア群 53a, 53b, 54a, 54bカ新たに設けられたことで、図 9に示すように、 受信用フィルタ 5の並列共振子 925a〜925dが接地される配線経路 (すなわち接地 用電極 923から接地用端子 52へ向けた配線経路)において、電気的に並列接続さ れる配線経路が増加する。このため、接地用電極 923から接地用端子 52に向けた 配線経路(回路)のインダクタンスが低下する。  FIG. 9 is a diagram showing an equivalent circuit of the duplexer 306A according to the second embodiment. Here, the ground via group 53a, 53b, 54a, 54b is newly provided, and as shown in FIG. 9, the wiring path (that is, the parallel resonators 925a to 925d of the reception filter 5 are grounded) In the wiring path from the grounding electrode 923 to the grounding terminal 52), the number of wiring paths that are electrically connected in parallel increases. For this reason, the inductance of the wiring path (circuit) from the grounding electrode 923 to the grounding terminal 52 decreases.
[0110] 以上のように、第 2実施形態に係る回路基板 800Aでは、信号線路 7, 8の周囲が、 複数組の誘電体層間に形成された複数の接地用パターン領域 30a, 30b, 44a, 44 bと、複数の接地用パターン領域 30a, 30b, 44a, 44bによって挟まれた誘電体層 L dを貫通し、かつ複数の接地用パターン領域 30a, 30b, 44a, 44bを電気的に接続 する導体(ここでは、ビア群 53a, 53b, 54a, 54b)とによって囲まれている。 [0111] このような構成を採用すると、回路基板 800A内部の線路間(整合回路 6、信号線 路 7、及び信号線路 8の各線路間)が電気的に遮蔽されるとともに、回路基板 800A 外部と、接地用の導体(ここでは、接地用パターン領域 30a, 30b, 44a, 44b、ビア 群 53a, 53b, 54a, 54b)によって囲まれた信号線路 7, 8との間も電気的に遮蔽され る。したがって、回路基板内部における電気的な干渉及び回路基板外部との間にお ける電気的な干渉を更に低減することができる。その結果、回路基板内部におけるァ イソレーシヨン特性、並びに回路基板外部との間におけるアイソレーション特性を更 に向上させること力 Sでさる。 [0110] As described above, in the circuit board 800A according to the second embodiment, the periphery of the signal lines 7 and 8 includes a plurality of ground pattern regions 30a, 30b, 44a, which are formed between a plurality of sets of dielectric layers. 44 b and a plurality of ground pattern regions 30a, 30b, 44a, 44b are passed through the dielectric layer Ld sandwiched between them, and the plurality of ground pattern regions 30a, 30b, 44a, 44b are electrically connected. It is surrounded by conductors (here, via groups 53a, 53b, 54a, 54b). [0111] By adopting such a configuration, the circuit board 800A is electrically shielded between the lines inside the circuit board 800A (between the matching circuit 6, the signal line 7 and the signal line 8). And the signal lines 7 and 8 surrounded by the grounding conductor (here, grounding pattern areas 30a, 30b, 44a and 44b, and via groups 53a, 53b, 54a and 54b) are also electrically shielded. The Therefore, electrical interference inside the circuit board and electrical interference between the outside of the circuit board can be further reduced. As a result, the force S can further improve the isolation characteristics inside the circuit board and the isolation characteristics with the outside of the circuit board.
[0112] また、受信側の信号線路 8の周囲に接地用パターン領域 30b, 44bが設けられたこ とで、信号線路 8の周囲において、複数の接地用パターン領域 30b, 44bの間に誘 電体層 Ldを貫通する導体であるビアを配置する事ができる領域 (位置)が増加する。 そして、受信用及び送信用フィルタのうち、相対的に高い通過周波数帯域を有する フィルタ(一般的には、受信用フィルタ)の並列共振子と接地用端子との間を電気的 に接続する線路 (すなわち、回路基板の導体パターン及び誘電体層を貫通するビア 等によって構成される導体)において生じるインダクタンスの値が小さくなれば、分波 器のうちの相対的に高い通過周波数帯域を有するフィルタの低周波側の帯域外減 衰量が大きくなる性質が存在することが知られている。  [0112] Further, since the ground pattern areas 30b and 44b are provided around the signal line 8 on the receiving side, the dielectric is provided between the plurality of ground pattern areas 30b and 44b around the signal line 8. The area (position) where a via that is a conductor penetrating the layer Ld can be arranged is increased. Of the reception and transmission filters, a line that electrically connects between the parallel resonator of the filter having a relatively high pass frequency band (generally, the reception filter) and the ground terminal ( In other words, if the inductance value generated in the conductor pattern of the circuit board and vias penetrating the dielectric layer is reduced, the filter having a relatively high pass frequency band in the duplexer is reduced. It is known that there is a property of increasing the out-of-band attenuation on the frequency side.
[0113] この性質に従えば、並列共振子に対して電気的に接続された接地用パターン 30, 44間を誘電体層を貫通して電気的に接続する導体であるビア(ここでは、ビア群 53a , 53b, 54a, 54b)カより多く酉己置されることで、ビア群 53a, 53b, 54a, 54b力並歹 lj の接地用の線路を形成して、並列共振子 925a〜925dと接地用端子 52との間のィ ンダクタンスの値が小さくなる。このため、受信用フィルタ 5の帯域外減衰量を増大さ せること力 Sできる。すなわち、ここでは、ビア群 53a, 53b, 54a、 54bを新しく設けるこ とができたことがインダクタンスの値の低減に寄与していると言える。  [0113] According to this property, vias (here, vias) that are conductors that electrically connect the ground patterns 30 and 44 electrically connected to the parallel resonators through the dielectric layer. Group 53a, 53b, 54a, 54b), and by forming a grounding line for via group 53a, 53b, 54a, 54b force parallel lj, parallel resonators 925a-925d and The inductance value with respect to the grounding terminal 52 decreases. For this reason, it is possible to increase the out-of-band attenuation amount of the reception filter 5. That is, it can be said that the fact that the via groups 53a, 53b, 54a, 54b can be newly provided contributes to the reduction of the inductance value.
[0114] したがって、回路基板 800Aにおいて、信号線路 7, 8の周囲をそれぞれ囲むように 、多数の接地用のビアが設けられることで、アイソレーション特性の更なる向上ととも に、受信用フィルタ 5の帯域外減衰量の増大による通信装置 100Aの通信特性の更 なる向上を図ることができる。 [0115] <変形例〉 [0114] Therefore, in the circuit board 800A, by providing a large number of grounding vias so as to surround the signal lines 7 and 8, respectively, the isolation filter is further improved and the reception filter 5 is provided. The communication characteristics of communication apparatus 100A can be further improved by increasing the out-of-band attenuation. [0115] <Modification>
なお、本発明は上述の実施の形態に限定されるものではなぐ本発明の要旨を逸 脱しな!/、範囲にお!/、て種々の変更、改良等が可能である。  It should be noted that the present invention is not limited to the above-described embodiments, and the gist of the present invention is not deviated from / within the scope of the present invention, and various changes and improvements can be made.
[0116] ◎例えば、上記第 1実施形態では、信号線路 7, 8の双方が、周囲を接地用パター ン領域 30a, 30b, 44a, 44bによって囲まれたが、これに限られず、例えば、信号線 路 7, 8のうちの少なくとも一方の信号線路の周囲力 相互に隣接した 1組以上の誘 電体層の層間に設けられた 1以上の接地用の導体 (例えば、導体パターン領域 30a , 30b, 44a, 44b等)によって囲まれれば、第 1実施形態と同様な効果を奏する。  [0116] For example, in the first embodiment, the signal lines 7 and 8 are both surrounded by the ground pattern areas 30a, 30b, 44a, and 44b. Peripheral force of at least one signal line of lines 7 and 8 One or more grounding conductors (for example, conductor pattern regions 30a, 30b) provided between one or more dielectric layers adjacent to each other , 44a, 44b, etc.), the same effects as in the first embodiment can be obtained.
[0117] 但し、アイソレーション特性をより向上させる観点から言えば、信号線路 7, 8の双方 の周囲が、より多くの相互に隣接した組の誘電体層の層間にそれぞれ形成された複 数の接地用の導体(例えば、導体パターン領域 30a, 30b, 44a, 44b)によって囲ま れる方が好ましい。  [0117] However, from the viewpoint of further improving the isolation characteristics, the periphery of both of the signal lines 7 and 8 is a plurality of multiple dielectric layers formed between the layers of the adjacent dielectric layers. It is preferable to be surrounded by a grounding conductor (for example, conductor pattern regions 30a, 30b, 44a, 44b).
[0118] ◎また、上記第 2実施形態では、接地用パターン領域 30a, 44a間を接地用のビア 群 53a, 53bによって電気的に接続し、接地用パターン領域 30b, 44b間を接地用の ビア群 54a, 54bによって電気的に接続した力 これに限られず、接地用パターン領 域 30a, 44a間、及び接地用パターン領域 30b, 44b間のうちの少なくとも一方をビア 群によって電気的に接続するようにしても、第 2実施形態と同様な効果を得ることがで きる。  [0118] In the second embodiment, the ground pattern areas 30a and 44a are electrically connected by the ground via groups 53a and 53b, and the ground pattern areas 30b and 44b are grounded vias. Forces electrically connected by the groups 54a and 54b Not limited to this, so that at least one of the ground pattern areas 30a and 44a and the ground pattern areas 30b and 44b is electrically connected by the via group. Even so, the same effect as in the second embodiment can be obtained.
[0119] 但し、アイソレーション特性をより向上させる観点、及びフィルタの帯域外減衰量を より増大させる観点から言えば、接地用パターン領域 30a, 44a間、及び接地用バタ ーン領域 30b, 44b間の双方を、より多くのビアによって電気的に接続する方が好ま しい。更に、多層基板を構成する誘電体層が 4層以上である場合には、より多くの相 互に隣接した複数組の誘電体層の層間にそれぞれ形成され、かつ各信号線路 7, 8 を囲む複数の接地用パターン領域力 より多くのビアによって電気的に接続される方 が好ましい。  [0119] However, from the viewpoint of further improving the isolation characteristics and from the viewpoint of further increasing the out-of-band attenuation of the filter, between the ground pattern areas 30a and 44a and between the ground pattern areas 30b and 44b. It is preferable to connect both of them electrically with more vias. Further, when there are four or more dielectric layers constituting the multilayer substrate, they are formed between a plurality of dielectric layers adjacent to each other and surround each signal line 7 and 8. More than one ground pattern area force It is preferable to be electrically connected by more vias.
[0120] ◎また、上記実施形態では、信号線路 7, 8を環状の接地用パターン領域 30a, 30 b, 44a, 44bによって囲ん 力 環状の接地用ノ ターン領域 30a, 30b, 44a, 44b については、接地用の電気的な接続を確保できる範囲内で、適宜スリット等が設けら れても構わない。 [0120] In the above embodiment, the signal lines 7 and 8 are surrounded by the annular ground pattern areas 30a, 30b, 44a, and 44b. For the annular ground pattern areas 30a, 30b, 44a, and 44b, As long as electrical connection for grounding can be secured, slits etc. are provided as appropriate. It does not matter.
[0121] また、信号線路 7, 8を囲む導体パターン領域 30a, 30b, 44a, 44bの形状は環状 である必要性はなぐ信号線路 7や信号線路 8の周囲を囲みかつ他方の信号線路 7 , 8ならびに整合回路 6との間を通るように設けられた接地用の導体パターンであれ ば、種々の形状のものを採用することができる。  [0121] The shape of the conductor pattern regions 30a, 30b, 44a, 44b surrounding the signal lines 7, 8 is not necessarily circular, and surrounds the signal line 7 and the signal line 8 and the other signal line 7, As long as the conductor pattern for grounding is provided so as to pass between 8 and the matching circuit 6, those of various shapes can be adopted.
[0122] ◎また、上記実施形態では、信号線路 7, 8の周囲を囲む導体が、誘電体層の層間 に形成された接地用の導体パターン及びビアによって構成されたが、これに限られ ず、誘電体の多層膜を貫通する接地用の導体であれば良い。  [0122] In the above embodiment, the conductor surrounding the periphery of the signal lines 7 and 8 is constituted by the grounding conductor pattern and via formed between the dielectric layers. However, the present invention is not limited to this. Any grounding conductor that penetrates the dielectric multilayer film may be used.
[0123] ◎また、上記実施形態では、整合回路 6が、 2層の螺旋状の導体パターン 28, 40 によって構成された力 S、これに限られず、例えば、所望のサイズやインダクタンスの値 が得られる場合には、 1層又は 3層以上の導体パターン等によって構成されても良い [0123] In the above embodiment, the matching circuit 6 is not limited to the force S formed by the two layers of the spiral conductor patterns 28, 40. For example, a desired size or inductance value can be obtained. May be composed of one or three or more layers of conductor patterns, etc.
Yes
[0124] ◎また、上記第 2実施形態では、送信用及び受信用フィルタ 4, 5のうち、受信用フ ィルタ 5の方が相対的に高い通過周波数帯域を有していた力 これに限られず、種々 の異なる規格等に従って、送信用フィルタ 4の方が相対的に高い通過周波数帯域を 有するようにしても良い。このとき、第 2実施形態に係る受信用フィルタ 5と同様に、送 信用フィルタ 4の並列共振子を接地用端子 52に対して電気的に接続するための線 路のインダクタンスをより低減することで、送信用フィルタ 4の帯域外減衰量を増大さ せること力 Sでさる。  [0124] Also, in the second embodiment, of the transmission and reception filters 4 and 5, the reception filter 5 has a relatively high pass frequency band. The transmission filter 4 may have a relatively high pass frequency band in accordance with various different standards. At this time, similarly to the reception filter 5 according to the second embodiment, the inductance of the line for electrically connecting the parallel resonator of the transmission filter 4 to the grounding terminal 52 is further reduced. Increase the out-of-band attenuation of the transmission filter 4 with the force S.
[0125] ◎また、上記第 2実施形態では、ラダー型フィルタの並列共振子 925a〜925dを接 地用端子 52に対して電気的に接続する線路のインダクタンスを低減することにより、 フィルタの帯域外減衰量を増大させる例を挙げて説明したが、これに限られず、例え ば、いわゆる DMSフィルタに並列共振子を設ける等、並列腕に共振子を有するフィ ルタ、すなわち並列腕の共振子(並列共振子)を有するフィルタであれば、当該並列 共振子を接地用端子に対して電気的に接続する線路のインダクタンスを低減するこ とで、フィルタの帯域外減衰量を増大させることができる。  [0125] Also, in the second embodiment described above, by reducing the inductance of the line that electrically connects the parallel resonators 925a to 925d of the ladder filter to the ground terminal 52, the out-of-band filter Although an example of increasing the amount of attenuation has been described, the present invention is not limited to this. For example, a filter having a resonator in a parallel arm, such as providing a parallel resonator in a so-called DMS filter, that is, a parallel arm resonator (parallel In the case of a filter having a resonator, the out-of-band attenuation of the filter can be increased by reducing the inductance of the line that electrically connects the parallel resonator to the ground terminal.
実施例  Example
[0126] (実施例) 実施例として、上記第 1実施形態に係る回路基板 800を用いた分波器 306、及び 上記第 2実施形態に係る回路基板 800Aを用いた分波器 306Aと同様な構成を有す る 2種類の分波器を作製した。なお、分波器 306に相当するものを実施例 1、分波器 306Aに相当するものを実施例 2とした。 [Example] As an example, there are two types having the same configuration as the duplexer 306 using the circuit board 800 according to the first embodiment and the duplexer 306A using the circuit board 800A according to the second embodiment. A duplexer was prepared. A device corresponding to the duplexer 306 was designated as Example 1, and a device corresponding to the duplexer 306A was designated as Example 2.
[0127] つまり、実施例 1に係る回路基板 800として、整合回路 6が、複数の誘電体層によつ て包囲された多層膜内部に配置されるとともに、信号線路 7, 8の双方が、複数の誘 電体層によって包囲された多層膜内部に配置され、かつ他方の信号線路 7, 8ならび に整合回路 6との間を通る接地用パターン領域 30a, 30b, 44a, 44bによって囲ま れたものを用いた。 That is, as the circuit board 800 according to the first embodiment, the matching circuit 6 is disposed inside the multilayer film surrounded by the plurality of dielectric layers, and both the signal lines 7 and 8 are Arranged inside the multilayer film surrounded by a plurality of dielectric layers and surrounded by ground pattern areas 30a, 30b, 44a, 44b passing between the other signal lines 7, 8 and the matching circuit 6. A thing was used.
[0128] また、実施例 2に係る回路基板 800Aとして、整合回路 6が、複数の誘電体層によつ て包囲された多層膜内部に配置されるとともに、信号線路 7, 8の双方が、複数の誘 電体層によって包囲された多層膜内部に配置され、かつ他方の信号線路 7, 8ならび に整合回路 6との間を通る接地用パターン領域 30a, 30b, 44a, 44bと、当該接地 用パターン領域 30a, 30b, 44a, 44bの間を電気的に接続する接地用のビア群 53a , 53b, 54a, 54bとによって囲まれたものを用いた。  Further, as the circuit board 800A according to the second embodiment, the matching circuit 6 is disposed inside the multilayer film surrounded by the plurality of dielectric layers, and both of the signal lines 7 and 8 are Ground pattern areas 30a, 30b, 44a, 44b, which are arranged inside a multilayer film surrounded by a plurality of dielectric layers and pass between the other signal lines 7, 8 and the matching circuit 6, and the ground What was surrounded by ground via groups 53a, 53b, 54a, 54b that electrically connect the pattern areas 30a, 30b, 44a, 44b for use was used.
[0129] 分波器 306, 306Aにおいては、圧電基板上に IDT (Inter Digital Transducer)電 極及び反射器電極を備えた共振器と、当該各共振器間を接続する配線電極と、回 路基板に接続するための接続端子とが形成された弾性表面波フィルタ(弾性表面波 素子) 900 (図 6)を用いた。  [0129] In the duplexers 306 and 306A, a resonator including an IDT (Inter Digital Transducer) electrode and a reflector electrode on a piezoelectric substrate, a wiring electrode connecting the resonators, and a circuit substrate A surface acoustic wave filter (surface acoustic wave element) 900 (Fig. 6) in which a connection terminal for connection to the substrate was formed was used.
[0130] ここで、弾性表面波素子 900を使用した分波器 306, 306A (実施例 1 , 2)の製造 について説明する。  Here, the manufacture of the duplexers 306 and 306A (Examples 1 and 2) using the surface acoustic wave element 900 will be described.
[0131] 弾性表面波素子 900の製造については、まず、タンタル酸リチウム(LiTaO )製の 圧電基板を用い、当該圧電基板の主面上に厚みが 6nmの Ti薄膜を形成し、当該 Ti 薄膜上に厚さが 125nmの A1— Cu薄膜を形成して、この Ti薄膜及び A1— Cu薄膜を 交互に各 3層ずつ積層することで、合計 6層の Ti/Al— Cu積層膜を形成した。  [0131] To manufacture the surface acoustic wave device 900, first, a piezoelectric thin film made of lithium tantalate (LiTaO) was used, and a Ti thin film having a thickness of 6 nm was formed on the main surface of the piezoelectric substrate. An A1-Cu thin film with a thickness of 125 nm was formed on this, and this Ti thin film and A1-Cu thin film were alternately laminated in three layers to form a total of six Ti / Al-Cu laminated films.
[0132] 次に、レジスト塗布装置によって厚さが約 0. 5 mのフォトレジストを塗布した。そし て、縮小投影露光装置 (ステッパー)等を用いて、図 6で示した共振器や信号線、及 びパッド電極等となるフォトレジストのパターンを形成した。受信用フィルタにおけるァ ンテナ側に最も近い並列共振子についても、この工程でフォトレジストのパターンが 形成される。更に、現像装置によって不要部分のフォトレジストをアルカリ現像液で溶 解させた。 [0132] Next, a photoresist having a thickness of about 0.5 m was applied by a resist coating apparatus. Then, using a reduction projection exposure apparatus (stepper) or the like, the photoresist pattern to be the resonator, signal line, pad electrode, etc. shown in FIG. 6 was formed. In the filter for reception The photoresist pattern is also formed in this process for the parallel resonator closest to the antenna. Furthermore, unnecessary portions of the photoresist were dissolved with an alkali developer by a developing device.
[0133] その次に、 RIE (Reactive Ion Etching)装置によって図 6で示した電極パターンを形 成した。そして、電極パターンの所定の領域上に保護膜を作製した。ここでは、 CVD (Chemical Vapor D印 osition)装置によって、電極パターン及び圧電基板の主面上に 厚さが約 15nmの SiO膜を形成した。  [0133] Next, the electrode pattern shown in Fig. 6 was formed by a RIE (Reactive Ion Etching) apparatus. And the protective film was produced on the predetermined area | region of the electrode pattern. Here, an SiO film having a thickness of about 15 nm was formed on the electrode pattern and the main surface of the piezoelectric substrate by a CVD (Chemical Vapor D-marked osition) apparatus.
[0134] 更に、フォトリソグラフィによってフォトレジストのパターユングを行ない、 RIE装置等 でフリップチップ用の電極部(入出力電極、接地電極及びパッド電極)を覆って!/、る S ΪΟ膜のエッチングを行った。そして、スパッタリング装置を使用して、 SiO膜を除去し た部分に Cr層、 Ni層、 Au層を積層してなる積層電極を成膜した。このときの積層電 極の膜厚は約 1 μ m、 Cr層、 Ni層、及び Au層の厚さをそれぞれ 0· 01 m、 1 m、 及び 0. 2 mとした。その後、フォトレジスト及び積層電極の不要箇所をリフトオフ法 によって同時に除去し、積層電極が形成された部分を、フリップチップ用のバンプを 電気的に接続するためのフリップチップ用の電極部とした。そして、圧電基板のダイ シング線に沿ってダイシング加工を施すことで、各弾性表面波素子 900を構成する チップに分割した。  [0134] Further, the photoresist is patterned by photolithography, and the flip chip electrode portion (input / output electrode, ground electrode and pad electrode) is covered with an RIE apparatus or the like! /, And the S film is etched. went. Then, using a sputtering apparatus, a laminated electrode was formed by laminating a Cr layer, a Ni layer, and an Au layer on the portion from which the SiO film was removed. At this time, the thickness of the laminated electrode was about 1 μm, and the thicknesses of the Cr layer, the Ni layer, and the Au layer were set to 0.01 m, 1 m, and 0.2 m, respectively. Thereafter, unnecessary portions of the photoresist and the laminated electrode were simultaneously removed by a lift-off method, and the portion where the laminated electrode was formed was used as a flip chip electrode portion for electrically connecting the flip chip bump. Then, by dicing along the dicing lines of the piezoelectric substrate, the surface acoustic wave element 900 was divided into chips.
[0135] 回路基板 800, 800Aの製造については、まず、セラミックス等の金属酸化物と有 機バインダとを有機溶剤等で均質混練したスラリーをシート状に成型したグリーンシ ートを作製した。そして、複数枚のグリーンシートに対して所望の導体パターン及びビ ァを形成した後に、複数枚のグリーンシートを積層して圧着することによって多層膜 を作製し、焼成することにより複数の回路基板 800, 800Aが集まった回路基板 (集 合回路基板)を作製した。集合回路基板に設けられた導体パターン等に用いられる 材料としては銀とガラスとを主成分としたものを用い、合計 3層の誘電体層とその表裏 面及び層間に形成された導体パターンを備えた集合回路基板を作製した。  [0135] Regarding the production of the circuit boards 800 and 800A, first, green sheets were produced by molding a slurry in which a metal oxide such as ceramics and an organic binder were homogeneously kneaded with an organic solvent or the like into a sheet. Then, after forming desired conductor patterns and vias on a plurality of green sheets, a plurality of green sheets are laminated and pressure-bonded to produce a multilayer film, and fired to produce a plurality of circuit boards 800. , 800A gathered circuit board (integrated circuit board). The material used for the conductor pattern, etc. provided on the collective circuit board is composed mainly of silver and glass, and has a total of three dielectric layers, conductor patterns formed on the front and back surfaces, and between the layers. An assembled circuit board was prepared.
[0136] 弾性表面波素子 900と集合回路基板とを電気的に接続する工程については、まず 導体配線パターン層 La (図 4(a),図 7(a))の導体パターン 11〜; 16の上に導電性を有 する材料 (導電材)を印刷した。この導電材としては半田を使用した。 [0137] そして、弾性表面波素子 900をフリップチップ実装装置によって、弾性表面波素子 900の電極形成面を下面にして集合回路基板上に仮接着した。この仮接着は Nガ ス雰囲気中で行った。更に、 Nガス雰囲気中でリフローを行ない、半田を溶融するこ とにより、弾性表面波素子 900と集合回路基板上とを接着し、気密封止を施した。 [0136] Regarding the process of electrically connecting the surface acoustic wave element 900 and the collective circuit board, first, the conductor patterns 11 to 16 of the conductor wiring pattern layer La (Figs. 4 (a) and 7 (a)); A conductive material (conductive material) was printed on top. Solder was used as the conductive material. [0137] Then, the surface acoustic wave element 900 was temporarily bonded to the collective circuit board by a flip chip mounting apparatus with the electrode forming surface of the surface acoustic wave element 900 as the bottom surface. This temporary bonding was performed in an N gas atmosphere. Further, by performing reflow in an N gas atmosphere and melting the solder, the surface acoustic wave element 900 and the collective circuit board were bonded and hermetically sealed.
[0138] そして、弾性表面波素子 900が接着された集合回路基板に樹脂を塗布し、 Nガス 雰囲気中でベータを行なうことで、弾性表面波素子 900を樹脂によって封止した。  [0138] Then, a resin was applied to the collective circuit board to which the surface acoustic wave element 900 was bonded, and beta was performed in an N gas atmosphere, thereby sealing the surface acoustic wave element 900 with the resin.
[0139] ここでは、複数の弾性表面波素子 900を搭載できる集合回路基板を用いたため、 集合回路基板のダイシング線に沿ってダイシング加工を施すことで、回路基板 800, 800Aの個片に分割することで、複数の分波器 306, 306Aを一度の工程で得た。な お、出来上がった各分波器 306, 306Aの寸法(できあがり寸法)を、実装面積 2. 5 mm X 2. Omm X高さ 0. 9mmとした。  Here, since the collective circuit board on which a plurality of surface acoustic wave elements 900 can be mounted is used, the circuit board is divided into individual pieces of the circuit boards 800 and 800A by performing dicing along the dicing lines of the collective circuit board. Thus, a plurality of duplexers 306 and 306A were obtained in one step. The dimensions (finished dimensions) of the completed duplexers 306 and 306A were set to a mounting area of 2.5 mm X 2. Omm X height of 0.9 mm.
[0140] このようにして作製された 2種類の分波器 306, 306Aについて、ネットワークアナラ ィザーを用いた測定値 (Sパラメータ)より送信側信号端子 1から受信側信号端子 2へ の透過係数 (すなわちアイソレーション)を得た。  [0140] For the two types of demultiplexers 306 and 306A fabricated in this way, the transmission coefficient from the transmission side signal terminal 1 to the reception side signal terminal 2 based on the measured value (S parameter) using a network analyzer ( That is, isolation was obtained.
[0141] (比較例)  [0141] (Comparative example)
一方、比較例として、第 1実施形態に係る回路基板 800から、信号線路 7, 8の双方 の周囲を囲む接地用パターン領域 30a, 30b, 44a, 44bが削除された回路基板を 用いた分波器を採用した。つまり、比較例としては、信号線路 7, 8の双方が、接地用 ノ ターンによっても接地用のビアによっても囲まれていない分波器を採用した。  On the other hand, as a comparative example, branching using a circuit board in which the ground pattern areas 30a, 30b, 44a, and 44b surrounding both signal lines 7 and 8 are deleted from the circuit board 800 according to the first embodiment. A vessel was adopted. In other words, as a comparative example, a duplexer was used in which both signal lines 7 and 8 were not surrounded by grounding vias or grounding vias.
[0142] 図 10及び図 11は、比較例に係る分波器に含まれる回路基板を構成する各層 La〜 Lgにおける導体パターン及びビアの配置を示す図である。  FIG. 10 and FIG. 11 are diagrams showing the arrangement of conductor patterns and vias in each layer La to Lg constituting the circuit board included in the duplexer according to the comparative example.
[0143] 図 10 (c)に示すように、変形例に係る導体配線パターン層 Lcでは、第 1実施形態 に係る導体配線パターン層 Lcの導体パターンから信号線路 7, 8をそれぞれ囲んで いた環状の接地用パターン領域 30a, 30bが除かれて、接地用の導体パターン 30が 3つの接地用の導体パターン 55〜57に分離された形態を有する。  [0143] As shown in FIG. 10 (c), in the conductor wiring pattern layer Lc according to the modified example, the signal lines 7 and 8 are respectively surrounded from the conductor pattern of the conductor wiring pattern layer Lc according to the first embodiment. The grounding pattern areas 30a and 30b are removed, and the grounding conductor pattern 30 is separated into three grounding conductor patterns 55 to 57.
[0144] また、図 11 (a)に示すように、変形例に係る導体配泉パターン層 Leでは、第 1実施 形態に係る導体配線パターン層 Leの導体パターンから信号線路 7, 8をそれぞれ囲 んでいた環状の接地用パターン領域 44a, 44bが除かれて、接地用の導体パターン 44が 3つの接地用の導体パターン 58〜60に分離された形態を有する。 Further, as shown in FIG. 11 (a), in the conductor arrangement pattern layer Le according to the modified example, the signal lines 7 and 8 are respectively surrounded by the conductor pattern of the conductor wiring pattern layer Le according to the first embodiment. The ring-shaped grounding pattern areas 44a and 44b were removed, and the grounding conductor pattern 44 is separated into three grounding conductor patterns 58-60.
[0145] なお、これらの特徴点を除いて、変形例に係る回路基板は、第 1実施形態に係る回 路基板 800と同様な構成を有するため、図 10及び図 11では、第 1実施形態に係る 回路基板 800と同様な部分については同様な符号を付して、説明を省略する。 [0145] Except for these feature points, the circuit board according to the modified example has the same configuration as the circuit board 800 according to the first embodiment. Therefore, in FIGS. Parts similar to those of the circuit board 800 according to FIG.
[0146] また、変形例に係る分波器は、実施例 1 , 2に係る分波器と同様に弾性表面波素子Further, the duplexer according to the modification is similar to the duplexer according to the first and second embodiments.
900を使用した分波器であり、当該分波器の製造方法については、上記実施形態 1900, and the manufacturing method of the duplexer is described in the first embodiment.
, 2に係る分波器と同様であるため説明を省略する。 , 2 are the same as those of the duplexer according to FIG.
[0147] このようにして作製された変形例に係る分波器についても、実施例 1 , 2に係る分波 器 306, 306Aと同様に、ネットワークアナライザーを用いた測定値(Sパラメータ)より 送信側信号端子 1から受信側信号端子 2への透過係数 (すなわちアイソレーション) を得た。 [0147] As with the duplexers 306 and 306A according to the first and second embodiments, the duplexer according to the modified example manufactured in this way is transmitted from the measured value (S parameter) using the network analyzer. The transmission coefficient (ie isolation) from the side signal terminal 1 to the reception side signal terminal 2 was obtained.
[0148] (実施例と比較例の比較)  [0148] (Comparison of Examples and Comparative Examples)
上述のようにして得られた、実施例 1 , 2に係る 2種類の分波器と、比較例に係る分 波器とについての、送信側信号端子 1から受信側信号端子 2への透過係数 (すなわ ちアイソレーション)を、図 12〜図 14、及び下表 1に示す。図 12〜図 14では、横軸は 周波数(単位: MHz)を、縦軸はアイソレーション(単位: dB)を示している。そして、実 施例 1のアイソレーションが実線 R1で示され、実施例 2のアイソレーションが太線 R2 で示され、更に、比較例のアイソレーションが破線 R3で示されている。また、図 12で は、広範囲の周波数帯域(760〜960MHz)におけるアイソレーションを示している。 図 13では、 US— CDMA方式で必要とされる送信用の周波数帯域(824〜849MH z)に着目したアイソレーション、すなわち図 12の太破線 A1で囲まれた領域に着目し たアイソレーションを示している。図 14では、 US— CDMA方式で必要とされる受信 用の周波数帯域(869〜894MHz)に着目したアイソレーション、すなわち図 12の太 破線 A2で囲まれた領域に着目したアイソレーションを示している。そして、下表 1で は、実施例 1、 2、及び比較例について、送信用の周波数帯域(824〜849MHz)に おけるアイソレーションの最大値、及び受信用の周波数帯域(869〜894MHz)にお けるアイソレーションの最大値がそれぞれ示されている。  Transmission coefficients from the transmission-side signal terminal 1 to the reception-side signal terminal 2 for the two types of duplexers according to Examples 1 and 2 and the duplexer according to the comparative example obtained as described above. (In other words, isolation) is shown in FIGS. 12 to 14 and Table 1 below. 12 to 14, the horizontal axis represents frequency (unit: MHz), and the vertical axis represents isolation (unit: dB). The isolation of Example 1 is indicated by a solid line R1, the isolation of Example 2 is indicated by a thick line R2, and the isolation of the comparative example is indicated by a broken line R3. Fig. 12 shows the isolation in a wide frequency band (760 to 960MHz). Fig. 13 shows the isolation focused on the transmission frequency band (824 to 849 MHz) required in the US-CDMA system, that is, the isolation focused on the area surrounded by the thick broken line A1 in Fig. 12. ing. Fig. 14 shows the isolation focused on the reception frequency band (869 to 894 MHz) required in the US-CDMA system, that is, the isolation focused on the area surrounded by the thick broken line A2 in Fig. 12. . In Table 1 below, the maximum value of isolation in the transmission frequency band (824 to 849 MHz) and the reception frequency band (869 to 894 MHz) for Examples 1, 2 and Comparative Example are shown. The maximum isolation values are shown respectively.
[0149] [表 1] 実施例 1 実施例 2 比較例 周灘(M H z )[0149] [Table 1] Example 1 Example 2 Comparative Example Zhou Yu (MH z)
—56 —5了 -53 824-849 アイソレ" 5 /ヨン (d B ) —56 —5 r -53 824-849 isole ”5 / yong (d B)
-41 -42 -42 869—894  -41 -42 -42 869—894
[0150] 信号線路 7, 8の双方の周囲を囲む接地用パターン領域 30a, 30b, 44a, 44b、及 びビア群 53a, 53b, 54a, 54bが設けられていない比較例の分波器では、送信用の 周波数帯域(824〜849MHz)におけるアイソレーションの最大値が— 53dBであり、 受信用の周波数帯域(869〜894MHz)におけるアイソレーションの最大値が— 42 dBであった。 [0150] In the branching filter of the comparative example in which the ground pattern areas 30a, 30b, 44a, 44b and the via groups 53a, 53b, 54a, 54b surrounding both the signal lines 7 and 8 are not provided, The maximum isolation value in the transmission frequency band (824 to 849 MHz) was -53 dB, and the maximum isolation value in the reception frequency band (869 to 894 MHz) was -42 dB.
[0151] 一方、信号線路 7, 8の双方の周囲を囲む接地用パターン領域 30a, 30b, 44a, 4 4bが設けられた実施例 1の分波器では、比較例と比べて、受信用の周波数帯域(86 9〜894MHz)におけるアイソレーションの最大値は一 41dBとほとんど変化しなかつ た力 送信用の周波数帯域(824〜849MHz)におけるアイソレーションの最大値が — 56dBと減少し、送受信の周波数帯域全体としてアイソレーション特性が向上した。 特に通信装置では受信信号と比較して送信信号の方が出力が大きい (ハイパワーで ある)為、送信用の周波数帯域におけるアイソレーションの向上が通信特性の改善に とって重要である点を考慮すると、比較例と比べて実施例 1では、送信用の周波数帯 域(824〜849MHz)におけるアイソレーションの最大値が 3dBも減少しており、通信 特性の改善に大きく寄与するアイソレーションの特性が向上したと言える。  [0151] On the other hand, in the duplexer of Example 1 in which the grounding pattern regions 30a, 30b, 44a, 44b surrounding the both sides of the signal lines 7, 8 are provided, compared with the comparative example, The maximum isolation value in the frequency band (86 9 to 894 MHz) was almost unchanged at 41 dB. The maximum isolation value in the frequency band for transmission (824 to 849 MHz) was reduced to -56 dB, and the frequency of transmission and reception. The isolation characteristics improved as a whole band. Considering the importance of improving isolation in the frequency band for transmission, especially for communication devices, because the output of the transmission signal is higher (higher power) than the received signal. Then, compared to the comparative example, in Example 1, the maximum value of isolation in the transmission frequency band (824 to 849 MHz) is reduced by 3 dB, and the isolation characteristics that greatly contribute to the improvement of communication characteristics It can be said that it has improved.
[0152] また、実施例 1の分波器に対して、更に信号線路 7, 8の双方の周囲を囲む接地用 のビア群 53a, 53b, 54a, 54bが設けられた実施例 2の分波器では、比較例と比べ て、受信用の周波数帯域(869〜894MHz)におけるアイソレーションの最大値は— 42dBと全く変化しな力、つた力 送信用の周波数帯域(824〜849MHz)におけるァ イソレーシヨンの最大値が 57dBと減少した。そして、実施例 2については、実施例 1と比較して、送信用の周波数帯域(824〜849MHz)及び受信用の周波数帯域(8 69〜894MHz)の双方にお!/、て、アイソレーションの最大値が若干減少する傾向を 示した。すなわち、信号線路 7, 8の双方の周囲を囲む接地用のビア群 53a, 53b, 5 4a, 54bが設けられたことで、アイソレーションの特性をより向上させることができた。 以上の結果より、信号線路 7, 8の双方を複数の誘電体層の内部に配置し、かつ信 号線路 7, 8の双方の周囲を、他方の信号線路 7, 8ならびに整合回路 6との間を通る 接地用の導体によって囲むことで、アイソレーション特性が向上した分波器が得られ る事を確認した。また、信号線路 7, 8の双方の周囲を、誘電体層の層間に設けられ た接地用パターンによって囲むだけよりも、更に接地用のビア群によって囲む方がァ イソレーシヨン特性が更に向上する傾向がある事を確認した。 [0152] In addition to the duplexer of the first embodiment, the demultiplexing of the second embodiment in which grounding via groups 53a, 53b, 54a, and 54b surrounding both the signal lines 7 and 8 are further provided. In comparison with the comparative example, the maximum isolation value in the receiving frequency band (869 to 894 MHz) is a force that does not change as much as -42 dB, and the combined force is the isolation in the transmitting frequency band (824 to 849 MHz). The maximum value of was reduced to 57dB. In the second embodiment, as compared with the first embodiment, both the transmission frequency band (824 to 849 MHz) and the reception frequency band (869 to 894 MHz) are! / The maximum value tended to decrease slightly. That is, by providing grounding via groups 53a, 53b, 54a, 54b surrounding both signal lines 7 and 8, the isolation characteristics can be further improved. Based on the above results, both signal lines 7 and 8 are arranged inside a plurality of dielectric layers, and the periphery of both signal lines 7 and 8 is connected to the other signal lines 7 and 8 and matching circuit 6. It was confirmed that a duplexer with improved isolation characteristics can be obtained by surrounding it with a grounding conductor that passes between them. Further, the isolation characteristics tend to be further improved by surrounding the signal lines 7 and 8 with grounding via groups rather than surrounding them with grounding patterns provided between the dielectric layers. I confirmed it.

Claims

請求の範囲 The scope of the claims
[1] 相互に積層された複数の誘電体層と、 [1] a plurality of dielectric layers stacked on each other;
前記複数の誘電体層によって包囲されているとともに、相互に通過周波数帯域が 異なる第 1及び第 2のフィルタ素子間のインピーダンスを調整するための整合回路用 線路と、  A matching circuit line for adjusting impedance between the first and second filter elements surrounded by the plurality of dielectric layers and having mutually different pass frequency bands;
前記複数の誘電体層によって包囲されているとともに、前記複数の誘電体層の最 上層から最下層に渡って形成され、かつ前記第 1のフィルタ素子と第 1の信号電送用 端子とを電気的に接続するための第 1の信号電送用線路と、  The first filter element and the first signal transmission terminal are electrically surrounded by the plurality of dielectric layers and formed from the uppermost layer to the lowermost layer of the plurality of dielectric layers. A first signal transmission line for connection to
前記第 2のフィルタ素子と第 2の信号電送用端子とを電気的に接続するための第 2 の信号電送用線路と、  A second signal transmission line for electrically connecting the second filter element and the second signal transmission terminal;
前記第 1の信号電送用線路と前記整合回路用線路との間、及び前記第 1の信号電 送用線路と前記第 2の信号電送用線路との間に設けられ、かつ前記第 1の信号電送 用線路を囲む第 1の接地用導体と、  Provided between the first signal transmission line and the matching circuit line, and between the first signal transmission line and the second signal transmission line, and the first signal. A first grounding conductor surrounding the transmission line;
を備えることを特徴とする分波器デバイス用回路基板。  A circuit board for a duplexer device, comprising:
[2] 請求項 1に記載の分波器デバイス用回路基板であって、 [2] A circuit board for a duplexer device according to claim 1,
前記第 2の信号電送用線路が、  The second signal transmission line is
前記複数の誘電体層によって包囲されているとともに、前記複数の誘電体層の最 上層から最下層に渡って形成され、  Surrounded by the plurality of dielectric layers and formed from an uppermost layer to a lowermost layer of the plurality of dielectric layers;
前記分波器デバイス用回路基板が、  The circuit board for the duplexer device,
前記第 2の信号電送用線路と前記整合回路用線路との間、及び前記第 2の信号電 送用線路と前記第 1の信号電送用線路との間に設けられ、かつ前記第 2の信号電送 用線路を囲む第 2の接地用導体、  Provided between the second signal transmission line and the matching circuit line, and between the second signal transmission line and the first signal transmission line, and the second signal. A second grounding conductor surrounding the transmission line,
を更に備えることを特徴とする分波器デバイス用回路基板。  A circuit board for a duplexer device, further comprising:
[3] 請求項 1に記載の分波器デバイス用回路基板であって、 [3] A circuit board for a duplexer device according to claim 1,
前記第 1の接地用導体が、  The first grounding conductor is
前記複数の誘電体層のうちの相互に隣接した 1組以上の誘電体層の層間に形成さ れた導体パターンを含むことを特徴とする分波器デバイス用回路基板。  A circuit board for a duplexer device, comprising a conductor pattern formed between one or more pairs of dielectric layers adjacent to each other among the plurality of dielectric layers.
[4] 請求項 3に記載の分波器デバイス用回路基板であって、 前記第 1の接地用導体が、 [4] A circuit board for a duplexer device according to claim 3, The first grounding conductor is
前記複数の誘電体層のうちの相互に隣接した複数組の誘電体層の層間にそれぞ れ形成された複数の導体パターン領域と、当該複数の導体パターン領域によって挟 まれた誘電体層を貫通し、かつ前記複数の導体パターン領域を相互に電気的に接 続した 1以上の導体と、  A plurality of conductor pattern regions formed between layers of a plurality of dielectric layers adjacent to each other among the plurality of dielectric layers, and a dielectric layer sandwiched between the plurality of conductor pattern regions. And one or more conductors that electrically connect the plurality of conductor pattern regions to each other; and
を含むことを特徴とする分波器デバイス用回路基板。  A circuit board for a duplexer device, comprising:
[5] 請求項 4に記載の分波器デバイス用回路基板であって、  [5] A circuit board for a duplexer device according to claim 4,
前記 1以上の導体が、  The one or more conductors are
前記第 1の信号電送用線路を囲むように設けられた複数の導体を含むことを特徴と する分波器デバイス用回路基板。  A circuit board for a duplexer device, comprising a plurality of conductors provided so as to surround the first signal transmission line.
[6] 請求項 1に記載の分波器デバイス用回路基板であって、  [6] The circuit board for a duplexer device according to claim 1,
前記第 1及び第 2のフィルタ素子が、  The first and second filter elements are:
それぞれラダー型のフィルタ素子であることを特徴とする分波器デバイス用回路基 板。  A circuit board for a duplexer device, wherein each is a ladder type filter element.
[7] 請求項 4に記載の分波器デバイス用回路基板であって、  [7] The circuit board for a duplexer device according to claim 4,
前記第 1及び第 2のフィルタ素子のうちの相対的に高い通過周波数帯域を有するフ ィルタ素子が、並列腕に共振子を有し、  The filter element having a relatively high pass frequency band among the first and second filter elements has a resonator in a parallel arm,
前記共振子が、  The resonator is
前記第 1の接地用導体に対して電気的に接続されていることを特徴とする分波器 デバイス用回路基板。  A duplexer device circuit board, wherein the duplexer device circuit board is electrically connected to the first grounding conductor.
[8] 請求項 2に記載の分波器デバイス用回路基板であって、 [8] A circuit board for a duplexer device according to claim 2,
前記第 1及び第 2の接地用導体が、  The first and second grounding conductors are
前記複数の誘電体層のうちの相互に隣接した 1組以上の誘電体層の層間に形成さ れた導体パターンをそれぞれ含むことを特徴とする分波器デバイス用回路基板。  A circuit board for a duplexer device, comprising a conductor pattern formed between one or more pairs of dielectric layers adjacent to each other among the plurality of dielectric layers.
[9] 請求項 8に記載の分波器デバイス用回路基板であって、  [9] The circuit board for a duplexer device according to claim 8,
前記第 1の接地用導体が、  The first grounding conductor is
前記複数の誘電体層のうちの相互に隣接した複数組の誘電体層の層間にそれぞ れ形成された複数の第 1の導体パターン領域と、当該複数の第 1の導体パターン領 域によって挟まれた誘電体層を貫通し、かつ前記複数の第 1の導体パターン領域を 相互に電気的に接続した 1以上の導体と、 A plurality of first conductor pattern regions respectively formed between layers of a plurality of dielectric layers adjacent to each other among the plurality of dielectric layers; and the plurality of first conductor pattern regions. One or more conductors penetrating through the dielectric layer sandwiched between the regions and electrically connecting the plurality of first conductor pattern regions to each other;
を含み、  Including
前記第 2の接地用導体が、  The second grounding conductor is
前記複数の誘電体層のうちの相互に隣接した複数組の誘電体層の層間にそれぞ れ形成された複数の第 2の導体パターン領域と、当該複数の第 2の導体パターン領 域によって挟まれた誘電体層を貫通し、かつ前記複数の第 2の導体パターン領域を 相互に電気的に接続した 1以上の導体と、  A plurality of second conductor pattern regions formed between layers of a plurality of dielectric layers adjacent to each other among the plurality of dielectric layers, and sandwiched between the plurality of second conductor pattern regions. One or more conductors penetrating the dielectric layer and electrically connecting the plurality of second conductor pattern regions to each other;
を含むことを特徴とする分波器デバイス用回路基板。  A circuit board for a duplexer device, comprising:
[10] 請求項 9に記載の分波器デバイス用回路基板であって、 [10] The circuit board for a duplexer device according to claim 9,
前記複数の第 1の導体パターン領域を相互に電気的に接続した 1以上の導体が、 前記第 1の信号電送用線路を囲むように設けられた複数の導体を含むことを特徴と する分波器デバイス用回路基板。  One or more conductors that electrically connect the plurality of first conductor pattern regions to each other include a plurality of conductors provided so as to surround the first signal transmission line. Circuit board for instrument devices.
[11] 請求項 9に記載の分波器デバイス用回路基板であって、 [11] The circuit board for a duplexer device according to claim 9,
前記複数の第 2の導体パターン領域を相互に電気的に接続した 1以上の導体が、 前記第 2の信号電送用線路を囲むように設けられた複数の導体を含むことを特徴と する分波器デバイス用回路基板。  One or more conductors that electrically connect the plurality of second conductor pattern regions to each other include a plurality of conductors provided so as to surround the second signal transmission line. Circuit board for instrument devices.
[12] 請求項 9に記載の分波器デバイス用回路基板であって、 [12] The circuit board for a duplexer device according to claim 9,
前記第 1及び第 2のフィルタ素子が、  The first and second filter elements are:
それぞれラダー型のフィルタ素子であることを特徴とする分波器デバイス用回路基 板。  A circuit board for a duplexer device, wherein each is a ladder type filter element.
[13] 請求項 9に記載の分波器デバイス用回路基板であって、  [13] The circuit board for a duplexer device according to claim 9,
前記第 1及び第 2のフィルタ素子のうちの相対的に高い通過周波数帯域を有するフ ィルタ素子が、並列腕に共振子を有し、  The filter element having a relatively high pass frequency band among the first and second filter elements has a resonator in a parallel arm,
前記共振子が、  The resonator is
前記第 1及び第 2の接地用導体に対して電気的に接続されていることを特徴とする 分波器デバイス用回路基板。  A circuit board for a duplexer device, wherein the circuit board is electrically connected to the first and second grounding conductors.
[14] 請求項 1に記載の分波器デバイス用回路基板であって、 前記第 1のフィルタ素子が、送信用フィルタ素子であり、 [14] The circuit board for a duplexer device according to claim 1, The first filter element is a transmission filter element;
前記第 2のフィルタ素子が、受信用フィルタ素子であることを特徴とする分波器デバ イス用回路基板。  The duplexer device circuit board, wherein the second filter element is a reception filter element.
[15] 請求項 1から請求項 14のいずれかに記載された分波器デバイス用回路基板と、 前記分波器デバイス用回路基板に対して実装された前記第 1及び第 2のフィルタ 素子と、  [15] The circuit board for the duplexer device according to any one of claims 1 to 14, and the first and second filter elements mounted on the circuit board for the duplexer device. ,
を備えることを特徴とする分波器。  A duplexer comprising:
[16] 請求項 15に記載の分波器であって、 [16] The duplexer according to claim 15,
前記第 1のフィルタ素子が、送信用フィルタ素子であり、  The first filter element is a transmission filter element;
前記第 2のフィルタ素子が、受信用フィルタ素子であり、  The second filter element is a receiving filter element;
前記第 1及び第 2のフィルタ素子が、アンテナに対して電気的に接続された共通端 子に共通して電気的に接続され、  The first and second filter elements are electrically connected in common to a common terminal electrically connected to an antenna;
前記整合回路の一端が、前記共通端子に対して電気的に接合され、  One end of the matching circuit is electrically joined to the common terminal,
前記整合回路の一端とは異なる前記整合回路の他端が、接地されて!/、ることを特 徴とする分波器。  A duplexer characterized in that the other end of the matching circuit different from one end of the matching circuit is grounded! /.
[17] 請求項 16に記載の分波器であって、 [17] The duplexer according to claim 16,
前記整合回路が、所定の受信用の周波数帯域の信号について前記共通端子から 送信回路へのインピーダンスがほぼ無限大となり、所定の送信用の周波数帯域の信 号について前記送信回路から受信回路へのインピーダンスがほぼ無限大となること を特徴とする分波器。  The matching circuit has an almost infinite impedance from the common terminal to the transmission circuit for a signal in a predetermined reception frequency band, and an impedance from the transmission circuit to the reception circuit for a signal in a predetermined transmission frequency band. A demultiplexer characterized in that is almost infinite.
[18] 請求項 17に記載の分波器であって、 [18] The duplexer according to claim 17,
前記受信用の周波数帯域力 s、 869〜 894MHzであり、 The frequency band power s for reception is 869 to 894 MHz,
前記送信用の周波数帯域が、 824〜849MHzであることを特徴とする分波器。  The duplexer characterized in that the frequency band for transmission is 824 to 849 MHz.
[19] 請求項 15に記載の分波器であって、 [19] A duplexer according to claim 15,
前記第 1及び第 2のフィルタ素子が、それぞれ環状電極部によって取り囲まれてい ることを特徴とする分波器。  The duplexer, wherein the first and second filter elements are each surrounded by an annular electrode portion.
[20] 請求項 15から請求項 19のいずれかに記載の分波器が搭載されたことを特徴とす る通 ί—S装置。 [20] A printing-S apparatus comprising the duplexer according to any one of claims 15 to 19.
PCT/JP2007/066451 2006-08-30 2007-08-24 Circuit board for wave separator device, wave separator, and communication device WO2008029641A1 (en)

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