WO2013010739A2 - Circuit d'alimentation et procédé d'alimentation d'une charge électrique - Google Patents

Circuit d'alimentation et procédé d'alimentation d'une charge électrique Download PDF

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Publication number
WO2013010739A2
WO2013010739A2 PCT/EP2012/061717 EP2012061717W WO2013010739A2 WO 2013010739 A2 WO2013010739 A2 WO 2013010739A2 EP 2012061717 W EP2012061717 W EP 2012061717W WO 2013010739 A2 WO2013010739 A2 WO 2013010739A2
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WO
WIPO (PCT)
Prior art keywords
voltage
load
output
control signal
phase
Prior art date
Application number
PCT/EP2012/061717
Other languages
German (de)
English (en)
Other versions
WO2013010739A3 (fr
Inventor
Thomas Jessenig
Peter BLIEM
Original Assignee
Ams Ag
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Filing date
Publication date
Application filed by Ams Ag filed Critical Ams Ag
Publication of WO2013010739A2 publication Critical patent/WO2013010739A2/fr
Publication of WO2013010739A3 publication Critical patent/WO2013010739A3/fr

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M11/00—Power conversion systems not covered by the preceding groups
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/37—Converter circuits
    • H05B45/3725—Switched mode power supply [SMPS]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/37—Converter circuits
    • H05B45/3725—Switched mode power supply [SMPS]
    • H05B45/375—Switched mode power supply [SMPS] using buck topology
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/37—Converter circuits
    • H05B45/3725—Switched mode power supply [SMPS]
    • H05B45/38—Switched mode power supply [SMPS] using boost topology
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y02B20/30—Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]

Definitions

  • the invention relates to a supply circuit for an electrical load and a method for supplying an electrical load.
  • DC-DC converter in particular clocked operated
  • DC-DC converters are used, for example, to supply power to a load having a periodically pulsed current.
  • a voltage converter can be used in a driver for light-emitting diodes, LEDs, in which the current is switched on and off by the LED in order to adjust the brightness.
  • the switching on and off for example, periodically with a pulse width-modulated, PWM, signal.
  • Clocked DC-DC converter have, for example, a
  • Control in order to generate corresponding control signals in dependence on the output side of the voltage applied ⁇ .
  • a control voltage is generated, which is converted into a pulse-modulated signal.
  • Such a regulation usually has a significant settling time, which is based on the presence of corresponding capacitances in the generation of the compensation voltage, which are charged during regulation. Due to the slow-running control process, it can be connected to an output capacitor of the
  • An object to be solved is to provide an improved Kon ⁇ zept for supplying an electrical load, wherein the supply of the load is pulse-shaped.
  • an output voltage is generated which is supplied switched in dependence from ⁇ a pulse-shaped load control signal of an elec trical ⁇ load.
  • the output voltage is he witnesses ⁇ on the basis of a pulse-shaped switching signal.
  • this is fed back to generate a compensation voltage, which is the basis for the pulse-shaped switching signal.
  • the compensation voltage is buffered to make it during a Zeitab ⁇ section of a subsequent load phase of the load control signal as a buffered compensation voltage and thereby speed up the control process can.
  • An embodiment of a supply circuit for an electrical load, to which an output voltage is supplied in response to a pulse-shaped load control signal comprises a switched DC-DC converter for generating the output voltage from an input voltage on the basis of a pulse-shaped switching signal. Further, a feedback path for generating a feedback voltage based on the output voltage is provided.
  • a comparator of the supply circuit is arranged on the basis of egg ⁇ nes comparing the feedback voltage with a reference voltage, a compensation voltage at aarrindus- the comparator.
  • a signal generating unit is for generating the switching signal on the basis of the compensation voltage.
  • the supply circuit also includes a buffer unit which is adapted to buffer a period of time a load phase of the load control signal, the Kompen ⁇ sationsschreib and dispense this gepuf ⁇ ferte compensation voltage at an output coupled to the comparator output terminal during a time period of a subsequent load phase of the load control signal.
  • the output voltage is delivered to the load, in particular during the load phase of the load control signal. Mainly during this time is also a regulation of the output ⁇ voltage on the compensation voltage and the resulting resulting switching signal. For example, during a
  • the compensation voltage buffered especially towards the end of the load phase.
  • the buffered compensating voltage can be delivered at the comparator output, especially at the beginning of the following load phase to an initial value for the control during this phase load horrstel ⁇ len.
  • the buffered compensating voltage can be delivered at the comparator output, especially at the beginning of the following load phase to an initial value for the control during this phase load horrstel ⁇ len.
  • with constant or little changing load in the load phase can be done faster to a regulation on the final value of the compensation voltage.
  • fewer transient processes occur in the output voltage at the output of the switched DC-DC converter than in the case of a conventional control in which a complete transient of a constant output value takes place in each load phase.
  • DC-DC converter buffered via a capacitor. If such a capacitor is designed as a ceramic capacitor, audible piezoelectric effects are avoided or redu ⁇ ed that would otherwise occur due to the buffering of the compensation ⁇ tension. Because of the lower voltage drops at the beginning of the load phases are the egg ⁇ properties regarding electromagnetic compatibility, EMC, improved. Further, an improved lead- ⁇ equal Bende brightness when using LEDs as a load reached the ⁇ , which is based on the reduced voltage dip.
  • the load control signal is for example a pulse-modulated signal, in particular a pulse width, for example, a control device is supplied modulated signal wel ⁇ ches from an external unit.
  • the switching signal is, for example, also a PWM signal which is derived from the compensation voltage .
  • the Signalerzeu ⁇ supply unit is adapted to generate the switching signal on the basis of egg ⁇ nes comparison of the compensation voltage with a periodic signal, in particular a triangular signal or a seeding gezähensignal.
  • the comparison signal of the signal generating unit ⁇ can be further processed to generate the switching signal.
  • the buffer unit has a first capacitor, which is switchably coupled to the comparator output, and a first buffer amplifier, which is connected on the input side to the first capacitor and is switchably coupled to the comparator output on the output side. Controlled by appropriate control signals thus the first capacitor is charged during a load phase to the compensation ⁇ voltage, wherein the switchable connection is open in a subsequent rest phase. In a subsequent load phase, especially at the beginning of the load phase, is in turn, controlled by a corresponding control signal, the buffer voltage stored on the first capacitor buffered output via the first buffer amplifier to the comparator output.
  • the buffer unit to a second buffer amplifier, whose input is coupled to the comparator output and the output side ⁇ switchably connected to the first capacitor. Accordingly, the compensation voltage applied to the comparison output can be buffered to the first capacitor to charge it. Due to the second buffer amplifier, the comparator output is not or only insignificantly loaded.
  • the buffer unit for example, further comprises a two ⁇ th capacitor and a third buffer amplifier, whose input is connected to the second capacitor, and switched to an output of the second buffer amplifier and the output side switchably connected to the first capacitor. For example, the Kompensa ⁇ tion voltage is buffered by the second buffer amplifier is supplied to the second capacitor to charge during the load phase.
  • the voltage stored on the second capacitor is buffered by the third buffer amplifier during a sampling phase supplied to the first capacitor for charging.
  • the voltage stored on the first capacitor is in turn supplied buffered during a precharge phase during the load phase, in particular at the beginning of the load phase via the first buffer amplifier to the comparator output.
  • the sampling phase begins, for example, with the end of the precharge phase, so that a corresponding control signal for the sampling phase results from an inverted control signal for the precharge phase.
  • a duration of the precharge phase or the sampling phase during the load phase is preferably defined in advance. Ins ⁇ particular the precharge phase at the beginning of the last phase before ⁇ is preferably shorter than the sampling at the end of the last phase.
  • the supply circuit to a entspre ⁇ sponding control circuit which generates the necessary dimensional Steuersig ⁇ for the precharge phase and the sampling for the control of corresponding switched connections from the load control signal.
  • the supply circuit is also designed for the switched supply of the output voltage to a further electrical load as a function of a further pulse-shaped load control signal.
  • the electrical load and the further electrical load are parallel to each other ge ⁇ switched to an output of the DC converter.
  • the supply circuit further has a second buffer unit, which is set up to buffer the compensation voltage during a time period of a load phase of the further load control signal and to output this buffered compensation voltage to a terminal coupled to the comparator output during a period of a subsequent load phase of the further load control signal.
  • the compensation voltages can cherausgang on comparisons for different load cases, so the supply of different loads, each buffered and especially at the beginning of the next load phase for the corresponding load will be restored, so each one mög ⁇ lichst fast Einriegelvorgang for the corresponding load phase to enable.
  • the supply circuit further comprises a third buffer unit that is set up during a Time period of a common load phase of the Lastêtsig ⁇ nals and the other load control signal to buffer the compensation ⁇ voltage and during a period of a following common load phase of the load control signal and the other load control signal to deliver this buffered compensation ⁇ voltage at one coupled to the comparator output terminal.
  • a third buffer unit that is set up during a Time period of a common load phase of the Last Gambsig ⁇ nals and the other load control signal to buffer the compensation ⁇ voltage and during a period of a following common load phase of the load control signal and the other load control signal to deliver this buffered compensation ⁇ voltage at one coupled to the comparator output terminal.
  • both the load control signal and the other Last Gambsig ⁇ nal have a load phase, so that the common load phase examples game, from an AND function of the two last phases resulted.
  • the common load phase thus represents ⁇ example, another load case, resulting in an individual compensation voltage at the comparator output.
  • the comparator comprises a connected to the comparator output buffer capacitor and is adapted, during a period of a Ru ⁇ hephase the load control signal, in particular at the beginning of Ru ⁇ hephase to unload the buffer capacitor.
  • a discharge for example, in a common rest phase carried out in which the in each case have in common a rest phase on ⁇ corresponding load control signals.
  • the discharge of the buffer capacitor can be done by bridging the buffer capacitor, so that a full ⁇ constant discharge takes place in the rest phase.
  • a discharge takes place to a predetermined Entla ⁇ voltage, so that the buffer capacitor is not completely discharged.
  • a discharge to a buffered voltage can take place from one of the buffer units associated with the next load case.
  • the corresponding buffered compensation voltage can be output more quickly and with less charge current.
  • the comparator has a transconductance amplifier, OTA, with a resistor element connected on the output side.
  • OTA transconductance amplifier
  • the control phase of the transconductance amplifier delivers a respective control current, which is converted via the resistive element in the Kompensati ⁇ insulation voltage.
  • no current flows through the resistance element.
  • a first buffer capacitor is connected directly to the comparator output and a second buffer capacitor is connected via a resistance element.
  • the first buffer capacitor preferably has a smaller capacitance value than the second buffer capacitor.
  • the buffer unit for buffering the compensation voltage is connected directly or via a resistance element to the comparator output and is connected to output the buffered compensation voltage directly or via a resistance element to the comparator output.
  • a tap of the compensation voltage to the buffer takes place directly at the comparator output, while the buffered one
  • Compensation voltage at a connection node between the resistance element and a buffer capacitor takes place.
  • an output voltage is generated from an input voltage on the basis of a pulse-shaped switching signal.
  • the output voltage is switched to the electrical load in response to a pulsed Laststeu ⁇ ersignals supplied.
  • a feedback voltage is generated.
  • a compensation voltage is generated at a comparator output.
  • the switching signal is generated on the basis of Kompensati ⁇ onsschreib.
  • the compensation voltage is buffered.
  • the compensation voltage buffered with respect to the load control signal is output at a terminal coupled to the comparator output during a period of a subsequent load phase of the load control signal.
  • a switched supply of the output voltage to a further electrical load takes place as a function of a further pulse-shaped load control signal.
  • the compensation voltage is a time ⁇ portion of a load phase of the further load control signal ge ⁇ buffers and with respect to the further load control signal ge ⁇ buffered compensation voltage is output to the cherausgang coupled to the comparisons connection during a Zeitab ⁇ section of a following load phase of the further load control signal.
  • the compensation voltage is buffered during a Zeitab ⁇ section of a common load phase of the load control signal and the further load control signal.
  • Figure 2 is a signal-time diagram for control signals of a
  • FIG. 3 shows an exemplary signal-time diagram of a load control signal and an output voltage
  • FIG. 4 shows an exemplary signal-time diagram with voltages and control signals of a supply circuit
  • FIG. 5 shows a further exemplary embodiment of a supply circuit
  • FIG. 6 shows an exemplary signal-time diagram with signals of the supply circuit from FIG. 5
  • FIG. 7 shows a further exemplary embodiment of a supply circuit
  • FIG. 8 shows a further exemplary embodiment of a supply circuit
  • FIG. 9 shows a further exemplary embodiment of a supply circuit
  • FIG. 10 shows a further exemplary embodiment of a supply circuit
  • Figure 11 shows another embodiment of a supply circuit ⁇ .
  • Figure 12 shows another embodiment of a supply circuit ⁇ .
  • FIG. 1 shows an embodiment of a supply scarf ⁇ tion 1, with which an output voltage VOUT of an electrical load LD is supplied in response to a pulse-shaped load control signal PWM1 connected.
  • the supply circuit 1 has a switched-operated DC-DC converter DCC, which has a coil L which is connected at one end to egg ⁇ nem voltage input for supplying an input voltage VIN and at its other end via a first switch SWl with a reference potential terminal GND and via a second switch SW2 is connected to an output terminal for outputting the output voltage VOUT.
  • An output capacitor COUT is connected to the output connection. sen.
  • a series circuit of the switch controlled by the load control signal PWM1 and a load LD shown as a current source is connected between the output terminal and the reference potential terminal GND.
  • the output terminal is also connected to a non-inverting input of a comparator DA via a feedback path FB, which comprises a feedback circuit FBC.
  • FB feedback path
  • VFB feedback voltage generated by the feedback path FB.
  • a comparison voltage VREF is supplied.
  • a comparator output VO of the comparator DA, to which a compensation voltage VCOMP is applied, is connected to an input of a signal generating unit PG.
  • Another input of the signal generation unit PG is connected to a signal generator SG which generates a periodic signal, for example a triangular signal or a sawtooth signal.
  • a signal generator SG which generates a periodic signal, for example a triangular signal or a sawtooth signal.
  • the Sig ⁇ nalerzeugungsech PG provides switching signals S_SW1 and S_SW2 for actuation of the first and second switches SW1, SW2 of the
  • the comparator DA is embodied, for example, as a transconductance amplifier, English Operational Transconductance Amplifier, OTA, which outputs an output current as a function of the voltage VFB, VREF applied on the input side, which is converted into the compensation voltage VCOMP via the resistance element Rl.
  • OTA English Operational Transconductance Amplifier
  • the supply circuit 1 further comprises a buffer unit PU1 with a first capacitor KU, which via a switch SMP1 and a connection point TRI or the
  • Comparator output VO is connected.
  • a second terminal of the capacitor KU is connected to the reference potential terminal GND connected.
  • Connected to the capacitor KU is a buffer amplifier PV11, which is connected on the output side via a switch SP1 to a connection node TC1 between a first resistance element R1 and a buffer capacitor C1.
  • the resistance element R1 is further connected to the connection point TRI, and the buffer capacitor C1 is further connected to the reference potential connection GND.
  • the buffer capacitor Cl is bridged via a switch SD switchable.
  • the supply circuit 1 further comprises a control circuit CTRL, which generates from the Lastêtsig ⁇ nal PWM1 a control signal for the switch S_SMP1 SMP1, a control signal for the switch S_SP1 SP1 and a control signal for the switch S_SD SD.
  • An exemplary embodiment of the control signals is shown in the signal-time diagram in FIG.
  • the load control signal PWM1 is in this embodiment, a pulse-width modulated, which causes the output ⁇ voltage Vout of the load LD only during the load phase, corresponding to a logic 1 or a gesche ⁇ NEN switch position is supplied to the PWM signal.
  • the switch SMP1 in the active phase which can be referred to as a sampling phase, placed in a closed state, whereby the capacitor KU to the compensation ⁇ voltage VCOMP is charged. Due to the buffer amplifier PV11, the voltage applied to the capacitor KU is delivered in buffered form, in particular without charge transfer from the capacitor KU, and in dependence on the control signal
  • the buffer amplifier PV11 is designed, for example, as a feedback operational amplifier.
  • the buffered compensation voltage By applying the buffered compensation voltage to the buffer capacitor C1, it is precharged to the value of the buffered compensation voltage during the active phase of the control signal S_SP1, which may also be referred to as the precharging phase. This can be adjusted more quickly, a control value of the compensation voltage V COMP, since only voltage differences between the buffered Kompensa ⁇ tion voltage and the newly set compensation voltage must be balanced.
  • the buffer capacitor C1 can be discharged via the switch SD and the corresponding control signal S_SD as a discharge phase during the quiescent phase. This prevents additional switching after the load phase, which would lead to an increase in the output voltage VOUT.
  • the COUT which is designed for example as a ceramic capacitor. Accordingly, audible piezoelectric effects are reduced in such a ceramic capacitor. Furthermore, the load LD is supplied with a more uniform output voltage, which has a positive effect on the brightness sensation, in particular in the case of light-emitting means as a load, for example LEDs. Furthermore, the voltage on the capacitor from ⁇ gear electromagnetic compatibility of the assembly is enhanced by the low ripple.
  • FIG. 4 shows a further signal-time diagram with signals in the supply circuit from FIG. 1, in which, in particular, a transient of the signals over the first periods of a load control signal PWM1 is illustrated. It can be seen that in each case the final value of the compensation voltage VCOMP is restored at the beginning of the next load phase of the load control signal PWM1 and is regulated from there to the respective end value of the compensation voltage.
  • the control value of the compensation voltage VCOMP corresponds to the buffered end value of the preceding period, so that the desired output voltage VOUT is set almost instantaneously can be.
  • the load voltage VLOAD across the load LD already reaches a desired value in the second period.
  • FIG. 5 shows a further exemplary embodiment of a supply circuit, which is a further development of the embodiment shown in FIG.
  • the embodiment shown in Figure 5 is designed to supply two electrical loads LD, LD2, which are each connected in series with egg ⁇ nem switch to the output terminal of the DC voltage converter DCC.
  • the two switches are controlled independently of one another by a first and a second load control signal PWM1, PWM2 in order to supply the loads LD, LD2 in each case connected to the output voltage VOUT.
  • the second buffer unit PU2 comprises a capacitor K12 which is directly connected via a switch SMP2 to the node TRI or the comparator output VO.
  • a buffer amplifier PV12 is connected to the capacitor K12, and connected on the output side via a switch SP2 to the node TCl.
  • the third buffer unit PU 3 has a capacitor K13, which is connected via a switch SMP3 to the node TRI and to which a further buffer amplifier PV13 is connected.
  • An output of the buffer amplifier PV13 is in turn connected to the node TCl via a switch SP3.
  • the output of the first buffer amplifier PV11 is also connected via a switch SD1 and the switch SD connected to the node TC1.
  • the output of the buffer amplifier PV12 is connected via the switches SD2 and SD and the output of the buffer amplifier PV13 via the switches SD3 and SD respectively to the node TC1.
  • the node TC1 is connected to the reference potential terminal GND via the switch SD and a switch SDO.
  • a different been regulated Kompensati ⁇ insulation voltage VCOMP results basically at the comparator output VO, wherein in the fourth load case in which no supply takes place, a re ⁇ gelung can also be omitted.
  • FIG. 6 shows an exemplary signal-time diagram with load control signals PWM1, PWM2 and exemplary switching signals for the switches in the buffer units PU1, PU2, PU3. It should be noted that in the present signal-time diagram on the wiring of the second buffer unit is omitted, but such a circuit is possible in other forms ⁇ out ⁇ forms in a corresponding manner.
  • the load control signals PWM1, PWM2 are pulse modulated signals, which in the present case but have the same period length difference ⁇ Liche edge times. Result from the superposition of the load control signals PWM1, PWM2 previously beschrie ⁇ surrounded four different load cases ST, wherein the load
  • the signal-time-diagram of the control signals determine S_SMP1, S_SP1, S_SMP3, S_SP3 and S_SD ent ⁇ speaking switch positions in the buffer units PU1 and PU3.
  • the scarf ⁇ ter is closed by the control signal S_SP1 SP1 to transmit the buffered on the capacitor KU compensation voltage on the buffer capacitor Cl and to achieve a fast Rege ⁇ lung to a required compensation voltage VCOMP at the beginning of the load phase.
  • the switch SP1 is correspondingly opened and the switch SMP1 is concluded in the entspre ⁇ sponding sampling phase by the control signal S_SMP1 to buffer the inserted regulated compensation voltage VCOMP to the capacitor KU.
  • the switch SP1 is correspondingly opened and the switch SMP1 is concluded in the entspre ⁇ sponding sampling phase by the control signal S_SMP1 to buffer the inserted regulated compensation voltage VCOMP to the capacitor KU.
  • the buffer capacitor Cl can be discharged via the switch SD, controlled by the control signal S_SD.
  • a discharge can take place, for example, by simultaneous activation of the switch SD0, so that the buffer capacitor C1 is completely discharged.
  • a discharge can also be defined to the buffered compensation voltage of the next load case, which is the load case of the present case.
  • the switch SD1 can also be closed simultaneously with the switch SD, as a result of which, in the following load case, for example, a regulation can take place more quickly.
  • FIG. 5 and FIG. 6 are chosen by way of example only.
  • ⁇ sondere also a larger number of parallel-connected, in particular independently connected loads can be provided at the starting terminal of the DC-DC converter DCC.
  • the various combination options increase in each case. controlled loads, the number of occurring load cases.
  • further buffer units with the same structure can be provided in the supply circuit, which are controlled by respective control signals to be generated for a precharge phase and a sampling phase.
  • the generation of the corresponding control signals can in turn be carried out in a corresponding control unit CTRL, which generates for example, by logic operations and time ⁇ members from the respective load control signals, the control signals for the switches in the buffer units.
  • FIG. 7 shows a further exemplary embodiment of a supply circuit 1, which is based on the embodiment shown in FIG.
  • the DC-DC converter DCC is in turn designed as a boost converter, which generates a higher output voltage VOUT from a lower input voltage VIN.
  • the signal generating unit comprises a PG here designed as operational amplifier differential amplifier with the periodic ramp signal, for example a triangular signal or a stake ⁇ geddlingsignal, compares the compensation voltage VCOMP. The comparison result is in the signal generating unit PG further processed by the switching signals and to generate S_SW1 S_SW2 which the corresponding switch SW1, SW2 of the DC-DC converter DCC ansteu ⁇ ren.
  • a second buffer capacitor C2 is provided in addition to the resistance element Rl and the first buffer capacitor Cl, which is connected directly to the comparator output VO.
  • the capacitors C 1, C 2 are each bridgeable via switches SD, SD 'in order to enable a discharge.
  • the buffer unit PU1 comprises, in addition to the elements already shown in FIG. 1 and FIG. 5, a second buffer amplifier PV21 which connects the comparator output VO to the capacitor KU via the switch SMP1. Accordingly the compensation voltage VCOMP is continued in the form of buffered during operation of the assembly and during the sampling phase used Ab ⁇ for charging the capacitor KU.
  • the output of the comparator DA is less or not loaded, so that during the load phase of the load control signal PWM1
  • a capacitance value of the second buffer capacitance C2 is preferably less than the capacity value of the first buffer capacity ⁇ Cl.
  • FIG. 8 shows another embodiment of a supply circuit ⁇ which forms in particular a development of the embodiment shown in FIG. 7
  • the buffer unit PU1 comprises in this embodiment a series circuit tion of buffer amplifiers PV21, PV31 and PV11 with capacitors KU and K21 in between.
  • the buffer amplifier PV21 on the input side to the comparator output VO and the output side via a switch SPWM, which is controlled by the load control signal PWM1, connected to the capacitor K21 and an input of the buffer amplifier PV31.
  • This buffer amplifier PV31 is connected on the output side via the switch S_NP1 to the capacitor KU and to an input of the buffer amplifier PV11.
  • the buffer amplifier PV11 is connected via the switch SP1 to the connection node of the resistance element R1 and of the first buffer capacitor C1.
  • the switch NP1 is controlled via a control signal S_NP1, which results in particular by inverting the control signal S_SP1.
  • the second capacitor is charged with the K21 buffered by the buffer amplifier PV21 compensation voltage VCOMP.
  • the voltage stored on the capacitor K21 is used during the time period of the load phase, which does not correspond to the precharge phase, via the buffer amplifier PV31 for charging the first capacitor KU.
  • the named period of time thus substantially corresponds to the sampling phase of the previously described embodiments.
  • a change in the charge or voltage on the capacitor KU takes place only during the time of the load phase of the load control signal PWM1, in which no precharging of the buffer capacitors C1, C2 takes place.
  • the additional buffer amplifier PV31 in comparison to the embodiment shown in FIG. terhin improved decoupling of the buffered voltage values reached each other.
  • FIG. 9 shows a further exemplary embodiment of a supply circuit which is essentially based on the embodiment shown in FIG.
  • the DC-DC converter DCC is performed in this embodiment as a buck converter having a input side input voltage VIN ⁇ output voltage to a lower output side fitting training VOUT reacted. Accordingly, the position of the switches SW1, SW2 is changed from the previously illustrated embodiments. In other respects, however, result in similar modes of operation, particularly with respect to the Rege ⁇ averaging the output voltage VOUT and the buffering of the compensation voltage VCOMP gelung used for re-.
  • FIG. 10 shows a further embodiment of a supply circuit 1 which is essentially based on the embodiment shown in FIG.
  • the return path FB is configured modified.
  • the load LD in the form of light between an output terminals is circuit of the DC-DC converter DCC and means connected to the loading zugspotenzialan gleich GND current sink switching ISNK connected ⁇ bar.
  • the DC-DC converter DCC is again designed as a boost converter.
  • the feedback path FB has a first branch FBI, which connects the direct-voltage converter DCC ⁇ via a switch SFB1 and a first feedback element FBC1 to the comparator DA to provide these, the feedback voltage FVB.
  • the first branch FBI is via the switch SFB1, which is controlled by the load control signal
  • PWM1 either connected to the voltage output of the DC-DC converter DCC, at which the output voltage ⁇ VOUT is delivered, or with a connection between see the load LD and the current sink ISNK or the corresponding switch in between. Accordingly, in a load phase of the voltage is below the load LD Bezie ⁇ hung, via the current sink ISNK is recycled, while the circuit applied to the output terminals VOUT voltage is directly returned in a rest phase of the load control signal PWM1.
  • a second branch FB2 of the feedback path FB connects the voltage output of the DC-DC converter DCC via switches SFB2, SFB3 and a second feedback element FBC2 to the second output of the comparator DA in order to supply a more adapted comparison voltage VREF to the comparator DA.
  • a capacitor CS is also connected to the second feedback path FB2, which stores the voltage present at output terminal output ⁇ voltage Vout during the load phase of the Last Trust- signal PWM1.
  • a reference voltage ⁇ source V2 is provided, which can be switched via the switch SFB3 switchable to the second feedback branch FB2. Accordingly, during the load phase PWM1, the voltage supplied by the reference voltage source V2 is fed back to effect a regulation of the voltage applied to the current sink ISNK to this voltage value.
  • the idle phase ⁇ phase of the load control signal PWM1 stored on the capacitor CS output voltage VOUT is fed back to achieve a regulation of the output voltage VOUT in the rest phase to the previously stored value.
  • the buffering of the compensation voltage VCOMP used for regulation corresponds to the embodiments described above.
  • FIG. 11 shows a further embodiment of a supply circuit 1, which in turn is based on the embodiment described in FIG.
  • the feedback path FB includes similar to FIG 10 a first and a second feedback path FBI, FB2 for returning a feedback voltage VFB ⁇ and a reference voltage VREF.
  • the DC-DC converter DCC is again designed as a boost converter.
  • a current source ISRC is connected, which emits a current controlled by the load control signal PWMl switch to the in turn designed as a light emitting diode LD.
  • the first feedback branch FBI returns the output voltage VOUT to produce the feedback voltage VFB.
  • the voltage across the load LD is fed back via the switch SFB1 to generate the feedback voltage VFB. Furthermore, during the load phase of the load control signal PWM1, the capacitor C1 in the second feedback branch FB2 is charged with the output voltage VOUT via the switch SFB2 in order to return the corresponding buffered voltage value in the quiescent phase via the switch SFB3 to generate the comparison voltage VREF.
  • the second feedback branch FB2 is connected via a voltage source V3 to the output terminal of the DC-DC converter DCC, to which the output voltage VOUT is applied.
  • FIG. 12 shows a further embodiment of a supply circuit 1, which in turn is based on the embodiment shown in FIG.
  • a Rei ⁇ henscrien is similarly connected to a current source ISRC a controlled by the load control signal ⁇ PWM switch and the load LD as the light-emitting diodes carried out as in FIG. 11
  • the feedback path FB is connected via a switch SFB4 to the load LD to return the load voltage VLOAD ⁇ during the last phase of the load control signal PWML across the load LD.
  • a capacitor CS2 is charged with the load voltage VLOAD.
  • the load voltage VLOAD or the voltage stored on the capacitor CS2 is subtracted from the instantaneous output voltage VOUT in order to generate the feedback voltage VFB therefrom. This in turn ensures that a fixed chip set voltage drop across the current source ISRC and thereby a defi ned ⁇ stream.
  • the buffer unit or the buffer units on the input side directly on the comparator output VO is ⁇ closed. Furthermore, a recirculation of the buffered voltage from the compensation or the PUF ferritten directly to the comparator output VO or to said node of the resistive element Rl and the Puf ⁇ ferkondensators Cl can be carried out.
  • the illustrated switches, in particular the switches SW1, SW2 may be implemented in conventional form, for example as MOSFET switches, bipolar switches, JFET switches or other semiconductor switches.
  • the switching signal S_SW2 results, for example, by inverting the switching signal
  • the switch SW2 may, for example, be designed as a switched diode or behave in this way.
  • the switch SW2 can also be replaced by a diode which is connected in the forward direction from the input of the DC-DC converter DCC via the coil L to the output.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

Circuit d'alimentation (1) d'une charge électrique (LD) servant à l'amenée d'une tension de sortie (VOUT) en fonction d'un signal de commande de charge (PWM1) en forme d'impulsion. Le circuit d'alimentation (1) selon l'invention comprend un convertisseur continu-continu (DCC) connecté pour générer la tension de sortie (VOUT) à partir d'une tension d'entrée (VIN) sur la base d'un signal de commutation (S_SW1, S_SW2) en forme d'impulsion, et un chemin de retour pour générer une tension de retour (VFB) sur la base de la tension de sortie (VOUT). Un comparateur (DA) est aménagé pour générer, sur la base d'une comparaison de la tension de retour (VFB) avec une tension comparative (VREF), une tension de compensation (VCOMP) sur une sortie (VO) du comparateur (DA). Le circuit d'alimentation (1) selon l'invention comprend en outre une unité de génération de signaux (PG) pour générer le signal de commutation (S_SW1, S_SW2) sur la base de la tension de compensation (VCOMP), et une unité tampon (PU1) qui est conçue pour amortir la tension de compensation (VCOMP) durant une phase de charge du signal de commande de charge (PWM1) et pour transmettre cette tension de compensation amortie à une connexion (TC1, TR1) couplée à la sortie (VO) du comparateur pendant une phase de charge suivante du signal de commande de charge (PWM1).
PCT/EP2012/061717 2011-07-19 2012-06-19 Circuit d'alimentation et procédé d'alimentation d'une charge électrique WO2013010739A2 (fr)

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DE102011108091A DE102011108091A1 (de) 2011-07-19 2011-07-19 Versorgungsschaltung und Verfahren zur Versorgung einer elektrischen Last
DE102011108091.4 2011-07-19

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CN113825279A (zh) * 2021-11-25 2021-12-21 上海南麟电子股份有限公司 Led驱动系统及其驱动方法

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JP7345326B2 (ja) 2019-09-06 2023-09-15 ローム株式会社 発光素子駆動装置

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CN108112149A (zh) * 2017-12-26 2018-06-01 生迪智慧科技有限公司 供电控制装置与灯具
CN108112149B (zh) * 2017-12-26 2023-07-07 生迪智慧科技有限公司 供电控制装置与灯具
CN113825279A (zh) * 2021-11-25 2021-12-21 上海南麟电子股份有限公司 Led驱动系统及其驱动方法
CN113825279B (zh) * 2021-11-25 2022-03-04 上海南麟电子股份有限公司 Led驱动系统及其驱动方法

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