WO2012176248A1 - Power supply voltage detection circuit - Google Patents

Power supply voltage detection circuit Download PDF

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Publication number
WO2012176248A1
WO2012176248A1 PCT/JP2011/005604 JP2011005604W WO2012176248A1 WO 2012176248 A1 WO2012176248 A1 WO 2012176248A1 JP 2011005604 W JP2011005604 W JP 2011005604W WO 2012176248 A1 WO2012176248 A1 WO 2012176248A1
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WO
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Prior art keywords
voltage
power supply
switching element
circuit
supply voltage
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PCT/JP2011/005604
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French (fr)
Japanese (ja)
Inventor
善之 鶴崎
香 西川
昌美 三好
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パナソニック株式会社
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Publication of WO2012176248A1 publication Critical patent/WO2012176248A1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16533—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application
    • G01R19/16538—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application in AC or DC supplies

Definitions

  • the present invention relates to a power supply voltage detection circuit for detecting a power supply voltage supplied from a DC power supply.
  • the power supply voltage is within the guaranteed operation range of the electronic circuit, and the reference voltage source is
  • a power supply voltage detection circuit that detects whether a constant reference voltage is output is connected to an electronic circuit, and the electronic circuit is operated or stopped based on a detection result of the power supply voltage detection circuit.
  • the power supply voltage detection circuit used in this technique is controlled on and off according to the reference voltage source 402 that outputs the reference voltage VREF based on the power supply voltage VCC and the magnitude of the reference voltage VREF.
  • a power supply voltage circuit that includes a comparator 404 that compares the voltage VS and can use the output of the comparator 404 as an enable signal that is input to an electronic circuit (see Patent Document 1).
  • the switching element 407 is composed of an N-channel MOSFET
  • the switching element 409 is composed of a P-channel MOSFET.
  • the voltage VS output from the voltage divider 403 increases as the power supply voltage VCC increases, and when the power supply voltage VCC reaches the voltage VOL, the magnitude relationship between the voltage VREF input to the comparator 404 and the voltage VS. Is reversed, and the output voltage VOUT of the comparator 404 is switched from the high level to the low level (0 V).
  • the voltage VOL is set so as to be within an operation guarantee range of the electronic circuit by appropriately setting a ratio of the magnitudes of the resistors 410 and 411 constituting the voltage divider 403. Since the electronic circuit operates at the timing (detection timing) at which the output voltage VOUT is detected from the high level to the low level, malfunction can be prevented.
  • a reference voltage source 500 that outputs a reference voltage VREF based on a power supply voltage VDD, a switching element 501 that is on / off controlled by the magnitude of the reference voltage VREF,
  • a voltage output circuit 502 that outputs a voltage VG obtained by dividing the voltage VDD, and a switching element 507 connected in series to the resistor 508, can be used as an enable signal for the electronic circuit.
  • a power supply voltage detection circuit has been proposed (see Patent Document 2).
  • the voltage output circuit 502 is formed by connecting a resistor 503 and two diodes 505 and 506 in series, and outputs a voltage VG generated at a connection point between the resistor 503 and the diode 504.
  • the switching element 501 is composed of an N channel MOSFET
  • the switching element 507 is composed of a P channel MOSFET.
  • the operation of the reference voltage source 500 is stabilized and the output voltage becomes the reference voltage VREF.
  • the switching element 501 is turned on, and a current flows through the resistor 503 and the diodes 505 and 506.
  • the voltage drop V2 at the diodes 505 and 506 is substantially constant regardless of the power supply voltage VDD.
  • the switching element 507 is in the off state and the voltage VOUT is at the low level (0 V).
  • the switching element 507 is turned on. VOUT becomes a high level.
  • the voltage VOL is set by the resistor 503 and the diodes 505 and 506 so as to be within the operation guarantee range of the electronic circuit. Since the electronic circuit operates at the timing (detection timing) at which the output voltage VOUT is detected from the low level to the high level, malfunction can be prevented.
  • MOS transistors are employed as the switching elements 501 and 507. Accordingly, parasitic capacitances C51 and C52 exist between the source and gate of the switching elements 501 and 507, respectively.
  • this type of power supply voltage detection circuit is generally designed so that only a few nA current flows through the switching elements 501 and 507 in consideration of low power consumption.
  • a resistance component (not shown) connected in series to the output terminal of the voltage VREF in the reference voltage source 500 becomes a current limiting element in the switching element 501. Yes.
  • the switching element 507, the resistor 503 and the switching element 501 are current limiting elements.
  • the reference voltage VREF output from the reference voltage source 500 is applied to the switching element 501, the parasitic capacitance C51 is charged and the switching element 501 is turned on.
  • the charging of C52 is started and the parasitic capacitance C52 is charged, the switching element 507 is turned on. Therefore, the detection timing is delayed by the charging period of the parasitic capacitance C51 and the parasitic capacitance C52.
  • the switching element 407 and 409 also employs MOS transistors as the switching elements 407 and 409, parasitic capacitances C41 and C42 exist between the source and gate of each of the switching elements 407 and 409, and the switching element 407 , 409 is designed so that only a current of several nA flows. Then, the reference voltage VREF output from the reference voltage source 402 is applied to the switching element 407, the parasitic capacitor C41 is charged to turn on the switching element 407, and then the charging of the parasitic capacitor C42 is started. Is charged, the switching element 409 is turned on, and thus has the same problem as the power supply voltage detection circuit shown in FIG.
  • the present invention has been made in view of the above reasons, and provides a power supply voltage detection circuit capable of suppressing a delay in detection timing.
  • a power supply voltage detection circuit is connected to a power supply line supplied with power from an external power supply, and outputs a voltage based on the voltage of the power supply line.
  • a second switching element that switches between on and off states, and a load resistor connected in series to a switch circuit formed by connecting the second switching element to the first switching element in series, the switch circuit and the load resistance, One end of the series circuit is connected to the power line and the other end is connected to the ground line, and the voltage generated at the connection point between the load resistor and the switch circuit is output. That.
  • the first switching element is switched on and off based on the voltage output from the voltage output circuit, whereas the second switching element outputs a reference voltage circuit different from the voltage output circuit. Since the ON / OFF state is switched based on the reference voltage, the charging period of the parasitic capacitance of the first switching element and the charging period of the parasitic capacitance of the second switching element when the ON / OFF state is switched can be detected. Timing delay can be suppressed.
  • the first switching element switches from the off state to the on state when the voltage output from the voltage output circuit is equal to or higher than a predetermined threshold voltage
  • the second switching element may be switched from the off state to the on state when the reference voltage is output.
  • the voltage output circuit includes the unidirectional element connected to the power supply line, one end connected to the unidirectional element, and the other end grounded.
  • a pull-down resistor that pulls down a voltage generated at the point, and outputs a voltage generated at a connection point between the unidirectional element and the pull-down resistor
  • the first switching element has a drain connected to the power supply line side
  • the N switching MOS transistor has a gate connected to the voltage output circuit
  • the second switching element has a drain connected to the source of the first switching element and a gate connected to the reference voltage circuit side.
  • the unidirectional element includes a P-channel MOS transistor in which a source is connected to the power supply line side and a gate and a drain are commonly connected to the pull-down resistor side. It may be a thing.
  • the detection voltage can depend on the threshold voltage Vth of the transistor.
  • an electronic circuit is often composed of transistors, and the guaranteed operation range depends on the threshold value Vth of the transistor. Therefore, the electronic circuit can be stably operated by making the detection voltage dependent on the threshold value Vth of the transistor. it can.
  • the first switching element may have a back gate grounded.
  • the voltage output circuit is connected to the power supply line at one end, and pulls up a voltage generated at the connection point.
  • the control voltage that is the output of the power supply voltage detection circuit can be inverted.
  • the unidirectional element includes an N-channel MOS transistor in which a drain and a gate are commonly connected to the other end of the pull-up resistor and a source is grounded. It may be.
  • the detection voltage can depend on the threshold voltage Vth of the transistor.
  • an electronic circuit is often composed of transistors, and the guaranteed operation range depends on the threshold value Vth of the transistor. Therefore, the electronic circuit can be stably operated by making the detection voltage dependent on the threshold value Vth of the transistor. it can.
  • the back gate of the first switching element may be connected to the power supply line.
  • the present invention may be an electronic circuit that determines the activation state of the reference voltage circuit based on the magnitude of the voltage output from the power supply voltage detection circuit.
  • FIG. 3 is a circuit diagram of a power supply voltage detection circuit according to the first embodiment.
  • FIG. FIG. 3 is an operation explanatory diagram of the power supply voltage detection circuit according to the first embodiment.
  • 3 is a time chart for explaining the operation of the power supply voltage detection circuit according to the first embodiment. It is a time chart for demonstrating operation
  • FIG. 6 is a circuit diagram of a power supply voltage detection circuit according to a second embodiment. 6 is an operation explanatory diagram of a power supply voltage detection circuit according to a second embodiment.
  • FIG. 6 is a time chart for explaining the operation of the power supply voltage detection circuit according to the second embodiment. It is a circuit diagram of the power supply voltage detection circuit which concerns on a prior art example.
  • the power supply voltage detection circuit includes a voltage output circuit 151, a reference voltage circuit 100, a voltage dividing circuit 154, and an enable signal output circuit 152, as shown in FIG.
  • the voltage output circuit 151 is connected to the power supply line L to which power is supplied from the external power supply, and outputs the voltage VGVDD1 based on the power supply voltage VDD of the power supply line L.
  • the voltage output circuit 151 includes a P-channel MOS transistor 104 and a pull-down resistor 105.
  • the source of the P-channel MOS transistor 104 is connected to the power supply line L, the drain is connected to the ground line GND through the resistor 105, and the gate is connected to the drain.
  • a voltage generated at the connection point between the drain of P-channel MOS transistor 104 and resistor 105 is output as voltage VGVDD1.
  • the P-channel MOS transistor 104 has a gate and a drain connected in common, and is in a so-called diode-connected state.
  • the reference voltage circuit 100 is connected to the power line L and outputs the reference voltage VREF.
  • the reference voltage circuit 100 includes a band gap reference or the like.
  • the voltage dividing circuit 154 outputs a voltage VGVREF1 obtained by dividing the reference voltage VREF.
  • the voltage dividing circuit 154 includes a series circuit including two resistors 1541 and 1542 connected between the output terminal of the reference voltage circuit 100 and the ground line GND.
  • the enable signal output circuit 152 outputs an enable signal to the electronic circuit 153.
  • the enable signal output circuit 152 includes a switch circuit in which the second switching element 103 is connected in series to the first switching element 102, and a pull-up resistor (load) connected to the switch circuit. Resistance) 101.
  • the series circuit including the switch circuit and the resistor 101 has one end connected to the power supply line L and the other end connected to the ground line GND.
  • a voltage VOUT generated at a connection point between the switch circuit and the resistor 101 is output as an enable signal for driving the electronic circuit 153.
  • This enable signal is at a low level (0 V) when the power supply voltage VDD is within the guaranteed operation range of the electronic circuit 153 and the reference voltage circuit 100 outputs the reference voltage VREF, and is at a high level otherwise. (Power supply voltage VDD).
  • the first switching element 102 is composed of an N channel MOS transistor.
  • the drain is connected to the power supply line L side, the gate is connected to the voltage output circuit 151, and the drain is connected to the drain of the second switching element 103.
  • the first switching element 102 monitors the voltage VGVDD1 output from the voltage output circuit 151. If the power supply voltage VDD is within the operation guarantee range of the electronic circuit 153, the first switching element 102 is turned on. When it is not, it is turned off.
  • the second switching element 103 is composed of an N channel MOS transistor.
  • the drain is connected to the source of the first switching element 102, the gate is connected to the reference voltage circuit 100 side, and the source is connected to the ground line GND.
  • the second switching element 103 monitors the reference voltage VREF output from the reference voltage circuit 100. When the reference voltage circuit 100 outputs the reference voltage VREF, the second switching element 103 is turned on, and the reference voltage VREF is supplied. When not outputting, it is turned off.
  • the power supply voltage VDD is within the operation guarantee range based on the configuration in which the pull-up resistor 101 is connected to the switch circuit including the second switching element 103 connected in series to the first switching element 102.
  • the reference voltage VREF is output, both the first switching element 102 and the second switching element 103 are turned on, and the potential at the connection point between the switch circuit and the resistor 101 is substantially grounded.
  • the potential becomes the same as that of the line GND, and the enable signal (output voltage VOUT) becomes the Low level.
  • the power supply voltage detection circuit inputs an enable signal to the electronic circuit 153.
  • the electronic circuit 153 is connected to the power supply line L and the ground line GND, receives the power supply voltage VDD from the power supply line L, and receives the voltage VREF from the reference voltage circuit 100.
  • the electronic circuit 153 is normally driven when the power supply voltage VDD is within the guaranteed operating range and the reference voltage circuit 100 outputs the reference voltage VREF.
  • the electronic circuit 153 monitors the input enable signal (the output voltage VOUT of the power supply voltage detection circuit) and drives when it detects that the enable signal has changed from the High level to the Low level.
  • the voltage VGVREF1 output from the voltage dividing circuit 154 is approximately 0V. Since P channel MOS transistor 104 is in an off state and no current flows through resistor 105, voltage VGVDD1 is also approximately 0V. As a result, the first switching element 102 and the second switching element 103 are both in the off state, and the power supply voltage VDD of the power supply line L is output as it is to the output terminal VOUT of the power supply voltage detection circuit.
  • the first switching element 102 Since the gate-source voltage VGS is still lower than the gate threshold voltage Vth of the first switching element 102, the first switching element 102 maintains the off state.
  • the voltage drop between the source and drain of the P-channel MOS transistor 104 is equal to the gate threshold voltage Vth, so that the voltage VGVDD1 is equal to the gate threshold voltage Vth. Then, the first switching element 102 is turned on. At this time, since both the first switching element 102 and the second switching element 103 are in the on state, the output voltage VOUT is substantially 0V.
  • the output voltage VOUT is maintained at 0V.
  • FIG. 3 shows the time series operation of the power supply voltage detection circuit according to this embodiment, and the time series operation of the power supply voltage detection circuit according to the conventional example shown in FIG. As shown in FIG. 3 and 4, the case where the power supply voltage VDD monotonously increases with time, such as immediately after power-on (see FIGS. 3A and 4A), will be described as an example.
  • the reference voltage source 500 When the power supply voltage VDD reaches the voltage V1 at time T (V1), the reference voltage source 500 is activated (see FIG. 4B). At this time, the voltage V1 is applied between the source and gate of the switching element 501, and the switching element 501 is turned on (see FIG. 4C).
  • the source-gate voltage VSG (507) of the switching element 507 also increases (FIG. 4 (f)).
  • the source-gate voltage VSG (507) reaches the gate threshold voltage Vth of the switching element 507, the switching element 507 is turned on, and the voltage VOUT (enable signal) changes from 0 V to a voltage greater than or equal to the voltage VOL. It changes (FIG. 4 (g)).
  • the gate-source voltage VGS (501) of the switching element 501 is The time when the reference voltage VREF is actually reached is delayed from the time T (V1) by the charging period T02 of the parasitic capacitance C51 (see FIG. 4H).
  • the gate-source voltage VGS (501) of the switching element 501 reaches the gate threshold voltage Vth, and the switching element 501 is turned on to start discharging the parasitic capacitance C52.
  • the voltage VDD-VG between both ends of the resistor 503 gradually increases from time T (CS) and reaches the time when the voltage VOL is reached at time T (VOL) (T (VOL) ⁇ T ( CS)) by discharging the parasitic capacitance C52, the period T01 until the source-gate voltage VSG (507) of the switching element 507 actually reaches the voltage VOL becomes longer (FIG. 4 ( h)).
  • the switching element 501 since it is assumed that the switching element 501 is in an ON state in order to apply a voltage between the source and gate of the switching element 507, the switching element 501 The charging period T02 of the parasitic capacitance C51 and the discharging period T01 of the parasitic capacitance C52 of the switching element 507 do not overlap.
  • the time from when the power is turned on until the voltage VOUT is output (hereinafter referred to as “detection time”) Td0 is the time when the power supply voltage VDD is 0.
  • detection time the time from when the power is turned on until the voltage VOUT is output
  • actual arrival time the time when the power supply voltage VDD is 0.
  • actual arrival time the period T02 of charging the parasitic capacitance C51 of the switching element 501 and the discharge of the parasitic capacitance C52 are caused. It becomes longer corresponding to both the delay time and the detection timing of the voltage VOL is delayed by that amount.
  • the P-channel MOS transistor 104 When the power supply voltage VDD reaches the gate threshold voltage Vth at time T (Vth), the P-channel MOS transistor 104 is turned on. Thereafter, the power supply voltage VDD rises and the current flowing through the resistor 105 increases, and the voltage VGVDD1 rises accordingly (see FIG. 3E). On the other hand, the magnitude of the voltage across the resistor 109 (VDD ⁇ VGVDD2) is kept substantially constant even when the power supply voltage VDD rises (see FIG. 3D).
  • the reference voltage source 100 When the power supply voltage VDD reaches the voltage V1 at time T (V1), the reference voltage source 100 is activated and the voltage dividing circuit 154 outputs the positive voltage VGVREF1 (see FIG. 3B). At this time, the second switching element 103 is turned on when the source-gate voltage VGS (103) exceeds the gate threshold voltage (see FIG. 3C). Thereafter, when the power supply voltage VDD reaches the voltage 2Vth that is within the operation guarantee range of the electronic circuit 153 at time T (2Vth), the first switching element 102 is turned on, and the voltage VOUT (enable signal) is as large as the voltage 2Vth. This voltage changes to 0 V (see FIG. 3G).
  • the source-gate of the second switching element 103 with respect to the step-like input from the voltage dividing circuit 154 to the gate of the second switching element 103 The inter-voltage VGS (103) is delayed by the period T11. This is because it takes only the period T12 to charge the parasitic capacitance C12 between the source and gate of the second switching element 103.
  • the voltage VGVDD1 across the resistor 105 reaches the voltage 2Vth earlier than the time T (2Vth), but the source of the first switching element 102 -Delay due to the need to charge the parasitic capacitance C11 between the gates.
  • the time during which the parasitic capacitance C11 is charged is a period T11 during which the source-gate voltage VGS (102) of the first switching element 102 reaches 0 to the gate threshold voltage Vth (FIG. 3 (h)).
  • the parasitic capacitance C11 of the first switching element 102 is reduced.
  • the charging period T11 overlaps the charging period T12 of the parasitic capacitance C12 of the second switching element 103. If the charging time T11 is longer than T12, the detection time Td corresponds to a delay time due to charging of the parasitic capacitance C11 of the first switching element 102, compared to the actual arrival time T1 until the voltage 2Vth is reached. However, it is not affected by the charging period T12 of the parasitic capacitance C12 of the second switching element 103.
  • the charging period T12 is included in the charging period T12, so that the detection error due to the detection timing delay can be reduced.
  • the power supply voltage detection circuit according to the present embodiment is configured not to use a comparator such as an operational amplifier, the circuit scale is reduced as compared with a power supply voltage detection circuit using a comparator as shown in FIG. Therefore, low power consumption can be achieved.
  • the power supply voltage detection circuit according to the present embodiment is the same as the power supply voltage detection circuit according to the first embodiment except that the P-channel MOS transistor 104 of the voltage output circuit 151 is changed to an N-channel MOS transistor, and an enable signal output is performed. In this configuration, the two N-channel MOS transistors 102 and 103 of the circuit 152 are changed to P-channel MOS transistors.
  • the power supply voltage detection circuit includes a voltage output circuit 251, a reference voltage circuit 100, a voltage dividing circuit 254, and an enable signal output circuit 252 as shown in FIG.
  • the voltage output circuit 251 is connected to the power supply line L to which power is supplied from the external power supply, and outputs the voltage VGVDD2 based on the power supply voltage VDD of the power supply line L.
  • the voltage output circuit 251 includes an N-channel MOS transistor 104 and a pull-up resistor 110.
  • the source of the N-channel MOS transistor 110 is connected to the ground line GND, the drain is connected to the power supply line L via the resistor 109, and the gate is connected to the drain.
  • a voltage generated at the connection point between the drain of N-channel MOS transistor 110 and resistor 109 is output as voltage VGVDD2.
  • N channel MOS transistor 110 has a gate and a drain connected in common, and is in a so-called diode connection state.
  • the reference voltage circuit 100 is the same as that of the first embodiment, and is connected to the power supply line L and outputs the reference voltage VREF.
  • the voltage dividing circuit 254 outputs a voltage VGVREF2 obtained by dividing the reference voltage VREF.
  • the voltage dividing circuit 254 includes a series circuit including two resistors 2541 and 2542 connected between the output terminal of the reference voltage circuit 100 and the ground line GND.
  • the enable signal output circuit 252 outputs an enable signal to the electronic circuit 253.
  • the enable signal output circuit 252 includes a switch circuit in which the second switching element 106 is connected in series to the first switching element 107, and a resistor (load resistance) 108 connected to the switch circuit. Is provided.
  • the series circuit including the switch circuit and the resistor 108 has one end connected to the power supply line L and the other end connected to the ground line GND.
  • an inverter 255 is connected between a connection point between the two resistors 2541 and 2542 and the gate of the second switching element 106.
  • a voltage VOUT generated at a connection point between the switch circuit and the resistor 108 is output as an enable signal for driving the electronic circuit 253.
  • This enable signal is at a high level (power supply voltage VDD) when the power supply voltage VDD is within the operation guarantee range of the electronic circuit 153 and the reference voltage circuit 100 outputs the reference voltage VREF, and otherwise. It becomes Low level (0V).
  • the first switching element 107 is composed of a P-channel MOS transistor.
  • the drain is connected to the ground line L via the resistor 108, the gate is connected to the voltage output circuit 251, and the source is connected to the drain of the second switching element 106. ing.
  • the first switching element 107 monitors the voltage VGVDD2 output from the voltage output circuit 251, and is turned on when the power supply voltage VDD is within the operation guarantee range of the electronic circuit 253, and is within the operation guarantee range. When it is not, it is turned off.
  • the second switching element 106 is composed of a P-channel MOS transistor.
  • the drain is connected to the source of the first switching element 102, the gate is connected to the reference voltage circuit 100, and the source is connected to the power supply line L.
  • the second switching element 106 monitors the reference voltage VREF output from the reference voltage circuit 100. If the reference voltage circuit 100 outputs the reference voltage VREF, the second switching element 106 is turned on, and the reference voltage VREF is reduced. When not outputting, it is turned off.
  • the power supply voltage VDD is within the guaranteed operating range based on the configuration in which the pull-down resistor 108 is connected to the switch circuit including the second switching element 106 connected in series to the first switching element 107.
  • both the first switching element 107 and the second switching element 106 are turned on, and the potential at the connection point between the switch circuit and the resistor 108 is substantially the power line. It becomes the same potential as GND, and the enable signal (output voltage VOUT) becomes High level.
  • the power supply voltage detection circuit inputs an enable signal to the electronic circuit 253.
  • the electronic circuit 253 is connected to the power supply line L and the ground line GND, receives the power supply voltage VDD from the power supply line L, and receives the voltage VREF from the reference voltage circuit 100.
  • the electronic circuit 253 is driven normally when the power supply voltage VDD is within the guaranteed operating range and the reference voltage circuit 100 outputs the reference voltage VREF.
  • the electronic circuit 253 monitors the input enable signal (the output voltage VOUT of the power supply voltage detection circuit), and drives when detecting that the enable signal has changed from the Low level to the High level.
  • the voltage VGVREF2 output from the voltage dividing circuit 254 is substantially equal to the voltage VDD. Since N channel MOS transistor 110 is in an off state and no current flows through resistor 109, voltage VGVDD2 is substantially equal to voltage VDD. As a result, both the first switching element 107 and the second switching element 106 are in the OFF state, and the output terminal VOUT of the power supply voltage detection circuit outputs 0 V, which is the voltage level of the ground line GND, as it is. become.
  • the voltage VGVREF2 having a magnitude equal to or higher than the gate threshold voltage Vth of the second switching element 103 is input from the voltage dividing circuit 254 to the gate of the second switching element 106.
  • the switching element 106 is turned on.
  • This voltage VGVREF2 is approximately 0V.
  • the voltage (source-gate voltage VGS) between the gate voltage VGVDD2 of the first switching element 107 and the source side power supply voltage VDD of the first switching element 102 is the first switching element 107. Since the gate threshold voltage Vth is still lower, the first switching element 107 maintains the off state.
  • the voltage drop between the source and drain of the N-channel MOS transistor 110 is equal to the gate threshold voltage Vth, so that the voltage VGVDD2 is equal to the gate threshold voltage Vth.
  • the first switching element 107 is turned on.
  • the output voltage VOUT is a voltage across the resistor 108.
  • the size of the resistor 108 is sufficiently larger than the on-resistance of the first switching element 107 and the second switching element 106, the output voltage VOUT becomes substantially equal to the power supply voltage VDD.
  • the output voltage VOUT becomes the voltage VDD.
  • the electronic circuit 253 since the output voltage VOUT is output after the reference voltage circuit 100 is in a state in which the constant reference voltage VREF is output, the electronic circuit 253 has the power supply voltage VDD within the guaranteed operation range of the electronic circuit 153. Regardless of this, it is possible to prevent malfunctions when the reference voltage VREF is not input.
  • FIG. 7 a case where the power supply voltage VDD monotonously increases with time, such as immediately after power-on (see FIG. 7A) will be described as an example.
  • the N-channel MOS transistor 110 When the power supply voltage VDD becomes equal to the gate threshold voltage Vth at time T (Vth), the N-channel MOS transistor 110 is turned on. Thereafter, even when the power supply voltage VDD rises, the voltage VGVDD2 is maintained substantially constant (see FIG. 7E). On the other hand, the voltage across the resistor 109 (VDD ⁇ VGVDD2) increases with the power supply voltage VDD (see FIG. 7D).
  • the reference voltage source 100 When the power supply voltage VDD reaches the voltage V1 at time T (V1), the reference voltage source 100 is activated and the voltage dividing circuit 254 outputs 0 V (see FIG. 7B), and the second switching element 106 is activated. Is turned on when the source-gate voltage VSG (106) exceeds the gate threshold voltage (see FIG. 7C).
  • the source-gate of the second switching element 106 with respect to the step-like input from the voltage dividing circuit 254 to the gate of the second switching element 106.
  • the inter-voltage VSG (106) is delayed by the period T21. This is because it takes only the period T21 to discharge the parasitic capacitance C22 between the source and gate of the second switching element 106.
  • the voltage across the resistor 109 (VDD ⁇ VGVDD2) reaches the voltage 2Vth earlier than the time Tth, but the parasitic capacitance C21 between the source and gate of the first switching element 107 needs to be discharged. It will be delayed by minutes.
  • the discharge period T21 of the parasitic capacitance C21 of the first switching element 107 as shown in FIG.
  • the discharge period T22 of the parasitic capacitance C22 of the switching element 106 is overlapped. If the discharge time T21 is longer than T22, the detection time Td is longer than the actual arrival time T2 until the voltage 2Vth is reached, corresponding to the delay time caused by the discharge of the parasitic capacitance C21 of the switching element 107. Thus, the second switching element 106 is not affected by the discharge period T22 of the parasitic capacitance C22.
  • the detection time Td can be freely set by changing the number of P-channel MOS transistors, so that the range of application of the power supply voltage detection circuit according to the guaranteed operation range of the electronic circuit 153 Can be spread.
  • the voltage output circuit 251 outputs a voltage generated at a connection point between a resistor 109 and a series circuit in which two or more N-channel MOS transistors are connected in series. Also good.
  • the present invention can be used for electronic devices that require low power consumption, for example, electronic devices such as home appliances, alarm devices, watches, power meters, and extra-small radio devices.

Abstract

This power supply voltage detection circuit is provided with: a voltage output circuit (151) for outputting a voltage (VGVDD1), a reference voltage circuit (100) for outputting a reference voltage circuit (VREF), a voltage-dividing circuit (154) for outputting a voltage (VGVREF1) obtained by dividing the reference voltage (VREF), a first switching element (102) that is switched on when the voltage (VGVDD1) is at a gate threshold voltage (Vth) or higher, a second switching element (103) that is switched on when the voltage (VGVREF1) is at a gate threshold voltage (Vth) or greater, and a resistor (101) connected to a switching circuit formed by serially connecting the second switching element (103) to the first switching element (102). The power supply voltage detection circuit outputs a voltage (VOUT) generated at a connection point between the resistor (101) and the series circuit.

Description

電源電圧検出回路Power supply voltage detection circuit
　本発明は、直流電源から供給される電源電圧を検出する電源電圧検出回路に関する。 The present invention relates to a power supply voltage detection circuit for detecting a power supply voltage supplied from a DC power supply.
　従来から、直流電源から電源電圧を受けると共に基準電圧源から基準電圧を受けて動作する電子回路の誤動作を防止する技術として、電源電圧が電子回路の動作保証範囲にあり、且つ、基準電圧源が一定の基準電圧を出力しているかを検出する電源電圧検出回路を電子回路に接続し、当該電源電圧検出回路の検出結果に基づいて電子回路の動作または停止を行わせる技術がある。 Conventionally, as a technique for preventing malfunction of an electronic circuit that operates by receiving a power supply voltage from a DC power supply and receiving a reference voltage from a reference voltage source, the power supply voltage is within the guaranteed operation range of the electronic circuit, and the reference voltage source is There is a technique in which a power supply voltage detection circuit that detects whether a constant reference voltage is output is connected to an electronic circuit, and the electronic circuit is operated or stopped based on a detection result of the power supply voltage detection circuit.
　この技術に用いられる電源電圧検出回路としては、例えば、図８に示すように、電源電圧ＶＣＣに基づいて基準電圧ＶＲＥＦを出力する基準電圧源４０２と、基準電圧ＶＲＥＦの大きさによりオンオフ制御されるスイッチング素子４０７と、電源電圧ＶＣＣを抵抗４１０，４１１により分圧してなる電圧を出力する分圧器４０３と、分圧器４０３に直列に接続されたスイッチング素子４０９と、基準電圧ＶＲＥＦと分圧器４０３の出力電圧ＶＳとを比較する比較器４０４とを備え、比較器４０４の出力を電子回路に入力するイネーブル信号として使用することができる電源電圧回路が提案されている（特許文献１参照）。ここで、スイッチング素子４０７は、ＮチャネルＭＯＳＦＥＴからなり、スイッチング素子４０９は、ＰチャネルＭＯＳＦＥＴからなる。 As shown in FIG. 8, for example, as shown in FIG. 8, the power supply voltage detection circuit used in this technique is controlled on and off according to the reference voltage source 402 that outputs the reference voltage VREF based on the power supply voltage VCC and the magnitude of the reference voltage VREF. The switching element 407, the voltage divider 403 that outputs a voltage obtained by dividing the power supply voltage VCC by the resistors 410 and 411, the switching element 409 connected in series to the voltage divider 403, and the output of the reference voltage VREF and the voltage divider 403 There has been proposed a power supply voltage circuit that includes a comparator 404 that compares the voltage VS and can use the output of the comparator 404 as an enable signal that is input to an electronic circuit (see Patent Document 1). Here, the switching element 407 is composed of an N-channel MOSFET, and the switching element 409 is composed of a P-channel MOSFET.
　この電源電圧検出回路では、図９に示すように、電源電圧ＶＣＣが電圧Ｖ１以上になると、基準電圧源４０２の動作が安定してその出力電圧が基準電圧ＶＲＥＦになる。このとき、スイッチング素子４０７がオンし、抵抗４０８に電流が流れてスイッチング素子４０９がオンする。すると、分圧器４０３の出力電圧ＶＳが電源電圧に応じた大きさになる。 In this power supply voltage detection circuit, as shown in FIG. 9, when the power supply voltage VCC becomes equal to or higher than the voltage V1, the operation of the reference voltage source 402 is stabilized and the output voltage becomes the reference voltage VREF. At this time, the switching element 407 is turned on, a current flows through the resistor 408, and the switching element 409 is turned on. Then, the output voltage VS of the voltage divider 403 becomes a magnitude corresponding to the power supply voltage.
　その後、分圧器４０３から出力される電圧ＶＳが、電源電圧ＶＣＣの増加にともなって増加し、電源電圧ＶＣＣが電圧ＶＯＬに達すると、比較器４０４に入力される電圧ＶＲＥＦと電圧ＶＳとの大小関係が逆転し、比較器４０４の出力電圧ＶＯＵＴがＨｉｇｈレベルからＬｏｗレベル（０Ｖ）に切り替わる。ここで、電圧ＶＯＬは、分圧器４０３を構成する抵抗４１０，４１１の大きさの比を適宜設定することにより、電子回路の動作保証範囲内になるように設定している。そして、電子回路は、出力電圧ＶＯＵＴがＨｉｇｈレベルからＬｏｗレベルへの切り替わりを検出するタイミング（検出タイミング）で動作するので、誤動作が防止できる。 Thereafter, the voltage VS output from the voltage divider 403 increases as the power supply voltage VCC increases, and when the power supply voltage VCC reaches the voltage VOL, the magnitude relationship between the voltage VREF input to the comparator 404 and the voltage VS. Is reversed, and the output voltage VOUT of the comparator 404 is switched from the high level to the low level (0 V). Here, the voltage VOL is set so as to be within an operation guarantee range of the electronic circuit by appropriately setting a ratio of the magnitudes of the resistors 410 and 411 constituting the voltage divider 403. Since the electronic circuit operates at the timing (detection timing) at which the output voltage VOUT is detected from the high level to the low level, malfunction can be prevented.
　また、別の回路例として、図１０に示すように、電源電圧ＶＤＤに基づいて基準電圧ＶＲＥＦを出力する基準電圧源５００と、基準電圧ＶＲＥＦの大きさによりオンオフ制御されるスイッチング素子５０１と、電源電圧ＶＤＤを分圧してなる電圧ＶＧを出力する電圧出力回路５０２と、抵抗５０８に直列に接続されたスイッチング素子５０７とを備え、抵抗５０８の両端間に生じる電圧を電子回路のイネーブル信号として使用できる電源電圧検出回路が提案されている（特許文献２参照）。ここで、電圧出力回路５０２は、抵抗５０３と２つのダイオード５０５，５０６とを直列に接続してなるものであり、抵抗５０３とダイオード５０４との間の接続点に生じる電圧ＶＧを出力する。また、スイッチング素子５０１は、ＮチャネルＭＯＳＦＥＴからなり、スイッチング素子５０７は、ＰチャネルＭＯＳＦＥＴからなる。 As another circuit example, as shown in FIG. 10, a reference voltage source 500 that outputs a reference voltage VREF based on a power supply voltage VDD, a switching element 501 that is on / off controlled by the magnitude of the reference voltage VREF, A voltage output circuit 502 that outputs a voltage VG obtained by dividing the voltage VDD, and a switching element 507 connected in series to the resistor 508, can be used as an enable signal for the electronic circuit. A power supply voltage detection circuit has been proposed (see Patent Document 2). Here, the voltage output circuit 502 is formed by connecting a resistor 503 and two diodes 505 and 506 in series, and outputs a voltage VG generated at a connection point between the resistor 503 and the diode 504. The switching element 501 is composed of an N channel MOSFET, and the switching element 507 is composed of a P channel MOSFET.
　この電源電圧検出回路は、図１１に示すように、電源電圧ＶＤＤが電圧Ｖ１以上になると、基準電圧源５００の動作が安定してその出力電圧が基準電圧ＶＲＥＦになる。このときスイッチング素子５０１がオンし、抵抗５０３およびダイオード５０５，５０６に電流が流れる。ここで、ダイオード５０５，５０６での降下電圧Ｖ２は、電源電圧ＶＤＤによらずに略一定である。そして、電圧ＶＤＤが電圧ＶＯＬ以下のときは、スイッチング素子５０７はオフ状態であり電圧ＶＯＵＴはＬｏｗレベル（０Ｖ）であり、電源電圧ＶＤＤが電圧ＶＯＬ以上になると、スイッチング素子５０７がオンし、出力電圧ＶＯＵＴはＨｉｇｈレベルとなる。 As shown in FIG. 11, in the power supply voltage detection circuit, when the power supply voltage VDD becomes equal to or higher than the voltage V1, the operation of the reference voltage source 500 is stabilized and the output voltage becomes the reference voltage VREF. At this time, the switching element 501 is turned on, and a current flows through the resistor 503 and the diodes 505 and 506. Here, the voltage drop V2 at the diodes 505 and 506 is substantially constant regardless of the power supply voltage VDD. When the voltage VDD is equal to or lower than the voltage VOL, the switching element 507 is in the off state and the voltage VOUT is at the low level (0 V). When the power supply voltage VDD is equal to or higher than the voltage VOL, the switching element 507 is turned on. VOUT becomes a high level.
　ここで、電圧ＶＯＬは、抵抗５０３およびダイオード５０５，５０６により、電子回路の動作保証範囲内になるように設定している。そして、電子回路は、出力電圧ＶＯＵＴがＬｏｗレベルからＨｉｇｈレベルへの切り替わりを検出するタイミング（検出タイミング）で動作するので、誤動作が防止できる。 Here, the voltage VOL is set by the resistor 503 and the diodes 505 and 506 so as to be within the operation guarantee range of the electronic circuit. Since the electronic circuit operates at the timing (detection timing) at which the output voltage VOUT is detected from the low level to the high level, malfunction can be prevented.
特開２０１０－２２３７９６号公報JP 2010-223796 A 特開２００５－２７８０５６号公報JP 2005-278056 A
　ところで、図１０に示す電源電圧検出回路では、スイッチング素子５０１，５０７としてＭＯＳトランジスタを採用している。従って、スイッチング素子５０１，５０７それぞれのソース－ゲート間には、寄生容量Ｃ５１，Ｃ５２が存在する。一方、この類の電源電圧検出回路では、低消費電力化を考慮して、スイッチング素子５０１，５０７には数ｎＡ程度の電流しか流れないように設計されているのが一般的である。例えば、図１０に示す電源電圧検出回路では、スイッチング素子５０１については、基準電圧源５００の内部で電圧ＶＲＥＦの出力端子に直列に接続された抵抗成分（図示せず）が限流要素となっている。また、スイッチング素子５０７については、抵抗５０３やスイッチング素子５０１が限流要素となっている。 Incidentally, in the power supply voltage detection circuit shown in FIG. 10, MOS transistors are employed as the switching elements 501 and 507. Accordingly, parasitic capacitances C51 and C52 exist between the source and gate of the switching elements 501 and 507, respectively. On the other hand, this type of power supply voltage detection circuit is generally designed so that only a few nA current flows through the switching elements 501 and 507 in consideration of low power consumption. For example, in the power supply voltage detection circuit shown in FIG. 10, a resistance component (not shown) connected in series to the output terminal of the voltage VREF in the reference voltage source 500 becomes a current limiting element in the switching element 501. Yes. Further, regarding the switching element 507, the resistor 503 and the switching element 501 are current limiting elements.
　従って、スイッチング素子５０１の寄生容量Ｃ５１の充電期間およびスイッチング素子５０７の充電期間が検出タイミングに与える影響は大きい。 Therefore, the influence of the charging period of the parasitic capacitance C51 of the switching element 501 and the charging period of the switching element 507 on the detection timing is great.
　また、図１０に示す電源電圧検出回路では、基準電圧源５００から出力される基準電圧ＶＲＥＦをスイッチング素子５０１に印加して、寄生容量Ｃ５１を充電してスイッチング素子５０１をオンさせた後に、寄生容量Ｃ５２の充電が開始され、寄生容量Ｃ５２が充電されると、スイッチング素子５０７がオンする構成なので、寄生容量Ｃ５１と寄生容量Ｃ５２の充電期間だけ検出タイミングが遅れることになる。 In the power supply voltage detection circuit shown in FIG. 10, the reference voltage VREF output from the reference voltage source 500 is applied to the switching element 501, the parasitic capacitance C51 is charged and the switching element 501 is turned on. When the charging of C52 is started and the parasitic capacitance C52 is charged, the switching element 507 is turned on. Therefore, the detection timing is delayed by the charging period of the parasitic capacitance C51 and the parasitic capacitance C52.
　従って、図１０に示す電源電圧検出回路では、寄生容量Ｃ５１の充電期間と寄生容量Ｃ５２の充電期間が大きくなると、検出タイミングの遅延が大きくなってしまう。 Therefore, in the power supply voltage detection circuit shown in FIG. 10, when the charging period of the parasitic capacitor C51 and the charging period of the parasitic capacitor C52 are increased, the detection timing delay is increased.
　特に、電源投入直後等、電源電圧ＶＤＤが時間とともに連続的に増加していく場合、このような検出タイミングの遅延が生じると、検出しようとしている電圧よりも高い電圧を検出してしまうこととなり、検出誤差の要因となる。 In particular, when the power supply voltage VDD continuously increases with time, such as immediately after the power is turned on, when such a detection timing delay occurs, a voltage higher than the voltage to be detected is detected. It becomes a factor of detection error.
　また、図８に示す電源電圧検出回路でも、スイッチング素子４０７,４０９としてＭＯＳトランジスタを採用し、スイッチング素子４０７,４０９それぞれのソース－ゲート間には、寄生容量Ｃ４１,Ｃ４２が存在し、スイッチング素子４０７，４０９には数ｎＡ程度の電流しか流れないように設計されている。そして、基準電圧源４０２から出力される基準電圧ＶＲＥＦをスイッチング素子４０７に印加して、寄生容量Ｃ４１を充電してスイッチング素子４０７をオンさせた後に、寄生容量Ｃ４２の充電が開始され、寄生容量Ｃ４２が充電されると、スイッチング素子４０９がオンする構成なので、図１０に示す電源電圧検出回路と同様の課題を有することになる。 8 also employs MOS transistors as the switching elements 407 and 409, parasitic capacitances C41 and C42 exist between the source and gate of each of the switching elements 407 and 409, and the switching element 407 , 409 is designed so that only a current of several nA flows. Then, the reference voltage VREF output from the reference voltage source 402 is applied to the switching element 407, the parasitic capacitor C41 is charged to turn on the switching element 407, and then the charging of the parasitic capacitor C42 is started. Is charged, the switching element 409 is turned on, and thus has the same problem as the power supply voltage detection circuit shown in FIG.
　本発明は、上記事由に鑑みてなされたものであり、検出タイミングの遅延を抑制することができる電源電圧検出回路を提供する。 The present invention has been made in view of the above reasons, and provides a power supply voltage detection circuit capable of suppressing a delay in detection timing.
　本発明に係る電源電圧検出回路は、外部電源から電力が供給される電源線に接続され、当該電源線の電圧に基づいて電圧を出力する電圧出力回路と、電源線に接続され、基準電圧を出力する基準電圧回路と、電圧出力回路が出力する電圧が所定の閾値電圧以上になるとオンオフ状態が切り替わる第１のスイッチング素子と、第１のスイッチング素子に直列に接続され且つ基準電圧が供給されるとオンオフ状態が切り替わる第２のスイッチング素子と、第１のスイッチング素子に第２のスイッチング素子を直列に接続してなるスイッチ回路に直列に接続された負荷抵抗とを備え、スイッチ回路と負荷抵抗との直列回路の一端側が電源線に接続され且つ他端側が接地線に接続されてなり、負荷抵抗とスイッチ回路との接続点に生じる電圧を出力する。 A power supply voltage detection circuit according to the present invention is connected to a power supply line supplied with power from an external power supply, and outputs a voltage based on the voltage of the power supply line. A reference voltage circuit to be output; a first switching element that switches on and off when the voltage output from the voltage output circuit exceeds a predetermined threshold voltage; and a reference voltage that is connected in series to the first switching element and supplied with the reference voltage And a second switching element that switches between on and off states, and a load resistor connected in series to a switch circuit formed by connecting the second switching element to the first switching element in series, the switch circuit and the load resistance, One end of the series circuit is connected to the power line and the other end is connected to the ground line, and the voltage generated at the connection point between the load resistor and the switch circuit is output. That.
　本構成によれば、第１のスイッチング素子が電圧出力回路から出力される電圧に基づいてオンオフ状態が切り替わるのに対して、第２のスイッチング素子が電圧出力回路とは異なる基準電圧回路が出力する基準電圧に基づいてオンオフ状態が切り替わるので、オンオフ状態が切り替わるときにおける第１のスイッチング素子の寄生容量の充電期間と第２のスイッチング素子の寄生容量の充電期間とを重複させることができるから、検出タイミングの遅延を抑制することができる。 According to this configuration, the first switching element is switched on and off based on the voltage output from the voltage output circuit, whereas the second switching element outputs a reference voltage circuit different from the voltage output circuit. Since the ON / OFF state is switched based on the reference voltage, the charging period of the parasitic capacitance of the first switching element and the charging period of the parasitic capacitance of the second switching element when the ON / OFF state is switched can be detected. Timing delay can be suppressed.
　また、本発明に係る電源電圧検出回路は、上記第１のスイッチング素子が、上記電圧出力回路が出力する電圧が所定の閾値電圧以上になるとオフ状態からオン状態に切り替わり、上記第２のスイッチング素子が、上記基準電圧が出力されるとオフ状態からオン状態に切り替わるものであってもよい。 In the power supply voltage detection circuit according to the present invention, the first switching element switches from the off state to the on state when the voltage output from the voltage output circuit is equal to or higher than a predetermined threshold voltage, and the second switching element However, it may be switched from the off state to the on state when the reference voltage is output.
　また、本発明に係る電源電圧検出回路は、上記電圧出力回路が、上記電源線に接続された一方向性素子と、一端側が一方向性素子に接続され且つ他端側が接地されてなり上記接続点に生じる電圧をプルダウンするプルダウン用抵抗とを有し、一方向性素子とプルダウン用抵抗との接続点に生じる電圧を出力し、第１のスイッチング素子が、ドレインが電源線側に接続され且つゲートが電圧出力回路に接続されたＮチャネルＭＯＳトランジスタからなり、第２のスイッチング素子が、ドレインが第１のスイッチング素子のソースに接続され且つゲートが上記基準電圧回路側に接続されるとともに、ソースが接地されてなるＮチャネルＭＯＳトランジスタからなり、負荷抵抗が、直列回路の高電位側に接続されてなるものであってもよい。 In the power supply voltage detection circuit according to the present invention, the voltage output circuit includes the unidirectional element connected to the power supply line, one end connected to the unidirectional element, and the other end grounded. A pull-down resistor that pulls down a voltage generated at the point, and outputs a voltage generated at a connection point between the unidirectional element and the pull-down resistor, the first switching element has a drain connected to the power supply line side, and The N switching MOS transistor has a gate connected to the voltage output circuit, the second switching element has a drain connected to the source of the first switching element and a gate connected to the reference voltage circuit side. May be composed of an N-channel MOS transistor that is grounded and a load resistor connected to the high potential side of the series circuit.
　また、本発明に係る電源電圧検出回路は、上記一方向性素子が、上記電源線側にソースが接続され且つ上記プルダウン用抵抗側にゲートおよびドレインが共通接続されてなるＰチャネルＭＯＳトランジスタからなるものであってもよい。 In the power supply voltage detection circuit according to the present invention, the unidirectional element includes a P-channel MOS transistor in which a source is connected to the power supply line side and a gate and a drain are commonly connected to the pull-down resistor side. It may be a thing.
　本構成によれば、検出電圧はトランジスタの閾値電圧Ｖｔｈに依存させることができる。通常、電子回路はトランジスタで構成されることが多く、その動作保証範囲はトランジスタの閾値Ｖｔｈに依存するため、検出電圧をトランジスタの閾値Ｖｔｈに依存させることによって安定して電子回路を動作させることができる。 According to this configuration, the detection voltage can depend on the threshold voltage Vth of the transistor. Usually, an electronic circuit is often composed of transistors, and the guaranteed operation range depends on the threshold value Vth of the transistor. Therefore, the electronic circuit can be stably operated by making the detection voltage dependent on the threshold value Vth of the transistor. it can.
　また、本発明に係る電源電圧検出回路は、上記第１のスイッチング素子が、バックゲートが接地されてなるものであってもよい。 In the power supply voltage detection circuit according to the present invention, the first switching element may have a back gate grounded.
　本構成によれば、電子回路の動作保証範囲がトランジスタの閾値できまる場合、検出電圧が動作保証範囲ぎりぎりとならないように第１スイッチング素子の基板バイアス効果によって検出電圧にマージンをとることができる。 According to this configuration, when the operation guarantee range of the electronic circuit is equal to the threshold value of the transistor, a margin can be taken in the detection voltage by the substrate bias effect of the first switching element so that the detection voltage does not reach the limit of the operation guarantee range.
　また、本発明に係る電源電圧検出回路は、上記電圧出力回路が、上記電源線に一端側が接続されてなり上記接続点に生じる電圧をプルアップするプルアップ用抵抗と、
プルアップ用抵抗の他端側に接続された一方向性素子とを有し、プルアップ用抵抗と一方向性素子との接続点に生じる電圧を出力し、上記第２のスイッチング素子が、ソースが電源線に接続され且つゲートが上記基準電圧回路に接続されたＰチャネルＭＯＳトランジスタからなり、上記第１のスイッチング素子が、ソースが第２のスイッチング素子のドレインに接続され且つゲートが電圧出力回路に接続されるとともに、ドレインが上記負荷抵抗に接続されてなるＰチャネルＭＯＳトランジスタからなり、負荷抵抗が、上記直列回路の低電位側に接続されてなるものであってもよい。 In the power supply voltage detection circuit according to the present invention, the voltage output circuit is connected to the power supply line at one end, and pulls up a voltage generated at the connection point.
A unidirectional element connected to the other end of the pull-up resistor, outputs a voltage generated at a connection point between the pull-up resistor and the unidirectional element, and the second switching element has a source Comprises a P-channel MOS transistor having a gate connected to the reference voltage circuit, a gate connected to the drain of the second switching element, and a gate connected to the voltage output circuit. And a P channel MOS transistor whose drain is connected to the load resistor, and the load resistor is connected to the low potential side of the series circuit.
　本構成によれば、電源電圧検出回路の出力である制御電圧を反転させることができる。
また、本発明に係る電源電圧検出回路は、上記一方向性素子が、上記プルアップ用抵抗の他端側にドレインおよびゲートが共通接続され且つソースが接地されてなるＮチャネルＭＯＳトランジスタからなるものであってもよい。 According to this configuration, the control voltage that is the output of the power supply voltage detection circuit can be inverted.
In the power supply voltage detection circuit according to the present invention, the unidirectional element includes an N-channel MOS transistor in which a drain and a gate are commonly connected to the other end of the pull-up resistor and a source is grounded. It may be.
　本構成によれば、検出電圧はトランジスタの閾値電圧Ｖｔｈに依存させることができる。通常、電子回路はトランジスタで構成されることが多く、その動作保証範囲はトランジスタの閾値Ｖｔｈに依存するため、検出電圧をトランジスタの閾値Ｖｔｈに依存させることによって安定して電子回路を動作させることができる。 According to this configuration, the detection voltage can depend on the threshold voltage Vth of the transistor. Usually, an electronic circuit is often composed of transistors, and the guaranteed operation range depends on the threshold value Vth of the transistor. Therefore, the electronic circuit can be stably operated by making the detection voltage dependent on the threshold value Vth of the transistor. it can.
　また、本発明に係る電源電圧検出回路は、上記第１のスイッチング素子のバックゲートが上記電源線に接続されてなるものであってもよい。 In the power supply voltage detection circuit according to the present invention, the back gate of the first switching element may be connected to the power supply line.
　本構成によれば、電子回路の動作保証範囲がトランジスタの閾値できまる場合、検出電圧が動作保証範囲ぎりぎりとならないように第１スイッチング素子の基板バイアス効果によって検出電圧にマージンをとることができる。 According to this configuration, when the operation guarantee range of the electronic circuit is equal to the threshold value of the transistor, a margin can be taken in the detection voltage by the substrate bias effect of the first switching element so that the detection voltage does not reach the limit of the operation guarantee range.
　また、本発明は、上記の電源電圧検出回路から出力される電圧の大きさに基づいて基準電圧回路の起動状態を判別する電子回路であってもよい。 Further, the present invention may be an electronic circuit that determines the activation state of the reference voltage circuit based on the magnitude of the voltage output from the power supply voltage detection circuit.
　本構成によれば、電源電圧検出回路を判別回路として使用することで、基準電圧の起動状態を正確に判別できる。 According to this configuration, it is possible to accurately determine the starting state of the reference voltage by using the power supply voltage detection circuit as the determination circuit.
実施の形態１に係る電源電圧検出回路の回路図である。3 is a circuit diagram of a power supply voltage detection circuit according to the first embodiment. FIG. 実施の形態１に係る電源電圧検出回路の動作説明図である。FIG. 3 is an operation explanatory diagram of the power supply voltage detection circuit according to the first embodiment. 実施の形態１に係る電源電圧検出回路の動作を説明するためのタイムチャートである。3 is a time chart for explaining the operation of the power supply voltage detection circuit according to the first embodiment. 従来例に係る電源電圧検出回路の動作を説明するためのタイムチャートである。It is a time chart for demonstrating operation | movement of the power supply voltage detection circuit which concerns on a prior art example. 実施の形態２に係る電源電圧検出回路の回路図である。FIG. 6 is a circuit diagram of a power supply voltage detection circuit according to a second embodiment. 実施の形態２に係る電源電圧検出回路の動作説明図である。6 is an operation explanatory diagram of a power supply voltage detection circuit according to a second embodiment. FIG. 実施の形態２に係る電源電圧検出回路の動作を説明するためのタイムチャートである。6 is a time chart for explaining the operation of the power supply voltage detection circuit according to the second embodiment. 従来例に係る電源電圧検出回路の回路図である。It is a circuit diagram of the power supply voltage detection circuit which concerns on a prior art example. 従来例に係る電源電圧検出回路の動作説明図である。It is operation | movement explanatory drawing of the power supply voltage detection circuit which concerns on a prior art example. 他の従来例に係る電源電圧検出回路の回路図である。It is a circuit diagram of a power supply voltage detection circuit according to another conventional example. 他の従来例に係る電源電圧検出回路の動作説明図である。It is operation | movement explanatory drawing of the power supply voltage detection circuit based on another prior art example.
　＜実施の形態１＞
＜１＞構成
　本実施の形態に係る電源電圧検出回路は、図１に示すように、電圧出力回路１５１と、基準電圧回路１００と、分圧回路１５４と、イネーブル信号出力回路１５２とを備える。 <Embodiment 1>
<1> Configuration The power supply voltage detection circuit according to the present embodiment includes a voltage output circuit 151, a reference voltage circuit 100, a voltage dividing circuit 154, and an enable signal output circuit 152, as shown in FIG.
　電圧出力回路１５１は、外部電源から電力が供給されている電源線Ｌに接続され、当該電源線Ｌの電源電圧ＶＤＤに基づいて電圧ＶＧＶＤＤ１を出力するものである。具体的には、電圧出力回路１５１は、ＰチャネルＭＯＳトランジスタ１０４とプルダウン用の抵抗１０５とを備える。ＰチャネルＭＯＳトランジスタ１０４のソースは電源線Ｌに接続され、ドレインは抵抗１０５を介して接地線ＧＮＤに接続され、ゲートはドレインに接続されている。ＰチャネルＭＯＳトランジスタ１０４のドレインと抵抗１０５との接続点に生じる電圧が電圧ＶＧＶＤＤ１として出力される。なお、ＰチャネルＭＯＳトランジスタ１０４は、ゲートとドレインとが共通接続されており、いわゆるダイオード接続の状態になっている。 The voltage output circuit 151 is connected to the power supply line L to which power is supplied from the external power supply, and outputs the voltage VGVDD1 based on the power supply voltage VDD of the power supply line L. Specifically, the voltage output circuit 151 includes a P-channel MOS transistor 104 and a pull-down resistor 105. The source of the P-channel MOS transistor 104 is connected to the power supply line L, the drain is connected to the ground line GND through the resistor 105, and the gate is connected to the drain. A voltage generated at the connection point between the drain of P-channel MOS transistor 104 and resistor 105 is output as voltage VGVDD1. Note that the P-channel MOS transistor 104 has a gate and a drain connected in common, and is in a so-called diode-connected state.
　基準電圧回路１００は、電源線Ｌに接続され、基準電圧ＶＲＥＦを出力するものである。具体的には、基準電圧回路１００は、バンドギャップリファレンス等からなる。 The reference voltage circuit 100 is connected to the power line L and outputs the reference voltage VREF. Specifically, the reference voltage circuit 100 includes a band gap reference or the like.
　分圧回路１５４は、基準電圧ＶＲＥＦを分圧してなる電圧ＶＧＶＲＥＦ１を出力するものである。具体的には、分圧回路１５４は、基準電圧回路１００の出力端と接地線ＧＮＤとの間に接続された２つの抵抗１５４１，１５４２からなる直列回路を備える。 The voltage dividing circuit 154 outputs a voltage VGVREF1 obtained by dividing the reference voltage VREF. Specifically, the voltage dividing circuit 154 includes a series circuit including two resistors 1541 and 1542 connected between the output terminal of the reference voltage circuit 100 and the ground line GND.
　イネーブル信号出力回路１５２は、電子回路１５３にイネーブル信号を出力するものである。具体的には、イネーブル信号出力回路１５２は、第１のスイッチング素子１０２に第２のスイッチング素子１０３を直列に接続してなるスイッチ回路と、当該スイッチ回路に接続されたプルアップ用の抵抗（負荷抵抗）１０１とを備える。このスイッチ回路と抵抗１０１とからなる直列回路は、一端側が電源線Ｌに接続され他端側が接地線ＧＮＤに接続されている。このスイッチ回路と抵抗１０１との接続点に生じる電圧ＶＯＵＴは、電子回路１５３を駆動させるためのイネーブル信号として出力される。このイネーブル信号は、電源電圧ＶＤＤが電子回路１５３の動作保証範囲内であり且つ基準電圧回路１００が基準電圧ＶＲＥＦを出力している場合は、Ｌｏｗレベル（０Ｖ）となり、それ以外の場合はＨｉｇｈレベル（電源電圧ＶＤＤ）となる。 The enable signal output circuit 152 outputs an enable signal to the electronic circuit 153. Specifically, the enable signal output circuit 152 includes a switch circuit in which the second switching element 103 is connected in series to the first switching element 102, and a pull-up resistor (load) connected to the switch circuit. Resistance) 101. The series circuit including the switch circuit and the resistor 101 has one end connected to the power supply line L and the other end connected to the ground line GND. A voltage VOUT generated at a connection point between the switch circuit and the resistor 101 is output as an enable signal for driving the electronic circuit 153. This enable signal is at a low level (0 V) when the power supply voltage VDD is within the guaranteed operation range of the electronic circuit 153 and the reference voltage circuit 100 outputs the reference voltage VREF, and is at a high level otherwise. (Power supply voltage VDD).
　第１のスイッチング素子１０２は、ＮチャネルＭＯＳトランジスタから構成されている。そして、この第１のスイッチング素子１０２では、ドレインが電源線Ｌ側に接続され且つゲートが電圧出力回路１５１に接続されるとともに、ドレインが第２のスイッチング素子１０３のドレインに接続されている。このように第１のスイッチング素子１０２は、電圧出力回路１５１から出力される電圧ＶＧＶＤＤ１をモニタリングしており、電源電圧ＶＤＤが電子回路１５３の動作保証範囲内であればオン状態となり、動作保証範囲内にないときはオフ状態となる。 The first switching element 102 is composed of an N channel MOS transistor. In the first switching element 102, the drain is connected to the power supply line L side, the gate is connected to the voltage output circuit 151, and the drain is connected to the drain of the second switching element 103. As described above, the first switching element 102 monitors the voltage VGVDD1 output from the voltage output circuit 151. If the power supply voltage VDD is within the operation guarantee range of the electronic circuit 153, the first switching element 102 is turned on. When it is not, it is turned off.
　第２のスイッチング素子１０３は、ＮチャネルＭＯＳトランジスタから構成されている。そして、この第２のスイッチング素子１０３では、ドレインが第１のスイッチング素子１０２のソースに接続され且つゲートが基準電圧回路１００側に接続されるとともに、ソースが接地線ＧＮＤに接続されている。このように第２のスイッチング素子１０３は、基準電圧回路１００から出力される基準電圧ＶＲＥＦをモニタリングしており、基準電圧回路１００が基準電圧ＶＲＥＦを出力していればオン状態となり、基準電圧ＶＲＥＦを出力していないときはオフ状態となる。 The second switching element 103 is composed of an N channel MOS transistor. In the second switching element 103, the drain is connected to the source of the first switching element 102, the gate is connected to the reference voltage circuit 100 side, and the source is connected to the ground line GND. As described above, the second switching element 103 monitors the reference voltage VREF output from the reference voltage circuit 100. When the reference voltage circuit 100 outputs the reference voltage VREF, the second switching element 103 is turned on, and the reference voltage VREF is supplied. When not outputting, it is turned off.
　つまり、第１のスイッチング素子１０２に直列に接続されてなる第２のスイッチング素子１０３からなるスイッチ回路に、プルアップ用の抵抗１０１を接続してなる構成に基づいて、電源電圧ＶＤＤが動作保証範囲内であり且つ基準電圧ＶＲＥＦが出力されている状態では、第１のスイッチング素子１０２および第２のスイッチング素子１０３が共にオン状態となり、スイッチ回路と抵抗１０１との間の接続点の電位が略接地線ＧＮＤと同電位となり、イネーブル信号（出力電圧ＶＯＵＴ）がＬｏｗレベルとなる。一方、電源電圧ＶＤＤが動作保証範囲内にないか、または、基準電圧ＶＲＥＦが出力されていない状態では、第１のスイッチング素子１０２または第２のスイッチング素子１０３のいずれかがオフ状態であり、抵抗１０１には電流が流れずスイッチ回路と抵抗１０１との間の接続点の電位が略電源線Ｌと同電位となり、イネーブル信号がＨｉｇｈレベルとなる。 In other words, the power supply voltage VDD is within the operation guarantee range based on the configuration in which the pull-up resistor 101 is connected to the switch circuit including the second switching element 103 connected in series to the first switching element 102. And the reference voltage VREF is output, both the first switching element 102 and the second switching element 103 are turned on, and the potential at the connection point between the switch circuit and the resistor 101 is substantially grounded. The potential becomes the same as that of the line GND, and the enable signal (output voltage VOUT) becomes the Low level. On the other hand, when the power supply voltage VDD is not within the guaranteed operating range or the reference voltage VREF is not output, either the first switching element 102 or the second switching element 103 is in an off state, and the resistance No current flows through 101, and the potential of the connection point between the switch circuit and the resistor 101 becomes substantially the same as that of the power supply line L, and the enable signal becomes High level.
　ところで、電源電圧検出回路は、電子回路１５３にイネーブル信号を入力する。電子回路１５３は、電源線Ｌと接地線ＧＮＤとに接続され、電源線Ｌから電源電圧ＶＤＤの供給を受けるとともに、基準電圧回路１００から電圧ＶＲＥＦの供給を受ける。この電子回路１５３は、電源電圧ＶＤＤが動作保証範囲内であり且つ基準電圧回路１００が基準電圧ＶＲＥＦを出力している場合に正常に駆動する。そして、電子回路１５３は、入力されるイネーブル信号（電源電圧検出回路の出力電圧ＶＯＵＴ）をモニタリングし、当該イネーブル信号がＨｉｇｈレベルからＬｏｗレベルに変化したことを検知すると駆動する。
＜２＞動作
　本実施の形態に係る電源電圧検出回路は、第１のスイッチング素子１０２と、第２のスイッチング素子１０３がともにオンすることで、イネーブル信号がＨｉｇｈレベルからＬｏｗレベルに変化する。以下、本実施の形態に係る電源電圧検出回路の動作について図１および図２を用いて詳細に説明する。 Incidentally, the power supply voltage detection circuit inputs an enable signal to the electronic circuit 153. The electronic circuit 153 is connected to the power supply line L and the ground line GND, receives the power supply voltage VDD from the power supply line L, and receives the voltage VREF from the reference voltage circuit 100. The electronic circuit 153 is normally driven when the power supply voltage VDD is within the guaranteed operating range and the reference voltage circuit 100 outputs the reference voltage VREF. The electronic circuit 153 monitors the input enable signal (the output voltage VOUT of the power supply voltage detection circuit) and drives when it detects that the enable signal has changed from the High level to the Low level.
<2> Operation In the power supply voltage detection circuit according to the present embodiment, when both the first switching element 102 and the second switching element 103 are turned on, the enable signal changes from the High level to the Low level. Hereinafter, the operation of the power supply voltage detection circuit according to the present embodiment will be described in detail with reference to FIGS.
　電源電圧ＶＤＤがＰチャネルＭＯＳトランジスタ１０４のゲート閾値電圧Ｖｔｈ未満の場合、分圧回路１５４が出力する電圧ＶＧＶＲＥＦ１は略０Ｖとなっている。また、ＰチャネルＭＯＳトランジスタ１０４は、オフ状態にあり、抵抗１０５には電流が流れないため電圧ＶＧＶＤＤ１も略０Ｖになっている。これにより、第１のスイッチング素子１０２と第２のスイッチング素子１０３は、共にオフ状態にあり、電源電圧検出回路の出力端子ＶＯＵＴは、電源線Ｌの電源電圧ＶＤＤがそのまま出力されることになる。 When the power supply voltage VDD is lower than the gate threshold voltage Vth of the P-channel MOS transistor 104, the voltage VGVREF1 output from the voltage dividing circuit 154 is approximately 0V. Since P channel MOS transistor 104 is in an off state and no current flows through resistor 105, voltage VGVDD1 is also approximately 0V. As a result, the first switching element 102 and the second switching element 103 are both in the off state, and the power supply voltage VDD of the power supply line L is output as it is to the output terminal VOUT of the power supply voltage detection circuit.
　ゲート・ソース間電圧ＶＧＳは、第１のスイッチング素子１０２のゲート閾値電圧Ｖｔｈよりもまだ低いので第１のスイッチング素子１０２はオフ状態を維持する。 Since the gate-source voltage VGS is still lower than the gate threshold voltage Vth of the first switching element 102, the first switching element 102 maintains the off state.
　また、電源電圧ＶＤＤが電圧２Ｖｔｈの場合、ＰチャネルＭＯＳトランジスタ１０４のソース－ドレイン間の電圧降下がゲート閾値電圧Ｖｔｈに等しいので、電圧ＶＧＶＤＤ１がゲート閾値電圧Ｖｔｈに等しくなる。そして、第１のスイッチング素子１０２がオン状態となる。このとき、第１のスイッチング素子１０２および第２のスイッチング素子１０３が共にオン状態となっていることから、出力電圧ＶＯＵＴは略０Ｖとなる。 When the power supply voltage VDD is 2 Vth, the voltage drop between the source and drain of the P-channel MOS transistor 104 is equal to the gate threshold voltage Vth, so that the voltage VGVDD1 is equal to the gate threshold voltage Vth. Then, the first switching element 102 is turned on. At this time, since both the first switching element 102 and the second switching element 103 are in the on state, the output voltage VOUT is substantially 0V.
　そして、電源電圧ＶＤＤが、電子回路１５３の動作保証範囲である電圧２Ｖｔｈ以上に維持される限り、出力電圧ＶＯＵＴは０Ｖで維持されることになる。 As long as the power supply voltage VDD is maintained at the voltage 2Vth or higher which is the operation guarantee range of the electronic circuit 153, the output voltage VOUT is maintained at 0V.
　基準電圧回路１００から一定の基準電圧ＶＲＥＦが出力される状態になった後に、出力電圧ＶＯＵＴが出力されるので、電子回路１５３が、電源電圧ＶＤＤが電子回路１５３の動作保証範囲内にも関わらず基準電圧ＶＲＥＦが入力されていない状態で誤動作してしまうことを防止できる。
＜３＞本実施の形態と従来例との比較
　本実施の形態に係る電源電圧検出回路の時系列動作を図３に示し、図１０に示す従来例に係る電源電圧検出回路の時系列動作を図４に示す。図３および図４では、電源投入直後等、電源電圧ＶＤＤが時間とともに単調増加していく場合（図３（ａ）および図４（ａ）参照）を例に挙げて説明する。 Since the output voltage VOUT is output after the reference voltage circuit 100 enters the state in which the constant reference voltage VREF is output, the electronic circuit 153 has the power supply voltage VDD within the guaranteed operation range of the electronic circuit 153. It is possible to prevent malfunctions in a state where the reference voltage VREF is not input.
<3> Comparison between this Embodiment and Conventional Example FIG. 3 shows the time series operation of the power supply voltage detection circuit according to this embodiment, and the time series operation of the power supply voltage detection circuit according to the conventional example shown in FIG. As shown in FIG. 3 and 4, the case where the power supply voltage VDD monotonously increases with time, such as immediately after power-on (see FIGS. 3A and 4A), will be described as an example.
　まず、図１０に示す従来例に係る電源電圧検出回路の動作について説明する。 First, the operation of the power supply voltage detection circuit according to the conventional example shown in FIG. 10 will be described.
　電源電圧ＶＤＤが、時刻Ｔ（Ｖ１）に電圧Ｖ１に達すると、基準電圧源５００が起動する（図４（ｂ）参照）。このとき、スイッチング素子５０１のソース－ゲート間に電圧Ｖ１が印加され、スイッチング素子５０１がオンする（図４（ｃ）参照）。 When the power supply voltage VDD reaches the voltage V1 at time T (V1), the reference voltage source 500 is activated (see FIG. 4B). At this time, the voltage V1 is applied between the source and gate of the switching element 501, and the switching element 501 is turned on (see FIG. 4C).
　そして、電源電圧ＶＤＤが更に上昇して電圧Ｖ２に等しくなると、電圧ＶＧが電圧Ｖ２で略一定に維持される（図４（ｅ）参照）。 When the power supply voltage VDD further rises and becomes equal to the voltage V2, the voltage VG is maintained substantially constant at the voltage V2 (see FIG. 4 (e)).
　その後、電源電圧ＶＤＤの上昇に伴って、抵抗５０３の両端間の電圧（ＶＤＤ－ＶＧ）が上昇していく（図４（ｄ）参照）。このとき、スイッチング素子５０７のソース－ゲート間電圧ＶＳＧ（５０７）も上昇していく（図４（ｆ））。そして、このソース－ゲート間電圧ＶＳＧ（５０７）が、スイッチング素子５０７のゲート閾値電圧Ｖｔｈに達するとスイッチング素子５０７がオンし、電圧ＶＯＵＴ（イネーブル信号）が０Ｖから電圧ＶＯＬ以上の大きさの電圧に変化する（図４（ｇ））。 Thereafter, as the power supply voltage VDD increases, the voltage (VDD−VG) between both ends of the resistor 503 increases (see FIG. 4D). At this time, the source-gate voltage VSG (507) of the switching element 507 also increases (FIG. 4 (f)). When the source-gate voltage VSG (507) reaches the gate threshold voltage Vth of the switching element 507, the switching element 507 is turned on, and the voltage VOUT (enable signal) changes from 0 V to a voltage greater than or equal to the voltage VOL. It changes (FIG. 4 (g)).
　図４（ｂ）に示すように、時刻Ｔ（Ｖ１）において、スイッチング素子５０１のゲートに基準電圧ＶＲＥＦがステップ状に入力されたとしても、スイッチング素子５０１のゲート－ソース間電圧ＶＧＳ（５０１）が実際に基準電圧ＶＲＥＦに到達する時刻は、寄生容量Ｃ５１の充電期間Ｔ０２だけ時刻Ｔ（Ｖ１）よりも遅れてしまう（図４（ｈ）参照）。また、図４（ｄ）に示すように、スイッチング素子５０１のゲート－ソース間電圧ＶＧＳ（５０１）がゲート閾値電圧Ｖｔｈに到達し、スイッチング素子５０１がオンすることにより寄生容量Ｃ５２の放電が開始する時刻Ｔ（ＣＳ）とすると、時刻Ｔ（ＣＳ）から抵抗５０３の両端間の電圧ＶＤＤ－ＶＧが漸増し、時刻Ｔ（ＶＯＬ）に電圧ＶＯＬに到達するまでの時間（Ｔ（ＶＯＬ）－Ｔ（ＣＳ））に比べて、寄生容量Ｃ５２を放電することにより、スイッチング素子５０７のソース－ゲート間電圧ＶＳＧ（５０７）が実際に電圧ＶＯＬに到達するまでの期間Ｔ０１は長くなってしまう（図４（ｈ）参照）。 As shown in FIG. 4B, even when the reference voltage VREF is input to the gate of the switching element 501 in a step shape at time T (V1), the gate-source voltage VGS (501) of the switching element 501 is The time when the reference voltage VREF is actually reached is delayed from the time T (V1) by the charging period T02 of the parasitic capacitance C51 (see FIG. 4H). As shown in FIG. 4D, the gate-source voltage VGS (501) of the switching element 501 reaches the gate threshold voltage Vth, and the switching element 501 is turned on to start discharging the parasitic capacitance C52. Assuming time T (CS), the voltage VDD-VG between both ends of the resistor 503 gradually increases from time T (CS) and reaches the time when the voltage VOL is reached at time T (VOL) (T (VOL) −T ( CS)) by discharging the parasitic capacitance C52, the period T01 until the source-gate voltage VSG (507) of the switching element 507 actually reaches the voltage VOL becomes longer (FIG. 4 ( h)).
　また、この電源電圧検出回路では、スイッチング素子５０７のソース－ゲート間に電圧が印加されるためには、スイッチング素子５０１がオン状態となっていることが前提となっているので、スイッチング素子５０１の寄生容量Ｃ５１の充電期間Ｔ０２とスイッチング素子５０７の寄生容量Ｃ５２の放電期間Ｔ０１とは重複することがない。 Further, in this power supply voltage detection circuit, since it is assumed that the switching element 501 is in an ON state in order to apply a voltage between the source and gate of the switching element 507, the switching element 501 The charging period T02 of the parasitic capacitance C51 and the discharging period T01 of the parasitic capacitance C52 of the switching element 507 do not overlap.
　従って、図４（ｃ）および図４（ｆ）に示すように、電源投入後から電圧ＶＯＵＴが出力されるまでの時間（以下、「検出時間」と称す。）Ｔｄ０は、電源電圧ＶＤＤが０から実際に電圧ＶＯＬに到達するまでの時間（以下、「実到達時間」と称す。）Ｔ０に比べて、スイッチング素子５０１の寄生容量Ｃ５１を充電する期間Ｔ０２と、寄生容量Ｃ５２の放電に起因する遅延時間との両方に相当するだけ長くなり、その分、電圧ＶＯＬの検出タイミングが遅れることになる。 Therefore, as shown in FIGS. 4C and 4F, the time from when the power is turned on until the voltage VOUT is output (hereinafter referred to as “detection time”) Td0 is the time when the power supply voltage VDD is 0. Compared to the time T0 until the voltage VOL is actually reached (hereinafter referred to as “actual arrival time”) T0, the period T02 of charging the parasitic capacitance C51 of the switching element 501 and the discharge of the parasitic capacitance C52 are caused. It becomes longer corresponding to both the delay time and the detection timing of the voltage VOL is delayed by that amount.
　次に、本実施の形態に係る電源電圧検出回路の動作について説明する。 Next, the operation of the power supply voltage detection circuit according to this embodiment will be described.
　電源電圧ＶＤＤが時刻Ｔ（Ｖｔｈ）にゲート閾値電圧Ｖｔｈに達すると、ＰチャネルＭＯＳトランジスタ１０４がオンする。その後、電源電圧ＶＤＤが上昇するとともに抵抗１０５に流れる電流が増加し、それに伴って電圧ＶＧＶＤＤ１も上昇していく（図３（ｅ）参照）。一方、抵抗１０９の両端間の電圧（ＶＤＤ－ＶＧＶＤＤ２）の大きさは、電源電圧ＶＤＤが上昇しても略一定に保たれる（図３（ｄ）参照）。 When the power supply voltage VDD reaches the gate threshold voltage Vth at time T (Vth), the P-channel MOS transistor 104 is turned on. Thereafter, the power supply voltage VDD rises and the current flowing through the resistor 105 increases, and the voltage VGVDD1 rises accordingly (see FIG. 3E). On the other hand, the magnitude of the voltage across the resistor 109 (VDD−VGVDD2) is kept substantially constant even when the power supply voltage VDD rises (see FIG. 3D).
　そして、電源電圧ＶＤＤが時刻Ｔ（Ｖ１）に電圧Ｖ１に達すると、基準電圧源１００が起動して分圧回路１５４が正の電圧ＶＧＶＲＥＦ１を出力する（図３（ｂ）参照）。このとき、第２のスイッチング素子１０３は、ソース－ゲート間電圧ＶＧＳ（１０３）がゲート閾値電圧を超えるとオンする（図３（ｃ）参照）。その後、電源電圧ＶＤＤが時刻Ｔ（２Ｖｔｈ）に電子回路１５３の動作保証範囲内である電圧２Ｖｔｈに達すると、第１のスイッチング素子１０２がオンし、電圧ＶＯＵＴ（イネーブル信号）が電圧２Ｖｔｈ程度の大きさの電圧から０Ｖに変化する（図３（ｇ）参照）。 When the power supply voltage VDD reaches the voltage V1 at time T (V1), the reference voltage source 100 is activated and the voltage dividing circuit 154 outputs the positive voltage VGVREF1 (see FIG. 3B). At this time, the second switching element 103 is turned on when the source-gate voltage VGS (103) exceeds the gate threshold voltage (see FIG. 3C). Thereafter, when the power supply voltage VDD reaches the voltage 2Vth that is within the operation guarantee range of the electronic circuit 153 at time T (2Vth), the first switching element 102 is turned on, and the voltage VOUT (enable signal) is as large as the voltage 2Vth. This voltage changes to 0 V (see FIG. 3G).
　ここで、図３（ｂ）および（ｃ）に示すように、分圧回路１５４から第２のスイッチング素子１０３のゲートへのステップ状の入力に対して、第２のスイッチング素子１０３のソース－ゲート間電圧ＶＧＳ（１０３）は、期間Ｔ１１だけ遅れる。これは、第２のスイッチング素子１０３のソース－ゲート間の寄生容量Ｃ１２を充電するのに期間Ｔ１２だけ要することによる。 Here, as shown in FIGS. 3B and 3C, the source-gate of the second switching element 103 with respect to the step-like input from the voltage dividing circuit 154 to the gate of the second switching element 103 The inter-voltage VGS (103) is delayed by the period T11. This is because it takes only the period T12 to charge the parasitic capacitance C12 between the source and gate of the second switching element 103.
　また、抵抗１０５の両端間の電圧ＶＧＶＤＤ１は、図３（ｅ）および（ｆ）に示すように、時刻Ｔ（２Ｖｔｈ）よりも早い時刻に電圧２Ｖｔｈに達するが、第１のスイッチング素子１０２のソース－ゲート間の寄生容量Ｃ１１を充電する必要がある分だけ遅れることになる。そして、寄生容量Ｃ１１を充電している時間は、第１のスイッチング素子１０２のソース－ゲート間電圧ＶＧＳ（１０２）が０Ｖからゲート閾値電圧Ｖｔｈに達するまでの間の期間Ｔ１１ということになる（図３（ｈ）参照）。 Further, as shown in FIGS. 3E and 3F, the voltage VGVDD1 across the resistor 105 reaches the voltage 2Vth earlier than the time T (2Vth), but the source of the first switching element 102 -Delay due to the need to charge the parasitic capacitance C11 between the gates. The time during which the parasitic capacitance C11 is charged is a period T11 during which the source-gate voltage VGS (102) of the first switching element 102 reaches 0 to the gate threshold voltage Vth (FIG. 3 (h)).
　ところで、本実施の形態に係る電源電圧検出回路では、図３（ｈ）に示すように、図１０に示す従来例に係る電源電圧検出回路と異なり、第１のスイッチング素子１０２の寄生容量Ｃ１１の充電期間Ｔ１１と、第２のスイッチング素子１０３の寄生容量Ｃ１２の充電期間Ｔ１２とを重複させている。充電時間Ｔ１１がＴ１２よりも長いとすると、検出時間Ｔｄは、電圧２Ｖｔｈに到達するまでの実到達時間Ｔ１に比べて、第１のスイッチング素子１０２の寄生容量Ｃ１１の充電に起因する遅延時間に相当するだけ長くなるが、第２のスイッチング素子１０３の寄生容量Ｃ１２の充電期間Ｔ１２の影響を受けないことになる。 Incidentally, in the power supply voltage detection circuit according to the present embodiment, as shown in FIG. 3 (h), unlike the power supply voltage detection circuit according to the conventional example shown in FIG. 10, the parasitic capacitance C11 of the first switching element 102 is reduced. The charging period T11 overlaps the charging period T12 of the parasitic capacitance C12 of the second switching element 103. If the charging time T11 is longer than T12, the detection time Td corresponds to a delay time due to charging of the parasitic capacitance C11 of the first switching element 102, compared to the actual arrival time T1 until the voltage 2Vth is reached. However, it is not affected by the charging period T12 of the parasitic capacitance C12 of the second switching element 103.
　従って、図１０に示す従来例の電源電圧検出回路に比べて、第２のスイッチング素子１０３の寄生容量Ｃ１２の充電期間Ｔ１２に相当する時間だけ、電源電圧ＶＤＤが電圧２Ｖｔｈに達したことを検出するタイミングの遅延を抑制することができる。 Therefore, as compared with the power supply voltage detection circuit of the conventional example shown in FIG. 10, it is detected that the power supply voltage VDD has reached the voltage 2Vth for a time corresponding to the charging period T12 of the parasitic capacitance C12 of the second switching element 103. Timing delay can be suppressed.
　また、Ｔ１２がＴ１１よりも長い場合も同様に、充電期間Ｔ１２に充電期間Ｔ１１が含まれるようになるので、検出タイミングの遅延による検出誤差を低減することができる。 Similarly, when T12 is longer than T11, the charging period T12 is included in the charging period T12, so that the detection error due to the detection timing delay can be reduced.
　なお、本実施の形態に係る電源電圧検出回路は、オペアンプ等の比較器を使用しない構成としているので、図１０に示すような比較器を用いた電源電圧検出回路に比べて回路規模を縮小することができ、低消費電力化を図れる。
＜実施の形態２＞
　本実施の形態に係る電源電圧検出回路は、概して言えば、実施の形態１に係る電源電圧検出回路について、電圧出力回路１５１のＰチャネルＭＯＳトランジスタ１０４をＮチャネルＭＯＳトランジスタに変更し、イネーブル信号出力回路１５２の２つのＮチャネルＭＯＳトランジスタ１０２，１０３をＰチャネルＭＯＳトランジスタに変更した構成である。そして、電源電圧ＶＤＤが動作保証範囲内であり且つ基準電圧回路１００が基準電圧ＶＲＥＦを出力している場合には、イネーブル信号がＨｉｇｈレベルとなり、それ以外の場合にはＬｏｗレベルとなる。以下、構成について詳細を述べる。
＜１＞構成
　本実施の形態に係る電源電圧検出回路は、図５に示すように、電圧出力回路２５１と、基準電圧回路１００と、分圧回路２５４と、イネーブル信号出力回路２５２とを備える。 Since the power supply voltage detection circuit according to the present embodiment is configured not to use a comparator such as an operational amplifier, the circuit scale is reduced as compared with a power supply voltage detection circuit using a comparator as shown in FIG. Therefore, low power consumption can be achieved.
<Embodiment 2>
Generally speaking, the power supply voltage detection circuit according to the present embodiment is the same as the power supply voltage detection circuit according to the first embodiment except that the P-channel MOS transistor 104 of the voltage output circuit 151 is changed to an N-channel MOS transistor, and an enable signal output is performed. In this configuration, the two N- channel MOS transistors 102 and 103 of the circuit 152 are changed to P-channel MOS transistors. When the power supply voltage VDD is within the guaranteed operation range and the reference voltage circuit 100 outputs the reference voltage VREF, the enable signal is at a high level, and otherwise, it is at a low level. Details of the configuration will be described below.
<1> Configuration The power supply voltage detection circuit according to the present embodiment includes a voltage output circuit 251, a reference voltage circuit 100, a voltage dividing circuit 254, and an enable signal output circuit 252 as shown in FIG.
　電圧出力回路２５１は、外部電源から電力が供給されている電源線Ｌに接続され、当該電源線Ｌの電源電圧ＶＤＤに基づいて電圧ＶＧＶＤＤ２を出力するものである。具体的には、電圧出力回路２５１は、ＮチャネルＭＯＳトランジスタ１０４とプルアップ用の抵抗１１０とを備える。ＮチャネルＭＯＳトランジスタ１１０のソースは接地線ＧＮＤに接続され、ドレインは抵抗１０９を介して電源線Ｌに接続され、ゲートはドレインに接続されている。ＮチャネルＭＯＳトランジスタ１１０のドレインと抵抗１０９との接続点に生じる電圧が電圧ＶＧＶＤＤ２として出力される。なお、ＮチャネルＭＯＳトランジスタ１１０は、ゲートとドレインとが共通接続されており、いわゆるダイオード接続の状態になっている。 The voltage output circuit 251 is connected to the power supply line L to which power is supplied from the external power supply, and outputs the voltage VGVDD2 based on the power supply voltage VDD of the power supply line L. Specifically, the voltage output circuit 251 includes an N-channel MOS transistor 104 and a pull-up resistor 110. The source of the N-channel MOS transistor 110 is connected to the ground line GND, the drain is connected to the power supply line L via the resistor 109, and the gate is connected to the drain. A voltage generated at the connection point between the drain of N-channel MOS transistor 110 and resistor 109 is output as voltage VGVDD2. N channel MOS transistor 110 has a gate and a drain connected in common, and is in a so-called diode connection state.
　基準電圧回路１００は、実施の形態１と同様であり、電源線Ｌに接続され、基準電圧ＶＲＥＦを出力するものである。 The reference voltage circuit 100 is the same as that of the first embodiment, and is connected to the power supply line L and outputs the reference voltage VREF.
　分圧回路２５４は、基準電圧ＶＲＥＦを分圧してなる電圧ＶＧＶＲＥＦ２を出力するものである。具体的には、分圧回路２５４は、基準電圧回路１００の出力端と接地線ＧＮＤとの間に接続された２つの抵抗２５４１，２５４２からなる直列回路を備える。 The voltage dividing circuit 254 outputs a voltage VGVREF2 obtained by dividing the reference voltage VREF. Specifically, the voltage dividing circuit 254 includes a series circuit including two resistors 2541 and 2542 connected between the output terminal of the reference voltage circuit 100 and the ground line GND.
　イネーブル信号出力回路２５２は、電子回路２５３にイネーブル信号を出力するものである。具体的には、イネーブル信号出力回路２５２は、第１のスイッチング素子１０７に第２のスイッチング素子１０６を直列に接続してなるスイッチ回路と、当該スイッチ回路に接続された抵抗（負荷抵抗）１０８とを備える。このスイッチ回路と抵抗１０８とからなる直列回路は、一端側が電源線Ｌに接続され他端側が接地線ＧＮＤに接続されている。また、２つの抵抗２５４１，２５４２の間の接続点と、第２のスイッチング素子１０６のゲートとの間には、インバータ２５５が接続されている。このスイッチ回路と抵抗１０８との接続点に生じる電圧ＶＯＵＴは、電子回路２５３を駆動させるためのイネーブル信号として出力される。このイネーブル信号は、電源電圧ＶＤＤが電子回路１５３の動作保証範囲内であり且つ基準電圧回路１００が基準電圧ＶＲＥＦを出力している場合は、Ｈｉｇｈレベル（電源電圧ＶＤＤ）となり、それ以外の場合はＬｏｗレベル（０Ｖ）となる。 The enable signal output circuit 252 outputs an enable signal to the electronic circuit 253. Specifically, the enable signal output circuit 252 includes a switch circuit in which the second switching element 106 is connected in series to the first switching element 107, and a resistor (load resistance) 108 connected to the switch circuit. Is provided. The series circuit including the switch circuit and the resistor 108 has one end connected to the power supply line L and the other end connected to the ground line GND. In addition, an inverter 255 is connected between a connection point between the two resistors 2541 and 2542 and the gate of the second switching element 106. A voltage VOUT generated at a connection point between the switch circuit and the resistor 108 is output as an enable signal for driving the electronic circuit 253. This enable signal is at a high level (power supply voltage VDD) when the power supply voltage VDD is within the operation guarantee range of the electronic circuit 153 and the reference voltage circuit 100 outputs the reference voltage VREF, and otherwise. It becomes Low level (0V).
　第１のスイッチング素子１０７は、ＰチャネルＭＯＳトランジスタから構成されている。そして、この第１のスイッチング素子１０７では、ドレインが接地線Ｌに抵抗１０８を介して接続され且つゲートが電圧出力回路２５１に接続されるとともに、ソースが第２のスイッチング素子１０６のドレインに接続されている。このように第１のスイッチング素子１０７は、電圧出力回路２５１から出力される電圧ＶＧＶＤＤ２をモニタリングしており、電源電圧ＶＤＤが電子回路２５３の動作保証範囲内であればオン状態となり、動作保証範囲内にないときはオフ状態となる。 The first switching element 107 is composed of a P-channel MOS transistor. In the first switching element 107, the drain is connected to the ground line L via the resistor 108, the gate is connected to the voltage output circuit 251, and the source is connected to the drain of the second switching element 106. ing. As described above, the first switching element 107 monitors the voltage VGVDD2 output from the voltage output circuit 251, and is turned on when the power supply voltage VDD is within the operation guarantee range of the electronic circuit 253, and is within the operation guarantee range. When it is not, it is turned off.
　第２のスイッチング素子１０６は、ＰチャネルＭＯＳトランジスタから構成されている。そして、この第２のスイッチング素子１０６では、ドレインが第１のスイッチング素子１０２のソースに接続され且つゲートが基準電圧回路１００に接続されるとともに、ソースが電源線Ｌに接続されている。このように第２のスイッチング素子１０６は、基準電圧回路１００から出力される基準電圧ＶＲＥＦをモニタリングしており、基準電圧回路１００が基準電圧ＶＲＥＦを出力していればオン状態となり、基準電圧ＶＲＥＦを出力していないときはオフ状態となる。 The second switching element 106 is composed of a P-channel MOS transistor. In the second switching element 106, the drain is connected to the source of the first switching element 102, the gate is connected to the reference voltage circuit 100, and the source is connected to the power supply line L. As described above, the second switching element 106 monitors the reference voltage VREF output from the reference voltage circuit 100. If the reference voltage circuit 100 outputs the reference voltage VREF, the second switching element 106 is turned on, and the reference voltage VREF is reduced. When not outputting, it is turned off.
　つまり、第１のスイッチング素子１０７に直列に接続されてなる第２のスイッチング素子１０６からなるスイッチ回路に、プルダウン用の抵抗１０８を接続してなる構成に基づいて、電源電圧ＶＤＤが動作保証範囲内であり且つ基準電圧ＶＲＥＦが出力されている状態では、第１のスイッチング素子１０７および第２のスイッチング素子１０６が共にオン状態となり、スイッチ回路と抵抗１０８との間の接続点の電位が略電源線ＧＮＤと同電位となり、イネーブル信号（出力電圧ＶＯＵＴ）がＨｉｇｈレベルとなる。一方、電源電圧ＶＤＤが動作保証範囲内にないか、または、基準電圧ＶＲＥＦが出力されていない状態では、第１のスイッチング素子１０７または第２のスイッチング素子１０６のいずれかがオフ状態であり、抵抗１０８には電流が流れずスイッチ回路と抵抗１０８との間の接続点の電位が略接地線ＧＮＤと同電位となり、イネーブル信号がＬｏｗレベルとなる。 That is, the power supply voltage VDD is within the guaranteed operating range based on the configuration in which the pull-down resistor 108 is connected to the switch circuit including the second switching element 106 connected in series to the first switching element 107. In the state where the reference voltage VREF is output, both the first switching element 107 and the second switching element 106 are turned on, and the potential at the connection point between the switch circuit and the resistor 108 is substantially the power line. It becomes the same potential as GND, and the enable signal (output voltage VOUT) becomes High level. On the other hand, in the state where the power supply voltage VDD is not within the guaranteed operation range or the reference voltage VREF is not output, either the first switching element 107 or the second switching element 106 is in an off state, and the resistance No current flows through 108, the potential of the connection point between the switch circuit and the resistor 108 becomes substantially the same potential as the ground line GND, and the enable signal becomes the low level.
　ところで、電源電圧検出回路は、電子回路２５３にイネーブル信号を入力する。電子回路２５３は、電源線Ｌと接地線ＧＮＤとに接続され、電源線Ｌから電源電圧ＶＤＤの供給を受けるとともに、基準電圧回路１００から電圧ＶＲＥＦの供給を受ける。この電子回路２５３は、電源電圧ＶＤＤが動作保証範囲内であり且つ基準電圧回路１００が基準電圧ＶＲＥＦを出力している場合に正常に駆動する。そして、電子回路２５３は、入力されるイネーブル信号（電源電圧検出回路の出力電圧ＶＯＵＴ）をモニタリングし、当該イネーブル信号がＬｏｗレベルからＨｉｇｈレベルに変化したことを検知すると駆動する。
＜２＞動作
　本実施の形態に係る電源電圧検出回路は、電源電圧ＶＤＤの大きさが電圧２Ｖｔｈ以上になると、イネーブル信号がＬｏｗレベルからＨｉｇｈレベルに変化する。以下、本実施の形態に係る電源電圧検出回路の動作について図６および図７を用いて詳細に説明する。 By the way, the power supply voltage detection circuit inputs an enable signal to the electronic circuit 253. The electronic circuit 253 is connected to the power supply line L and the ground line GND, receives the power supply voltage VDD from the power supply line L, and receives the voltage VREF from the reference voltage circuit 100. The electronic circuit 253 is driven normally when the power supply voltage VDD is within the guaranteed operating range and the reference voltage circuit 100 outputs the reference voltage VREF. The electronic circuit 253 monitors the input enable signal (the output voltage VOUT of the power supply voltage detection circuit), and drives when detecting that the enable signal has changed from the Low level to the High level.
<2> Operation In the power supply voltage detection circuit according to the present embodiment, when the magnitude of the power supply voltage VDD becomes equal to or higher than the voltage 2Vth, the enable signal changes from the Low level to the High level. Hereinafter, the operation of the power supply voltage detection circuit according to the present embodiment will be described in detail with reference to FIGS.
　電源投入直後等、電源電圧ＶＤＤがＮチャネルＭＯＳトランジスタ１１０のゲート閾値電圧Ｖｔｈ未満の場合、分圧回路２５４が出力する電圧ＶＧＶＲＥＦ２は略電圧ＶＤＤと等しくとなっている。また、ＮチャネルＭＯＳトランジスタ１１０は、オフ状態にあり、抵抗１０９には電流が流れないため電圧ＶＧＶＤＤ２は略電圧ＶＤＤと等しくなっている。これにより、第１のスイッチング素子１０７と第２のスイッチング素子１０６とは、共にオフ状態にあり、電源電圧検出回路の出力端子ＶＯＵＴは、接地線ＧＮＤの電圧レベルである０Ｖがそのまま出力されることになる。 When the power supply voltage VDD is lower than the gate threshold voltage Vth of the N-channel MOS transistor 110, such as immediately after the power is turned on, the voltage VGVREF2 output from the voltage dividing circuit 254 is substantially equal to the voltage VDD. Since N channel MOS transistor 110 is in an off state and no current flows through resistor 109, voltage VGVDD2 is substantially equal to voltage VDD. As a result, both the first switching element 107 and the second switching element 106 are in the OFF state, and the output terminal VOUT of the power supply voltage detection circuit outputs 0 V, which is the voltage level of the ground line GND, as it is. become.
　そして、電源電圧ＶＤＤが電圧Ｖ１の場合、分圧回路２５４から第２のスイッチング素子１０６のゲートに、第２のスイッチング素子１０３のゲート閾値電圧Ｖｔｈ以上の大きさの電圧ＶＧＶＲＥＦ２が入力され、第２のスイッチング素子１０６がオン状態となる。この電圧ＶＧＶＲＥＦ２は、略０Ｖである。このとき、第１のスイッチング素子１０７のゲートの電圧ＶＧＶＤＤ２と、第１のスイッチング素子１０２のソース側の電源電圧ＶＤＤとの間の電圧（ソース－ゲート間電圧ＶＧＳ）は、第１のスイッチング素子１０７のゲート閾値電圧Ｖｔｈよりもまだ低いので第１のスイッチング素子１０７はオフ状態を維持する。 When the power supply voltage VDD is the voltage V1, the voltage VGVREF2 having a magnitude equal to or higher than the gate threshold voltage Vth of the second switching element 103 is input from the voltage dividing circuit 254 to the gate of the second switching element 106. The switching element 106 is turned on. This voltage VGVREF2 is approximately 0V. At this time, the voltage (source-gate voltage VGS) between the gate voltage VGVDD2 of the first switching element 107 and the source side power supply voltage VDD of the first switching element 102 is the first switching element 107. Since the gate threshold voltage Vth is still lower, the first switching element 107 maintains the off state.
　また、電源電圧ＶＤＤが電圧２Ｖｔｈの場合、ＮチャネルＭＯＳトランジスタ１１０のソース－ドレイン間の電圧降下がゲート閾値電圧Ｖｔｈに等しいから、電圧ＶＧＶＤＤ２がゲート閾値電圧Ｖｔｈに等しくなる。そして、第１のスイッチング素子１０７がオン状態となる。このとき、第１のスイッチング素子１０７および第２のスイッチング素子１０６が共にオン状態となっていることから、出力電圧ＶＯＵＴは抵抗１０８の両端間の電圧となる。ここで、抵抗１０８の大きさは、第１のスイッチング素子１０７および第２のスイッチング素子１０６のオン抵抗に比べて十分大きいので、出力電圧ＶＯＵＴは、電源電圧ＶＤＤに略等しくなる。 When the power supply voltage VDD is 2Vth, the voltage drop between the source and drain of the N-channel MOS transistor 110 is equal to the gate threshold voltage Vth, so that the voltage VGVDD2 is equal to the gate threshold voltage Vth. Then, the first switching element 107 is turned on. At this time, since both the first switching element 107 and the second switching element 106 are in the on state, the output voltage VOUT is a voltage across the resistor 108. Here, since the size of the resistor 108 is sufficiently larger than the on-resistance of the first switching element 107 and the second switching element 106, the output voltage VOUT becomes substantially equal to the power supply voltage VDD.
　そして、電源電圧ＶＤＤが電子回路２５３の動作保証範囲内である電圧２Ｖｔｈ以上である限り、出力電圧ＶＯＵＴは電圧ＶＤＤとなる。 As long as the power supply voltage VDD is equal to or higher than the voltage 2Vth that is within the operation guarantee range of the electronic circuit 253, the output voltage VOUT becomes the voltage VDD.
　また、基準電圧回路１００から一定の基準電圧ＶＲＥＦが出力される状態になった後に、出力電圧ＶＯＵＴが出力されるので、電子回路２５３が、電源電圧ＶＤＤが電子回路１５３の動作保証範囲内にも関わらず基準電圧ＶＲＥＦが入力されていない状態で誤動作してしまうことを防止できる。 In addition, since the output voltage VOUT is output after the reference voltage circuit 100 is in a state in which the constant reference voltage VREF is output, the electronic circuit 253 has the power supply voltage VDD within the guaranteed operation range of the electronic circuit 153. Regardless of this, it is possible to prevent malfunctions when the reference voltage VREF is not input.
　次に、この電源電圧検出回路の時系列動作を図７に示す。図７では、電源投入直後等、電源電圧ＶＤＤが時間とともに単調増加していく場合（図７（ａ）参照）を例に挙げて説明する。 Next, the time series operation of this power supply voltage detection circuit is shown in FIG. In FIG. 7, a case where the power supply voltage VDD monotonously increases with time, such as immediately after power-on (see FIG. 7A) will be described as an example.
　電源電圧ＶＤＤが時刻Ｔ（Ｖｔｈ）にゲート閾値電圧Ｖｔｈに等しくなると、ＮチャネルＭＯＳトランジスタ１１０がオンする。その後、電源電圧ＶＤＤが上昇しても電圧ＶＧＶＤＤ２は略一定に維持される（図７（ｅ）参照）。一方、抵抗１０９の両端間の電圧（ＶＤＤ－ＶＧＶＤＤ２）の大きさは、電源電圧ＶＤＤとともに上昇していく（図７（ｄ）参照）。 When the power supply voltage VDD becomes equal to the gate threshold voltage Vth at time T (Vth), the N-channel MOS transistor 110 is turned on. Thereafter, even when the power supply voltage VDD rises, the voltage VGVDD2 is maintained substantially constant (see FIG. 7E). On the other hand, the voltage across the resistor 109 (VDD−VGVDD2) increases with the power supply voltage VDD (see FIG. 7D).
　そして、電源電圧ＶＤＤが時刻Ｔ（Ｖ１）に電圧Ｖ１に達すると、基準電圧源１００が起動して分圧回路２５４が０Ｖを出力し（図７（ｂ）参照）、第２のスイッチング素子１０６は、ソース－ゲート間電圧ＶＳＧ（１０６）がゲート閾値電圧を超えるとオンする（図７（ｃ）参照）。 When the power supply voltage VDD reaches the voltage V1 at time T (V1), the reference voltage source 100 is activated and the voltage dividing circuit 254 outputs 0 V (see FIG. 7B), and the second switching element 106 is activated. Is turned on when the source-gate voltage VSG (106) exceeds the gate threshold voltage (see FIG. 7C).
　その後、電源電圧ＶＤＤが時刻Ｔ（２Ｖｔｈ）に電子回路２５３の動作保証範囲内である電圧２Ｖｔｈに達すると、第１のスイッチング素子１０７がオンし、電圧ＶＯＵＴが出力される（図７（ｇ）参照）。 After that, when the power supply voltage VDD reaches the voltage 2Vth that is within the guaranteed operation range of the electronic circuit 253 at time T (2Vth), the first switching element 107 is turned on and the voltage VOUT is output (FIG. 7 (g)). reference).
　ここで、図７（ｂ）および（ｃ）に示すように、分圧回路２５４から第２のスイッチング素子１０６のゲートへのステップ状の入力に対して、第２のスイッチング素子１０６のソース－ゲート間電圧ＶＳＧ（１０６）は、期間Ｔ２１だけ遅れる。これは、第２のスイッチング素子１０６のソース－ゲート間の寄生容量Ｃ２２を放電するのに期間Ｔ２１だけ要することによる。 Here, as shown in FIGS. 7B and 7C, the source-gate of the second switching element 106 with respect to the step-like input from the voltage dividing circuit 254 to the gate of the second switching element 106. The inter-voltage VSG (106) is delayed by the period T21. This is because it takes only the period T21 to discharge the parasitic capacitance C22 between the source and gate of the second switching element 106.
　また、抵抗１０９の両端間の電圧（ＶＤＤ－ＶＧＶＤＤ２）は、時刻Ｔｔｈよりも早い時刻に電圧２Ｖｔｈに達するが、第１のスイッチング素子１０７のソース－ゲート間の寄生容量Ｃ２１を放電する必要がある分だけ遅れることになる。 The voltage across the resistor 109 (VDD−VGVDD2) reaches the voltage 2Vth earlier than the time Tth, but the parasitic capacitance C21 between the source and gate of the first switching element 107 needs to be discharged. It will be delayed by minutes.
　ところで、本実施の形態に係る電源電圧検出回路では、図７（ｈ）に示すように、実施の形態１と同様に、第１のスイッチング素子１０７の寄生容量Ｃ２１の放電期間Ｔ２１と、第２のスイッチング素子１０６の寄生容量Ｃ２２の放電期間Ｔ２２とを重複させている。放電時間Ｔ２１がＴ２２よりも長いとすると、検出時間Ｔｄは、電圧２Ｖｔｈに到達するまでの実到達時間Ｔ２に比べて、スイッチング素子１０７の寄生容量Ｃ２１の放電に起因する遅延時間に相当するだけ長くなり、第２のスイッチング素子１０６の寄生容量Ｃ２２の放電期間Ｔ２２の影響を受けないことになる。 By the way, in the power supply voltage detection circuit according to the present embodiment, as shown in FIG. 7 (h), the discharge period T21 of the parasitic capacitance C21 of the first switching element 107, as shown in FIG. The discharge period T22 of the parasitic capacitance C22 of the switching element 106 is overlapped. If the discharge time T21 is longer than T22, the detection time Td is longer than the actual arrival time T2 until the voltage 2Vth is reached, corresponding to the delay time caused by the discharge of the parasitic capacitance C21 of the switching element 107. Thus, the second switching element 106 is not affected by the discharge period T22 of the parasitic capacitance C22.
　従って、図１０に示す従来例の電源電圧検出回路に比べて、第２のスイッチング素子１０６の寄生容量Ｃ２２の放電期間Ｔ２２に相当する時間だけ、電源電圧ＶＤＤが電圧２Ｖｔｈに達したことを検出するタイミングの遅延を抑制することができる。 Accordingly, as compared with the power supply voltage detection circuit of the conventional example shown in FIG. 10, it is detected that the power supply voltage VDD has reached the voltage 2Vth for a time corresponding to the discharge period T22 of the parasitic capacitance C22 of the second switching element 106. Timing delay can be suppressed.
　また、Ｔ２２がＴ２１よりも長い場合も上記同様に、放電期間Ｔ２２に放電期間Ｔ２１が含まれるようになるので、検出タイミングの遅延による検出誤差を低減することができる。
＜変形例＞
　（１）前述の実施の形態１では、電圧出力回路１５１が１つのＰチャネルＭＯＳトランジスタ１０４を有する例について説明したが、これに限定されるものではない。例えば、２個以上のＰチャネルＭＯＳトランジスタを直列に接続してなる直列回路と抵抗１０５との接続点に生じる電圧を出力するものであってもよい。 In addition, when T22 is longer than T21, the discharge period T21 is included in the discharge period T22 as described above, so that a detection error due to a detection timing delay can be reduced.
<Modification>
(1) In the above-described first embodiment, the example in which the voltage output circuit 151 has one P-channel MOS transistor 104 has been described. However, the present invention is not limited to this. For example, a voltage generated at a connection point between a series circuit formed by connecting two or more P-channel MOS transistors in series and the resistor 105 may be output.
　本変形例によれば、ＰチャネルＭＯＳトランジスタの個数を変更することにより、検出時間Ｔｄを自由に設定することができるので、電子回路１５３の動作保証範囲内に応じて電源電圧検出回路の適用範囲を広げることができる。 According to this modification, the detection time Td can be freely set by changing the number of P-channel MOS transistors, so that the range of application of the power supply voltage detection circuit according to the guaranteed operation range of the electronic circuit 153 Can be spread.
　なお、前述の実施の形態２に係る電圧出力回路２５１について、２個以上のＮチャネルＭＯＳトランジスタを直列に接続してなる直列回路と抵抗１０９との接続点に生じる電圧を出力するものであってもよい。 The voltage output circuit 251 according to the second embodiment outputs a voltage generated at a connection point between a resistor 109 and a series circuit in which two or more N-channel MOS transistors are connected in series. Also good.
　本発明は、低消費電力化が要求される電子機器、例えば、家電、警報機、時計、電力メータおよび特小無線機等の電子機器に利用可能である。 The present invention can be used for electronic devices that require low power consumption, for example, electronic devices such as home appliances, alarm devices, watches, power meters, and extra-small radio devices.
１００　基準電圧回路
１０１，１０５，１０８，１０９　抵抗
１０２，１０３，１０６，１０７　スイッチング素子
１０４　ＮチャネルＭＯＳトランジスタ
１１０　ＰチャネルＭＯＳトランジスタ
６０１，６０２，７０１，７０２　インバータ
ＶＯＵＴ　出力電圧
Ｖｔｈ　ゲート閾値電圧
ＶＤＤ　電源電圧
ＶＲＥＦ　基準電圧 100 Reference voltage circuit 101, 105, 108, 109 Resistor 102, 103, 106, 107 Switching element 104 N channel MOS transistor 110 P channel MOS transistor 601, 602, 701, 702 Inverter VOUT Output voltage Vth Gate threshold voltage VDD Power supply voltage VREF Reference voltage

Claims (9)

  1. 　外部電源から電力が供給される電源線に接続され、当該電源線の電圧に基づいて電圧を出力する電圧出力回路と、
    　基準電圧を出力する基準電圧回路と、
    　前記電圧出力回路が出力する電圧が所定の閾値電圧以上になるとオンオフ状態が切り替わる第１のスイッチング素子と、
    　前記第１のスイッチング素子に直列に接続され且つ前記基準電圧が供給されるとオンオフ状態が切り替わる第２のスイッチング素子と、
    　前記第１のスイッチング素子に前記第２のスイッチング素子を直列に接続してなるスイッチ回路に直列に接続された負荷抵抗とを備え、
    　前記スイッチ回路と前記負荷抵抗との直列回路の一端側が前記電源線に接続され且つ他端側が接地線に接続されてなり、前記負荷抵抗と前記スイッチ回路との接続点に生じる制御電圧を出力する
    　ことを特徴とする電源電圧検出回路。     A voltage output circuit connected to a power supply line to which power is supplied from an external power supply and outputting a voltage based on the voltage of the power supply line;
    A reference voltage circuit for outputting a reference voltage;
    A first switching element that switches on and off when the voltage output from the voltage output circuit is equal to or higher than a predetermined threshold voltage;
    A second switching element connected in series to the first switching element and switched on and off when the reference voltage is supplied;
    A load resistor connected in series to a switch circuit formed by connecting the second switching element in series to the first switching element;
    One end of a series circuit of the switch circuit and the load resistor is connected to the power supply line and the other end is connected to a ground line, and a control voltage generated at a connection point between the load resistor and the switch circuit is output. A power supply voltage detection circuit.
  2. 　前記第１のスイッチング素子は、前記電圧出力回路が出力する電圧が所定の閾値電圧以上になるとオフ状態からオン状態に切り替わり、
    　前記第２のスイッチング素子は、前記基準電圧が出力されるとオフ状態からオン状態に切り替わる
    　ことを特徴とする請求項１記載の電源電圧検出回路。     The first switching element switches from an off state to an on state when a voltage output from the voltage output circuit is equal to or higher than a predetermined threshold voltage,
    The power supply voltage detection circuit according to claim 1, wherein the second switching element is switched from an off state to an on state when the reference voltage is output.
  3. 　前記電圧出力回路は、前記電源線に接続された一方向性素子と、一端側が前記一方向性素子に接続され且つ他端側が接地されてなり前記接続点に生じる電圧をプルダウンするプルダウン用抵抗とを有し、前記一方向性素子と前記プルダウン用抵抗との接続点に生じる電圧を出力し、
    　前記第１のスイッチング素子は、ドレインが前記電源線側に接続され且つゲートが前記電圧出力回路に接続されたＮチャネルＭＯＳトランジスタからなり、
    　前記第２のスイッチング素子は、ドレインが前記第１のスイッチング素子のソースに接続され且つゲートが前記基準電圧回路側に接続されるとともに、ソースが接地されてなるＮチャネルＭＯＳトランジスタからなり、
    　前記負荷抵抗は、前記直列回路の高電位側に接続されてなる
    　ことを特徴とする請求項２記載の電源電圧検出回路。     The voltage output circuit includes a unidirectional element connected to the power supply line, a pull-down resistor that pulls down a voltage generated at the connection point, with one end connected to the unidirectional element and the other end grounded. And outputs a voltage generated at a connection point between the unidirectional element and the pull-down resistor,
    The first switching element comprises an N-channel MOS transistor having a drain connected to the power supply line side and a gate connected to the voltage output circuit,
    The second switching element comprises an N-channel MOS transistor having a drain connected to the source of the first switching element and a gate connected to the reference voltage circuit side, and a source grounded.
    The power supply voltage detection circuit according to claim 2, wherein the load resistor is connected to a high potential side of the series circuit.
  4. 　前記一方向性素子は、前記電源線側にソースが接続され且つ前記プルダウン用抵抗側にゲートおよびドレインが共通接続されてなるＰチャネルＭＯＳトランジスタからなる
    　ことを特徴とする請求項３記載の電源電圧検出回路。     4. The power supply voltage according to claim 3, wherein the unidirectional element comprises a P-channel MOS transistor having a source connected to the power supply line side and a gate and a drain commonly connected to the pull-down resistor side. Detection circuit.
  5. 　前記第１のスイッチング素子は、バックゲートが接地されてなる
    　ことを特徴とする請求項１乃至４のいずれか１項に記載の電源電圧検出回路。     5. The power supply voltage detection circuit according to claim 1, wherein a back gate of the first switching element is grounded. 6.
  6. 　前記電圧出力回路は、前記電源線に一端側が接続されてなり前記接続点に生じる電圧をプルアップするプルアップ用抵抗と、前記プルアップ用抵抗の他端側に接続された一方向性素子とを有し、前記プルアップ用抵抗と前記一方向性素子との接続点に生じる電圧を出力し、
    　前記第２のスイッチング素子は、ソースが前記電源線に接続され且つゲートが前記基準電圧回路側に接続されたＰチャネルＭＯＳトランジスタからなり、
    　前記第１のスイッチング素子は、ソースが前記第２のスイッチング素子のドレインに接続され且つゲートが前記電圧出力回路に接続されるとともに、ドレインが前記負荷抵抗に接続されてなるＰチャネルＭＯＳトランジスタからなり、
    　前記負荷抵抗は、前記直列回路の低電位側に接続されてなる
    　ことを特徴とする請求項２記載の電源電圧検出回路。     The voltage output circuit includes a pull-up resistor connected to the power supply line and pulling up a voltage generated at the connection point, and a unidirectional element connected to the other end of the pull-up resistor. Output a voltage generated at a connection point between the pull-up resistor and the unidirectional element,
    The second switching element comprises a P-channel MOS transistor having a source connected to the power supply line and a gate connected to the reference voltage circuit side.
    The first switching element comprises a P-channel MOS transistor having a source connected to the drain of the second switching element, a gate connected to the voltage output circuit, and a drain connected to the load resistor. ,
    The power supply voltage detection circuit according to claim 2, wherein the load resistor is connected to a low potential side of the series circuit.
  7. 　前記一方向性素子は、前記プルアップ用抵抗の前記他端側にドレインおよびゲートが共通接続され且つソースが接地されてなるＮチャネルＭＯＳトランジスタからなる
    　ことを特徴とする請求項６記載の電源電圧検出回路。     The power supply voltage according to claim 6, wherein the unidirectional element comprises an N-channel MOS transistor in which a drain and a gate are commonly connected to the other end of the pull-up resistor and a source is grounded. Detection circuit.
  8. 　前記第２のスイッチング素子は、バックゲートが前記電源線に接続されてなる
    　ことを特徴とする請求項６または請求項７に記載の電源電圧検出回路。     The power supply voltage detection circuit according to claim 6 or 7, wherein the second switching element has a back gate connected to the power supply line.
  9. 　請求項１乃至８のいずれか１項に記載の電源電圧検出回路から出力される電圧の大きさに基づいて前記基準電圧回路の起動状態を判別する
    　ことを特徴とする電子回路。     9. An electronic circuit, wherein an activation state of the reference voltage circuit is determined based on a magnitude of a voltage output from the power supply voltage detection circuit according to any one of claims 1 to 8.
PCT/JP2011/005604 2011-06-20 2011-10-04 Power supply voltage detection circuit WO2012176248A1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104360229A (en) * 2014-11-13 2015-02-18 国网河南省电力公司南阳供电公司 Long-standby-time electric-larceny-preventing inspection instrument
CN115183822A (en) * 2022-09-13 2022-10-14 深圳市瑞芬科技有限公司 Internet of things sensor for monitoring geological settlement and vibration characteristics and control method

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JP2002228690A (en) * 2001-02-01 2002-08-14 Matsushita Electric Ind Co Ltd Power source detection circuit
JP2003338555A (en) * 1997-03-31 2003-11-28 Matsushita Electric Ind Co Ltd Electronic switch device and its manufacturing method
JP2010223796A (en) * 2009-03-24 2010-10-07 Renesas Electronics Corp Power supply voltage detection circuit

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JP2003338555A (en) * 1997-03-31 2003-11-28 Matsushita Electric Ind Co Ltd Electronic switch device and its manufacturing method
JP2002228690A (en) * 2001-02-01 2002-08-14 Matsushita Electric Ind Co Ltd Power source detection circuit
JP2010223796A (en) * 2009-03-24 2010-10-07 Renesas Electronics Corp Power supply voltage detection circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104360229A (en) * 2014-11-13 2015-02-18 国网河南省电力公司南阳供电公司 Long-standby-time electric-larceny-preventing inspection instrument
CN115183822A (en) * 2022-09-13 2022-10-14 深圳市瑞芬科技有限公司 Internet of things sensor for monitoring geological settlement and vibration characteristics and control method

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