WO2012167461A1

WO2012167461A1 - Method and system for realizing interconnection fault-tolerance between cpus

Info

Publication number: WO2012167461A1
Application number: PCT/CN2011/076471
Authority: WO
Inventors: 常胜; 王海彬; 张�杰
Original assignee: 华为技术有限公司
Priority date: 2011-06-28
Filing date: 2011-06-28
Publication date: 2012-12-13
Also published as: CN102763087B; CN102763087A

Abstract

A method for realizing interconnection fault-tolerance between CPUs comprises: data channels for status information of transmission link connection and link control signals are added both in a first SerDes (Serial Deserial) interface module of a first FPGA (Field-Programmable Gate Array) and a second SerDes interface module of a second FPGA; a control logical module monitors the status of the transmission link connection between an opposite end FPGA and the corresponding CPU and controls the status of the transmission link connection between a local end FPGA and the corresponding CPU; when any connection link for realizing interconnection between the first CPU and the second CPU has a fault, the FPGA connected with the fault link sends a link control signal to the fault link through self-added data channel so as to recover the normal status of the fault link; when the fault link has been recovered to be the normal status, each FPGA uses each link with normal status of the own connection respectively, thereby realizing the connection of each link interconnected between the first CPU and the second CPU.

Description

Method and system for implementing fault tolerance between CPUs

The present invention relates to the field of communications technologies, and in particular, to a method and system for implementing fault tolerance between CPUs.

Background technique

In the prior art, there are two solutions for implementing interconnection between CPUs:

One implementation is that the IBM PCB (Printed Circuit Board) is directly connected to each other to interconnect the CPUs. Each IBM Power CPU comes with seven high-speed interconnects that can be interconnected with seven Power CPUs simultaneously. Eight Power CPUs can be combined into an 8P system through a full direct connection. However, because the Power CPU integrates the functions of the NC (Node control node controller), the cost is high. Limited by the number of Power CPU interconnect interfaces, the CPU system consisting of Power CPUs has poor scalability and low flexibility;

Another implementation is that HP uses the NC node controller and the switch module to interconnect the CPUs, and the system of the entire interconnect architecture is complex. The solution adds two chips to the entire system to implement NC node control and switch module functions. Because the solution uses the switch module to exchange data between NCs, each switch module needs to perform jump point judgment, which increases the delay of data transmission, and the system performance is lower and the cost is higher.

Therefore, the current CPU interconnection scheme has poor scalability, long data transmission delay, and low system performance. In addition, in any link that implements CPU interconnection, any link error may cause the CPU involved. There is an abnormality in the interconnection between the two, and there is no related prior art for the solution of the fault tolerance between the CPUs.

Summary of the invention

The present invention solves the above technical problems in the background art, and proposes a method and system for implementing fault tolerance between CPUs, which can improve the scalability of interconnection between CPUs and realize fault tolerance between CPUs.

The technical solution of the present invention is:

An embodiment of the present invention provides a method for implementing fault tolerance between CPUs, where the method includes: connecting, by a first CPU, a first fast channel interconnect QPI connection of a first field programmable gate array FPGA The second module is connected to the second QPI interface module of the second FPGA, and the first serial deserialized SerDes interface module of the first FPGA is connected to the second SerDes interface module of the second FPGA, and is connected by the first control logic module. a second SerDes interface module of the second FPGA is connected to the second QPI interface module by the second control logic module to implement interconnection between the first CPU and the second CPU; wherein the first SerDes A data channel for transmitting link connection state information and a link control signal is added to the interface module and the second SerDes interface module; and the control between the corresponding QPI interface module and the SerDes interface module in the first FPGA and the second FPGA a logic module, configured to monitor a state of a transmission link connection between the peer FPGA and the corresponding CPU, and control a state of a transmission link connection between the local FPGA and the corresponding CPU;

When any connection link that implements interconnection between the first CPU and the second CPU fails, the FPGA connected to the faulty link sends a link control signal to the faulty link to recover the fault chain through the data channel added by itself. The normal state of the road;

When the faulty link is restored to the normal state, the FPGAs respectively enable the links of the respective normal states connected to each other, and perform the connection of the links that are interconnected between the first CPU and the second CPU.

An implementation system for interconnecting faults between CPUs, the system comprising: at least a first CPU, a second

a CPU, a first FPGA and a second FPGA; the first CPU is connected to the first QPI interface module of the first FPGA, the second CPU is connected to the second QPI interface module of the second FPGA, and the first SerDes interface module of the first FPGA is connected to the second The second SerDes interface module of the FPGA is connected to the first QPI interface module by using the first control logic module, and the second SerDes interface module of the second FPGA is connected to the second QPI interface module by using the second control logic module to implement the An interconnection between a CPU and a second CPU; wherein, the first SerDes interface module and the second SerDes interface module respectively add a data channel for transmitting link connection state information and a link control signal; the first FPGA And a control logic module between the corresponding QPI interface module and the SerDes interface module in the second FPGA, used to monitor the state of the transmission link connection between the peer FPGA and the corresponding CPU, and control the transmission between the local FPGA and the corresponding CPU The status of the link connection;

When any connection link that implements interconnection between the first CPU and the second CPU fails, the FPGA connected to the faulty link sends a link control signal to the faulty link to recover the fault chain through the data channel added by itself. The normal state of the road; when the faulty link returns to the normal state, each FPGA enables each link of each normal state connected to each other, and performs between the first CPU and the second CPU The connection of the various links that implement the interconnection.

In the embodiment of the present invention, by setting the FPGA for the CPU, the transparent transmission function based on the FPGA, and the interconnection between the CPUs through the connection between the FPGAs, when the internal interconnected CPU is increased or decreased, the dedicated FPGA can be increased or decreased. The number is achieved. Therefore, the scalability of the interconnection between the CPUs can be improved; and, by adding a data channel on the FPGA, when any connection link between the interconnected CPUs fails, the connection state information of the links of the CPU interconnections is transmitted through the data channel. And link control signals to achieve fault tolerance between CPUs.

DRAWINGS

1 is a schematic structural diagram of an FPGA for implementing interconnection between CPUs according to an embodiment of the present invention; FIG. 2 is a schematic structural diagram of implementing CPU interconnection by using the FPGA of FIG. 1;

FIG. 3 is a schematic diagram of link connection involved in the interconnection architecture in FIG. 2.

detailed description

The technical solutions in the embodiments of the present invention will be described in detail with reference to the accompanying drawings. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without the creative work are all within the scope of the present invention.

First, referring to FIG. 1, FIG. 1 is a schematic structural diagram of an FPGA for implementing interconnection between CPUs according to an embodiment of the present invention. The FPGA (Field-Programmable Gate Array) is provided with a QPI (Quick Path Interconnect) interface module 11 and a SerDes (Serial Deserial) interface module 12, and a QPI interface module 11 of the FPGA. Connected to the QPI interface of the CPU, responsible for completing high-speed data transmission with the CPU; a control logic module 13 is also disposed between the QPI interface module and the SerDes interface module, and the SerDes interface module 12 is connected to the control logic module 13, and The SerDes interface module 12 set on an FPGA is connected by a high speed cable (CXP Cable).

Figure 2 shows the structure of the CPU interconnect using the above FPGA.

For convenience of description, an example is described in which two CPUs are interconnected, and two interconnected CPUs are named as a first CPU (CPU0) and a second CPU (CPU1), and the first CPU and the second CPU are respectively connected to an FPGA. , that is, the first FPGA (FPGA0) and the second FPGA (FPGA1).

The links interconnected between the first CPU and the second CPU are in a normal state, on the FPGA The QPI interface module 11 can convert serial QPI data transmitted by the CPU into parallel QPI data. Since the QPI interface module converts the serial QPI data sent by the CPU into parallel QPI data, the frequency of the QPI data is reduced to accommodate the data processing frequency inside the FPGA.

The parallel QPI data received from the QPI interface module 11 can be converted into high-speed serial SerDes data by the SerDes interface module 12 on the FPGA, and sent to the peer CPU through the SerDes interface module 12 set on another FPGA, and The high-speed serial SerDes data sent by the SerDes interface module on the peer FPGA is received, and the received high-speed serial SerDes data is converted into parallel QPI data and sent to the CPU connected to itself.

Since the SerDes interface module will not support QPI data of long-distance cable interconnection and topology DC characteristics, it can be converted into AC-type SerDes interface, which can support long-distance high-speed cable interconnection and topology, and realize inter-board processing. High speed interconnect. In the embodiment of the present invention, at least one data channel is added on the basis of the original data channel in the SerDes interface module. Unlike the original data channel, the added data channel is not used for data transmission between the interconnected CPUs. It is used to connect the connection status information and link control signals of each link between the FPGAs.

In addition, a control logic module is disposed between the QPI interface module and the SerDes interface module in the FPGA, which is used to monitor the state of the transmission link connection between the peer FPGA and the corresponding CPU, and control the transmission chain between the local FPGA and the corresponding CPU. The state of the road connection.

Corresponding to the foregoing interconnection architecture, an embodiment of the present invention provides an implementation method for interconnecting fault tolerance between CPUs.

In a specific implementation, the first CPU is connected to the first QPI interface module of the first FPGA (FPGA0), the second CPU is connected to the second QPI interface module of the second FPGA (FPGA1), and the first SerDes interface module of the first FPGA is connected to the second The second SerDes interface module of the FPGA is connected to the first QPI interface module by using the first control logic module, and the second SerDes interface module of the second FPGA is connected to the second QPI interface module by using the second control logic module to implement the An interconnection between a CPU and a second CPU; wherein the first SerDes interface module is provided with a first data channel for transmitting link connection state information and a link control signal, and the second SerDes interface module is added a second data channel for transmitting link connection state information and a link control signal; a control logic module between the corresponding QPI interface module and the SerDes interface module in the first FPGA and the second FPGA, configured to monitor the peer FPGA and The status of the link connection between the corresponding CPUs, and control the local FPGA and The state of the link connection between the corresponding CPUs;

Therefore, the interconnect architecture in the embodiment of the present invention relates to a QPI link between CPU0 and FPGA0, a high-speed SerDes link between FPGA0 and FPGA1, and a QPI link between FPGA1 and CPU1, among the above three links. If any link fails, it will cause an interconnection abnormality between CPU0 and CPU1.

In the embodiment of the present invention, when any connection link that is interconnected between the first CPU and the second CPU fails, the FPGA connected to the faulty link sends a link to the faulty link through the data channel added by itself. Control signals to restore the normal state of the faulty link;

In order to facilitate a full understanding of the technical solutions of the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described.

As shown in FIG. 3, it is a schematic diagram of link connection involved in the interconnection architecture in the embodiment of the present invention. The corresponding links include: QPI link between CPU0 and FPGA0 (referred to as A link), high-speed SerDes link between FPGA0 and FPGA1 (referred to as B link), and QPI link between FPGA1 and CPU1. (C link is abbreviated as C link), and the faulty state of the A, B, and C links may be abnormal. Therefore, the fault-tolerant solution in the embodiment of the present invention solves the problem on any link of the eight, B, and C links. Abnormal state.

Embodiment 1

When the control logic module in the first FPGA or the second FPGA detects that the B link between the first SerDes interface module and the second SerDes interface module fails, the first FPGA and the second FPGA The control logic module sends a link control signal to the B link through the respective added data channels to restore the normal state of the B link; At the same time, the first control logic module in the first FPGA controls the A link between the first QPI interface module and the first CPU to be in a reset state by using a data channel added in the first SerDes interface module. The second control logic module in the second FPGA controls the C link between the second QPI interface module and the second CPU to remain in a reset state by using a data channel added in the second SerDes interface module, to wait for the B link. Successfully establishing, until the B link returns to normal, the first control logic module controls the connection of the A link by using a data channel added in the first SerDes interface module; meanwhile, the second control The logic module controls the connection of the C link through a data channel added in the second SerDes interface module.

In the specific implementation, after the B link is successfully established, the first FPGA controls the QPI initialization process of the A link, and at the same time, the second FPGA controls the QPI initialization process of the C link, thereby implementing the connection of the A and C links.

After the three links A, B, and C are all established, the first CPU and the second CPU can start normal link communication, thereby completing the interconnection between the first CPU and the second CPU.

Embodiment 2

When the first control logic module detects that the A link is faulty, and the second control logic module detects that the C link is faulty, the first control logic module passes the fault information of the A link through the The data channel added in the first SerDes interface module is sent to the second FPGA; at the same time, the second control logic module sends the fault information of the C link through the data channel added in the second SerDes interface module. To the first FPGA; that is, the first FPGA and the second FPGA perform the interaction of the local QPI link state through the respective added data channels;

The control logic module of the first FPGA and the second FPGA that first receives the fault signal of the connection link sends a link control signal to the connection link connecting the corresponding CPU through the data channel added by itself to restore the connection chain. The normal state of the path; and the link control signal is sent to the peer FPGA through the data channel added by itself to control the recovery operation of the corresponding connection link of the control logic module of the peer FPGA.

The first FPGA and the second FPGA control the operation signals by exchanging links, so that the A and C links respectively enter the initialization process, and the A and C links are re-established.

Embodiment 3

When the B link fails and the C link is normal, the first control logic module can monitor Go to the abnormal link, so that the A channel is kept in the reset state by the data channel added in the first SerDes interface module; meanwhile, the second control logic module can detect the B link abnormality, thereby The second control logic module controls the C link to remain in a reset state by using a data channel added in the second SerDes interface module, and waits for the B link to be re-established;

In addition, the first control logic module and the second control logic module send a link control signal to the B link through the respective added data channels to restore the normal state of the B link; until when the B link returns to normal, the The first control logic module controls the connection of the A link through the data channel added in the first SerDes interface module, and the second control logic module controls the C chain through the data channel added in the second SerDes interface module. The connection of the road.

In the embodiment of the present invention, the failure of the VIII link and the B link are normal, and the B link is taken as an example.

When the C link fails and the A link is normal, the interconnection fault tolerance scheme between the first CPU and the second CPU is similar to this embodiment.

Embodiment 4

When the A link is faulty and the B and C links are normal, the first control logic module sends the fault information of the A link to the second FPGA through the data channel added in the first SerDes interface module. And sending a link control signal to the second FPGA, so that the second control logic module controls the C link to be in a reset state by using a data channel added in the second SerDes interface module; the first control logic module continues Transmitting, by the data channel added in the first SerDes interface module, a link control signal to the second FPGA, so that the first control logic module controls the A link by using a data channel added in the first SerDes interface module The connection, at the same time, the second control logic module controls the connection of the C link through the data channel added in the second SerDes interface module, thereby realizing the re-establishment of the A link.

In the embodiment of the present invention, the A link fails, and the B and C links are normal. The fault tolerance scheme between the first CPU and the second CPU is used when the C link fails and the A and B links are normal. Similar to this embodiment.

It can be seen from the above embodiments that the FPGA-based transparent transmission function realizes the interconnection structure between the CPUs through the high-speed cable connection, and the fault-tolerant solution of the embodiment of the present invention can well solve the interconnection chain between the interconnected CPUs. The fault state that may occur on the road causes the faulty link to return to the normal state in time, so that the interconnected CPU maintains a stable working state. Correspondingly, the embodiment of the present invention further provides an implementation system for interconnecting faults between CPUs, where the system includes: at least a first CPU, a second CPU, a first FPGA, and a second FPGA; and the first CPU is connected to the first FPGA. The first QPI interface module, the second CPU is connected to the second QPI interface module of the second FPGA, the first SerDes interface module of the first FPGA is connected to the second SerDes interface module of the second FPGA, and is connected by the first control logic module. a second SerDes interface module of the second FPGA is connected to the second QPI interface module by the second control logic module to implement interconnection between the first CPU and the second CPU; wherein the first SerDes A data channel for transmitting link connection state information and a link control signal is added to the interface module and the second SerDes interface module; and the control between the corresponding QPI interface module and the SerDes interface module in the first FPGA and the second FPGA a logic module, configured to monitor a state of a transmission link connection between the peer FPGA and the corresponding CPU, and control a state of a transmission link connection between the local FPGA and the corresponding CPU;

When any connection link that implements interconnection between the first CPU and the second CPU fails, the FPGA connected to the faulty link sends a link control signal to the faulty link to recover the fault chain through the data channel added by itself. The normal state of the road; when the faulty link returns to the normal state, each FPGA enables the links of the respective normal states that are connected to each other, and performs the connection of the links that are interconnected between the first CPU and the second CPU. .

In the above system embodiment, by setting the FPGA for the CPU, the FPGA-based transparent transmission function, and the interconnection between the CPUs through the connection between the FPGAs, when the internal interconnected CPU is increased or decreased, the dedicated FPGA can be increased or decreased. The number is achieved. Therefore, the scalability of the interconnection between the CPUs can be improved; and, by adding a data channel on the FPGA, when any connection link between the interconnected CPUs fails, the connection state information of the links of the CPU interconnections is transmitted through the data channel. And link control signals to achieve fault tolerance between CPUs.

In a specific implementation, when the control logic module in the first FPGA and/or the second FPGA detects that the second connection link between the first SerDes interface module and the second SerDes interface module fails, The control logic module in the first FPGA and the second FPGA is configured to send a link control signal to the second connection link through the respective added data channels to restore the normal state of the second connection link; The first control logic module in the FPGA controls the first connection between the first QPI interface module and the first CPU by using a data channel added in the first SerDes interface module The second control logic module in the second FPGA controls the third connection chain between the second QPI interface module and the second CPU by using a data channel added in the second SerDes interface module. The first control logic module controls the connection of the first connection link through the data channel added in the first SerDes interface module, when the second connection link returns to normal. At the same time, the second control logic module controls the connection of the third connection link by using a data channel added in the second SerDes interface module.

When the first control logic module detects that the first connection link is faulty and the second control logic module detects that the third connection link is faulty, the first control logic module is configured to: The fault information of the connection link is sent to the second FPGA through the data channel added in the first SerDes interface module; meanwhile, the second control logic module passes the fault information of the third connection link through the The additional data channel in the second SerDes interface module is sent to the first FPGA;

When the first (three) connection link and the second connection link are faulty, when the third (one) connection link is normal, the first (second) control logic module is configured to pass the An additional data channel in the first (2) SerDes interface module controls the first (three) connection link to remain in a reset state; meanwhile, the second (one) control logic module passes the second (one) SerDes The additional data channel in the interface module controls the third (1) connection link to remain in a reset state, and the first control logic module and the second control logic module send a chain to the second connection link through respective added data channels. a road control signal to restore a normal state of the second connection link; until the second connection link returns to normal, the first (second) control logic module is added through the first (second) SerDes interface module The data channel controls the connection of the first (three) connection link, and the second (one) control logic module passes the data added in the second (one) SerDes interface module The channel controls the connection of the third (one) connection link.

When the first (three) connection link fails, the first (two) control logic module is configured to: pass the failure information of the first (three) connection link to the first (2) SerDes interface An additional data channel in the module is sent to the second (1) FPGA, and a link control signal is sent to the second (1) FPGA, so that the second (1) control logic module passes the second ( a) an additional data channel in the SerDes interface module controls the third (one) link to be in a reset state;

The first (2) control logic module is further configured to: continue to send a link control signal to the second (1) FPGA by using a data channel added in the first (2) SerDes interface module, so that the first a control logic module controls a connection of the first connection link by using a data channel added in the first SerDes interface module, and the second control logic module passes an additional data channel in the second SerDes interface module Controlling the connection of the third connection link.

Therefore, in the implementation system of the inter-CPU interconnection fault tolerance, the FPGA-based transparent transmission function realizes the interconnection structure between the inter-board CPUs through the high-speed cable connection, and the fault-tolerant solution of the embodiment of the present invention can solve the interconnection well. The fault state that may occur in the inter-CPU interconnect link causes the faulty link to return to the normal state in time, so that the interconnected CPU maintains a stable working state. For the system embodiment, since it basically corresponds to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiment. The system embodiments described above are merely illustrative, wherein the modules described as separate components may or may not be physically separate, and the components displayed as modules may or may not be physical modules, ie may be located One place, or it can be distributed to multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the embodiment. Those of ordinary skill in the art can understand and implement without any creative effort.

The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the embodiments of the invention. . Therefore, the present embodiments of the invention are not to be limited to the embodiments shown herein, but are to be accorded to the broadest scope of the principles and novel features disclosed herein.

Claims

Rights request

A method for implementing fault tolerance between CPUs, the method comprising: connecting, by a first CPU, a first fast channel interconnect QPI interface module of a first field programmable gate array FPGA, and a second CPU connecting a second FPGA The second QPI interface module, the first serial deserialized SerDes interface module of the first FPGA is connected to the second SerDes interface module of the second FPGA, and is connected to the first QPI interface module by the first control logic module, and the second FPGA The SerDes interface module is connected to the second QPI interface module by using the second control logic module to implement interconnection between the first CPU and the second CPU; wherein, the first SerDes interface module and the second SerDes interface module are a data channel is provided with transmission link connection state information and a link control signal; a control logic module between the corresponding QPI interface module and the SerDes interface module in the first FPGA and the second FPGA is used to monitor the peer FPGA and The status of the link connection between the corresponding CPUs is controlled, and the state of the transmission link connection between the local FPGA and the corresponding CPU is controlled;

2. The method for implementing fault tolerance between CPUs according to claim 1, wherein when any connection link between the first CPU and the second CPU fails, an FPGA connected to the faulty link is provided. The link control signal is sent to the faulty link to restore the normal state of the faulty link through the data channel that is added by itself, including:

When the control logic module in the first FPGA or the second FPGA detects that the second connection link between the first SerDes interface module and the second SerDes interface module fails, the first FPGA and the second The control logic module in the FPGA sends a link control signal to the second connection link to restore the normal state of the second connection link through the respective added data channels; meanwhile, the first control logic module in the first FPGA passes the An additional data channel in a SerDes interface module controls the first connection link between the first QPI interface module and the first CPU to remain in a reset state, and the second control logic module in the second FPGA passes the second SerDes The additional data channel in the interface module controls the third connection link between the second QPI interface module and the second CPU to remain in a reset state. The first control logic module controls the connection of the first connection link by using a data channel added in the first SerDes interface module until the second connection link returns to normal; The control logic module controls the connection of the third connection link through a data channel added in the second SerDes interface module.

3. The method for implementing fault tolerance between CPUs according to claim 2, wherein when any connection link between the first CPU and the second CPU fails, the FPGA connected to the faulty link The link control signal is sent to the faulty link to restore the normal state of the faulty link through the data channel that is added by itself, including:

When the first control logic module detects that the first connection link fails and the second control logic module detects that the third connection link fails, the first control logic module connects the first connection link The fault information is sent to the second FPGA by using a data channel added in the first SerDes interface module; meanwhile, the second control logic module passes the fault information of the third connection link to the second SerDes An additional data channel in the interface module is sent to the first FPGA;

The method for implementing fault tolerance between CPUs according to claim 2, wherein when any connection link between the first CPU and the second CPU fails, the FPGA connected to the faulty link The link control signal is sent to the faulty link to restore the normal state of the faulty link through the data channel that is added by itself, including:

When the first connection link and the second connection link are faulty, when the third connection link is normal, the first control logic module controls the data channel through the additional data channel in the first SerDes interface module. The first connection link is maintained in a reset state; at the same time, the second control logic module controls the third connection link to remain in a reset state by using a data channel added in the second SerDes interface module, the first The control logic module and the second control logic module send a link control signal to the second connection link through the respective added data channels to restore the normal state of the second connection link; until when the second connection link returns to normal, The first control logic module passes the first SerDes interface The data channel added in the module controls the connection of the first connection link, and the second control logic module controls the connection of the third connection link through the data channel added in the second SerDes interface module.

When the first connection link fails, the first control logic module sends the fault information of the first connection link to the second FPGA by using a data channel added in the first SerDes interface module. And sending a link control signal to the second FPGA, so that the second control logic module controls the third connection link to be in a reset state by using a data channel added in the second SerDes interface module;

The first control logic module continues to send a link control signal to the second FPGA by using a data channel added in the first SerDes interface module, so that the first control logic module passes through the first SerDes interface module. The additional data channel controls the connection of the first connection link, and the second control logic module controls the connection of the third connection link by using a data channel added in the second SerDes interface module.

6. The system for implementing fault tolerance between CPUs, wherein the system comprises: at least a first CPU, a second CPU, a first FPGA, and a second FPGA; and the first CPU is connected to the first QPI interface of the first FPGA. The module, the second CPU is connected to the second QPI interface module of the second FPGA, the first SerDes interface module of the first FPGA is connected to the second SerDes interface module of the second FPGA, and the first QPI interface module is connected by the first control logic module. The second SerDes interface module of the second FPGA is connected to the second QPI interface module by using the second control logic module to implement interconnection between the first CPU and the second CPU; wherein the first SerDes interface module and the first A data channel for transmitting link connection state information and a link control signal is added to the second SerDes interface module; and a control logic module between the corresponding QPI interface module and the SerDes interface module in the first FPGA and the second FPGA is used. Monitoring the state of the transmission link connection between the peer FPGA and the corresponding CPU, and controlling the state of the transmission link connection between the local FPGA and the corresponding CPU;

When any connection link that implements interconnection between the first CPU and the second CPU fails, The FPGA connected to the faulty link sends a link control signal to the faulty link through its own added data channel to restore the normal state of the faulty link. When the faulty link returns to the normal state, each FPGA enables each connected link. The link in the normal state is connected to each link that implements interconnection between the first CPU and the second CPU.

The system for implementing fault tolerance between CPUs according to claim 6, wherein when the control logic module in the first FPGA or the second FPGA monitors the first SerDes interface module and the second SerDes interface When the second connection link between modules fails,

The control logic module in the first FPGA and the second FPGA is configured to send a link control signal to the second connection link through the respective added data channels to restore the normal state of the second connection link; The first control logic module in an FPGA controls the first connection link between the first QPI interface module and the first CPU to be in a reset state by using a data channel added in the first SerDes interface module, the second FPGA The second control logic module controls the third connection link between the second QPI interface module and the second CPU to remain in a reset state through a data channel added in the second SerDes interface module until the second connection When the link is restored, the first control logic module controls the connection of the first connection link by using a data channel added in the first SerDes interface module; meanwhile, the second control logic module passes the The additional data channel in the two SerDes interface modules controls the connection of the third connection link.

The system for implementing fault tolerance between CPUs according to claim 7, wherein when the first control logic module detects that the first connection link fails, and the second control logic module detects the third connection When the link fails,

The first control logic module is configured to send fault information of the first connection link to the second FPGA by using a data channel added in the first SerDes interface module; and, the second control logic The module sends the fault information of the third connection link to the first FPGA through the data channel added in the second SerDes interface module;

The system for implementing fault tolerance between CPUs according to claim 7, wherein when the first connection link and the second connection link fail, when the third connection link is normal, The first control logic module is configured to control, by using a data channel added in the first SerDes interface module, that the first connection link remains in a reset state; and at the same time, the second control logic module passes the second SerDes The additional data channel in the interface module controls the third connection link to remain in a reset state, and the first control logic module and the second control logic module send a link control signal to the second connection link through respective added data channels. To restore the normal state of the second connection link; until the second connection link returns to normal, the first control logic module controls the first connection by using a data channel added in the first SerDes interface module a connection of the link, and the second control logic module controls the third by using a data channel added in the second SerDes interface module Contact connection link.

10. The system for implementing fault tolerance between CPUs according to claim 7, wherein when the first connection link fails,

The first control logic module is configured to send fault information of the first connection link to the second FPGA by using a data channel added in the first SerDes interface module, and send the fault information to the second FPGA a link control signal, so that the second control logic module controls the third connection link to be in a reset state by using a data channel added in the second SerDes interface module;

The first control logic module is further configured to: continue to send a link control signal to the second FPGA by using a data channel added in the first SerDes interface module, so that the first control logic module passes the first The data channel added in the SerDes interface module controls the connection of the first connection link, and the second control logic module controls the connection of the third connection link through the data channel added in the second SerDes interface module. connection.