WO2012103736A1

WO2012103736A1 - Data processing node, system and method

Info

Publication number: WO2012103736A1
Application number: PCT/CN2011/076735
Authority: WO
Inventors: 刘建根; 卢广; 郑伟
Original assignee: 华为技术有限公司
Priority date: 2011-06-30
Filing date: 2011-06-30
Publication date: 2012-08-09
Also published as: CN102301363A

Abstract

A data processing node, system and method is disclosed by the embodiments of the present invention which relates to the computer field and enables the flexible extension of the computer system. Said data processing node includes multiple Central Processing Units (CPUs), each CPU including multiple interconnect interfaces. Said CPUs are fully connected through the interconnect interfaces to form a CPU module. At least one interconnect interface is reserved in said CPU module to connect with the inner interconnect interface of an interconnect board. The interconnect board includes at least one outer interconnect interface which is used for connecting with the outer interconnect interfaces of the interconnect boards of other data processing nodes. The invention can be applied in the computer field.

Description

Data processing node, system and method

The present invention relates to computer systems, and more particularly to a data processing node, system and method. Background technique

The data processing node may include a plurality of CPUs. In a system in which a plurality of data processing nodes exist and the nodes include multiple CPUs, how the CPUs between different nodes access each other is a core technology, that is, the interconnection between the CPUs is The core technology of the system. At present, the data processing nodes can realize the interconnection between CPUs by means of full interconnection, and the interconnection between CPUs can also be realized by the form of interconnection modules.

As shown in Figure 1 (a), when the interconnection between CPUs is implemented by the full interconnection method, any two nodes in the system need to be directly connected through a high-speed interconnection interface, and the control function module must be integrated inside the node. The control function module has the function of a node controller (NC). As shown in Figure 1 (b), when the interconnection between the CPUs is realized by the form of the interconnection module, the nodes in the system are connected by the interconnection module, and the nodes therein include a plurality of interconnected CPUs and NCs. .

In the process of implementing the embodiments of the present invention, the inventors have found that the prior art has at least the following problems:

When the interconnection between the CPUs is realized by the full interconnection method as shown in FIG. 1(a), the cost of each node is high due to the need to integrate the control function modules in the nodes, and the high-speed interconnection interface is adopted. The number of restrictions, the system's scalability is poor, and the flexibility is low;

When the interconnection between the CPUs is realized in the form of an interconnection module as shown in FIG. 1(b), although the expansion of the system can be realized, the access between the nodes in the system needs to be selectively interconnected through the interconnection module, resulting in The access delay between nodes is large, which affects the operating efficiency of the system.

Summary of the invention

Embodiments of the present invention provide a data processing node, system, and method to implement flexible expansion of a computer system. To achieve the above objective, the embodiment of the present invention adopts the following technical solutions:

A data processing node includes a plurality of CPUs, each CPU includes a plurality of interconnect interfaces, and the CPUs are completely interconnected through an interconnect interface to form a CPU module, and the CPU module reserves at least one interconnect interface and An interconnecting interface of the interconnect board, the interconnect board including at least one external interconnect interface for interfacing with external interconnects of interconnect boards of other data processing nodes.

A data processing system comprising at least two of the above data processing nodes, an interconnection between the at least two nodes.

A data processing method for a data processing system, the data processing system includes a plurality of data processing nodes, the data processing node includes a plurality of processor CPUs, and a plurality of CPUs are completely interconnected through an interconnection interface to form a CPU module, wherein the CPU module reserves at least one interconnect interface and an internal interconnect interface of the interconnect board, the interconnect board includes at least one external interconnect interface, and is used for interconnecting with other data processing nodes. Connected to the external interconnect interface, the interconnect board is a field programmable gate array FPGA interconnect board, the FPGA interconnect board includes an FPGA chip corresponding to the reserved interconnect interface, and each FPGA chip provides at least An internal interconnection interface and an external interconnection interface, the data processing method includes: converting a data packet into a high-speed transmission signal, and transmitting the high-speed transmission signal to other data processing nodes connected to the data processing node; The high speed transmission signal is converted into a data packet that the CPU can process, and the data packet is sent to the CPU.

A data processing method is applied to a data processing system, where the data processing node includes a plurality of processor CPUs, and a plurality of CPUs are completely interconnected through an interconnection interface to form a CPU module, and the CPU module is reserved at least An interconnection interface is connected to an internal interconnection interface of the interconnection board, and the interconnection board includes at least one external interconnection interface for external interconnection with other data processing node interconnection boards a connection port, the interconnection board is a node control NC chip, and the NC chip includes an internal interconnection interface corresponding to the reserved interconnection interface, and an NC chip with the other data processing node The external interconnection interface that is connected to the external interconnection interface, and the data processing method includes:

The NC chip routes the data packets sent by the CPU to its corresponding CPU.

The data processing node provided by the embodiment of the present invention includes a CPU module and an interconnection board. Since the CPU module is formed by full interconnection between the CPUs, the CPU module can be used as a single node, and, in addition, the CPU module is at least Retaining an interconnect interface to connect to an interconnecting interface of the interconnect board, the interconnect board including at least one external interconnect interface for connecting to an external interconnect interface of the interconnecting boards of other data processing nodes, The CPU module can also be extended to use with multi-node systems in conjunction with interconnect boards. Whether as a stand-alone node or as a multi-node system, each CPU in the node realizes interconnection between CPUs in the node through full interconnection, and CPUs of different nodes realize CPU between different nodes through the interconnection board. The interconnection improves the scalability of the minicomputer system. DRAWINGS

Figure 1 (a) is a system architecture diagram of the full interconnection mode in the prior art;

Figure 1 (b) shows the system architecture connected in the form of interconnect modules in the prior art;

2 is a schematic structural diagram of a data processing node according to an embodiment of the present invention;

3( a ) is a schematic diagram of a data processing node architecture provided by another embodiment of the present invention; FIG. 3 ( b ) is a schematic structural diagram of an FPGA chip in the data processing node provided in FIG. 3 ( a ); FIG. 4 ( a ) is The schematic diagram of the CPU interconnection architecture in the 2P node provided by the embodiment of the present invention; FIG. 4(b) is a schematic diagram of the 2P node architecture provided by the embodiment of the present invention;

5(a) is a schematic diagram of a CPU interconnection architecture in a 4P node according to an embodiment of the present invention; FIG. 5(b) is a schematic diagram of a 4P node architecture according to an embodiment of the present invention;

6 is a schematic structural diagram of a data processing node according to still another embodiment of the present invention;

FIG. 7 is a schematic structural diagram of an 8P system according to an embodiment of the present invention;

FIG. 8 is a flowchart of a data processing method according to an embodiment of the present invention. detailed description In order to achieve flexible extension of the computer system, an embodiment of the present invention provides a data processing node. As shown in FIG. 2, a data processing node according to an embodiment of the present invention includes a plurality of CPUs, each CPU includes a plurality of interconnect interfaces, and the CPUs are completely interconnected through interconnect interfaces to form a CPU module. The CPU module reserves at least one interconnect interface connected to the interconnecting interface of the interconnect board, the interconnect board includes at least one external interconnect interface, and an external interconnect interface for interconnecting boards with other data processing nodes. connection.

It is worth noting that the number of CPUs included in the data processing node is set according to the total number of interconnected interfaces of the CPU and the system architecture formed by the data processing node. It is ensured that at least one interconnect interface is reserved for connection to the interconnect board after each CPU in the node is fully interconnected. Specifically, when the CPU includes four fast interconnect channel (QPI) interfaces, when setting up this type of CPU in the data processing node, up to four can be set, and each CPU inside the node is performed. The interconnection needs to occupy three QPI interfaces, and a QPI interface is reserved for connection with the interconnect board for system expansion. In addition, the number of CPUs included in the node needs to be set according to the system architecture formed by the node. If the system architecture of the node is an 8P system (a system with 8 CPUs) and consists of 4 nodes, then each node in the system can set 2 CPUs.

The data processing node provided by the embodiment of the present invention includes a CPU module and an interconnection board. Since the CPU module is formed by full interconnection between the CPUs, the CPU module can be used as a single node, and, in addition, the CPU module is at least Retaining an interconnect interface to connect to an interconnecting interface of the interconnect board, the interconnect board including at least one external interconnect interface for connecting to an external interconnect interface of the interconnecting boards of other data processing nodes, The CPU module can also be extended to use with multi-node systems in conjunction with interconnect boards. Whether as a stand-alone node or as a multi-node system, each CPU in the node realizes interconnection between CPUs in the node through full interconnection, and CPUs of different nodes realize CPU between different nodes through the interconnection board. The interconnection, and the external interconnection interface provided by the interconnection board between the nodes, realizes the connection, and does not need to pass through the interconnection module, thereby reducing the delay caused by the interconnection module.

In order to facilitate the understanding of those skilled in the art, the data provided by another embodiment of the present invention is now provided. The node is detailed. In this embodiment, the interconnect board is a Field Programmable Gate Array (FPGA) interconnect board.

As shown in FIG. 3( a ), a data processing node according to another embodiment of the present invention includes a plurality of CPUs, each CPU includes a plurality of interconnect interfaces, and the CPUs are completely interconnected through interconnect interfaces to form a CPU module, wherein the CPU module reserves at least one interconnect interface and an internal interconnect interface of the interconnect board, and the FPGA interconnect board includes an FPGA chip corresponding to the reserved interconnect interface, and each FPGA The chip provides at least one internal interconnect interface and one external interconnect interface. The external interconnect interface is used to connect with an external interconnect interface of the interconnecting boards in other data processing nodes.

In this embodiment, as shown in FIG. 3(b), the FPGA chip includes: a module of a physical layer initialization process.

The string de-serialization module 32 is configured to: when receiving a data packet sent by the CPU, convert the data packet into a high-speed transmission signal and send the data to another data processing node, and when receiving the high-speed transmission signal sent by another data processing node, The high speed transmission signal is converted to a data packet that the CPU can process and sent to the CPU.

Further, in order to avoid the long-term connection of the string de-serialization module when transmitting a high-speed transmission signal

0, the 1 condition causes the clock recovery circuit to be in error, and the serial deserialization module converts the data packet into a high-speed transmission signal by using 8B/10B coding, and then sends the data packet to another data processing node, and receives the data transmission node and sends it to another data processing node. When the signal is transmitted at a high speed, the high-speed transmission signal is decoded by 10B/8B and converted into a data packet that the CPU can process. Thus, during the transmission of data from one of the data processing nodes to another of the data processing nodes, there is no other processing of the data, as seen by any of the data processing nodes, as if directly with another The data processing nodes are connected, and data is transparently transmitted from one of the data processing nodes to another of the data processing nodes.

A CPU with four interconnect interfaces (QPI) is taken as an example for detailed description. When the data processing node includes multiple CPUs, if the CPU only includes four interconnect interfaces, the multiple CPUs are at most Four CPUs are now described in detail with 2P nodes and 4P nodes as examples. (1) 2P node: includes 2 CPUs, respectively CPUO, CPU1, as shown in FIG. 4(a), CPUO and CPU1 are interconnected by a QPI interface to form a CPU module. In this embodiment, the CPU0 and The CPU 1 is interconnected by two QPI interfaces, that is, two interconnected channels are formed between the CPUO and the CPU 1, one of which is used for interconnecting communication and the other is used for redundant backup. As shown in FIG. 4(b), the CPU module reserves four QPI interfaces for external interconnection, and the CPU0 and the CPU1 respectively provide two QPI interfaces. The four QPI interfaces reserved by the CPU module are respectively connected to the FPGA interconnect board through a dedicated plug-in Air max, wherein the FPGA interconnect board includes FPGA chips corresponding to the reserved four QPI interfaces, respectively fpgaO , Q) gal , Q) ga2 , fpga3 , each FPGA chip provides an internal interconnect interface for its corresponding QPI interface and provides an external interconnect interface for external connections.

In this embodiment, the reserved ^four QPI interfaces are respectively provided by CPU0 and CPU1, and at least one reserved QPI interface of CPU0 and CPU1 is used for external interconnection.

It is worth noting that the data processing system using the above 2P nodes can realize the system expansion of 4P and 8P.

(2) 4P node: including 4 CPUs, respectively CPUO, CPU1, CPU2, CPU3, as shown in Figure 5 (a), CPUO, CPU1, CPU2, CPU3 are fully interconnected to form a CPU module. In the embodiment, the CPU0-CPU3 needs to adopt three QPI interfaces to implement full interconnection. As shown in Figure 5 (b), the CPU module reserves four QPI interfaces for external interconnection, and one QPI interface is provided by CPU0, CPU1, CPU2, and CPU3, respectively. The four QPI interfaces reserved by the CPU module are respectively connected to the FPGA interconnect board through a dedicated plug-in Air max, wherein the FPGA interconnect board includes FPGA chips corresponding to the reserved four QPI interfaces, respectively Ga0 , fpgal , ga2 , ga3 , each FPGA chip provides an internal interconnect interface for its corresponding QPI interface and provides an external interconnect interface for external connections.

In this embodiment, due to the limitation of the number of CPU interconnection interfaces, four CPUs are set in each node, and the QPI interfaces of each CPU are used for interconnection between CPUs, so Redundant backup. It is worth noting that the data processing system using the above 4P node can realize the system expansion of 8P and 16P.

It should be noted that the interconnecting board may also be an NC chip. In another embodiment of the present invention, a data processing node is provided, which includes an interconnecting board as an NC chip, and the following interconnecting board is an NC chip data processing. The node performs a detailed description.

As shown in FIG. 6, a data processing node according to another embodiment of the present invention includes a plurality of processor CPUs, each CPU includes a plurality of interconnect interfaces, and the CPUs are completely interconnected through interconnect interfaces to form a CPU module, the CPU module at least one interconnect interface for connecting to an internal interconnect interface of the NC chip, the NC chip including an interconnecting interface corresponding to the reserved interconnect interface And at least one external interconnect interface for connecting to an external interconnect interface of the NC chip of the other data processing node.

In this embodiment, the NC chip integrates a routing module, and the routing module routes the data packet received by the NC chip to its corresponding CPU.

The data processing node provided by the embodiment of the present invention includes a CPU module and an interconnection board. Since the CPU module is formed by full interconnection between the CPUs, the CPU module can be used as a single node, and, in addition, the CPU module is at least Reserve an interconnection interface and the interconnection of the interconnection board The connection port is connected, and the interconnection board includes at least one external interconnection interface for connecting with an external interconnection interface of the interconnection board of other data processing nodes, so the CPU module can also be extended with the interconnection board to extend to the multi-node system. . Whether as a stand-alone node or as a multi-node system, each CPU in the node realizes interconnection between CPUs in the node through full interconnection, and CPUs of different nodes realize CPU between different nodes through the interconnection board. The interconnection, and the external interconnection interface provided by the interconnection board between the nodes, realizes the connection, and does not need to pass through the interconnection module, thereby reducing the delay caused by the interconnection module.

The data processing system provided by the embodiment of the present invention includes at least two data processing nodes provided by the foregoing embodiments, where the at least two data processing nodes implement the at least two data processing through an external interconnection interface on the interconnect board thereof. Interconnection between nodes.

Specifically, the at least two data processing nodes implement interconnection between the at least two data processing nodes through external interconnect ports on the interconnecting board, including:

Performing partial node direct connection between the at least three data processing nodes through the external interconnection interface on the interconnect board between the at least three data processing nodes, and implementing the remaining nodes by directly connecting the partial nodes Indirect interconnection. Or

The at least two data processing nodes implement full interconnection between the at least two data processing nodes via an external interconnect interface on their interconnect boards.

Further, the interconnection board may further be provided with an interconnection interface as a backup redundancy interface. In the present embodiment, a 2P node is described as a data processing node, i.e., a basic node of the data processing system, in detail.

As shown in FIG. ,, the four 2P nodes are extended to an 8P data processing system through a high speed transmission line. The structure diagram of the 2P node is shown in FIG. 5( a ) and FIG. 5 ( b ), and details are not described herein again. The 2P node reserves four QPI interfaces externally, which are provided by CPU0 and CPU1, respectively.

When node 1-4 implements partial node direct connection, and through the direct connection of the partial node to realize the indirect interconnection of the remaining nodes, node 1-4 still has an unused QPI interface, then, the remaining QPI The interface is used to implement full interconnection between nodes. In the implementation of the full interconnection between nodes, nodes 1-4 also have unused QPI interfaces, which can be used as redundant backups.

It is worth noting that since the function of the NC chip has more powerful processing functions than the function of the FPGA chip, it is relatively powerful in the above, so the data processing system is composed of 2P nodes, which can realize a higher level of system expansion. I will not go into details here.

The data processing system provided by the embodiment of the present invention includes a CPU module and an interconnection board. Since the CPU module is formed by full interconnection between the CPUs, the CPU module can be used as a single node, and at least, the CPU module is at least Retaining an interconnect interface to connect to an interconnecting interface of the interconnect board, the interconnect board including at least one external interconnect interface for connecting to an external interconnect interface of the interconnecting boards of other data processing nodes, The CPU module can also be extended to use with multi-node systems in conjunction with interconnect boards. Whether as a stand-alone node or as a multi-node system, each CPU in the node realizes interconnection between CPUs in the node through full interconnection, and CPUs of different nodes realize CPU between different nodes through the interconnection board. The interconnection, and the external interconnection interface provided by the interconnection board between the nodes, realizes the connection, and does not need to pass through the interconnection module, thereby reducing the delay caused by the interconnection module.

As shown in FIG. 8, the embodiment of the present invention provides a data processing method for a data processing system, where the data processing system includes a plurality of data processing nodes, and the data processing node includes multiple CPUs, and multiple CPUs pass each other. The connection ports are all interconnected to form a CPU module, and the CPU module reserves at least one interconnection interface to be connected to the interconnection interface of the interconnection board, the interconnection board includes at least one external interconnection interface, and the other An external interconnect interface of the interconnecting board of the data processing node, the interconnecting board is a field programmable gate array FPGA interconnect board, and the FPGA interconnect board includes an FPGA chip corresponding to the reserved interconnect interface Each FPGA chip provides at least one internal interconnection interface and one external interconnection interface, and the data processing method includes: converting the data packet into a high speed transmission signal, and transmitting the high speed transmission signal to the Other data processing nodes to which the data processing node is connected. Step 802,

The high-speed transmission signal converts the high-speed transmission signal into a data packet that the CPU can process, and transmits the data packet to the CPU.

Further, the method further includes:

When the data processing system is initialized, the FPGA chip completes the physical layer initialization process of the interconnection interface in conjunction with the CPU connected thereto.

The data processing method provided by the embodiment of the present invention includes a CPU module and an interconnection board. Since the CPU module is formed by full interconnection between the CPUs, the CPU module can be used as a single node, and, in addition, the CPU module Retaining at least one interconnect interface with an interconnecting interface of the interconnect board, the interconnect board including at least one external interconnect interface for connecting to an external interconnect interface of the interconnecting boards of other data processing nodes, Therefore, the CPU module can also be extended to the multi-node system in conjunction with the interconnect board. Whether as a stand-alone node or as a multi-node system, each CPU in the node realizes interconnection between CPUs in the node through full interconnection, and CPUs of different nodes realize CPU between different nodes through the interconnection board. The interconnection, and the external interconnection interface provided by the interconnection board between the nodes, realizes the connection, and does not need to pass through the interconnection module, thereby reducing the delay caused by the interconnection module.

The data processing method provided by the embodiment of the present invention is applied to a data processing system, where the data processing node includes a plurality of CPUs, and multiple CPUs are completely interconnected through an interconnection interface to form a CPU module, and the CPU module is Retaining at least one interconnect interface with an interconnecting interface of the interconnect board, the interconnect board including at least one external interconnect interface for connecting to an external interconnect interface of the interconnecting boards of other data processing nodes, The interconnecting board is a node control NC chip, and the NC chip includes an interconnecting interface corresponding to the reserved interconnecting interface, and an external interconnecting interface with an NC chip of the other data processing node. The data connection processing method includes: the NC chip routing the data packet sent by the CPU to its corresponding CPU.

The data processing method provided by the embodiment of the present invention includes a CPU module and an interconnection board. Since the CPU module is formed by full interconnection between the CPUs, the CPU module can be separately used as One node is used. In addition, since the CPU module reserves at least one interconnection interface and the interconnection interface of the interconnection board, the interconnection board includes at least one external interconnection interface for mutual interaction with other data processing nodes. The external interface of the board is connected, so the CPU module can also be extended to the multi-node system in conjunction with the interconnect board. Whether as a stand-alone node or as a multi-node system, each CPU in the node realizes interconnection between CPUs in the node through full interconnection, and CPUs of different nodes realize CPU between different nodes through the interconnection board. The interconnection, and the connection between the nodes provided by the interconnection board to the external interconnection interface, improves the scalability of the minicomputer system.

The data processing node, system and method provided by the embodiments of the present invention can be applied to a computer system.

A person skilled in the art can understand that all or part of the steps of implementing the above embodiments can be completed by a program to instruct related hardware, and the program can be stored in a computer readable storage medium, such as ROM/RAM, magnetic. Disc or CD. The above is only the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope of the present invention. It should be covered by the scope of the present invention. Therefore, the scope of the invention should be determined by the scope of the appended claims.

Claims

Claim

A data processing node, comprising a plurality of processor CPUs, each CPU comprising a plurality of interconnect interfaces, wherein the CPUs are completely interconnected by interconnecting interfaces to form a CPU module, the CPU module At least one interconnect interface is reserved for interconnection to the interconnect interface of the interconnect board, the interconnect board including at least one external interconnect interface for interfacing with external interconnect interfaces of interconnect boards of other data processing nodes.

2. The data processing node according to claim 1, wherein the number of CPUs included in the data processing node is set according to a total number of interconnected interfaces of the CPU and a system architecture formed by the data processing node.

The data processing node according to claim 1 or 2, wherein the interconnection board is a field programmable gate array FPGA interconnection board, and the FPGA interconnection board includes an interconnection with the reservation The FPGA chip corresponding to the interface, each FPGA chip provides at least one internal interconnection interface and one external interconnection interface.

The data processing node according to claim 3, wherein the FPGA chip comprises:

An initialization module: a module for performing a physical layer initialization process with a CPU connected to the FPGA chip;

The string de-serialization module is configured to: when receiving a data packet sent by the CPU, convert the data packet into a high-speed transmission signal and send it to another data processing node, and when receiving the high-speed transmission signal sent by another data processing node, The high-speed transmission signal is converted to a data packet that the CPU can process and sent to the CPU.

The data processing node according to claim 1 or 2, wherein the interconnection board is a node controller NC chip, and the NC chip includes a corresponding pair with the reserved interconnection interface. An internal interconnect interface and an external interconnect interface coupled to the external interconnect interface of the NC chip of the other data processing node.

The data processing node according to claim 5, wherein the NC chip is integrated with a routing module, and the routing module routes the data packet received by the NC chip to its corresponding CPU.

A data processing system, comprising: at least two data processing nodes according to any one of claims 1-6, wherein the at least two data processing nodes communicate with each other through an interconnecting board thereof The connection port implements interconnection between the at least two data processing nodes.

8. The data processing system according to claim 7, wherein the interconnection between the at least two data comprises:

Performing partial node direct connection between the at least three data processing nodes through the external interconnection interface on the interconnect board between the at least three data processing nodes, and implementing the remaining nodes by directly connecting the partial nodes Indirect interconnection; or,

9. The data processing system according to claim 8, wherein the interconnection board is further provided with an interconnection interface as a backup redundancy interface.

10. A data processing method for a data processing system, the data processing system comprising a plurality of data processing nodes, wherein the data processing node comprises a plurality of processor CPUs, and the plurality of CPUs are interconnected The interfaces are fully interconnected to form a CPU module, the CPU module at least one interconnect interface being interconnected with an interconnecting interface of the interconnect board, the interconnect board including at least one external interconnect interface for use with other data The external interconnect interface of the interconnecting board of the processing node, the interconnecting board is a field programmable gate array FPGA interconnect board, and the FPGA interconnect board includes an FPGA chip corresponding to the reserved interconnect interface. The data processing method includes: converting a packet into a high-speed transmission signal, transmitting the high-speed transmission signal to other data processing nodes connected to the data processing node; transmitting a signal, converting the high-speed transmission signal into a CPU capable Processed packet, the packet Sent to the CPU.

The method according to claim 10, further comprising:

When the data processing system is initialized, the FPGA chip cooperates with a CPU connected thereto to complete the physical layer initialization process of the internal interconnection interface.

12. A data processing method, applied in a data processing system, wherein the data processing node comprises a plurality of processor CPUs, and the plurality of CPUs are completely interconnected through an interconnection interface to form a CPU module. The CPU module reserves at least one interconnect interface connected to the interconnecting interface of the interconnect board, and the interconnect board includes at least one external interconnect interface for external interconnection of interconnect boards with other data processing nodes. An interface is connected, the interconnecting board is a node control NC chip, and the data processing method includes: the NC chip routing a data packet sent by the CPU to its corresponding CPU.