CN1172248C - Method of realizing multiple CPU totally interconnected using synchronous serial port - Google Patents
Method of realizing multiple CPU totally interconnected using synchronous serial port Download PDFInfo
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- CN1172248C CN1172248C CNB011342161A CN01134216A CN1172248C CN 1172248 C CN1172248 C CN 1172248C CN B011342161 A CNB011342161 A CN B011342161A CN 01134216 A CN01134216 A CN 01134216A CN 1172248 C CN1172248 C CN 1172248C
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Abstract
The present invention discloses a method of realizing the total interconnection of multiple CPUs by using synchronous serial ports. The method at least comprises the following steps: a. the signal transmission terminal of each CPU is connected with an upstream input signal line of a time slot interchange module by a synchronous serial port, and the signal reception terminal of each CPU is connected with a downstream output signal line of the time slot interchange module by a synchronous serial port; b. each CPU makes information communicated with each CPU loaded on different time sheets of the upstream input signal line connected with the CPU; c. the time slot interchange module interchanges information on each time sheet of the upstream input signal line to the corresponding time sheets of the corresponding downstream output signal line according to overlapping relationship. Multiple CPUs can be totally interconnected and communicated by simple synchronous serial ports by using the method, and the quickness and the real time of communication are guaranteed; used protocols are simple without extra CPU expenses.
Description
Technical field
The present invention relates to central processing unit (CPU) interconnection technique, be meant that especially a kind of synchronous serial interface that utilizes connects CPU and Switching Module, realizes a plurality of CPU totally interconnected method in real time by time gas exchange.
Background of invention
At communications electronics and relate in the system that signal message handles, usually need collaborative work between a plurality of CPU, this just requires between a plurality of CPU exchange message mutually.Generally, the communication between the CPU all is to utilize synchronous serial interface to realize.
At present, utilize synchronous serial interface to realize that maximum is point-to-point communication between two CPU, and realize that the communication between a plurality of CPU mainly contains two kinds of methods: a kind of is that the receiving and transmitting signal of each CPU is all connected together, by certain agreement, guarantee to have only on this bus a CPU sending data, other CPU is monitoring, and each CPU receives only the information that oneself needs.Its syndeton as shown in Figure 1, n CPU is connected on the universal serial bus 11 simultaneously, when CPU sent data, other n-1 CPU was in listening state, receives one's own data at any time.But, the software protocol complexity that this method adopted, each CPU also needs extra expense.And, because all CPU take turns time-sharing multiplex ground and use universal serial bus, just can not guarantee to communicate simultaneously between each CPU, can't satisfy the exigent occasion of application real-time.Another kind method need to be realized by a host CPU forward packets through other general interface, but this method has and the similar shortcoming of first method equally.
Summary of the invention
In view of this, fundamental purpose of the present invention is to provide a kind of synchronous serial interface that utilizes to realize the method that a plurality of CPU are totally interconnected, makes it can not only reach a plurality of CPU by the totally interconnected communication of simple synchronous serial interface, and guarantees that communication fast, in real time, the employing agreement is simple, need not extra CPU expense.
For achieving the above object, technical scheme of the present invention specifically is achieved in that
A kind of synchronous serial interface that utilizes is realized the method that a plurality of CPU are totally interconnected, and key is that this method comprises the steps: at least
A. the signal sending end with each CPU is connected with the up input signal cable of time gas exchange module by synchronous serial interface, and the signal receiving end of each CPU is connected with the descending output signal line of time gas exchange module by synchronous serial interface;
B. each CPU will be carried on respectively with the information that each CPU communicates by letter on the different time sheet of the up input signal cable that it was connected;
C. the time gas exchange module according to bonding relation with the message exchange on each timeslice of up input signal cable on the corresponding timeslice of corresponding downstream output signal line, wherein, described bonding relation is: j timeslice of the up input signal cable of i bar is connected with i timeslice of the descending output signal line of j bar.Here, the value of i and j can be identical or different.
Described CPU directly is connected with the hardware connection mode with descending output signal line with the up input signal cable of time gas exchange module, and a up input signal cable and a descending output signal line of the corresponding time gas exchange module of each CPU.The quantity of this CPU is decided by the communication flows between the exchange capacity of time gas exchange module, the signal wire number that can provide and the CPU.
A time slot in the described timeslice corresponding data frame; An or above time slot in the corresponding data frame.The number of described timeslice is by every maximum operation frequency decision that input, output line can be supported in the maximum operation frequency of CPU serial ports, exchange capacity that the time gas exchange module can be supported and the time gas exchange module.
Described time gas exchange module is the dedicated time slot exchange chip, or is logical circuit.
By such scheme as can be seen, the synchronous serial interface that utilizes provided by the present invention is realized the method that a plurality of CPU are totally interconnected, has following advantage and characteristics:
1) real-time: the present invention makes full use of the time gas exchange module will need information transmitted to be carried on the different time sheet of same upward signal line between certain CPU and each CPU, and exchange on the same timeslice of different downgoing signal lines, simultaneously each rs 232 serial interface signal is isolated, make when realizing between the different CPU by the different time sheet that takies the rs 232 serial interface signal line between each CPU communication, realized totally interconnected in real time between a plurality of CPU fully.
2) applied widely: link to each other by synchronous serial interface fully between each CPU and the time gas exchange module among the present invention, therefore, applicable to the communication between the CPU of all band synchronous serial interfaces.
3) circuit is simple: this circuit connection is simple, and the just connection between serial ports does not need the link setup of shaking hands before complicated communication protocol communicates, and only adopts common synchronous serial interface agreement to get final product.In addition, the time gas exchange module can directly adopt special-purpose time gas exchange chip or logic to realize, therefore, and integrated circuit simplicity of design, standard.
4) circuit cost is low: owing to do not need to increase arbitration and the control that host CPU communicates in addition, reduced circuit cost.
5) communication efficiency height: because CPU does not need extra expense, do not take the resource of CPU in addition, alleviated the burden of CPU, improved communication efficiency and communication performance.
Description of drawings
The syndeton synoptic diagram of Fig. 1 for communicating by letter between a plurality of CPU in the prior art;
The theory diagram of Fig. 2 for communicating by letter between a plurality of CPU among the present invention;
The enforcement illustration of Fig. 3 for communicating by letter between a plurality of CPU among the present invention.
Embodiment
The present invention is further described in more detail below in conjunction with drawings and the specific embodiments.
Method of the present invention is that the serial ports of each CPU is set up semipermanent connection by the time gas exchange module, and some that stipulate that communication between every couple of CPU only takies high-speed data-flow (HW) be time slot fixedly, to reach totally interconnected between the CPU.Generally, the signal wire of a transmitting high speed data is called a HW line.So-called HW is made up of timeslice data at a high speed, and each timeslice can transmit a speech data, and each timeslice can be carried a voice channel.HW is divided into several types such as 16M, 8M, 2M according to transfer rate.
For certain input term signal, every frame data have been divided m time slot, and the value of this m is by the clock frequency of serial ports and the interval determination of frame synchronizing signal.Such as: when the serial ports frequency of operation is 2.048Mhz, when frame synchronizing signal was 8K, m was 32 time slots; When the serial ports frequency of operation is 8.196Mhz, when frame synchronizing signal was 8K, m was 128 time slots; When the serial ports frequency of operation is 16.384Mhz, frame synchronizing signal is 8K, and m is 256 time slots.When certain CPU communicates by letter with other CPU, on the different time-gap of the up input signal cable (UHW) that the information that exchanges to different CPU is carried to this CPU respectively and is connected, by the time gas exchange module, exchange on the corresponding time slot of corresponding descending output signal line (DHW) then.
Among the present invention, be corresponding one by one directly between the UHW in CPU and the time gas exchange module by the hardware line; And the bonding relation of time gas exchange inside modules also is to set as required in advance, is finished by the primary processor control of this module of control when module initialization.When the number of CPU changed, relevant hardware line and inner bonding relation also changed thereupon, and the variation of this bonding relation is by the primary processor of controlling this module it to be configured again.
As shown in Figure 2, n CPU connection communication being arranged, is that example describes its principle of work in detail with CPU0:
When CPU0 will be with each CPU, be when intercoming mutually between CPU0, the CPU1....CPUn, CPU0 links to each other by the up input signal cable UHW0 of synchronous serial interface and article one, simultaneously regulation: the communication information between CPU0 and CPU0, the CPU1....CPUn is carried on timeslice TS0, the TS1....TSn respectively successively.What wherein, carried on the TS0 is the certainly ring information of CPU0 to CPU0.The predefined bonding relation of this time gas exchange inside modules is as follows:
UHW(i)ch(j)＝DHW(j)ch(i) (1)
Wherein, ch refers to timeslice; I and j are respectively the signal wire sequence number of input signal UHW and output signal DHW, and i and j value are 0～n.When i=j, this passage leads directly to, and can be used to support the near-end loopback test of synchronous serial interface.N is the timeslice number, and n≤m, when timeslice and frame slot one by one at once, n=m; When an a plurality of frame slot of timeslice correspondence, n＜m.That is to say that an above time slot that can take in the Frame between any two CPU communicates, specifically take 1,2, a 4.... time slot determines according to actual conditions and design needs.Scope as for the n value is specifically decided by Devices Characteristics, the main in the present invention and maximum operation frequency of CPU serial ports, exchange capacity and every I/O that the time gas exchange device can be supported, promptly the maximum operation frequency that can support of UHW, DHW signal wire is relevant.
Can release according to (1) formula, the information of last each timeslice of UHW0 has exchanged to respectively on the TS0 timeslice of n bar DHW, exactly be exactly: the message exchange of UHW0.TS0 has been arrived on the TS0 of DHW0, the message exchange of UHW0.TS1 has been arrived on the TS0 of DHW1 ... the message exchange of .UHWn.TS16 has been arrived on the TS0 of DHWn.
Other n-1 CPU is identical with the message exchange principle and the CPU0 that communicate by letter between each CPU.Therefore, release according to (1) formula, the beared information of descending output signal line DHW is as follows:
The n of DHW0 the corresponding UHW0.TS0 ‖ of timeslice UHW1.TS0 ‖ .... ‖ UHWn.TS0;
The n of DHW1 the corresponding UHW0.TS1 ‖ of timeslice UHW1.TS1 ‖ .... ‖ UHWn.TS1;
............................
The n of DHWn the corresponding UHW0.TSn ‖ of timeslice UHW1.TSn ‖ .... ‖ UHWn.TSn.That is to say that the output information when each CPU communicates by letter with all CPU all is placed in the corresponding timeslice identical with this CPU sequence number, be placed among the TS0 of each output line such as the communication information of CPU0 and all CPU; The communication information of CPU1 and all CPU is placed among the TS1 of each output line; ... the communication information of .CPUn and all CPU is placed among the TSn of each output line.
The CPU number that the inventive method support connects in theory can be a lot, but in the running environment of reality, the CPU quantity that can interconnect is finally decided by the communication flows between the exchange capacity of time gas exchange chip, the HW line number that can provide and the CPU.
As seen, the present invention utilizes synchronous serial interface to realize the method that a plurality of CPU are totally interconnected, can not only guarantee communication simultaneously between a plurality of CPU, does not disturb mutually, thereby has significantly reduced the stand-by period that CPU causes owing to conflict; And, do not need complicated software handshake agreement to set up the connection of communication, alleviated the burden of CPU greatly.
Fig. 3 is a concrete application example of the present invention, has 16 digital signal processors (DSP) to utilize the synchronous serial interface of himself--multichannel buffered serial port (McBSP), realize totally interconnected between 16 DSP by the time gas exchange module.In the present embodiment, the time gas exchange module adopts special-purpose time gas exchange chip SD539, and the bonding relation of (1) formula of employing, and the serial ports frequency of operation is 16.384Mhz, frame synchronizing signal is 8K, therefore, and m=256, n=16, m=16n, i.e. corresponding 16 time slots of timeslice.
Referring to shown in Figure 3, DSP0～DSP15 is respectively by sending 16 up input signal cable UHW0～UHW15 that signal end DX0～DX15 connects time gas exchange chip SD539, simultaneously, 16 of time gas exchange chip SD539 descending output signal line DHW0～DHW15 link to each other with DSP respectively by received signal end DR0～DR15 of DSP0～DSP15 respectively.Because corresponding 16 every signal line of DSP have been divided 16 timeslices, i.e. TS0～TS15 is so 16 actual time slots in corresponding Frame of timeslice TSi.
According to the regulation of (1) formula, the communication information of DSP0 and 16 DSP is placed on respectively among the TS0 of descending output signal line DHW0～DHW15; The communication information of DSP1 and 16 DSP is placed on respectively among the TS1 of descending output signal line DHW0～DHW15; ... the communication information of .DSP15 and 16 DSP is placed on respectively among the TS15 of descending output signal line DHW0～DHW15.The beared information of then descending 16 output signal line DHWi is respectively:
The corresponding UHW0.TS0 ‖ of the frame data of DHW0 UHW1.TS0 ‖ .... ‖ UHW15.TS0;
The corresponding UHW0.TS1 ‖ of the frame data of DHW1 UHW1.TS1 ‖ .... ‖ UHW15.TS1;
............................
The corresponding UHW0.TS15 ‖ of the frame data of DHW15 UHW1.TS15 ‖ .... ‖ UHW15.TS15.
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.
Claims (8)
1, a kind of synchronous serial interface that utilizes is realized the method that a plurality of CPU are totally interconnected, it is characterized in that this method comprises the steps: at least
A. the signal sending end with each CPU is connected with the up input signal cable of time gas exchange module by synchronous serial interface, and the signal receiving end of each CPU is connected with the descending output signal line of time gas exchange module by synchronous serial interface;
B. each CPU will be carried on respectively with the information that each CPU communicates by letter on the different time sheet of the up input signal cable that it was connected;
C. the time gas exchange module according to bonding relation with the message exchange on each timeslice of up input signal cable on the corresponding timeslice of corresponding downstream output signal line, wherein, described bonding relation is: j timeslice of the up input signal cable of i bar is connected with i timeslice of the descending output signal line of j bar.
2, method according to claim 1, it is characterized in that: described CPU directly is connected with the hardware connection mode with descending output signal line with the up input signal cable of time gas exchange module, and a up input signal cable and a descending output signal line of the corresponding time gas exchange module of each CPU.
3, method according to claim 1 is characterized in that: the value of described i and j is identical, or the value difference.
4, method according to claim 1 and 2 is characterized in that: the quantity of described CPU is decided by the communication flows between the exchange capacity of time gas exchange module, the signal wire number that can provide and the CPU.
5, method according to claim 1 is characterized in that: a time slot in the described timeslice corresponding data frame.
6, method according to claim 1 is characterized in that: an above time slot in the described timeslice corresponding data frame.
7, method according to claim 1 is characterized in that: the number of described timeslice is by every maximum operation frequency decision that input, output line can be supported in the maximum operation frequency of CPU serial ports, exchange capacity that the time gas exchange module can be supported and the time gas exchange module.
8, method according to claim 1 is characterized in that: described time gas exchange module is the dedicated time slot exchange chip, or is logical circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011342161A CN1172248C (en) | 2001-10-26 | 2001-10-26 | Method of realizing multiple CPU totally interconnected using synchronous serial port |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB011342161A CN1172248C (en) | 2001-10-26 | 2001-10-26 | Method of realizing multiple CPU totally interconnected using synchronous serial port |
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| CN1414483A CN1414483A (en) | 2003-04-30 |
| CN1172248C true CN1172248C (en) | 2004-10-20 |
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| JP4509827B2 (en) * | 2005-03-04 | 2010-07-21 | 富士通株式会社 | Computer system using serial connect bus and method of connecting multiple CPU units by serial connect bus |
| WO2012103736A1 (en) * | 2011-06-30 | 2012-08-09 | 华为技术有限公司 | Data processing node, system and method |
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