WO2014019346A1

WO2014019346A1 - Dynamic link configuration device and method for multipath server

Info

Publication number: WO2014019346A1
Application number: PCT/CN2013/070356
Authority: WO
Inventors: 王恩东; 胡雷钧; 李仁刚
Original assignee: 浪潮(北京)电子信息产业有限公司
Priority date: 2012-08-01
Filing date: 2013-01-11
Publication date: 2014-02-06
Also published as: CN102880583A; CN102880583B

Abstract

A dynamic link configuration device and method for a multipath server. In order to rationally verify a multipath server system structure and realize interconnected communication among various processors, the dynamic link configuration device and method for a multipath server use a double-step configuration to realize dynamic conversion of an interconnecting link of the processors from a direct connection mode to an FPGA verification chip. The initialization on links between a multipath processor and interface logics realized by an FPGA chip is realized respectively, and a control logic is used to realize intraconnection of the interface logics realized by the FPGA chip, so that the interconnected communication during processing is performed only through a test link realized by the FPGA chip. It is ensured that an interconnecting link among processors in a multipath server system exists at any moment, and at the same time, the dynamic availability conversion of a physical link among the processors is realized, greatly reducing the complexity of hardware design of a verification platform, and completing the transparent transmission of a physical link among processors based on an FPGA chip.

Description

Multi-way server dynamic link configuration device and method

Technical field

The present invention relates to the field of high-end servers, and in particular, to a multi-way server dynamic link configuration apparatus and method.

Background technique

With the rapid development of computer technology and integrated circuit technology, in order to meet the needs of economic and social development, high-end server systems have become one of the bottlenecks restricting key areas of social development. The enormous data computing and data analysis, complex graphical analysis and scientific budgeting fields require extremely high performance for server systems. Therefore, it is necessary to build a huge multi-way server system to better adapt to the application needs of today's various fields, but on the other hand, it is also caught in the technical problem of multi-channel server system inter-processor interconnect verification and system key chipset verification platform design. . Summary of the invention

In order to reasonably verify the multi-way server system structure and realize interconnection communication between the various processors, the present invention provides a multi-way server dynamic link configuration apparatus and method.

In order to solve the above technical problem, the present invention provides a multi-way server dynamic link configuration device, including a configuration module, a link initialization control module, and a plurality of processor logic interfaces.

The processor logic interface is configured to: be in communication with the corresponding processor according to a configuration of the configuration module;

The configuration module is configured to: configure, for each processor, a processor logical interface corresponding to the processor, and establish an interface link between the processor and the corresponding processor logical interface; The control module is configured to: configure an internal interconnect link of each processor logical interface according to a pre-connected link between the processors, so that each processor passes an interface link with the corresponding processor logic interface, each processor An internal interconnect link of the logical interface establishes the pre-connected link;

The interface link is a communication link between a processor and a processor logical interface, and the internal interface A link is a logical communication link between two processor logical interfaces.

Preferably, the pre-connected link between the respective processors is a direct link of each processor, and the direct link is a communication link between every two processors.

Preferably, the link initialization control module and the plurality of processor logic interfaces are implemented by using an FPGA.

Preferably, the configuration module is further configured to: configure a direct link of each processor before configuring an interface link between each processor and a logical interface of the processor, where the direct link is for every two processes Communication link between the devices.

Preferably, the link initialization control module is further configured to: after all internal interconnect links are established, feed back a link completion signal to the configuration module;

The configuration module is further configured to: disconnect some or all of the direct links after receiving the link completion signal.

Preferably, the configuration device further includes a monitoring module,

The monitoring module is configured to: monitor the working state of the link initialization control module and the plurality of processor logic interfaces, and issue a warning when any one or more processor logic interfaces and/or link initialization control modules work abnormally.

Preferably, the working state includes an interface link connection state of each processor and a corresponding processor logical interface and an internal interconnect link connection state of each processor logical interface; the working abnormality refers to any one of the processors and The interface link of the corresponding processor logic interface or the internal interconnect chain of any one of the processor logic interfaces fails or is not successfully initialized.

In order to solve the above technical problem, the present invention also provides a multi-path server dynamic link configuration method, including:

Step A: Configure an interface link between each processor and a corresponding processor logical interface; Step B: Configure an internal interconnection link of each processor logical interface;

The interface link is a communication link between a processor and a processor logical interface, and the internal interconnection link is a logical communication link between two processor logical interfaces.

Preferably, before step A, the method further includes: configuring a direct link of each processor, the straight The link is the communication link between every two processors.

Preferably, after step B, the method further includes: disconnecting some or all of the direct links.

Advantageously, the method further comprises monitoring the operational status of the link initialization control module and the plurality of processor logic interfaces, and issuing a warning when any one or more of the processor logic interfaces and/or the link initialization control module are operating abnormally.

The multi-way server dynamic link configuration apparatus and method of the embodiment of the present invention implements dynamic conversion of the processor interconnect link from the direct connection mode to the FPGA verification chip by using a two-step configuration. The link initialization of the interface logic implemented by the multiprocessor and the FPGA chip is respectively implemented, and the control logic is used to implement the internal interconnection of the interface logic implemented by the FPGA chip, so that the interconnect communication communicates only through the test link implemented by the FPGA chip during processing. It ensures the existence of interconnected links between processors in a multi-path server system, and realizes the dynamic availability conversion of physical links between processors, greatly reducing the complexity of the hardware design of the verification platform, and completing the processing based on FPGA chips. Transparent transmission of physical links between devices. It also ensures that the FPGA chip implements the interconnection interface protocol logic and the completeness of the system key chipset logic verification platform. BRIEF abstract

1 is a schematic structural diagram of a two-way server dynamic link configuration apparatus according to an embodiment of the present invention; FIG. 2 is a schematic structural diagram of a three-way server dynamic link configuration apparatus according to an embodiment of the present invention; FIG. 4 is a schematic flowchart of a method for configuring a dynamic link of a multi-path server according to an embodiment of the present invention; FIG.

Preferred embodiment of the invention

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in the case of no conflict, the features in the embodiments and the embodiments in the present application may be arbitrarily combined with each other. The multi-way server dynamic link configuration apparatus and scheme of the embodiment of the present invention mainly considers the characteristics of the inter-processor interconnect link design structure in the multi-path server system, and firstly implements the multi-channel processor and

The FPGA chip interface link is initialized, and the internal logic interconnection of the interface is implemented by the control logic, thereby completing the interconnection communication between the multiple processors.

The multi-way server dynamic link configuration apparatus provided by the embodiment of the present invention, as shown in FIG. 1, mainly includes a configuration module 1, a link initialization control module 2, and a plurality of processor logic interfaces 3,

The configuration module 1 is configured to configure an interface link between each processor and the corresponding processor logical interface 3;

The link initialization control module 2 is configured to configure an internal interconnect link of each processor logical interface 3, such that each processor passes an interface link with the corresponding processor logical interface 3, and each processor logical interface 3 The internal interconnect link establishes a pre-connected link;

The interface link is a communication link between the processor and the processor logical interface 3, and the internal interconnect link is a logical communication link between the two processor logical interfaces 3.

The configuration module 1 is equivalent to the communication between the multi-processor and the processor logical interface 3 as indicated in the above principle;

Each processor is connected to a processor logic interface 3;

The link initialization control module 2 is equivalent to the internal interconnection between the processor logic interfaces 3 indicated in the above principle.

The pre-connected link is a communication link that is desired or ready to be established between the various processors.

The multi-way server dynamic link configuration apparatus of the embodiment of the present invention can also implement a dynamic conversion of the processor interconnect link from the direct connection mode to the FPGA verification chip by using a two-step configuration method:

The configuration module 1 first configures a direct link of each processor, and configures an interface link between each processor and the processor logical interface 3 based on the completion of the direct link initialization between the processors, and then The internal interconnect link of each processor logical interface 3 is configured by a link initialization control module 2, which is a communication link between every two processors.

The multi-way server dynamic link configuration device fully considers the interface logic structure realized by the FPGA chip, and can realize the dynamic conversion of the processor interconnection link from the direct connection mode to the FPGA verification chip. It is also possible to disconnect some or all of the direct links through configuration module 1 after all internal interconnect links have been established.

The directly connected link of the initially completed configuration is disconnected so that the interconnect communication during processing only passes through the internal interconnect link implemented by the FPGA chip.

The above process, whether it is the dynamic conversion of the processor interconnect link from the direct connection mode to the FPGA verification chip, or the direct link disconnection, enables the interconnection communication to be performed only through the internal interconnect link of the FPGA chip during processing, It ensures the existence of interconnected links between processors in a multi-path server system, which greatly reduces the complexity of the hardware design of the verification platform.

The multi-way server dynamic link configuration apparatus provided by the embodiment of the present invention may further include a monitoring module 4,

The monitoring module 4 is configured to monitor the working states of the link initialization control module 2 and the plurality of processor logic interfaces 3;

A warning is issued when any one or more of processor logic interface 3 and/or link initialization control module 2 are operating abnormally.

The working state includes an interface link connection state of each processor and a corresponding processor logical interface 3 and an internal interconnect link connection state of each processor logical interface 3; the working abnormality refers to any one processor and corresponding The interface link of the processor logical interface 3 or the internal interconnect chain of any one of the processor logical interfaces 3 fails or the initialization is unsuccessful.

The connection status and link initialization status of all links are displayed through the monitoring module 4. When any link fails or the initialization is unsuccessful, the monitoring module 4 can monitor the current fault status, thereby facilitating analysis and solving the problem. For example, when the link initialization is unsuccessful, the monitoring module 4 checks the fault status of the link and analyzes the cause of the fault. For example, when the link transmission quality is poor, the monitoring module 4 checks the number of link retransmissions. Provide an analysis basis for further optimizing link transmission quality.

The embodiment of the present invention further provides a method for configuring a dynamic link of a multi-path server. As shown in FIG. 4, the method is implemented by a multi-server dynamic link configuration apparatus, where the configuration method includes:

Step A: configuring an interface link between each processor and the processor logical interface 3; Step B: configuring an internal interconnect link of each processor logical interface 3;

Before step A, the method further includes: configuring a direct link of each processor, where the direct link is a communication link between every two processors.

After step B, the method may further include: disconnecting some or all of the direct links.

Through the configuration module 1, the processor direct link is used to realize the initialization of the multi-path server interconnection link, and the system interconnection is realized. On the basis of the completion of the processor direct link completion, the configuration module 1 respectively implements multiple paths. The interface link of the processor and the processor logic interface 3 is initialized; on the basis that the multi-channel processor completes the interface link initialization with the processor logic interface 3, the link initialization control module 2 implements the multi-processor through the processor logic. The interconnection communication of the interface 3 realizes the internal interconnection of the plurality of processor logic interfaces 3, thereby realizing the interconnection communication between the multiple processors in the multi-path server system; on the basis of the initialization of the interconnection of the multi-processor interconnects The configuration module 1 is configured to disconnect the direct link of the processor, so that the multi-processor realizes the interconnection communication only through the FPGA chip.

The two-step initialization chip configuration process of the above dynamic link availability conversion ensures the interconnection communication of the multi-way server system, realizes the dynamic availability conversion of the inter-server system processor interconnection link, and is dynamically converted by the processor direct link to The FPGA chip realizes the interconnection communication and provides a platform for the design verification of the system key chipset. This dynamic configuration implementation method also effectively reduces the complexity and development cycle of the verification platform hardware design, in the high-end server key chipset design verification process. Has a very high application value and technical value.

Example 1

The content of the embodiment of the present invention will be described below with reference to FIG.

The two-step initialization chip configuration flow implementation method for dynamic link availability conversion in the embodiment of the present invention mainly includes: processor direct link initialization, interface link initialization between each processor and processor logical interface 3, and processor logic. The internal interconnect link of interface 3 disconnects the direct link.

In the process of high-end server chipset verification and system initialization link usability testing, considering the characteristics of the link design structure, in order to improve the system structure test efficiency, reduce the test complexity, and adopt the two-step initialization implementation method of dynamic link availability conversion, Achieve multiple transmission links in high-end server systems The usability test, while implementing FPGA implementation of key chipset interface logic availability verification.

The system is powered on under the initial conditions, and the direct connection link between the two processors is configured through the configuration module 1, so that the first CPU and the second CPU are interconnected through the direct link, and the interface link and the internal interconnection link are Disconnected, that is, the first CPU communicates with the second CPU only through the direct link.

When the direct link completes initialization, the configuration module 1 configures the first CPU and the first processor logical interface 3, and the interface link between the second CPU and the second processor logical interface 3, and the link initialization control module 2 completes The first processor logic interface 3 is interconnected with the second processor logic interface 3, so that the first CPU and the second CPU communicate through the interconnection of the internal interconnection link, at this time, the direct link and the internal interconnection link Simultaneous communication, that is, communication between the first CPU and the second CPU through two links at the same time.

When the internal interconnect link is initialized, the direct link between the first CPU and the second CPU is disconnected through the configuration module 1, and the interface between the first CPU and the second CPU only passes through the interface link and the internal Interlink communication. At this point, the system realizes the connectivity, transformation, and disconnection of multiple links through dynamic configuration. The configuration process is completed in the process of initializing the link of each interface of the system, and in the process, the interworking link exists between the processors. Guarantee the stable operation of the system effectively realizes the dynamic switching of multiple links of the system, which plays a huge role in the verification and debugging phase of the high-end server system.

Example 2

Referring to FIG. 2, this embodiment is a high-end server system with a three-way processor, wherein a direct link between processors is similar to a triangle, wherein three processors are located at three vertices of a triangle, between processors A direct link is similar to the three sides of a triangle, enabling communication between every two processors. Similarly, the internal interconnect link between processor logic interfaces 3 is also similar to a triangle, where three processor logic interfaces 3 are located at three vertices of the triangle, and the internal interconnect links between processor logic interfaces 3 are similar. The logical communication between each two processor logical interfaces 3 is implemented on the three sides of the triangle.

The system realizes connectivity, conversion, and disconnection operations and embodiments of multiple links through dynamic configuration.

1 is consistent.

Example 3

Referring to FIG. 3, this embodiment is a high-end server system with a four-way processor, wherein the processor A direct link between them, similar to a quadrilateral, where four processors are located at four vertices of the quadrilateral, and the direct link between the processors is similar to the four sides of the quadrilateral and two diagonals, achieving each two Communication between processors. Similarly, the internal interconnect link between the processor logic interfaces 3 is also similar to a quadrilateral, where four processor logic interfaces 3 are located at four vertices of the quadrilateral, and the internal interconnect links between the processor logical interfaces 3 are similar. The logical communication between each two processor logic interfaces 3 is achieved by four sides and two diagonal lines of the edge.

The system realizes the connectivity, conversion, and disconnection operations of multiple links through dynamic configuration, which are consistent with Embodiments 1 and 2.

The above embodiments are only intended to illustrate the technical solutions of the present invention and are not to be construed as limiting the invention. It should be understood by those skilled in the art that the present invention may be modified or equivalently substituted without departing from the spirit and scope of the invention.

Industrial applicability

The multi-way server dynamic link configuration apparatus and method of the embodiment of the present invention implements dynamic conversion of the processor interconnect link from the direct connection mode to the FPGA verification chip by using a two-step configuration. The link initialization of the interface logic implemented by the multiprocessor and the FPGA chip is respectively implemented, and the control logic is used to implement the internal interconnection of the interface logic implemented by the FPGA chip, so that the interconnect communication communicates only through the test link implemented by the FPGA chip during processing. It ensures the existence of interconnected links between processors in a multi-path server system, and realizes the dynamic availability conversion of physical links between processors, greatly reducing the complexity of the hardware design of the verification platform, and completing the processing based on FPGA chips. Transparent transmission of physical links between devices. It also ensures that the FPGA chip implements the interconnection interface protocol logic and the completeness of the system key chipset logic verification platform.

Claims

claims

1. A multi-channel server dynamic link configuration device, the configuration device includes a configuration module (1), a link initialization control module (2) and multiple processor logical interfaces (3),

The processor logical interface (3) is set to: connect with the corresponding processor according to the configuration of the configuration module (1);

The configuration module (1) is configured to: configure a processor logical interface (3) corresponding to the processor for each processor, and establish a connection between the processor and the corresponding processor logical interface (3). interface link;

The link initialization control module (2) is set to: configure the internal interconnection link of each processor logical interface (3) according to the pre-connection link between each processor, so that each processor passes the corresponding processing The interface link of the processor logical interface (3) and the internal interconnection link of each processor logical interface (3) establish the pre-connection link;

The interface link is a communication link between the processor and the processor logical interface (3), and the internal interconnection link is a logical communication link between the two processor logical interfaces (3).

2. The configuration device according to claim 1, wherein the pre-connected link between each processor is a direct link between each processor, and the direct link is between every two processors. communication link.

3. The configuration device according to claim 1, wherein the link initialization control module (2) and multiple processor logical interfaces (3) are implemented using FPGA.

4. The configuration device according to claim 1, 2 or 3, wherein,

The configuration module (1) is also configured to: before configuring the interface link between each processor and the processor logical interface (3), configure the direct link of each processor, and the direct link is for each processor. Communication link between two processors.

5. The configuration device as claimed in claim 4, wherein,

The link initialization control module (2) is also configured to: after all internal interconnection links are established, feed back a link completion signal to the configuration module (1);

The configuration module (1) is also set to: after receiving the link completion signal, disconnect part or all of the direct link.

6. The configuration device according to claim 1 or 2 or 3 or 5, wherein the configuration device further includes a monitoring module (4),

The monitoring module (4) is set to: monitor the working status of the link initialization control module (2) and multiple processor logical interfaces (3). When any one or multiple processor logical interfaces (3) and/or link When the circuit initialization control module (2) works abnormally, a warning is issued.

7. The configuration device according to claim 6, wherein the working state includes the interface link connection state of each processor and the corresponding processor logical interface (3) and the internal interaction of each processor logical interface (3). Link connection status; The abnormal operation means that the interface link between any processor and the corresponding processor logical interface (3) or the internal interconnection link of any processor logical interface (3) fails or fails to initialize. success.

8. A multi-channel server dynamic link configuration method, the method is implemented based on the configuration device according to claims 1-7, the configuration method includes:

Step A. Configure the interface link between each processor and the corresponding processor logical interface (3); Step B. Configure the internal interconnection link of each processor logical interface (3);

9. The configuration method as claimed in claim 8, wherein,

Before step A, it also includes: configuring a direct link of each processor, where the direct link is a communication link between every two processors.

10. The configuration method as claimed in claim 9, wherein,

After step B, also include: Disconnecting some or all direct links.

11. The configuration method according to claim 8 or 9 or 10, further comprising monitoring the working status of the link initialization control module (2) and multiple processor logical interfaces (3). When any one or more processes When the controller logical interface (3) and/or the link initialization control module (2) work abnormally, a warning is issued.

12. The configuration method according to claim 11, wherein the working status includes the interface link connection status of each processor and the corresponding processor logical interface (3) and each processor logical interface (3) The connection status of the internal interconnection link; the abnormal operation refers to the failure of the interface link between any processor and the corresponding processor logical interface (3) or the internal interconnection link of any processor logical interface (3) Or the initialization was unsuccessful.