WO2012167450A1 - 薄膜晶体管矩阵及液晶显示面板 - Google Patents

薄膜晶体管矩阵及液晶显示面板 Download PDF

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Publication number
WO2012167450A1
WO2012167450A1 PCT/CN2011/075937 CN2011075937W WO2012167450A1 WO 2012167450 A1 WO2012167450 A1 WO 2012167450A1 CN 2011075937 W CN2011075937 W CN 2011075937W WO 2012167450 A1 WO2012167450 A1 WO 2012167450A1
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Prior art keywords
pixel
sub
coupled
pixel unit
liquid crystal
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PCT/CN2011/075937
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English (en)
French (fr)
Inventor
李仕琦
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US13/258,798 priority Critical patent/US20120313915A1/en
Publication of WO2012167450A1 publication Critical patent/WO2012167450A1/zh
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update

Definitions

  • the present patent application relates to a transistor matrix and a display panel thereof, and in particular to a thin film transistor matrix and a liquid crystal display panel.
  • FIG. 1 is a schematic structural view of a prior art thin film transistor matrix 100.
  • the thin film transistor matrix 100 is mainly composed of a plurality of pixel units (pixel
  • the unit 102 is composed of a plurality of scan lines 104 and a plurality of data lines 106.
  • the pixel units 102 are electrically connected to the scan lines 104 and the data lines 106.
  • Each of the pixel units 102 has a transistor 108 and a liquid crystal capacitor (liquid-crystal).
  • Capacitor, CLC)110 and storage capacitor (storage capacitor, CS) wherein each transistor 108 has a gate G, a source S, and a drain D, and the gate G is connected to the scan line 104, and the source S is connected to the data line 106.
  • the drain D is connected in common with a liquid crystal capacitor (CLC) 110 and a storage capacitor (CS) 112.
  • the liquid crystal capacitor (CLC) 110 and the storage capacitor (CS) 112 are grounded (as shown in FIG. 1) or connected to a shared line. (common Line) (not shown).
  • the thin film transistor 108 connected to the first scan line (SL1) is turned on (switch On, the pixel electrodes of the liquid crystal capacitors are electrically connected to the data lines 106 in the vertical direction, and the corresponding video signals are fed through the vertical data lines to charge the liquid crystal capacitors to an appropriate voltage level; in other words, to these
  • the liquid crystal capacitor corresponding to the pixel unit is charged to drive liquid crystal molecules in the liquid crystal layer to display an image on the liquid crystal display; and at the same time, the storage capacitors 112 connected to the data line are charged, and the storage capacitor 112 is a liquid crystal capacitor
  • the voltage across the 110 is maintained at a constant value, that is, the voltage across the liquid crystal capacitor 110 is maintained by the storage capacitor 112 before the data update is performed.
  • the patent application provides a thin film transistor matrix and a liquid crystal display panel to solve the problem that the pixel charging time is too long.
  • the purpose of this patent application is to provide a thin film transistor matrix and a liquid crystal display panel to solve the problem that the pixel charging time is too long, which transmits a video signal to one pixel unit and charges the other pixel unit when the control transistor When the gate is turned off and the voltage is applied by the other scan line, the second pixel charged in the other pixel unit charges the first pixel, thereby achieving the purpose of fast charging.
  • the present application provides a thin film transistor matrix and a liquid crystal display panel.
  • the thin film transistor matrix includes a plurality of scan lines, a plurality of data lines, a plurality of pixel units, and a plurality of control transistors, and the plurality of data lines are interleaved with the plurality of scan lines. Settings.
  • Each of the pixel units is coupled to a scan line and a data line, and each of the pixel units includes a first sub-pixel and a second sub-pixel coupled to the first sub-pixel, wherein the first sub-pixel is coupled The scan line and the data line, the second sub-pixel is coupled to the scan line; and each control transistor is coupled to the scan line, another data line, a pixel unit, and another pixel unit Between the second sub-pixels, the second sub-pixel of the other pixel unit is charged to the first sub-pixel of the other pixel unit.
  • each control transistor further includes a gate, a source, and a drain.
  • a gate is coupled to the scan line to connect the first sub-pixel of the pixel unit and the second sub-pixel; a source is coupled to the other data line; and a drain is coupled to the other a second sub-pixel of the pixel unit; wherein when the scan line applies a voltage to turn the gate of the control transistor on, transmitting a video signal to one pixel unit and a second sub-pixel to the other pixel unit Charging, when the gate of the control transistor is turned off and the other scan line applies the voltage, causing the second sub-pixel of the another pixel unit to charge the first sub-pixel of the other pixel unit .
  • the first sub-pixel further includes a switching transistor, a liquid crystal capacitor, and a storage capacitor.
  • a switching transistor coupled to the other scan line, the data line, and a gate of another control transistor; a liquid crystal capacitor coupled to the switching transistor; and a storage capacitor coupled to the switching transistor and in parallel with the liquid crystal capacitor .
  • the second sub-pixel further includes a switching transistor, a liquid crystal capacitor, and a storage capacitor.
  • a switching transistor coupled to the other scan line and a drain of the control transistor; a liquid crystal capacitor coupled to the switching transistor and a drain of the other control transistor; and a storage capacitor coupled to the switching transistor and the The other controls the drain of the transistor and the storage capacitor is in parallel with the liquid crystal capacitor.
  • the switching transistor of the first sub-pixel is connected to the switching transistor of the second sub-pixel.
  • the present patent application further provides a liquid crystal display panel, including a scan driving module and a data driving module, wherein the liquid crystal display panel further includes a thin film transistor matrix, and the scan driving module and the data driving module are used to drive the A thin film transistor matrix comprising a plurality of scan lines, a plurality of data lines, a plurality of pixel units, and a plurality of control transistors, the plurality of data lines being interleaved with the plurality of scan lines.
  • Each of the pixel units is coupled to a scan line and a data line, and each of the pixel units includes a first sub-pixel and a second sub-pixel coupled to the first sub-pixel, wherein the first sub-pixel is coupled The scan line and the data line, the second sub-pixel is coupled to the scan line; and each control transistor is coupled to the scan line, another data line, a pixel unit, and another pixel unit Between the second sub-pixels, the second sub-pixel of the other pixel unit is charged to the first sub-pixel of the other pixel unit.
  • each control transistor further includes a gate, a source, and a drain.
  • a gate is coupled to the scan line to connect the first sub-pixel of the pixel unit and the second sub-pixel; a source is coupled to the other data line; and a drain is coupled to the other a second sub-pixel of the pixel unit; wherein when the scan line applies a voltage to turn the gate of the control transistor on, transmitting a video signal to one pixel unit and a second sub-pixel to the other pixel unit Charging, when the gate of the control transistor is turned off and the other scan line applies the voltage, causing the second sub-pixel of the another pixel unit to charge the first sub-pixel of the other pixel unit .
  • the first sub-pixel further includes a switching transistor, a liquid crystal capacitor, and a storage capacitor.
  • a switching transistor coupled to the other scan line, the data line, and a gate of another control transistor; a liquid crystal capacitor coupled to the switching transistor; and a storage capacitor coupled to the switching transistor and in parallel with the liquid crystal capacitor .
  • the second sub-pixel further includes a switching transistor, a liquid crystal capacitor, and a storage capacitor.
  • a switching transistor coupled to the other scan line and a drain of the control transistor; a liquid crystal capacitor coupled to the switching transistor and a drain of the other control transistor; and a storage capacitor coupled to the switching transistor and the The other controls the drain of the transistor and the storage capacitor is in parallel with the liquid crystal capacitor.
  • the thin film transistor matrix and the liquid crystal display panel of the present application open a control transistor, and when a voltage is applied to the scan line to turn on the gate of the control transistor, a video signal is transmitted to one pixel unit and the other pixel is The second pixel of the cell is charged, and when the gate of the control transistor is turned off and the voltage is applied by the other scan line, the second pixel in the other pixel unit is charged to the other The first pixel of a pixel unit is charged, thereby achieving the purpose of fast charging.
  • FIG. 1 is a schematic structural view of a prior art thin film transistor matrix.
  • FIG. 2 is a schematic structural view of a thin film transistor matrix in accordance with an embodiment of the present patent application.
  • FIG. 3 is a schematic structural view of a liquid crystal display panel having a thin film transistor matrix according to an embodiment of the present patent application.
  • the thin film transistor matrix 200 includes a plurality of scan lines 202, a plurality of data lines 204, a plurality of pixel units 206, and a plurality of control transistors 208.
  • a plurality of scan lines 202 and a plurality of data lines 204 are arranged alternately with each other.
  • two scan lines SL(n-1), SLn 202 is interleaved with two data lines DL1, DL2 204, two pixel units P(n-1), Pn 206, and two control transistors CT(n-1), CTn 208 is taken as an example, but the number is not limited thereto.
  • a plurality of pixel units P(n-1) and Pn 206 are respectively disposed on the two scan lines SL(n-1), SLn 202 is adjacent to the interlaced position of the two data lines DL1, DL2 204.
  • One of the pixel units P(n-1) 206 is coupled to a scan line SL(n-1) 202 and a data line DL1.
  • pixel unit P (n-1) 206 includes a first sub-pixel 206a and a second sub-pixel 206b coupled to the first sub-pixel 206a, wherein the first sub-pixel 206a is coupled to the scan line SL(n-1) 202 and the data line DL1 204, the second sub-pixel 206b is coupled to the scan line SL(n-1) 202. Similarly, the other pixel unit Pn 206 is coupled to a scan line SLn.
  • pixel unit Pn 206 includes a first sub-pixel 206a and a second sub-pixel 206b coupled to the first sub-pixel 206a, wherein the first sub-pixel 206a is coupled to the scan line SLn 202 and the data line DL1 204.
  • the second sub-pixel 206b is coupled to the scan line SLn 202.
  • a plurality of control transistors CT(n-1), CTn 208 are disposed in the pixel unit P(n-1), Pn Between 206.
  • One of the control transistors CTn 208 is coupled to the scan line SL(n-1) 202 and another data line DL2. 204, between the pixel unit P(n-1) 206, and the second sub-pixel 206b of another pixel unit Pn 206, so that the other pixel unit Pn
  • the second sub-pixel 206b of 206 charges the first sub-pixel 206a of the other pixel unit Pn 206.
  • another control transistor CT(n-1) 208 is coupled to the scan line (not shown), another data line DL2 204, the pixel unit (not shown), and the pixel unit P(n-1) Between the second sub-pixels 206b of 206, such that the second sub-pixel 206b of the pixel unit P(n-1) 206 is paired with the other pixel unit P(n-1) The first pixel 206a of 206 is charged.
  • a voltage (eg, a positive voltage) is applied to the scan line SL(n-1).
  • 202 by turning on the switching transistors TFT_(n-1)a, TFT_(n-1)b of the pixel unit P(n-1) 206, even if the scan line SL(n-1)
  • the transistors on 202 are all turned on to charge the pixel unit P(n-1) 206.
  • the control transistor CTn 208 is simultaneously turned on by the positive voltage to turn another data line DL2.
  • the video signal of 204 is transmitted to the second sub-pixel 206b of the other pixel unit Pn to pre-charge the second sub-pixel 206b of the other pixel unit Pn 206.
  • Another voltage (eg, a negative voltage) is applied to the scan line SL(n-1) 202, to turn off the switching transistors TFT_(n-1)a, TFT_(n-1)b, and the control transistor CTn 208.
  • the positive voltage is applied to the other scan line SLn 202, by turning on the switching transistor TFT_na to use the data line DL1 204 to the other pixel unit Pn
  • the first pixel 206a of 206 is charged (i.e., the video signal is transmitted).
  • the switching transistor TFT_nb is turned on, and the other pixel unit Pn is turned on.
  • the second sub-pixel 206b of 206 charges the first sub-pixel 206a of the other pixel unit Pn 206.
  • the switching transistors TFT_na and TFT_nb are both turned on, except for the data line DL1
  • the second sub-pixel 206b of the other pixel unit Pn 206 may be further utilized to the pixel unit Pn.
  • the first pixel 206a of the 206 is charged to achieve the purpose of fast charging, effectively shortening the charging time of the pixel.
  • control transistor CTn 208 also includes a gate G, a source S, and a drain D.
  • the gate G is coupled to the scan line SL(n-1) 202 of the scan line to connect the pixel unit P(n-1) The first sub-pixel 206a of 206 and the second sub-pixel 206b.
  • the source S is coupled to the other data line DL2 204.
  • the drain D is coupled to the other pixel unit Pn The second subpixel 206b of 206. Wherein the other data line DL2 is applied when the scan line SL(n-1) 202 applies a voltage to turn on the gate G of the control transistor CTn 208.
  • the second sub-pixel 206b of 206 transmits a video signal); when the gate G of the control transistor CTn 208 is turned off and the other scan line SLn 202 applies the voltage, the other pixel unit Pn is caused The second sub-pixel 206b of 206 charges the first sub-pixel 206a of the other pixel unit Pn 206. It should be noted that the function of the control transistor CT(n-1) 208 and the control transistor CTn 208 is the same and will not be described here.
  • the first sub-pixel 206a of 206 further includes a switching transistor TFT_(n-1)a, a liquid crystal capacitor (liquid-crystal capacitor, CLC) CLC_(n-1)a and storage capacitor (storage capacitor, CS) CS_(n-1)a.
  • the switching transistor TFT_(n-1)a is coupled to the scan line SL(n-1) 202, the data line DL1 204, and another control transistor CTn.
  • the liquid crystal capacitor CLC_(n-1)a is coupled to the switching transistor TFT_(n-1)a.
  • the storage capacitor CS_(n-1)a is coupled to the switching transistor TFT_(n-1)a and is connected in parallel with the liquid crystal capacitor CLC_(n-1)a.
  • the second sub-pixel 206b of the pixel unit P(n-1) 206 further includes a switching transistor TFT_(n-1)b, a liquid crystal capacitor CLC_(n-1)b, and a storage capacitor CS_(n-1)b.
  • the switching transistor TFT_(n-1)b is coupled to the scan line SL(n-1) and the control transistor CTn Bungee D of 208.
  • the liquid crystal capacitor CLC_(n-1)b is coupled to the switching transistor TFT_(n-1)b and the other control transistor CT(n-1) Bungee D of 208.
  • the storage capacitor CS_(n-1)b is coupled to the switching transistor TFT_(n-1)b and the other control transistor CT(n-1) The drain D of 208, and the storage capacitor CS_(n-1)b is connected in parallel with the liquid crystal capacitor CLC_(n-1)b.
  • the switching transistor TFT_(n-1)a of the first sub-pixel 206a is electrically connected to the switching transistor TFT_(n-1)b of the second sub-pixel 206b; In another embodiment, the switching transistor TFT_(n-1)b may also be directly connected to the data line DL1.
  • the first sub-pixel 206a and the second sub-pixel 206b of 206 are similar.
  • the pixel unit Pn The first sub-pixel 206a of 206 further includes a switching transistor TFT_na, a liquid crystal capacitor CLC_na, and a storage capacitor CS_na.
  • the switching transistor TFT_na is coupled to the scan line SLn and the data line DL1 204 and a gate of another control transistor (not shown).
  • the liquid crystal capacitor CLC_na is coupled to the switching transistor TFT_na.
  • the storage capacitor CS_na is coupled to the switching transistor TFT_na and is connected in parallel with the liquid crystal capacitor CLC_na.
  • the pixel unit Pn The second sub-pixel 206b of 206 further includes a switching transistor TFT_nb, a liquid crystal capacitor CLC_nb, and a storage capacitor CS_nb.
  • the switching transistor TFT_nb is coupled to the scan line SLn 202 and the drain D of the control transistor CTn 208.
  • the liquid crystal capacitor CLC_nb is coupled to the switching transistor TFT_nb and the other control transistor CTn Bungee D of 208.
  • the storage capacitor CS_nb is coupled to the switching transistor TFT_nb and the other control transistor CTn The drain D of 208, and the storage capacitor CS_nb is connected in parallel with the liquid crystal capacitor CLC_nb.
  • the switching transistor TFT_na of the first sub-pixel 206a is electrically connected to the switching transistor TFT_nb of the second sub-pixel 206b; in another embodiment, the switching transistor TFT_nb may also be directly connected to the data line DL1.
  • FIG. 3 is a schematic structural diagram of a liquid crystal display panel 300 having a thin film transistor matrix 200 according to an embodiment of the present patent application.
  • the liquid crystal display panel 300 includes a scan driving module 302, a data driving module 304, and a thin film transistor matrix 200.
  • the scan driving module 302 and the data driving module 304 are used to drive the thin film transistor matrix 200, that is, the scan driving module 302 applies a voltage to the scan line 202 to control the control transistors CTn, CT(n-1) connected to the scan line 202. 208.
  • the switching transistors TFT_na, TFT_nb, TFT_(n-1)a, and TFT_(n-1)b are turned on or off.
  • the data driving module 304 transmits the video signal to the pixel units Pn, Pn(-1) 206. Further, the liquid crystal capacitors corresponding to the pixel units Pn and P(n-1) 206 are charged to drive liquid crystal molecules in the liquid crystal layer to display an image on the liquid crystal display.
  • the thin film transistor matrix 200 includes a plurality of scan lines 202, a plurality of data lines 204, a plurality of pixel units 206, and a plurality of control transistors 208.
  • a plurality of scan lines 202 and a plurality of data lines 204 are arranged alternately with each other.
  • Several pixel units P(n-1), Pn 206 are respectively disposed near the interlaced positions of the two scanning lines SL(n-1), SLn 202 and the two data lines DL1, DL2 204.
  • One of the pixel units P(n-1) 206 is coupled to a scan line SL(n-1) 202 and a data line DL1 204, and the pixel unit P(n-1) 206 includes a first sub-pixel 206a and a second sub-pixel 206b coupled to the first sub-pixel 206a, wherein the first sub-pixel 206a is coupled to the scan line SL(n-1) 202 and the data line DL1 204, the second sub-pixel 206b is coupled to the scan line SL(n-1) 202.
  • the other pixel unit Pn 206 is coupled to a scan line SLn.
  • pixel unit Pn 206 includes a first sub-pixel 206a and a second sub-pixel 206b coupled to the first sub-pixel 206a, wherein the first sub-pixel 206a is coupled to the scan line SLn 202 and the data line DL1 204.
  • the second sub-pixel 206b is coupled to the scan line SLn 202.
  • a plurality of control transistors CT(n-1), CTn 208 are disposed in the pixel unit P(n-1), Pn Between 206.
  • One of the control transistors CTn 208 is coupled to the scan line SL(n-1) 202 and another data line DL2. 204, between the pixel unit P(n-1) 206, and the second sub-pixel 206b of another pixel unit Pn 206, so that the other pixel unit Pn
  • the second sub-pixel 206b of 206 charges the first sub-pixel 206a of the other pixel unit Pn 206.
  • the technical solution adopted by the patent application is to turn on the control transistor, and when the scan line applies a voltage to turn on the gate of the control transistor, the video signal is transmitted to a pixel unit and The second sub-pixel of the other pixel unit is charged, and when the gate of the control transistor is turned off and the other scan line applies the voltage, the second pixel of the other pixel unit is charged The pixel charges the first pixel of the other pixel unit to achieve the purpose of fast charging.

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Abstract

一种薄膜晶体管矩阵（200）及液晶显示面板（300），所述薄膜晶体管矩阵（200）包括若干扫描线（202）、若干数据线（204）、若干像素单元（206）以及若干控制晶体管（208）。当一控制晶体管（CTn208）开启并且对一像素单元（P(n-1)206）传送视频信号时，同时对所述另一像素单元（Pn206）的第二次像素（206b）作充电；当所述控制晶体管（CTn208）关闭且所述另一像素单元（Pn206）的第二次像素（206b）之切换晶体管（TFT_nb）开启时，使所述另一像素单元（Pn206）的第二次像素（206b）对所述另一像素单元（Pn206）的第一次像素（206a）作快速充电，以缩短像素的充电时间。

Description

薄膜晶体管矩阵及液晶显示面板 技术领域
本专利申请涉及一种晶体管矩阵及其显示面板，且特别是涉及一种薄膜晶体管矩阵及液晶显示面板。
 背景技术
薄膜晶体管矩阵(Thin-Film Transistor Array, TFT Array)是液晶显示器(Liquid Crystal Display, LCD)不可或缺的重要显示组件，图1是现有技术的薄膜晶体管矩阵100的结构示意图。其中薄膜晶体管矩阵100主要是由若干个像素单元(pixel unit)102、若干条扫描线(scan line)104以及若干条数据线(data line)106所组成。
这些像素单元102电性连接这些扫描线104与数据线106，每一像素单元102具有一晶体管108、液晶电容(liquid-crystal capacitor, CLC)110以及储存电容(storage capacitor, CS)，其中每一晶体管108具有一闸极(gate)G、一源极(source)S以及一汲极(drain)D，而闸极G连接扫描线104，源极S连接数据线106，且汲极D共同连接液晶电容(CLC)110以及储存电容(CS)112，所述液晶电容(CLC)110以及储存电容(CS)112接地(如图1所示)或是共同连接至共享线(common line)(未图示)。
当第一扫描线(SL1)上施加足够大的正电压时，连接所述第一扫描线(SL1)上的薄膜晶体管108会被开启(switch on)，使这些液晶电容的像素电极与垂直方向的资料线106电性导通，而经由垂直数据线送入对应的视频信号，以将这些液晶电容充电至适当的电压水平；换言之，对这些像素单元所对应的液晶电容进行充电，以驱动液晶层内的液晶分子，使液晶显示器显示影像；同时，对连接所述数据线的这些储存电容112进行充电，所述储存电容112在于使液晶电容110两端的电压维持在一定值下，亦即在未进行数据更新之前，液晶电容110的两端电压藉由储存电容112维持住。接着，施加足够大的负电压，关闭(switch off)薄膜晶体管108，直到下次再重新写入视频信号，其间使得电荷保存在液晶电容110上，此时再启动次一条水平扫描线(SL2)104，而经由垂直数据线106送入其对应的视频信号。
然而，必须在目前扫描线(SL1)上的薄膜晶体管108关闭之后，才能对次扫描线(SL2)的像素单元(P2)的液晶电容110以及储存电容充电，耗费较长的充电时间。因此需要发展一种新式的薄膜晶体管矩阵，以解决上述充电时间过长的问题。
 技术问题
本专利申请提供一种薄膜晶体管矩阵及液晶显示面板，以解决像素充电时间过长的问题。
 技术解决方案
本专利申请的目的在于提供一种薄膜晶体管矩阵及液晶显示面板，以解决像素充电时间过长的问题，其对一像素单元传送视频信号并且对所述另一像素单元充电，当所述控制晶体管的闸极关闭且所述另一扫描线施加所述电压时，使所述另一像素单元中已充电的第二次像素对第一次像素作充电，进而达到快速充电的目的。
为达到上述发明目的，本专利申请提供一种薄膜晶体管矩阵及液晶显示面板，薄膜晶体管矩阵包括若干扫描线、若干数据线、若干像素单元以及若干控制晶体管，若干数据线与所述若干扫描线交错设置。每一像素单元分别耦接一扫描线以及一数据线，每一像素单元包括一第一次像素以及耦接所述第一次像素的一第二次像素，其中所述第一次像素耦接所述扫描线与所述数据线，所述第二次像素耦接所述扫描线；以及每一控制晶体管耦接于所述扫描线、另一数据线、一像素单元、以及另一像素单元的第二次像素之间，以使所述另一像素单元的第二次像素对所述另一像素单元的第一次像素作充电。
在一实施例中，每一控制晶体管还包括闸极、源极以及汲极。闸极耦接所述扫描线，以连接所述像素单元的第一次像素以及所述第二次像素；源极耦接所述另一资料线；以及一汲极，耦接所述另一像素单元的第二次像素；其中当所述扫描线施加一电压以使所述控制晶体管的闸极开启时，对一像素单元传送视频信号并且对所述另一像素单元的第二次像素作充电，当所述控制晶体管的闸极关闭且所述另一扫描线施加所述电压时，使所述另一像素单元的第二次像素对所述另一像素单元的第一次像素作充电。
在一实施例中，第一次像素还包括切换晶体管、液晶电容以及储存电容。切换晶体管耦接所述另一扫瞄线、所述数据线以及另一控制晶体管的闸极；液晶电容耦接所述切换晶体管；以及储存电容耦接所述切换晶体管并且与所述液晶电容并联。
在一实施例中，第二次像素还包括切换晶体管、液晶电容以及储存电容。切换晶体管耦接所述另一扫描线以及所述控制晶体管的汲极；液晶电容耦接所述切换晶体管以及所述另一控制晶体管的汲极；以及储存电容耦接所述切换晶体管以及所述另一控制晶体管的汲极，并且所述储存电容与所述液晶电容并联。
在一实施例中，第一次像素的切换晶体管连接第二次像素的切换晶体管。
本专利申请另提供一种液晶显示面板，包括扫描驱动模块以及数据驱动模块，其特征在于，所述液晶显示面板还设置一薄膜晶体管矩阵，所述扫描驱动模块以及数据驱动模块用以驱动所述薄膜晶体管矩阵，所述薄膜晶体管矩阵包括若干扫描线、若干数据线、若干像素单元以及若干控制晶体管，若干数据线与所述若干扫描线交错设置。每一像素单元分别耦接一扫描线以及一数据线，每一像素单元包括一第一次像素以及耦接所述第一次像素的一第二次像素，其中所述第一次像素耦接所述扫描线与所述数据线，所述第二次像素耦接所述扫描线；以及每一控制晶体管耦接于所述扫描线、另一数据线、一像素单元、以及另一像素单元的第二次像素之间，以使所述另一像素单元的第二次像素对所述另一像素单元的第一次像素作充电。
在一实施例中，每一控制晶体管还包括闸极、源极以及汲极。闸极耦接所述扫描线，以连接所述像素单元的第一次像素以及所述第二次像素；源极耦接所述另一资料线；以及一汲极，耦接所述另一像素单元的第二次像素；其中当所述扫描线施加一电压以使所述控制晶体管的闸极开启时，对一像素单元传送视频信号并且对所述另一像素单元的第二次像素作充电，当所述控制晶体管的闸极关闭且所述另一扫描线施加所述电压时，使所述另一像素单元的第二次像素对所述另一像素单元的第一次像素作充电。
在一实施例中，第一次像素还包括切换晶体管、液晶电容以及储存电容。切换晶体管耦接所述另一扫瞄线、所述数据线以及另一控制晶体管的闸极；液晶电容耦接所述切换晶体管；以及储存电容耦接所述切换晶体管并且与所述液晶电容并联。
在一实施例中，第二次像素还包括切换晶体管、液晶电容以及储存电容。切换晶体管耦接所述另一扫描线以及所述控制晶体管的汲极；液晶电容耦接所述切换晶体管以及所述另一控制晶体管的汲极；以及储存电容耦接所述切换晶体管以及所述另一控制晶体管的汲极，并且所述储存电容与所述液晶电容并联。
 有益效果
本专利申请之薄膜晶体管矩阵及液晶显示面板通过开启控制晶体管，当所述扫描线施加一电压以使所述控制晶体管的闸极开启时，对一像素单元传送视频信号并且对所述另一像素单元的第二次像素作充电，当所述控制晶体管的闸极关闭且所述另一扫描线施加所述电压时，使所述另一像素单元中已充电的第二次像素对所述另一像素单元的第一次像素作充电，进而达到快速充电的目的。
附图说明
图1为现有技术的薄膜晶体管矩阵的结构示意图。
图2为根据本专利申请实施例中薄膜晶体管矩阵的结构示意图。
图3为根据本专利申请实施例中具有薄膜晶体管矩阵的液晶显示面板的结构示意图。
 本发明的最佳实施方式
本专利申请提供不同的实施例来说明本专利申请不同实施方式的技术特征。实施例中的各组件的配置是为了清楚说明本专利申请揭示的内容，并非用以限制本专利申请。在不同的图式中，相同的组件符号表示相同或相似的组件。
参考图2，其为根据本专利申请实施例中薄膜晶体管矩阵200的结构示意图。所述薄膜晶体管矩阵200包括若干扫描线202、若干数据线204、若干像素单元206以及若干控制晶体管208。若干扫描线202与若干数据线204互相交错排列设置。此处是以两条扫描线SL(n-1)、SLn 202与两条资料线DL1、DL2 204交错排列设置，两个像素单元P(n-1)、Pn 206，以及两个控制晶体管CT(n-1)、CTn 208为例作说明，但是其数量不限于此。
若干像素单元P(n-1)、Pn 206分别设置于两条扫描线SL(n-1)、SLn 202与两条资料线DL1、DL2 204的交错位置附近。其中一像素单元P(n-1) 206耦接一扫描线SL(n-1) 202以及一数据线DL1 204，像素单元P(n-1) 206包括第一次像素206a以及耦接所述第一次像素206a的第二次像素206b，其中所述第一次像素206a耦接所述扫描线SL(n-1) 202与所述资料线DL1 204，所述第二次像素206b耦接所述扫描线SL(n-1) 202。类似地，另一像素单元Pn 206耦接一扫描线SLn 202以及一数据线DL1 204，像素单元Pn 206包括第一次像素206a以及耦接所述第一次像素206a的第二次像素206b，其中所述第一次像素206a耦接所述扫描线SLn 202与所述资料线DL1 204，所述第二次像素206b耦接所述扫描线SLn 202。
若干控制晶体管CT(n-1)、CTn 208设置于像素单元P(n-1)、Pn 206之间。其中一控制晶体管CTn 208耦接于所述扫描线SL(n-1) 202、另一数据线DL2 204、所述像素单元P(n-1)206、以及另一像素单元Pn 206的第二次像素206b之间，以使所述另一像素单元Pn 206的第二次像素206b对所述另一像素单元Pn 206的第一次像素206a作充电。类似地，另一控制晶体管CT(n-1) 208耦接于扫描线(未图标)、另一数据线DL2 204、所述像素单元(未图标)、以及像素单元P(n-1) 206的第二次像素206b之间，以使所述像素单元P(n-1) 206的第二次像素206b对所述另一像素单元P(n-1) 206的第一次像素206a作充电。
具体来说，本专利申请之薄膜晶体管矩阵200运作时，施加一电压(例如正电压)至所述扫描线SL(n-1) 202，藉由开启像素单元P(n-1) 206的切换晶体管TFT_(n-1)a、TFT_(n-1)b，亦即使扫描线SL(n-1) 202上的晶体管全部开启，以对所述像素单元P(n-1) 206进行充电。此时，同时利用所述正电压开启所述控制晶体管CTn 208，以将另一数据线DL2 204的视频讯号传送至所述另一像素单元Pn的第二次像素206b，以对所述另一像素单元Pn 206的第二次像素206b预先进行充电。
接着，施加另一电压(例如负电压)至所述扫描线SL(n-1) 202，以关闭所述切换晶体管TFT_(n-1)a、TFT_(n-1)b以及所述控制晶体管CTn 208。然后，施加所述正电压至所述另一扫描线SLn 202，藉由开启所述切换晶体管TFT_na，以利用数据线DL1 204对所述另一像素单元Pn 206的第一次像素206a进行充电(亦即传送视频讯号)。同时，利用开启所述切换晶体管TFT_nb，并且使所述另一像素单元Pn 206的第二次像素206b对所述另一像素单元Pn 206的第一次像素206a进行充电。换言之，当切换晶体管TFT_na、TFT_nb均开启时，除了数据线DL1 204对第一次像素206a充电之外，可以进一步利用另一像素单元Pn 206中已预先充电的第二次像素206b对像素单元Pn 206的第一次像素206a进行充电，以达到快速充电的目的，有效缩短像素的充电时间。
进一步地，控制晶体管CTn 208还包括闸极G、源极S以及汲极D。闸极G耦接所述扫描线所述扫描线SL(n-1) 202，以连接所述像素单元P(n-1) 206的第一次像素206a以及所述第二次像素206b。源极S耦接所述另一资料线DL2 204。汲极D耦接所述另一像素单元Pn 206的第二次像素206b。其中当所述扫描线SL(n-1) 202施加一电压以使所述控制晶体管CTn 208的闸极G开启时，所述另一数据线DL2 204对所述另一像素单元Pn 206的第二次像素206b作预先充电(亦即所述另一数据线DL2 204对所述另一像素单元Pn 206的第二次像素206b传送视频信号)；当所述控制晶体管CTn 208的闸极G关闭且所述另一扫描线SLn 202施加所述电压时，使所述另一像素单元Pn 206的第二次像素206b对所述另一像素单元Pn 206的第一次像素206a作充电。应注意的是，控制晶体管CT(n-1) 208的作用与控制晶体管CTn 208相同，在此不予赘述。
所述像素单元P(n-1) 206的第一次像素206a还包括切换晶体管TFT_(n-1)a、液晶电容(liquid-crystal capacitor, CLC)CLC_(n-1)a以及储存电容(storage capacitor, CS)CS_(n-1)a。所述切换晶体管TFT_(n-1)a耦接所述扫瞄线SL(n-1) 202、所述数据线DL1 204以及另一控制晶体管CTn 208的闸极。所述液晶电容CLC_(n-1)a耦接所述切换晶体管TFT_(n-1)a。储存电容CS_(n-1)a耦接所述切换晶体管TFT_(n-1)a并且与所述液晶电容CLC_(n-1)a并联。所述像素单元P(n-1)206的第二次像素206b还包括切换晶体管TFT_(n-1)b、液晶电容CLC_(n-1)b以及储存电容CS_(n-1)b。切换晶体管TFT_(n-1)b耦接所述扫描线SL(n-1)以及所述控制晶体管CTn 208的汲极D。液晶电容CLC_(n-1)b耦接所述切换晶体管TFT_(n-1)b以及所述另一控制晶体管CT(n-1) 208的汲极D。储存电容CS_(n-1)b耦接所述切换晶体管TFT_(n-1)b以及所述另一控制晶体管CT(n-1) 208的汲极D，并且所述储存电容CS_(n-1)b与所述液晶电容CLC_(n-1)b并联。
在像素单元P(n-1)206中，所述第一次像素206a的切换晶体管TFT_(n-1)a电性连接所述第二次像素206b的切换晶体管TFT_(n-1)b；另一实施例中，切换晶体管TFT_(n-1)b亦可直接连接至数据线DL1。
同样地，所述像素单元Pn 206的第一次像素206a以及第二次像素206b分别与所述像素单元P(n-1) 206的第一次像素206a以及第二次像素206b类似。具体而言，所述像素单元Pn 206的第一次像素206a还包括切换晶体管TFT_na、液晶电容CLC_na以及储存电容CS_na。所述切换晶体管TFT_na耦接所述扫瞄线SLn、所述数据线DL1 204以及另一控制晶体管(未图示)的闸极。所述液晶电容CLC_na耦接所述切换晶体管TFT_na。储存电容CS_na耦接所述切换晶体管TFT_na并且与所述液晶电容CLC_na并联。所述像素单元Pn 206的第二次像素206b还包括切换晶体管TFT_nb、液晶电容CLC_nb以及储存电容CS_nb。切换晶体管TFT_nb耦接所述扫描线SLn 202以及所述控制晶体管CTn 208的汲极D。液晶电容CLC_nb耦接所述切换晶体管TFT_nb以及所述另一控制晶体管CTn 208的汲极D。储存电容CS_nb耦接所述切换晶体管TFT_nb以及所述另一控制晶体管CTn 208的汲极D，并且所述储存电容CS_nb与所述液晶电容CLC_nb并联。
在像素单元Pn 206中，所述第一次像素206a的切换晶体管TFT_na电性连接所述第二次像素206b的切换晶体管TFT_nb；另一实施例中，切换晶体管TFT_nb亦可直接连接至数据线DL1。
参考图2以及图3，图3为根据本专利申请实施例中具有薄膜晶体管矩阵200的液晶显示面板300的结构示意图。液晶显示面板300包括扫描驱动模块302、数据驱动模块304以及薄膜晶体管矩阵200。扫描驱动模块302以及数据驱动模块304用以驱动薄膜晶体管矩阵200，亦即扫描驱动模块302施加电压至扫描线202上，以控制连接于扫描线202的控制晶体管CTn、CT(n-1) 208、切换晶体管TFT_na、TFT_nb、TFT_(n-1)a、TFT_(n-1)b之开启或是关闭状态。数据驱动模块304传送视频信号至像素单元Pn、Pn(-1) 206，进而对这些像素单元Pn、P(n-1) 206所对应的液晶电容进行充电，以驱动液晶层内的液晶分子，使液晶显示器显示影像。
所述薄膜晶体管矩阵200包括若干扫描线202、若干数据线204、若干像素单元206以及若干控制晶体管208。若干扫描线202与若干数据线204互相交错排列设置。若干像素单元P(n-1)、Pn 206分别设置于两条扫描线SL(n-1)、SLn 202与两条资料线DL1、DL2 204的交错位置附近。其中一像素单元P(n-1) 206耦接一扫描线SL(n-1) 202以及一数据线DL1 204，像素单元P(n-1) 206包括第一次像素206a以及耦接所述第一次像素206a的第二次像素206b，其中所述第一次像素206a耦接所述扫描线SL(n-1) 202与所述资料线DL1 204，所述第二次像素206b耦接所述扫描线SL(n-1) 202。类似地，另一像素单元Pn 206耦接一扫描线SLn 202以及一数据线DL1 204，像素单元Pn 206包括第一次像素206a以及耦接所述第一次像素206a的第二次像素206b，其中所述第一次像素206a耦接所述扫描线SLn 202与所述资料线DL1 204，所述第二次像素206b耦接所述扫描线SLn 202。
若干控制晶体管CT(n-1)、CTn 208设置于像素单元P(n-1)、Pn 206之间。其中一控制晶体管CTn 208耦接于所述扫描线SL(n-1) 202、另一数据线DL2 204、所述像素单元P(n-1)206、以及另一像素单元Pn 206的第二次像素206b之间，以使所述另一像素单元Pn 206的第二次像素206b对所述另一像素单元Pn 206的第一次像素206a作充电。
为达到缩短像素的充电时间，本专利申请采取的技术方案是通过开启控制晶体管，当所述扫描线施加一电压以使所述控制晶体管的闸极开启时，对一像素单元传送视频信号并且对所述另一像素单元的第二次像素作充电，当所述控制晶体管的闸极关闭且所述另一扫描线施加所述电压时，使所述另一像素单元中已充电的第二次像素对所述另一像素单元的第一次像素作充电，进而达到快速充电的目的。
虽然本专利申请已用较佳实施例揭露如上，然其并非用以限定本专利申请，本专利申请所属技术领域中具有通常知识者，在不脱离本专利申请的精神和范围内，当可作各种的更动与润饰，因此本专利申请的保护范围当视后附的权利要求范围所界定者为准。
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Claims (10)

  1. 一种薄膜晶体管矩阵，其特征在于，所述薄膜晶体管矩阵包括：
    若干扫描线；
    若干数据线，以与所述若干扫描线交错设置；
    若干像素单元，每一像素单元分别耦接一扫描线以及一数据线，每一像素单元包括一第一次像素以及耦接所述第一次像素的一第二次像素，其中所述第一次像素耦接所述扫描线与所述数据线，所述第二次像素耦接所述扫描线；以及
    若干控制晶体管，每一控制晶体管耦接于所述扫描线、另一数据线、一像素单元、以及另一像素单元的第二次像素之间，以使所述另一像素单元的第二次像素对所述另一像素单元的第一次像素作充电。
  2. 根据权利要求1所述的薄膜晶体管矩阵，其特征在于，每一控制晶体管还包括：
    一闸极，耦接所述扫描线，以连接所述像素单元的第一次像素以及所述第二次像素；
    一源极，耦接所述另一资料线；以及
    一汲极，耦接所述另一像素单元的第二次像素；
    其中当所述扫描线施加一电压以使所述控制晶体管的闸极开启时，对一像素单元传送视频信号并且对所述另一像素单元的第二次像素作充电，当所述控制晶体管的闸极关闭且所述另一扫描线施加所述电压时，使所述另一像素单元的第二次像素对所述另一像素单元的第一次像素作充电。
  3. 根据权利要求2所述的薄膜晶体管矩阵，其特征在于，所述第一次像素还包括：
    一切换晶体管，耦接所述另一扫瞄线、所述数据线以及另一控制晶体管的闸极；
    一液晶电容，耦接所述切换晶体管；以及
    一储存电容，耦接所述切换晶体管并且与所述液晶电容并联。
  4. 根据权利要求3所述的薄膜晶体管矩阵，其特征在于，所述第二次像素还包括：
    一切换晶体管，耦接所述另一扫描线以及所述控制晶体管的汲极；
    一液晶电容，耦接所述切换晶体管以及所述另一控制晶体管的汲极；以及
    一储存电容，耦接所述切换晶体管以及所述另一控制晶体管的汲极，并且所述储存电容与所述液晶电容并联。
  5. 根据权利要求4所述的薄膜晶体管矩阵，其特征在于，所述第一次像素的切换晶体管连接所述第二次像素的切换晶体管。
  6. 一种液晶显示面板，包括扫描驱动模块以及数据驱动模块，其特征在于，所述液晶显示面板还设置一薄膜晶体管矩阵，所述扫描驱动模块以及数据驱动模块用以驱动所述薄膜晶体管矩阵，所述薄膜晶体管矩阵包括：
    若干扫描线；
    若干数据线，以与所述若干扫描线交错设置；
    若干像素单元，每一像素单元分别耦接一扫描线以及一数据线，每一像素单元包括一第一次像素以及耦接所述第一次像素的一第二次像素，并且所述第一次像素分别耦接所述扫描线与所述数据线，所述第二次像素耦接所述扫描线；以及
    若干控制晶体管，每一控制晶体管耦接于所述扫描线、另一数据线、一像素单元、以及另一像素单元的第二次像素之间，以使所述另一像素单元的第二次像素对所述另一像素单元的第一次像素作充电。
  7. 根据权利要求1所述的液晶显示面板，其特征在于，每一控制晶体管还包括：
    一闸极，耦接所述扫描线，以连接所述像素单元的第一次像素以及所述第二次像素；
    一源极，耦接所述另一资料线；以及
    一汲极，耦接所述另一像素单元的第二次像素；
    其中当所述控制晶体管的闸极开启时，对所述另一像素单元的第二次像素作充电，当所述控制晶体管的闸极关闭且所述另一像素单元的第二次像素之切换晶体管开启时，使所述另一像素单元的第二次像素对所述另一像素单元的第一次像素作充电。
  8. 根据权利要求7所述的液晶显示面板，其特征在于，所述另一像素单元的第一次像素还包括：
    一切换晶体管，耦接所述另一扫瞄线、所述数据线以及另一控制晶体管的闸极；
    一液晶电容，耦接所述切换晶体管；以及
    一储存电容，耦接所述切换晶体管并且与所述液晶电容并联。
  9. 根据权利要求8所述的液晶显示面板，其特征在于，所述另一像素单元的第二次像素还包括：
    一切换晶体管，耦接所述另一扫描线以及所述控制晶体管的汲极；
    一液晶电容，耦接所述切换晶体管以及所述另一控制晶体管的汲极；以及
    一储存电容，耦接所述切换晶体管以及所述另一控制晶体管的汲极，并且所述储存电容与所述液晶电容并联。
  10. 根据权利要求9所述的液晶显示面板，其特征在于，所述第一次像素的切换晶体管连接所述第二次像素的切换晶体管。
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