WO2018233040A1 - 显示面板的驱动方法及显示面板 - Google Patents

显示面板的驱动方法及显示面板 Download PDF

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Publication number
WO2018233040A1
WO2018233040A1 PCT/CN2017/099968 CN2017099968W WO2018233040A1 WO 2018233040 A1 WO2018233040 A1 WO 2018233040A1 CN 2017099968 W CN2017099968 W CN 2017099968W WO 2018233040 A1 WO2018233040 A1 WO 2018233040A1
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Prior art keywords
sub
pixel
pixels
charging
time period
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PCT/CN2017/099968
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English (en)
French (fr)
Inventor
胡水秀
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惠科股份有限公司
重庆惠科金渝光电科技有限公司
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Priority to US16/624,031 priority Critical patent/US11348546B2/en
Publication of WO2018233040A1 publication Critical patent/WO2018233040A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/067—Special waveforms for scanning, where no circuit details of the gate driver are given

Definitions

  • the present application relates to the field of display technologies, and in particular, to a driving method of a display panel and a display panel.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display is one of the main types of flat panel display, and has become an important display platform in modern IT and video products.
  • the main driving principle of the thin film transistor liquid crystal display is that the system motherboard connects the red/green/blue compression signal, the control signal and the power through the wire to the connector on the printed circuit board (PCB), and the data passes through the printed circuit board.
  • the TCON Timing Controller chip After the TCON Timing Controller chip is processed, the S-COF Source-Chip on Film and the G-COF Gate-Chip on Film are displayed on the printed circuit board. The zones are connected so that the display obtains the required power, signal.
  • each data line (data) is connected to two sub-pixels, so the data line is doubled compared to the general pixel structure.
  • the plurality of data lines charge the left sub-pixel of the two connected sub-pixels, and turn on the second-row gate scan.
  • a plurality of data lines charge the right sub-pixel of the two connected sub-pixels, so that the gate scan line trace is turned on line by line to perform complete display of the picture.
  • a driving method of a display panel comprising:
  • the first preset time period charging the target sub-pixel for the first time
  • the second preset time period is to charge the target sub-pixel a second time, and simultaneously charge the next sub-pixel that is electrically connected to the same data line as the target sub-image and has the same polarity.
  • a display panel comprising:
  • each set of sub-pixel column groups including adjacent two columns of sub-pixels
  • a driving circuit comprising a data line, the data line is disposed between the adjacent two columns of sub-pixels, and the adjacent two columns of sub-pixels are electrically connected to the data line;
  • control module configured to set a polarity of a sub-pixel adjacent to a row of the plurality of sub-pixels arranged in a matrix to be opposite;
  • the charging module is configured to charge the target sub-pixel for the first time in the first preset time period; charge the target sub-pixel for the second time in the second preset time period, and simultaneously use the same data line electrical property as the target sub-image The next sub-pixel connected and of the same polarity is charged for the first time.
  • a driving method of a display panel comprising:
  • the second preset time period is to charge the target sub-pixel a second time, and simultaneously charge the next sub-pixel that is electrically connected to the same data line as the target sub-image and has the same polarity.
  • the gate scanning line is doubled, and the charging time of each sub-pixel is doubled, so the target sub-pixel is in the first preset.
  • the time period is first charged for pre-charging of the target sub-pixel, and then the second charging is performed with the actual voltage for the second predetermined time period, wherein the first charging and the second charging have the same polarity So, before the actual voltage is charged for the second time, a pre-charging has been performed.
  • the second charging is no longer starting from zero. It takes less time to reach the preset target value, and the target sub-pixel is performed. After two charging, the charging time is increased, the charging efficiency is improved, the optical performance of the picture is improved, and the process demand is unchanged, and the product cost is not improved.
  • FIG. 1 is a flow chart showing a driving method of a display panel in an embodiment
  • FIG. 2 is a schematic diagram showing a polarity distribution of a sub-pixel in an embodiment
  • FIG. 3 is a schematic diagram showing a polarity distribution of a sub-pixel in another embodiment
  • FIG. 4 is a schematic structural diagram of a sub-pixel of a display panel in an embodiment
  • FIG. 5 is a timing chart of driving signals of a gate scan line in an embodiment
  • Figure 6 is a block diagram of a display panel in an embodiment
  • FIG. 7 is a flow chart of a driving method of a display panel in another embodiment.
  • FIG. 1 is a flow chart of a driving method of a display panel, wherein the display panel includes a plurality of sub-pixels arranged in a matrix; the display panel includes a plurality of vertically arranged data lines, and a plurality of horizontally arranged grids A pole scan line; the method includes steps S110-S140. among them:
  • Step S110 dividing a plurality of sub-pixels arranged in a matrix into a plurality of sets of sub-pixel columns, wherein each set of sub-pixel columns includes two adjacent columns of sub-pixels, and one data is set between the adjacent two columns of sub-pixels a line, the adjacent two columns of sub-pixels are electrically connected to the data line.
  • Step S120 The polarity of the sub-pixels adjacent to the row is set to be opposite.
  • Step S130 The first preset time period is to charge the target sub-pixel for the first time.
  • Step S140 The second preset time period is to charge the target sub-pixel a second time, and simultaneously charge the next sub-pixel that is electrically connected to the same data line as the target sub-image and has the same polarity.
  • the gate scan line is doubled, and the single-charge time of the gate scan line of each sub-pixel is doubled. Therefore, the target sub-pixel is first performed in the first preset time period. Recharging the target sub-pixels with one charge, and then performing a second charging with the actual voltage for a second predetermined period of time, wherein the first charge and the second charge have the same polarity, thus the actual voltage
  • a pre-charging has been performed before the second charging, the second charging is no longer starting from zero, only less time is required to reach the preset target value, and the target sub-pixel is charged twice. Increased charging time, improved charging efficiency, improved optical performance of the picture, and The demand for the process is unchanged and the product cost is not improved.
  • the method can be applied to a display panel of a dual-gate sub-pixel architecture.
  • the method further includes: setting a gate scan line on each of the upper and lower sides of each row of sub-pixels, wherein one of the sub-pixels of the sub-pixel column group is electrically connected to the gate scan line on the upper side of the column of sub-pixels, and the sub-pixel column Another column of sub-pixels of the group is electrically connected to the gate scan lines on the lower side of the column of sub-pixels.
  • the method further includes: the sub-pixel structure can have two data inversion modes, namely, 1+2n rows and 2n rows, and n is a natural number.
  • the data inversion mode of 1+2n rows indicates that the polarity of the data on a certain data line is "+--++--" or "-++--++", so the sub-picture shown in Figure 2 can be obtained.
  • the two sub-pixels 210 of the same row of adjacent two columns of sub-pixels in each group of sub-pixel column groups are opposite in polarity.
  • the data inversion mode of 2n rows indicates that the polarity of the data on a certain data line is "--++--" or "++--++", so the data polarity of the sub-pixel 210 shown in FIG. 3 can be obtained.
  • the two sub-pixels 210 of the same row of adjacent two columns of sub-pixels in each group of sub-pixel column groups are opposite in polarity.
  • the data polarities of the lateral and vertical sub-pixels 210 may be uniformly displayed to reduce flicker.
  • each of the data lines 220 is connected to the two sub-pixels 210 on the trace, so that the data line 220 is reduced by half compared with the general sub-pixel structure.
  • the data lines D1, D2, ..., DN, DN+1 charge the left sub-pixels of the two connected sub-pixels
  • the second-row gate scan line G2 is turned on
  • the data lines D1, D2, ..., DN, DN+1 charge the right sub-pixel of the two connected sub-pixels, so that the gate scan line trace is turned on line by line to perform complete display of the picture.
  • the polarity control signal (POL Polarity) is detected internally by the TCON Timing Controller of the display panel.
  • POL Polarity For the sub-pixels on the same data line, the data polarity on the M-th gate scan line
  • the sub-pixels on the two gate scan lines are double-scanned and charged, wherein the sub-pixels on the M-th gate scan line are charged for the second time, that is, when actually charging, and also on the M+1th gate scan line.
  • the sub-pixel is charged for the first time, that is, pre-charged.
  • the next sub-pixel of the same polarity on the same data line is scanned and charged.
  • the polarity of the sub-pixel data on the M-th and M+3 gate scan lines is the same, and the M-th and M+3 gate scan lines can be used.
  • the sub-pixel performs double scan charging, that is, when the sub-pixel on the Mth gate scan line is charged for the second time, that is, when the actual charge is performed, the sub-pixel on the M+3 gate scan line is also charged for the first time. Precharged.
  • FIG. 5 shows the drive signal of the gate scan line during dual scan charging.
  • the gate scan line signal turns on each row of sub-pixels row by row, and the gate scan line signal of each row is divided into two preset time segments, and the first preset time period is performed for the first time with other sub-pixel voltages of the same polarity.
  • Charging, that is, the pre-charging section, the second predetermined period of time is the second charging with the voltage actually set, that is, therefore, only two rows of thin film transistors (TFTs) are simultaneously turned on at the same time.
  • the charging time of the first preset time period may be equal to the charging time of the second preset time period, which is convenient for operation.
  • the first preset time period and the second preset time period are adjacently set or spaced apart by two charging time settings.
  • the data inversion mode is exemplified as 1+2n rows, wherein the polarity of the gate scan line G1 row data is the same as the polarity of the G4 row data, so the thin film transistor is charged with the actual voltage on the gate scan line G1 row.
  • the sub-pixels of the gate scanning line G4 are precharged, as shown by pulses P1 and P5 in FIG.
  • the gate scan line G2 row data polarity is the same as the gate scan line G3 row data polarity, so the gate scan line G3 row sub-pixel is precharged while the gate scan line G2 row charges the sub-pixel with the actual voltage. , as shown by pulses P2 and P3 in Figure 5.
  • the polarity of the row of the gate scan line G3 is the same as the polarity of the row of the gate scan line G6. Therefore, the sub-pixels of the gate scan line G6 are precharged while the sub-pixel is charged with the actual voltage on the gate scan line G3. , as shown by pulses P4 and P8 in Figure 5.
  • the polarity of the row of the gate scan line G4 is the same as the polarity of the row of the gate scan line G5. Therefore, the sub-pixels of the gate scan line G5 are precharged while the sub-pixel is charged with the actual voltage on the gate scan line G4. , as shown by pulses P6 and P7 in Figure 5.
  • each subsequent line will The other line of the same data polarity is precharged with the actual voltage. Similarly, when the data inversion mode is 2n lines, the sub-pixels are charged in a similar manner.
  • FIG. 6 is a block diagram of a display panel including a plurality of sub-pixels 210, a driving circuit 230, a charging module 240, and a control module 250 arranged in a matrix.
  • the drive circuit 230 includes a data line 220.
  • the plurality of sub-pixels 210 are divided into a plurality of sets of sub-pixel column groups, and each set of sub-pixel column groups includes two adjacent columns of sub-pixels.
  • the data line 220 is disposed between the adjacent two columns of sub-pixels, and the adjacent two columns of sub-pixels are electrically connected to the data line 220.
  • the control module 250 is configured to set the polarity of the sub-pixels adjacent to the rows of the plurality of sub-pixels arranged in a matrix to be opposite.
  • the charging module 240 is configured to charge the target sub-pixel for the first time in the first preset time period; charge the target sub-pixel for the second time in the second preset time period, and simultaneously elect the same data line 220 as the target sub-image. The next sub-pixel connected and of the same polarity is charged for the first time.
  • the driving circuit may further include a plurality of vertically disposed data lines 220 and a plurality of horizontally disposed gate scanning lines 230.
  • a gate scan line is disposed on each of the upper and lower sides of each row of sub-pixels.
  • One column of sub-pixels of the sub-pixel column group is electrically connected to the gate scan line on the upper side of the column of sub-pixels, and the other column of the sub-pixel column group is electrically connected.
  • the gate is connected to the gate scan line on the lower side of the column of sub-pixels. Due to the dual-gate sub-pixel architecture, the gate scan line is doubled, and the single-charge time of the gate scan line of each sub-pixel is doubled. Therefore, the target sub-pixel is first performed in the first preset time period.
  • the sub-pixel structure has two data inversion modes, which are 1+2n rows and 2n rows respectively. Way, n is a natural number.
  • the data inversion mode of 1+2n rows indicates that the polarity of the data on a certain data line is "+--++--" or "-++--++", so the sub-picture shown in Figure 2 can be obtained.
  • Display of pixel data polarity The two sub-pixels of the same row of adjacent two columns of sub-pixels in each group of sub-pixel column groups are set to have opposite polarities.
  • the data inversion mode of 2n rows indicates that the polarity of the data on a certain data line is "--++--" or "++--++", so the polarity of the sub-pixel data shown in FIG. 3 can be obtained.
  • display The two sub-pixels of the same row of adjacent two columns of sub-pixels in each group of sub-pixel column groups are set to have opposite polarities.
  • the data polarities of the horizontal and vertical sub-pixels can be uniformly displayed to reduce flicker.
  • the charging module is further configured to charge the target sub-pixel for the first time while charging the last sub-pixel of the same polarity that is electrically connected to the same data line of the target sub-pixel.
  • the polarity control signal (POL Polarity) is detected internally by the TCON Timing Controller of the display panel.
  • the charging module is used for the Mth gate scan line.
  • the polarity of the data on the same polarity as the data on the M+1 gate scan line is the same, then the sub-pixels on the two gate scan lines are double-scanned and charged, wherein the Mth gate scan line
  • the sub-pixel on the M+1th gate scan line is also charged for the first time, that is, pre-charged.
  • the next sub-pixel of the same polarity on the same data line is scanned and charged.
  • the polarity of the sub-pixel data on the M-th and M+3 gate scan lines is the same, and the M-th and M+3 gate scan lines can be used.
  • the sub-pixel performs double scan charging, that is, when the sub-pixel on the Mth gate scan line is charged for the second time, that is, when the actual charge is performed, the sub-pixel on the M+3 gate scan line is also charged for the first time. Precharged.
  • the display panel further includes a timer, wherein the timer is configured to calculate a charging time of the first time period and a charging time of the second time period; wherein the charging time of the first time period is equal to the charging time of the second time period, the first time period and the Two time periods are set adjacent or two charging time intervals are set.
  • the driving signal of the gate scan line during dual scan charging.
  • the gate scan line signal turns on each row of sub-pixels row by row, and the gate scan line signal of each row is divided into two preset time segments, and the first preset time period is performed for the first time with other sub-pixel voltages of the same polarity.
  • the segment is charged a second time at the voltage actually set, that is, therefore, only two rows of thin film transistors (TFTs) are simultaneously turned on at the same time.
  • the charging time of the first preset time period may be equal to the charging time of the second preset time period, which is convenient for operation.
  • the first preset time period and the second preset time period are adjacently set or spaced apart by two charging time settings.
  • the following is an example of a data inversion manner of 1+2n rows, wherein the polarity of the gate scan line G1 row data is the same as the polarity of the G4 row data, so the thin film transistor is charged with the actual voltage on the gate scan line G1 row.
  • the sub-pixels of the gate scanning line G4 are precharged, as shown by pulses P1 and P5 in FIG.
  • the gate scan line G2 row data polarity is the same as the gate scan line G3 row data polarity, so the gate scan line G3 row sub-pixel is precharged while the gate scan line G2 row charges the sub-pixel with the actual voltage. , as shown by pulses P2 and P3 in Figure 5.
  • the polarity of the row of the gate scan line G3 is the same as the polarity of the row of the gate scan line G6. Therefore, the sub-pixels of the gate scan line G6 are precharged while the sub-pixel is charged with the actual voltage on the gate scan line G3. , as shown by pulses P4 and P8 in Figure 5.
  • the polarity of the row of the gate scan line G4 is the same as the polarity of the row of the gate scan line G5. Therefore, the sub-pixels of the gate scan line G5 are precharged while the sub-pixel is charged with the actual voltage on the gate scan line G4. , as shown by pulses P6 and P7 in Figure 5.
  • each subsequent row will be precharged with another line of the same data polarity with the actual voltage.
  • the data inversion mode is 2n lines, the sub-pixels are charged in a similar manner.
  • Each gate scan line of the display panel is turned on twice, each sub-pixel is first charged for the first time with other pixel voltages of the same polarity, and the second time is charged with the actual pixel voltage; the internal counter of the clock controller The sex inversion signal is detected.
  • the two rows of sub-pixels are double-scanned and charged.
  • the charging time of each sub-pixel is increased, thereby improving the charging efficiency and improving the optical performance of the picture.
  • the display panel may be a TN (Twisted Nematic), an OCB (Optically Compensated Birefringence), or a VA (Vertical Alignment) type liquid crystal display panel, but is not limited thereto.
  • the display panel can be RGB three primary colors Panel, RGBW four-color panel or RGBY four-color panel, but not limited to this. This driving method is also applicable to the case when the display panel is a curved panel.
  • the display panel can also be, for example, an OLED display panel, a QLED display panel, a curved display panel, or other display panel. It is not limited to this.
  • FIG. 7 is a flow chart of a driving method of a display panel according to another embodiment, the method comprising the following steps:
  • Step S210 dividing a plurality of sub-pixels arranged in a matrix into a plurality of sets of sub-pixel column groups, wherein each group of sub-pixel column groups includes two adjacent columns of sub-pixels, and data lines are disposed between the adjacent two columns of sub-pixels The adjacent two columns of sub-pixels are electrically connected to the data line.
  • Step S220 The polarity of the sub-pixels adjacent to the row is set to be opposite.
  • step S230 the target sub-pixel is charged for the first time, and the previous sub-pixel electrically connected to the same data line of the target sub-pixel is charged for the second time.
  • Step S240 The second preset time period is to charge the target sub-pixel a second time, and simultaneously charge the next sub-pixel that is electrically connected to the same data line as the target sub-image and has the same polarity.

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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal (AREA)

Abstract

公开了一种显示面板的驱动方法，包括：将呈矩阵排列的多个子像素中划分为多组子像素列组，其中每一组子像素列组包括相邻的两列子像素，该相邻的两列子像素之间设置一条数据线，该相邻的两列子像素均电性连接于该数据线（S110）；将行相邻的子像素极性设为相反（S120）；第一预设时间段，对目标子像素第一次充电（S130）；第二预设时间段，对目标子像素第二次充电，同时对与目标子像同一条数据线电性连接的且极性相同的下一个子像素第一次充电（S140）。

Description

显示面板的驱动方法及显示面板
相关申请的交叉引用
本申请要求于2017年06月19日提交中国专利局、申请号为201710466081.8、申请名称为“显示面板的驱动方法及显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，特别是涉及一种显示面板的驱动方法及显示面板。
背景技术
薄膜晶体管液晶显示器(TFT-LCD Thin Film Transistor Liquid Crystal Display)是当前平板显示的主要品种之一，已经成为了现代IT、视讯产品中重要的显示平台。薄膜晶体管液晶显示器主要驱动原理为，系统主板将红/绿/蓝压缩信号、控制信号及动力通过线材与印刷电路板(PCB板)上的连接器(connector)相连接，数据经过印刷电路板上的时序控制器(TCON Timing Controller)芯片处理后，经印刷电路板，通过源极驱动芯片(S-COF Source-Chip on Film)和删极驱动芯片(G-COF Gate-Chip on Film)与显示区连接，从而使得显示器获得所需的电源、信号。
现在很多薄膜晶体管液晶显示器采用双栅极(dual-gate)的像素(pixel)架构，该像素架构比一般的像素架构增加了一倍的栅极扫描线(gate)走线，因此称之为双栅极。而且每条数据线(data)走线上连接两个子像素，因此比一般的像素架构减少了一倍的数据线走线。打开第一行栅极扫描线时，多条数据线对所连接的两个子像素中的左侧子像素进行充电，打开第二行栅极扫 描线时，多条数据线对所连接的两个子像素中的右侧子像素进行充电，这样逐行打开栅极扫描线走线进行画面的完整的显示。当画面刷新频率为f=60Hz时，每个子像素充电时间为t＝1/60M(M为栅极扫描线走线的个数)。由于双栅极像素架构的栅极扫描线走线增加一倍，因此每个子像素充电时间变短，充电效率降低，最终降低画面的光学性能。
发明内容
基于此，有必要提供一种能够提高充电效率的显示面板的驱动方法及显示面板。
一种显示面板的驱动方法，包括：
将呈矩阵排列的多个子像素中划分为多组子像素列组，其中每一组子像素列组包括相邻的两列子像素，所述相邻的两列子像素之间设置一条数据线，所述相邻的两列子像素电性连接于所述数据线；
将行相邻的子像素极性设为相反；
第一预设时间段，对目标子像素第一次充电；以及
第二预设时间段，对目标子像素第二次充电，同时对与目标子像同一条数据线电性连接的且极性相同的下一个子像素第一次充电。
一种显示面板，包括：
多个子像素，呈矩阵排列，所述多个子像素划分为多组子像素列组，每一组子像素列组包括相邻的两列子像素；
驱动电路，包括数据线，所述数据线设置在所述相邻的两列子像素之间，所述相邻的两列子像素电性连接于所述数据线；
控制模块，设置为将呈矩阵排列的多个子像素中的行相邻的子像素极性设为相反；以及
充电模块，设置为在第一预设时间段对目标子像素第一次充电；在第二预设时间段对目标子像素第二次充电，同时对与目标子像同一条数据线电性 连接的且极性相同的下一个子像素第一次充电。
一种显示面板的驱动方法，包括：
将呈矩阵排列的多个子像素中划分为多组子像素列组，其中每一组子像素列组包括相邻的两列子像素，所述相邻的两列子像素之间设置一条数据线，所述相邻的两列子像素电性连接于所述数据线；
将行相邻的子像素极性设为相反；
第一预设时间段，对目标子像素第一次充电，同时对与目标子像同一条数据线电性连接的且极性相同的上一个子像素第二次充电；以及
第二预设时间段，对目标子像素第二次充电，同时对与目标子像同一条数据线电性连接的且极性相同的下一个子像素第一次充电。
上述显示面板的驱动方法及显示面板中，由于采用双栅极子像素架构，栅极扫描线增加了一倍，每个子像素的充电时间降低了一倍，因此对目标子像素在第一预设时间段先进行第一次充电，实现对目标子像素的预充电，然后在第二预设时间段再以实际电压进行第二次充电，其中第一次充电和第二次充电的极性相同，如此在实际电压进行第二次充电前已经进行了一次预充电，第二次充电就不再是从零开始，只需要更少的时间就能达到预设目标值，对目标子像素就进行了两次充电，充电时间增加，提高了充电效率，改善了画面的光学性能，而且对制程需求不变，产品成本没有提高。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为一实施例中的显示面板的驱动方法的流程图；
图2为一实施例中的子像素的极性分布示意图；
图3为另一实施例中的子像素的极性分布示意图；
图4为一实施例中的显示面板的子像素的架构示意图；
图5为一实施例中的栅极扫描线的驱动信号时序图；
图6为一实施例中的显示面板的框图；
图7为另一实施例中的显示面板的驱动方法的流程图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的较佳实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容的理解更加透彻全面。
图1为一种显示面板的驱动方法的流程图，其中显示面板包括呈矩阵排列的多个子像素(pixel)；显示面板包括多条竖直设置的数据线(data)、多条水平设置的栅极扫描线(gate)；该方法包括步骤S110-步骤S140。其中：
步骤S110：将呈矩阵排列的多个子像素中划分为多组子像素列组，其中每一组子像素列组包括相邻的两列子像素，所述相邻的两列子像素之间设置一条数据线，所述相邻的两列子像素电性连接于所述数据线。
步骤S120：将行相邻的子像素极性设为相反。
步骤S130：第一预设时间段，对目标子像素第一次充电。
步骤S140：第二预设时间段，对目标子像素第二次充电，同时对与目标子像同一条数据线电性连接的且极性相同的下一个子像素第一次充电。
由于采用双栅极子像素架构，栅极扫描线增加了一倍，每个子像素的栅极扫描线单次充电时间降低了一倍，因此对目标子像素在第一预设时间段先进行第一次充电，实现对目标子像素的预充电，然后在第二预设时间段再以实际电压进行第二次充电，其中第一次充电和第二次充电的极性相同，如此在实际电压进行第二次充电前已经进行了一次预充电，第二次充电就不再是从零开始，只需要更少的时间就能达到预设目标值，对目标子像素就进行了两次充电，充电时间增加，提高了充电效率，改善了画面的光学性能，而且 对制程需求不变，产品成本没有提高。该方法可以应用在双栅极(dual-gate)子像素架构的显示面板中。
其中，该方法还包括：每行子像素的上下两侧各设置一条栅极扫描线，子像素列组的其中一列子像素电性连接于该列子像素上侧的栅极扫描线，子像素列组的另一列子像素电性连接于该列子像素下侧的栅极扫描线。
其中，该方法还包括：该子像素架构可以有两种数据反转方式，分别为1+2n行与2n行两种方式，n为自然数。其中1+2n行的数据反转方式表示某条数据线上数据的极性为“+--++--”或“-++--++”，因此可以得到图2所示的子像素210数据极性的显示。使得每一组子像素列组中的相邻的两列子像素同一行的两个子像素210极性相反。2n行的数据反转方式表示某条数据线上数据的极性为“--++--”或“++--++”，因此可以得到图3所示的子像素210数据极性的显示。使得每一组子像素列组中的相邻的两列子像素同一行的两个子像素210极性相反。横向和竖向子像素210的数据极性不同可以均匀显示降低闪烁。
图4为显示面板的子像素的架构示意图，该子像素架构比一般的子像素架构增加了一倍的栅极扫描线走线230。而且每条数据线220走线上连接两个子像素210，因此比一般的子像素架构减少了一半的数据线220走线。
打开第一行栅极扫描线G1时，数据线D1、D2……DN、DN+1对所连接的两个子像素中的左侧子像素进行充电，打开第二行栅极扫描线G2时，数据线D1、D2……DN、DN+1对所连接的两个子像素中的右侧子像素进行充电，这样逐行打开栅极扫描线走线进行画面的完整的显示。当画面刷新频率为f＝60Hz时，每个子像素充电时间为t＝1/60M(M为栅极扫描线走线的个数)。由于栅极扫描线增加一倍，因此每条栅极扫描线对每个子像素单次充电时间变短。
显示面板的时钟控制器(TCON Timing Controller)内部对极性反转信号(POL Polarity)进行检测，对于同一条数据线上的子像素而言，当第M条栅极扫描线上的数据极性与第M+1条栅极扫描线上的数据极性相同时，那么对 该两条栅极扫描线上的子像素进行双扫描充电，其中第M条栅极扫描线上的子像素第二次充电即实际充电时，还对第M+1条栅极扫描线上的子像素进行第一次充电即预充电。当第M条栅极扫描线上的数据极性与第M+1条栅极扫描线上的数据极性不同时，那么就对同一条数据线上的下一个极性相同的子像素扫描充电，根据上述实施例的数据反转方式可知，第M条与M+3条栅极扫描线上的子像素数据极性相同，则可以对第M条与M+3条栅极扫描线上的子像素进行双扫描充电，即其中第M条栅极扫描线上的子像素第二次充电即实际充电时，还对第M+3条栅极扫描线上的子像素进行第一次充电即预充电。
如图5所示为双扫描充电时栅极扫描线的驱动信号。栅极扫描线信号逐行开启每行子像素，每行的栅极扫描线信号分为两个预设时间段，第一预设时间段是以相同极性的其他子像素电压进行第一次充电，即预充电段，第二预设时间段是以实际所要设定的电压进行第二次充电，即因此同一时间有且仅有两行薄膜晶体管(TFT)同时打开。其中，第一预设时间段的充电时间可以等于第二预设时间段的充电时间，方便操作。第一预设时间段和第二预设时间段相邻设置或间隔两个充电时间设置。
具体的，下面以数据反转方式为1+2n行举例说明，其中栅极扫描线G1行数据极性与G4行数据极性一致，因此在栅极扫描线G1行以实际电压对薄膜晶体管充电的同时，对栅极扫描线G4行子像素进行预充电，如图5中脉冲P1和P5所示。栅极扫描线G2行数据极性与栅极扫描线G3行数据极性一致，因此在栅极扫描线G2行以实际电压对子像素充电的同时对栅极扫描线G3行子像素进行预充电，如图5中脉冲P2和P3所示。栅极扫描线G3行数据极性与栅极扫描线G6行数据极性一致，因此在栅极扫描线G3行以实际电压对子像素充电的同时对栅极扫描线G6行子像素进行预充电，如图5中脉冲P4和P8所示。栅极扫描线G4行数据极性与栅极扫描线G5行数据极性一致，因此在栅极扫描线G4行以实际电压对子像素充电的同时对栅极扫描线G5行子像素进行预充电，如图5中脉冲P6和P7所示。同理，后续每行都会 以实际电压对相同数据极性的另外一行进行预充电。同理，当数据反转方式为2n行时，采用类似的方法对子像素充电。
图6为一实施例中显示面板的框图，该显示面板包括呈矩阵排列的多个子像素210、驱动电路230、充电模块240和控制模块250。其中驱动电路230包括数据线220。
结合图4，其中多个子像素210呈矩阵排列，多个子像素210划分为多组子像素列组，每一组子像素列组包括相邻的两列子像素。
数据线220设置在所述相邻的两列子像素之间，相邻的两列子像素电性连接于所述数据线220。
控制模块250用于将呈矩阵排列的多个子像素中的行相邻的子像素极性设为相反。
充电模块240用于在第一预设时间段对目标子像素第一次充电；在第二预设时间段对目标子像素第二次充电，同时对与目标子像同一条数据线220电性连接的且极性相同的下一个子像素第一次充电。
驱动电路还可以包括多条竖直设置的数据线220和多条水平设置的栅极扫描线230。每行子像素的上下两侧各设置一条栅极扫描线，子像素列组的其中一列子像素电性连接于该列子像素上侧的栅极扫描线，子像素列组的另一列子像素电性连接于该列子像素下侧的栅极扫描线。由于采用双栅极子像素架构，栅极扫描线增加了一倍，每个子像素的栅极扫描线单次充电时间降低了一倍，因此对目标子像素在第一预设时间段先进行第一次充电，实现对目标子像素的预充电，然后在第二预设时间段再以实际电压进行第二次充电，其中第一次充电和第二次充电的极性相同，如此在实际电压进行第二次充电前已经进行了一次预充电，第二次充电就不再是从零开始，只需要更少的时间就能达到预设目标值，对目标子像素就进行了两次充电，充电时间增加，提高了充电效率，改善了画面的光学性能，而且对制程需求不变，产品成本没有提高。
其中，该子像素架构有两种数据反转方式，分别为1+2n行与2n行两种 方式，，n为自然数。其中1+2n行的数据反转方式表示某条数据线上数据的极性为“+--++--”或“-++--++”，因此可以得到图2所示的子像素数据极性的显示。如此设置每一组子像素列组中的相邻的两列子像素同一行的两个子像素极性相反。2n行的数据反转方式表示某条数据线上数据的极性为“--++--”或“++--++”，因此可以得到图3所示的子像素数据极性的显示。如此设置每一组子像素列组中的相邻的两列子像素同一行的两个子像素极性相反。横向和竖向子像素的数据极性不同可以均匀显示降低闪烁。
充电模块还用于对目标子像素第一次充电同时对与目标子像素同一条数据线电性连接的且极性相同的上一个子像素第二次充电。
显示面板的时钟控制器(TCON Timing Controller)内部对极性反转信号(POL Polarity)进行检测，对于同一条数据线上的子像素而言，充电模块用于，当第M条栅极扫描线上的数据极性与第M+1条栅极扫描线上的数据极性相同时，那么对该两条栅极扫描线上的子像素进行双扫描充电，其中第M条栅极扫描线上的子像素第二次充电即实际充电时，还对第M+1条栅极扫描线上的子像素进行第一次充电即预充电。当第M条栅极扫描线上的数据极性与第M+1条栅极扫描线上的数据极性不同时，那么就对同一条数据线上的下一个极性相同的子像素扫描充电，根据上述实施例的数据反转方式可知，第M条与M+3条栅极扫描线上的子像素数据极性相同，则可以对第M条与M+3条栅极扫描线上的子像素进行双扫描充电，即其中第M条栅极扫描线上的子像素第二次充电即实际充电时，还对第M+3条栅极扫描线上的子像素进行第一次充电即预充电。
显示面板还包括计时器，计时器用于计算第一时间段的充电时间和第二时间段的充电时间；其中第一时间段的充电时间等于第二时间段的充电时间，第一时间段和第二时间段相邻设置或间隔两个充电时间设置。具体的，如图5所示为双扫描充电时栅极扫描线的驱动信号。栅极扫描线信号逐行开启每行子像素，每行的栅极扫描线信号分为两个预设时间段，第一预设时间段是以相同极性的其他子像素电压进行第一次充电，即预充电段，第二预设时间 段是以实际所要设定的电压进行第二次充电，即因此同一时间有且仅有两行薄膜晶体管(TFT)同时打开。其中，第一预设时间段的充电时间可以等于第二预设时间段的充电时间，方便操作。第一预设时间段和第二预设时间段相邻设置或间隔两个充电时间设置。
进一步地，下面以数据反转方式为1+2n行举例说明，其中栅极扫描线G1行数据极性与G4行数据极性一致，因此在栅极扫描线G1行以实际电压对薄膜晶体管充电的同时，对栅极扫描线G4行子像素进行预充电，如图5中脉冲P1和P5所示。栅极扫描线G2行数据极性与栅极扫描线G3行数据极性一致，因此在栅极扫描线G2行以实际电压对子像素充电的同时对栅极扫描线G3行子像素进行预充电，如图5中脉冲P2和P3所示。栅极扫描线G3行数据极性与栅极扫描线G6行数据极性一致，因此在栅极扫描线G3行以实际电压对子像素充电的同时对栅极扫描线G6行子像素进行预充电，如图5中脉冲P4和P8所示。栅极扫描线G4行数据极性与栅极扫描线G5行数据极性一致，因此在栅极扫描线G4行以实际电压对子像素充电的同时对栅极扫描线G5行子像素进行预充电，如图5中脉冲P6和P7所示。同理，后续每行都会以实际电压对相同数据极性的另外一行进行预充电。同理，当数据反转方式为2n行时，采用类似的方法对子像素充电。
该显示面板中每条栅极扫描线打开两次，每个子像素第一次以相同极性的其他像素电压进行第一次充电，第二次以实际像素电压进行充电；时钟控制器内部对极性反转信号进行检测，当检测到某两行数据极性一样时，就对该两行子像素进行双扫描充电。采用预充电方式后，每个子像素的充电时间增加，从而提高充电效率，改善画面的光学性能。在不增加成本的前提下，解决了该子像素架构因为栅极扫描线走线加倍导致的充电效率降低的问题，对制程需求不变。
显示面板可以为TN(Twisted Nematic，扭曲向列)、OCB(Optically Compensated Birefringence，光学补偿弯曲排列)、VA(Vertical Alignment，垂直配向)型液晶显示面板，但并不限于此。该显示面板可以为RGB三原色 面板、RGBW四色面板或者RGBY四色面板，但并不限于此。该驱动方法同样适用于显示面板为曲面面板时的情形。
在某些实施方式中，显示面板还可例如为OLED显示面板、QLED显示面板、曲面显示面板或其他显示面板。然不限于此。
图7为另一实施例的显示面板的驱动方法的流程图，该方法包括以下步骤：
步骤S210：将呈矩阵排列的多个子像素划分为多组子像素列组，其中每一组子像素列组包括相邻的两列子像素，所述相邻的两列子像素之间设置有数据线，所述相邻的两列子像素电性连接于所述数据线。
步骤S220：将行相邻的子像素极性设为相反。
步骤S230：第一预设时间段，对目标子像素第一次充电，同时对与目标子像素同一条数据线电性连接的且极性相同的上一个子像素第二次充电。
步骤S240：第二预设时间段，对目标子像素第二次充电，同时对与目标子像同一条数据线电性连接的且极性相同的下一个子像素第一次充电。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (19)

  1. 一种显示面板的驱动方法，包括：
    将呈矩阵排列的多个子像素划分为多组子像素列组，其中每一组子像素列组包括相邻的两列子像素，所述相邻的两列子像素之间设置有数据线，所述相邻的两列子像素电性连接于所述数据线；
    将行相邻的子像素极性设为相反；
    第一预设时间段，对目标子像素第一次充电；以及
    第二预设时间段，对目标子像素第二次充电，同时对与目标子像同一条数据线电性连接的且极性相同的下一个子像素第一次充电。
  2. 根据权利要求1所述的方法，还包括：
    将每一组所述子像素列组中的相邻的两列子像素同一行的两个子像素极性设为相同。
  3. 根据权利要求1所述的方法，还包括：
    将每一组所述子像素列组中的相邻的两列子像素同一行的两个子像素极性设为相反。
  4. 根据权利要求1所述的方法，还包括：
    对所述目标子像素第一次充电同时对与目标子像素同一条数据线电性连接的且极性相同的上一个子像素第二次充电。
  5. 根据权利要求1所述的方法，还包括：
    所述第一预设时间段的充电时间等于第二预设时间段的充电时间。
  6. 根据权利要求1所述的方法，还包括：
    所述第一预设时间段和第二预设时间段相邻设置。
  7. 根据权利要求1所述的方法，还包括：
    所述第一预设时间段和第二预设时间段间隔两个充电时间设置。
  8. 根据权利要求1所述的方法，还包括：
    每行子像素的上下两侧各设置一条栅极扫描线。
  9. 根据权利要求8所述的方法，其中：
    所述子像素列组的其中一列子像素电性连接于该列子像素上侧的栅极扫描线，所述子像素列组的另一列子像素电性连接于该列子像素下侧的栅极扫描线。
  10. 根据权利要求8所述的方法，其中：
    所述栅极扫描线信号逐行开启每行子像素。
  11. 一种显示面板，包括：
    多个子像素，呈矩阵排列，所述多个子像素组成为多组子像素列组，每一组子像素列组包括相邻的两列子像素；
    驱动电路，包括数据线，所述数据线设置在所述相邻的两列子像素之间，所述相邻的两列子像素电性连接于所述数据线；
    控制模块，设置为将呈矩阵排列的多个子像素中的行相邻的子像素极性设为相反；以及
    充电模块，设置为第一预设时间段，对目标子像素第一次充电；还设置为第二预设时间段，对目标子像素第二次充电，同时对与目标子像同一条数据线电性连接的且极性相同的下一个子像素第一次充电。
  12. 根据权利要求11所述的显示面板，其中：
    所述每一组子像素列组中的相邻的两列子像素同一行的两个子像素极性相同。
  13. 根据权利要求11所述的显示面板，其中：
    所述每一组子像素列组中的相邻的两列子像素同一行的两个子像素极性相反。
  14. 根据权利要求11所述的显示面板，其中：
    所述充电模块还设置为对目标子像素第一次充电同时对与目标子像素同一条数据线电性连接的且极性相同的上一个子像素第二次充电。
  15. 根据权利要求11所述的显示面板，所述显示面板还包括：
    计时器，所述计时器设置为计算第一预设时间段的充电时间和第二预设时间段的充电时间；
    其中，所述第一预设时间段的充电时间等于第二预设时间段的充电时间，所述第一预设时间段和第二预设时间段相邻设置或间隔两个充电时间设置。
  16. 根据权利要求11所述的显示面板，所述驱动电路还包括：
    多条水平设置的栅极扫描线，每行子像素的上下两侧各设置一条栅极扫描线。
  17. 根据权利要求16所述的显示面板，其中：
    所述子像素列组的其中一列子像素电性连接于该列子像素上侧的栅极扫描线，所述子像素列组的另一列子像素电性连接于该列子像素下侧的栅极扫描线。
  18. 根据权利要求16所述的显示面板，其中：
    所述栅极扫描线信号逐行开启每行子像素。
  19. 一种显示面板的驱动方法，包括：
    将呈矩阵排列的多个子像素划分为多组子像素列组，其中每一组子像素列组包括相邻的两列子像素，所述相邻的两列子像素之间设置有数据线，所述相邻的两列子像素电性连接于所述数据线；
    将行相邻的子像素极性设为相反；
    第一预设时间段，对目标子像素第一次充电，同时对与目标子像素同一条数据线电性连接的且极性相同的上一个子像素第二次充电；以及
    第二预设时间段，对目标子像素第二次充电，同时对与目标子像素同一条数据线电性连接的且极性相同的下一个子像素第一次充电。
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