WO2012157649A1 - Dispositif d'affichage - Google Patents

Dispositif d'affichage Download PDF

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Publication number
WO2012157649A1
WO2012157649A1 PCT/JP2012/062432 JP2012062432W WO2012157649A1 WO 2012157649 A1 WO2012157649 A1 WO 2012157649A1 JP 2012062432 W JP2012062432 W JP 2012062432W WO 2012157649 A1 WO2012157649 A1 WO 2012157649A1
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WO
WIPO (PCT)
Prior art keywords
board
signal
inter
fail
timing controller
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PCT/JP2012/062432
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English (en)
Japanese (ja)
Inventor
直大 北城
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シャープ株式会社
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Publication of WO2012157649A1 publication Critical patent/WO2012157649A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3666—Control of matrices with row and column drivers using an active matrix with the matrix divided into sections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/02—Composition of display devices
    • G09G2300/026—Video wall, i.e. juxtaposition of a plurality of screens to create a display screen of bigger dimensions
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/04—Display device controller operating with a plurality of display units
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/06—Use of more than one graphics processor to process data before displaying to one or more screens
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/18—Timing circuits for raster scan displays

Definitions

  • the present invention relates to a display device equipped with a plurality of timing controllers.
  • the display screen is divided into multiple partial display areas in order to cope with the shortening of the writing time to each pixel accompanying the high definition of the liquid crystal display device and the dullness of the signal waveform accompanying the enlargement of the liquid crystal display device.
  • a configuration (screen division method) for driving display areas separately has been proposed (see, for example, Patent Documents 1 to 3).
  • this screen division method for example, one screen is divided vertically (the upper area is the first area and the lower area is the second area), the first half of the frame (upper side) is displayed in the first area, and the second The second half (lower side) of the frame is displayed in the area.
  • QFHD Quant Full High Definition
  • 4K2K a standard of SHV (Super Hi-Vision or UHDTV: Ultra High Definition Television)
  • 8K4K a standard of SHV (Super Hi-Vision or UHDTV: Ultra High Definition Television)
  • the timing controller does not prepare for output of the video signal normally for some reason, an image may not be displayed only in the partial display area corresponding to the timing controller. For example, an abnormality occurred in the operation of the timing controller itself, when the power was turned on, the device in the previous stage of the timing controller was not yet started and no video signal was input, or the operation of one of the devices in the previous stage was abnormal It is conceivable that the timing of the video signal input to the timing controller is not appropriate due to the occurrence of the error or the video signal input to the display device being inappropriate.
  • the timing of the video signal is not appropriate, for example, the sync width, front porch width, back porch width, effective period of the horizontal synchronization signal, or the sync width, front porch width, back porch width of the vertical synchronization signal, and effective This indicates that the period or DataEnable signal is not appropriate.
  • the timing of the video signal input to a certain timing controller is not appropriate, there is a possibility that the display of the corresponding partial display area will fail. For this reason, it is preferable not to display an image of the entire display area (for example, to display black) rather than to display an image in a state where some displays are not normal.
  • the present invention has been made in view of the above-described problems, and the object thereof is a display device that performs parallel processing of video data by a plurality of timing controllers when an abnormality occurs in any of the timing controllers.
  • An object of the present invention is to realize a display device capable of preventing inappropriate display.
  • a display device includes a display unit including a first region and a second region, a first substrate provided with a first timing controller that performs display control of the first region, and display control of the second region.
  • a second board provided with a second timing controller for performing the above-described operation, and an inter-board connection unit for connecting the first board and the second board, wherein the first timing controller controls display of the first area. If an abnormality occurs, a fail-safe signal is transmitted to the inter-board connection section to notify the second timing controller that the abnormality has occurred.
  • the 1st timing controller and the 2nd timing controller can perform suitable treatment (for example, self-running control) to the above-mentioned abnormality.
  • the occurrence of an abnormality in the display control of the first timing controller provided on the first substrate can be transmitted to the second timing controller provided on another second substrate.
  • the 1st timing controller and the 2nd timing controller can perform suitable treatment (for example, self-running control) to the above-mentioned abnormality.
  • FIG. 1 is a block diagram illustrating an overall configuration of a display device according to an embodiment of the present invention. It is a block diagram which shows the detailed structure of the pixel of the said display apparatus. It is a table
  • the liquid crystal display device LCD according to the present embodiment corresponds to a video standard having a pixel number (8K4K) that is 16 times the number of full HD pixels (for example, Super Hi-Vision having a resolution of horizontal 7680 pixels ⁇ vertical 4320 pixels).
  • an input processing circuit IPC an input processing circuit IPC, a pixel mapping circuit PMC, four display control boards (timing controller boards) DC1 to DC4, a liquid crystal panel (display unit) LCP, four gate drivers GD1 to GD4, 2 One source driver SD1 to SD2, four CS drivers CD1 to CD4, three power supply devices (not shown) connected to different commercial power sources, a power supply controller (not shown), a backlight BL, and a backlight driver BLD And a backlight controller BLC.
  • IPC input processing circuit
  • a pixel mapping circuit PMC four display control boards (timing controller boards) DC1 to DC4, a liquid crystal panel (display unit) LCP, four gate drivers GD1 to GD4, 2 One source driver SD1 to SD2, four CS drivers CD1 to CD4, three power supply devices (not shown) connected to different commercial power sources, a power supply controller (not shown), a backlight BL, and a backlight driver BLD And a backlight controller BLC.
  • the video signal input to the input processing circuit IPC may be a video signal (for example, Super Hi-Vision) having a block scan format of 8K4K pixels, or a video signal having a number of 8K4K pixels of a multi-display format. Also good. Of course, it may be a video signal having the number of 4K2K pixels or a video signal having the number of 2K1K pixels (the number of full HD pixels).
  • the block scan format is a method in which one frame (entire image having 8K4K pixels) is divided into 16 coarse (full HD pixel) whole images (so-called thinned images) and transmitted.
  • each of the 16 video signals Qa1 to Qa16 input to the input processing circuit IPC is a rough overall image (the number of full HD pixels).
  • the multi-display format is a system in which one frame (entire image having the number of 8K4K pixels) is divided into 16 without changing the fineness of the frame, and divided into 16 partial images for transmission.
  • each of the 16 video signals Qa1 to Qa16 input to the input processing circuit IPC is a fine partial image (the number of full HD pixels).
  • the input processing circuit IPC performs video data synchronization processing, ⁇ correction processing, color temperature correction processing, color gamut conversion processing, and the like, and outputs video signals Qb1 to Qb16 to the pixel mapping circuit PMC.
  • the display control board DC1 includes two video processing circuits EP1 and EP2 and two timing controllers TC1 and TC2, and the display control board DC2 includes two video processing circuits EP3 and EP4 and two timing controllers TC3 and TC4.
  • the display control board DC3 includes two video processing circuits EP5 and EP6 and two timing controllers TC5 and TC6, and the display control board DC4 includes two video processing circuits EP7 and EP8 and two timing controllers TC7 and TC8. Is provided.
  • the pixel mapping circuit PMC generates two video signals (number of pixels 2K2K) corresponding to the left half AR1 of the first region (upper left region when the liquid crystal panel LCP is divided into upper, lower, left, and right) into four (full HD pixel number images).
  • the video signal Qc3 / Qc4) is divided and output to the video processing circuit EP2 of the display control board DC1, and the video corresponding to the left half AR3 of the second region (the upper right region when the liquid crystal panel LCP is divided into four parts vertically and horizontally)
  • the signal (number of pixels 2K2K) is divided into two (video signals Qc5 and Qc6 having the number of full HD pixels) and output to the video processing circuit EP3 of the display control board DC2, and the right half of the second area
  • the video signal (number of pixels 2K2K) corresponding to AR4 is divided into two (video signals Qc7 and Qc8 having the number of full HD pixels) and output to the video processing circuit EP4 of the display control board DC2, and the third region (liquid crystal panel) Display control board by
  • the video signal (number of pixels 2K2K) corresponding to the right half AR6 of the third region is divided into two (video signals Qc11 and Qc12 having the number of full HD pixels) and output to the video processing circuit EP5 of DC3.
  • the video signal (number of pixels 2K2K) corresponding to the left half AR7 of the fourth area (the lower right area when the liquid crystal panel LCP is divided into four parts vertically and horizontally) is output to the video processing circuit EP6 of the substrate DC3.
  • the image signal is divided into two (video signals Qc13 and Qc14 having the number of full HD pixels) and output to the video processing circuit EP7 of the display control board DC4, and the video signal (pixel number 2K2K) corresponding to the right half AR8 of the fourth region is output. It is divided into two (video signals Qc15 and Qc16 having the number of full HD pixels) and output to the video processing circuit EP8 of the display control board DC4.
  • the pixel mapping circuit PMC outputs a synchronization signal SYS (vertical synchronization signal, horizontal synchronization signal, clock signal, data enable signal, polarity inversion signal, etc.) to the timing controller TC1 of the display control board DC1, and receives this timing.
  • the controller TC1 transmits this synchronization signal SYS to the inter-substrate shared line SSL connected to the display control substrates DC1 to DC4.
  • the timing controller TC1 receives the synchronization signal SYS received from the pixel mapping circuit PMC and cooperates with the video processing circuit EP1 to perform video processing such as gradation conversion processing and frame rate conversion (FRC) processing on the video signals Qc1 and Qc2.
  • the source control signal SC1 is output to the source driver substrate (not shown) corresponding to AR1
  • the gate control signal GC1 is output to the gate driver substrate (not shown) of the gate driver GD1
  • the CS driver CD1 is output.
  • the CS control signal CC1 is output.
  • the timing controller TC2 receives the synchronization signal SYS transmitted from the timing controller TC1 via the inter-substrate shared line SSL, cooperates with the video processing circuit EP2, performs the video processing on the video signals Qc3 and Qc4, and then performs AR2
  • a source control signal SC2 is output to a source driver board (not shown) corresponding to
  • the timing controller TC3 receives the synchronization signal SYS transmitted from the timing controller TC1 via the inter-substrate shared line SSL, cooperates with the video processing circuit EP3, performs the video processing on the video signals Qc5 and Qc6, and then performs AR3.
  • a source control signal SC3 is output to a source driver board (not shown) corresponding to
  • the timing controller TC4 receives the synchronization signal SYS transmitted from the timing controller TC1 via the inter-substrate shared line SSL, cooperates with the video processing circuit EP4, performs the video processing on the video signals Qc7 and Qc8, and then performs AR4.
  • the source control signal SC4 is output to the source driver board (not shown) corresponding to the above, the gate control signal GC2 is output to the gate driver board (not shown) of the gate driver GD2, and the CS control signal CC2 is sent to the CS driver CD2. Output.
  • the timing controller TC5 receives the synchronization signal SYS transmitted from the timing controller TC1 via the inter-substrate shared line SSL, cooperates with the video processing circuit EP5, performs the video processing on the video signals Qc9 and Qc10, and then performs AR5.
  • the source control signal SC5 is output to the source driver board (not shown) corresponding to the above, the gate control signal GC3 is output to the gate driver board (not shown) of the gate driver GD3, and the CS control signal CC3 is sent to the CS driver CD3. Output.
  • the timing controller TC6 receives the synchronization signal SYS transmitted from the timing controller TC1 via the inter-substrate shared line SSL, cooperates with the video processing circuit EP6, performs the video processing on the video signals Qc11 and Qc12, and then performs AR6.
  • a source control signal SC6 is output to a source driver board (not shown) corresponding to
  • the timing controller TC7 receives the synchronization signal SYS transmitted from the timing controller TC1 via the inter-substrate shared line SSL, cooperates with the video processing circuit EP7, performs the video processing on the video signals Qc13 and Qc14, and then performs AR7.
  • a source control signal SC7 is output to a source driver board (not shown) corresponding to
  • the timing controller TC8 receives the synchronization signal SYS transmitted from the timing controller TC1 via the inter-substrate shared line SSL, cooperates with the video processing circuit EP8, performs the video processing on the video signals Qc15 and Qc16, and then performs AR8.
  • the source control signal SC8 is output to the source driver board (not shown) corresponding to the above, the gate control signal GC4 is output to the gate driver board (not shown) of the gate driver GD4, and the CS control signal CC4 is sent to the CS driver CD4. Output.
  • the source control signals SC1 to SC8 include a data signal, a data enable signal (DE signal), a source start pulse, and a source clock.
  • the gate control signals GC1 to GC4 include an initial signal, a gate start pulse, and a gate. A clock is included.
  • the fail-safe signal transmitted from the display control board in which the abnormality has occurred is transmitted to all other display control boards. And all the display control boards instantaneously enter the self-running (black display) mode. Thereby, the video failure is avoided.
  • the liquid crystal panel LCP includes an active matrix substrate, a liquid crystal layer (not shown), and a counter substrate (not shown).
  • the active matrix substrate includes a plurality of pixel electrodes (not shown) and a plurality of TFTs (thin film transistors, FIG. Scanning signal lines Ga to Gd extending in the row direction (the direction along the long side of the panel), a plurality of data signal lines Sa to Sd extending in the column direction, and a storage capacitor wiring (CS wiring extending in the row direction).
  • CSa to CSd and CS trunk wires Ma to Mh extending in the column direction are provided, and a common electrode (not shown), a color filter, and a black matrix (not shown) are provided on the counter substrate. .
  • the liquid crystal panel LCP is provided with two data signal lines corresponding to the upper half (upstream side of the panel) of one pixel column, and 2 corresponding to the lower half (downstream side of the panel) of this pixel column. It has a so-called upper / lower divided double source structure (a structure in which four data signal lines are provided per pixel column and four scanning signal lines can be selected simultaneously) provided with two data signal lines. Quadruple speed drive is possible. Furthermore, the liquid crystal panel LCP is a so-called multi-pixel method in which at least two pixel electrodes are provided in one pixel, and the viewing angle characteristics can be enhanced by a bright region and a dark region formed in one pixel. ing.
  • scanning signal lines Ga and Gb and storage capacitor lines CSa and CSb are provided in the upper half (upstream side) of the panel, and scanning signals are provided in the lower half (downstream side) of the panel.
  • Lines Gc and Gd and storage capacitor lines CSc and CSd are provided, and the upper half (upstream side) of one pixel column PL1 includes two pixels Pa and Pb adjacent in the column direction, and the lower half of the pixel column PL1
  • Two pixels Pc and Pd adjacent in the column direction are included on the (downstream side)
  • data signal lines Sa and Sb are provided corresponding to the upper half (upstream side) of the pixel column PL1, and below the pixel column PL1.
  • Data signal lines Sc and Sd are provided corresponding to the half (downstream side).
  • the TFT 12A connected to the pixel electrode 17A and the TFT 12a connected to the pixel electrode 17a are connected to the data signal line Sa and the scanning signal line Ga, respectively.
  • 17A forms a storage capacitor line and a storage capacitor
  • the pixel electrode 17a forms a storage capacitor line CSa and a storage capacitor
  • the TFT 12B is connected to the pixel electrode 17B of the two pixel electrodes 17B and 17b included in the pixel Pb.
  • the TFT 12b connected to the pixel electrode 17b is connected to the data signal line Sb and the scanning signal line Gb, the pixel electrode 17B forms the storage capacitor line CSa and the storage capacitor, and the pixel electrode 17b holds the storage capacitor line CSb.
  • a capacitor is formed, and an image of the two pixel electrodes 17C and 17c included in the pixel Pc is further formed.
  • the TFT 12C connected to the electrode 17C and the TFT 12c connected to the pixel electrode 17c are respectively connected to the data signal line Sc and the scanning signal line Gc, the pixel electrode 17C forms a storage capacitor line and a storage capacitor, and the pixel electrode 17c holds The capacitor wiring CSc and the storage capacitor are formed, and the TFT 12D connected to the pixel electrode 17D and the TFT 12d connected to the pixel electrode 17d of the two pixel electrodes 17D and 17d included in the pixel Pd are scanned with the data signal line Sd.
  • the pixel electrode 17D forms a storage capacitor line CSc and a storage capacitor, and the pixel electrode 17d forms a storage capacitor line CSd and a storage capacitor.
  • the four scanning signal lines Ga to Gd are connected to the signal line Gd. Selected at the same time.
  • the scanning signal line Gc is The scanning signal line Gb is the M + 2161th line in the (M + 2160) th line counted from the upper long side, and the Mth line data signal of the Nth frame is written in the scanning signal line Ga provided in the upper half of the panel. Then, the data signal of the (M + 2160) th line of the (N ⁇ 1) th frame, which is the previous frame, is written to the scanning signal line Gc provided in the lower half of the panel.
  • the polarity of the data signal supplied to one data signal line is inverted every vertical scanning period (1V), and is supplied to one and the other of the two adjacent data signal lines in the same vertical scanning period.
  • the polarity of the data signal is reversed.
  • each data signal line is inverted by 1V (that is, the polarity inversion period is lengthened and power consumption is reduced), and the polarity distribution of the pixels in the screen is inverted by dots (thus turning off the TFT). Flicker caused by the pull-in voltage generated at the same time can be suppressed).
  • the gate driver GD1 includes a plurality of gate driver chips I provided along one of the two short sides of the upper half of the liquid crystal panel LCP and arranged in the column direction.
  • the vertical driver GD2 includes a plurality of gate driver chips I provided along the other of the two short sides of the upper half of the liquid crystal panel LCP and arranged in the column direction.
  • the gate driver GD3 includes a plurality of gate driver chips I provided along one of the two short sides of the lower half of the liquid crystal panel LCP and arranged in the column direction.
  • the vertical driver GD4 is provided along the other of the two short sides of the lower half of the liquid crystal panel LCP, and includes a plurality of gate driver chips I arranged in the column direction.
  • the scanning signal lines provided in the upper half of the panel are driven by the gate drivers GD1 and GD2, and the scanning signal lines provided in the lower half of the panel are driven by the gate drivers GD3 and GD4. That is, one scanning signal line is connected to two gate drivers arranged on both sides thereof, and a scanning (pulse) signal having the same phase is supplied from the two gate drivers to the one scanning signal line. By so doing, it is possible to suppress variations in signal dullness (the degree of signal dullness varies depending on the position in the row direction) caused by CR (time constant) of the scanning signal line.
  • the source driver SD1 is provided along one long side of the upper half of the liquid crystal panel LCP, and 48 source driver chips J arranged in the row direction (the number of output terminals of one source driver chip is 960), 4 source driver boards (not shown) are included (12 source driver chips J are mounted on one source driver board).
  • the source driver SD2 is provided along one long side of the lower half of the liquid crystal panel LCP, and 48 source driver chips J arranged in the row direction (the number of output terminals of one source driver chip is 960). And four source driver boards (not shown) (12 source driver chips J are mounted on one source driver board).
  • Each data signal line provided in the upper half of the panel is driven by the source driver SD1, and each data signal line provided in the lower half of the panel is driven by the source driver SD2.
  • the data signal line Sa is driven by the source driver SD1
  • the data signal line Sc is driven by the source driver SD2.
  • the source driver chip J cannot be arranged along the long side of the panel due to the space, it is arranged on the short side of the panel with sufficient space (the source driver chip J and the gate driver chip I are arranged side by side). Can be arranged).
  • a relay line that connects the data signal line and the source terminal on the short side of the panel is provided on the counter substrate side, or other than the source layer of the active matrix substrate (the source / drain electrode formation layer of the TFT) It can also be provided in a lower layer (gate layer) of the gate insulating film or a layer between the source layer and the ITO layer (pixel electrode formation layer).
  • the CS trunk lines Ma and Mb are provided close to one of the two short sides of the upper half of the active matrix substrate, and are driven by the CS driver CD1 so that each has a different phase.
  • the CS trunk lines Mc and Md are provided close to the other of the two short sides of the upper half of the active matrix substrate, and are driven by the CS driver CD2 so that each has a different phase.
  • the CS trunk lines Me and Mf are provided close to one of the two short sides of the lower half of the active matrix substrate, and are driven by the CS driver CD3 so that each has a different phase.
  • the CS trunk wiring Mg ⁇ Mh is provided close to the other of the two short sides of the lower half of the active matrix substrate, and is driven by the CS driver CD4 so that each has a different phase.
  • One storage capacitor line is connected to two CS trunk lines arranged on both sides thereof, and a modulation (pulse) signal having the same phase is transmitted from the two CS trunk lines to the one storage capacitor line. Is supplied.
  • the storage capacitor line CSa is connected to the CS trunk lines Ma and Mc
  • the storage capacitor line CSb is connected to the CS trunk lines Mb and Md
  • the storage capacitor line CSc is connected to the CS trunk lines Me and Mg
  • the storage capacitor line CSd is connected to CS trunk lines Mf and Mh. Therefore, for example, when the potentials of the CS trunk lines Ma and Mb are controlled to be in opposite phases, the potentials of the storage capacitor lines CSa and CSb are also reversed in phase, and in the pixel Pb, the pixel electrode of the two pixel electrodes 17B and 17b.
  • the four display control boards DC1 to DC4 process in parallel video data corresponding to two partial display areas of the eight partial display areas AR1 to AR8, respectively.
  • Each of the display control boards DC1 to DC4 controls the display of the partial display areas AR1 to AR8 that are different from each other.
  • the entire display area is set to the free-running (black display) mode to appropriately control the display of the entire display area. Therefore, it is necessary to share abnormality information among the display control boards DC1 to DC4. Also, in order to control the display of the entire display area at the same time (black display or the like), immediacy is required for sharing abnormality information.
  • the fail safe signal is a signal for the timing controllers TC1 to TC8 to perform an operation (self-running control) according to the abnormal state when an abnormality occurs. Whether the certain timing controller is in a normal state or an abnormal state Is a signal for transmitting to other timing controllers. Even if an abnormality occurs in any of the timing controllers TC1 to TC8, in order for all the timing controllers TC1 to TC8 to share the abnormality information, bidirectional communication must be possible.
  • the two timing controllers may be connected by wired-or connection using a single-ended signal line. Then, by transmitting and receiving a fail safe signal between two timing controllers mounted on one board, it is possible to share abnormality information.
  • each IC chip constituting a plurality of timing controllers arranged close to each other in the substrate may be connected by a signal line.
  • timing controllers when a plurality of timing controllers are mounted on different boards as in this embodiment, when the plurality of boards are located apart from each other, a signal that connects the timing controllers (transmits a fail-safe signal) Lines will be placed extending long between the substrates. When the signal line becomes long, there arises a problem that it is easily affected by external noise.
  • FIG. 1 is a block diagram showing a detailed configuration of the display control board.
  • FIG. 1 only the configuration of the four display control boards DC1 to DC4 is shown, and the other components are not shown.
  • illustration of outputs from the timing controllers TC1 to TC8 to the outside of each display control board is omitted.
  • the display control board DC1 includes two video processing circuits EP1 and EP2, two timing controllers TC1 and TC2, and one inter-board signal sharing circuit (interface unit) SH1.
  • the display control board DC2 includes two video processing circuits EP3 and EP4, two timing controllers TC3 and TC4, and one inter-board signal sharing circuit SH2.
  • the display control board DC3 includes two video processing circuits EP5 and EP6, two timing controllers TC5 and TC6, and one inter-board signal sharing circuit SH3.
  • the display control board DC4 includes two video processing circuits EP7 and EP8, two timing controllers TC7 and TC8, and one inter-board signal sharing circuit SH4. Since the display control boards DC1 to DC4 are arranged close to the positions of the corresponding partial display areas AR1 to AR8 and the corresponding source driver chip J, they are separated from each other.
  • the inter-substrate signal sharing circuit SH1 includes an input / output switching unit IFS1, an LVDS (Low voltage differential) driver (differential signal output unit) LD1, and an LVDS receiver (differential signal input unit) LR1.
  • the LVDS driver LD1 and the LVDS receiver LR1 constitute a differential signal transmission / reception unit as a set.
  • the inter-substrate signal sharing circuit SH2 includes an input / output switching unit IFS2, an LVDS driver LD2, and an LVDS receiver LR2.
  • the inter-substrate signal sharing circuit SH3 includes an input / output switching unit IFS3, an LVDS driver LD3, and an LVDS receiver LR3.
  • the inter-substrate signal sharing circuit SH4 includes an input / output switching unit IFS4, an LVDS driver LD4, and an LVDS receiver LR4.
  • the LVDS receivers LR1 to LR4 are Type-2 specification multi-point LVDS.
  • the Type-2 specification (with fail-safe function) multipoint LVDS receiver is a receiver obtained by offsetting a High / Low determination threshold by 100 mV, and an input with a potential difference of 0 V is determined to be Low.
  • the fail-safe function of the Type-2 specification mentioned here is not related to the fail-safe signal of the present invention.
  • the LVDS drivers LD1 to LD4 and the LVDS receivers LR1 to LR4 are multi-point connected to a pair of inter-substrate signal lines (inter-substrate connection portions) for transmitting differential signals.
  • the inter-substrate signal sharing circuits SH1 to SH4 are connected to each other.
  • a termination resistor is provided between a pair of inter-substrate signal lines in the vicinity of two LVDS receivers LR1 and LR3 (located at both ends of the bus) among the LVDS receivers LR1 to LR4.
  • Each LVDS driver LD1 to LD4 is always supplied with an H level voltage as a voltage to be used for output.
  • the video processing circuits EP1 to EP8 perform various types of video processing in cooperation with the timing controllers TC1 to TC8, respectively, as described above.
  • the timing controller TC1 monitors whether or not the video processing for the video signals Qc1 and Qc2 of a certain frame is completed at a predetermined timing (within a predetermined period). That is, when the source control signal SC1, the gate control signal GC1, and the CS control signal CC1 are ready to be output at a predetermined timing, the timing controllers TC1 to TC8 normally perform the input of the video signal and the video processing. Is determined to be in a normal state. In the normal state, the control signals are output from the timing controllers TC1 to TC8 to the drivers without delay, and the video is displayed normally.
  • the timing controllers TC1 to TC8 perform video signal input or video processing. It is determined that the state is not performed normally (abnormal state). The timing controllers TC1 to TC8 that are in an abnormal state cannot output a control signal at a normal timing. Therefore, in order to control the display of each of the partial display areas AR1 to AR8 so as to prevent the video display from failing, the timing controller determined to be in an abnormal state needs to notify the other timing controllers of the abnormal state. .
  • the timing controller TC1, timing controller TC2 and inter-board signal sharing circuit SH1 mounted on the same display control board DC1 are connected by wired-or connection using a single-end in-board signal line.
  • the timing controller TC1, the timing controller TC2, and the inter-substrate signal sharing circuit SH1 transmit and receive an in-board fail-safe signal via the in-board signal line.
  • the outputs of the timing controllers TC1 and TC2 and the inter-board signal sharing circuit SH1 to the in-board signal line are OFF, and the in-board fail-safe signal is DISABLE (invalid). Is maintained at the H level.
  • the timing controllers TC1 and TC2 set the in-board signal line ports of the timing controllers TC1 and TC2 as input ports. As a result, the timing controllers TC1 and TC2 monitor the ENABLE (valid) / DISABLE (invalid) (voltage level of the signal line in the board) of the in-board failsafe signal.
  • the timing controllers TC1 and TC2 enter a self-running mode and generate a control signal for self-running control according to a preset timing inside itself without depending on the input signal.
  • a control signal for self-running control (a source control signal including a gate control signal and a black video data signal) is output to each driver, and the corresponding partial display areas AR1 and AR2 are displayed in black.
  • the timing controllers TC1 and TC2 determine that they are in an abnormal state, the in-board signal line ports of the timing controllers TC1 and TC2 are set as output ports, and the in-board fail-safe signal is set to ENABLE (valid). That is, the voltage of the signal line in the substrate is driven to L level (Low).
  • the timing controllers TC1 and TC2 enter the free-running mode. Then, a control signal for self-running control is output to each driver, and the corresponding partial display areas AR1 and AR2 are displayed in black.
  • the input / output switching unit IFS1 transmits a fail-safe signal from the timing controllers TC1 and TC2 in the display control board DC1 to the timing controllers TC3 to TC8 outside the display control board DC1, and outside the display control board DC1. It plays a role of switching between modes transmitted from the timing controllers TC3 to TC8 to the timing controllers TC1 and TC2 in the display control board DC1.
  • the input / output switching unit IFS1 sets the in-board signal line side port of the inter-board signal sharing circuit SH1 as an input port. Then, the input / output switching unit IFS1 of the inter-substrate signal sharing circuit SH1 monitors the ENABLE (valid) / DISABLE (invalid) (voltage level of the intra-substrate signal line) of the intra-board fail safe signal.
  • the input / output switching unit IFS1 When the in-board failsafe signal is DISABLE (invalid), the input / output switching unit IFS1 outputs an input / output control signal (L level) for driver / receiver switching to the LVDS driver LD1 and the LVDS receiver LR1. When the in-board failsafe signal is ENABLE (valid), the input / output switching unit IFS1 outputs an input / output control signal (H level) to the LVDS driver LD1 and the LVDS receiver LR1.
  • the input / output switching unit IFS1 sets the in-board signal line side port of the inter-board signal sharing circuit SH1 as an output port,
  • the in-board fail-safe signal is set to ENABLE (valid), that is, the voltage of the in-board signal line is driven to L level.
  • the LVDS driver LD1 When the input / output control signal is at the L level, the LVDS driver LD1 becomes inactive and the LVDS receiver LR1 becomes active. That is, the inter-substrate signal line side (LVDS driver LD1 and LVDS receiver LR1) of the inter-substrate signal sharing circuit SH1 is set to the input mode. Therefore, the differential signal (inter-board fail-safe signal) of the pair of inter-board signal lines is the L level (DISABLE (invalid)) of the pair of inter-substrate signal lines in the Type-2 specification of the M-LVDS type receiver. Is smaller than the threshold).
  • the LVDS driver LD1 becomes active and the LVDS receiver LR1 becomes inactive.
  • the inter-substrate signal line side of the inter-substrate signal sharing circuit SH1 is set to the output mode. Accordingly, the differential signal of the pair of inter-substrate signal lines is at the H level (the positive polarity potential of the pair of inter-substrate signal lines is higher than the negative polarity by a threshold value, for example, in FIG. (+ Polarity) is higher than the threshold of signal 2 (-polarity) by a threshold). At this time, the inter-board fail-safe signal is ENABLE (valid).
  • LVDS receiver LR1 in the input mode receives the inter-board fail-safe signal and outputs a signal corresponding to the inter-board fail-safe signal to the input / output switching unit IFS1. That is, when the inter-board failsafe signal is DISABLE (invalid) (L level), the LVDS receiver LR1 in the input mode outputs an L level signal to the input / output switching unit IFS1. When the inter-board fail safe signal is ENABLE (valid) (H level), the LVDS receiver LR1 in the input mode outputs an H level signal to the input / output switching unit IFS1.
  • the states of the inter-substrate signal sharing circuit SH1 and the inter-substrate signal sharing circuit SH2 when all the timing controllers TC1 to TC8 are in the normal state are as shown in the table of FIG.
  • both the intra-board fail safe signal and the inter-board fail safe signal are DISABLE (invalid).
  • the in-substrate signal line side port is set as an input port.
  • the input / output control signals output by the input / output switching units IFS1 and IFS2 are at the L level, and the inter-substrate signal line side (LVDS drivers LD1 and LD2 and LVDS receivers LR1 and LR2) is set to the input mode.
  • the timing controller TC1 When the timing controller TC1 is in an abnormal state, it is assumed that an abnormality occurs in the processing of the video processing circuit EP1, the video signal input to the timing controller TC1 is not appropriate, and the timing controller TC1 determines that it is in an abnormal state. At this time, the timing controller TC1 changes itself to the self-running mode. Further, the timing controller TC1 sets the in-board signal line port of the timing controller TC1 as an output port, and drives the in-board fail-safe signal to ENABLE (valid) (L level). When the timing controller TC2 detects that the in-board fail safe signal of the display control board DC1 is ENABLE (valid), it changes itself to the self-running mode.
  • the input / output switching unit IFS1 detects that the in-board failsafe signal is ENABLE (valid), it outputs an input / output control signal (H level) to the LVDS driver LD1 and the LVDS receiver LR1.
  • LVDS driver LD1 to which an input / output control signal of H level is input becomes active, and LVDS receiver LR1 becomes inactive. That is, the inter-substrate signal line side of the inter-substrate signal sharing circuit SH1 is set to the output mode.
  • the LVDS driver LD1 outputs an inter-board fail safe signal ENABLE (valid) (H level).
  • the LVDS receiver LR2 of the display control board DC2 in the input mode detects that the inter-board failsafe signal is ENABLE (valid), and outputs an H level signal to the input / output switching unit IFS2.
  • the input / output switching unit IFS2 to which the H level signal is input from the LVDS receiver LR2 sets the in-board signal line side port of the inter-board signal sharing circuit SH2 as an output port, and the in-board fail-safe signal of the display control board DC2 Is driven to ENABLE (valid) (L level).
  • timing controllers TC3 and TC4 detect that the in-board fail-safe signal of the display control board DC2 is ENABLE (valid), the timing controllers TC3 and TC4 change to the self-running mode.
  • timing controllers TC5 to TC8 are similarly changed to the self-running mode.
  • the states of the inter-substrate signal sharing circuit SH1 and the inter-substrate signal sharing circuit SH2 are as shown in the table of FIG.
  • both the intra-board fail safe signal and the inter-board fail safe signal are ENABLE (valid).
  • the intra-substrate signal line side port is set as an input port.
  • the in-substrate signal line side port is set as an output port.
  • the input / output control signal output by the input / output switching unit IFS1 is at the H level, and the inter-substrate signal line side (LVDS driver LD1 and LVDS receiver LR1) of the inter-substrate signal sharing circuit SH1 is set to the output mode.
  • the input / output control signal output by the input / output switching unit IFS2 is at the L level, and the inter-substrate signal line side (LVDS driver LD2 and LVDS receiver LR2) of the inter-substrate signal sharing circuit SH2 is set to the input mode.
  • timing controllers TC1 to TC8 are provided. Immediately transmitted to TC8. Therefore, all the timing controllers TC1 to TC8 are immediately changed to the free-running mode. For this reason, in the present embodiment, it is possible to prevent an inappropriate display in which the display of some partial display areas and the display of other partial display areas are not consistent. Further, since the scanning signal lines Ga to Gd and the storage capacitor lines (CS lines) CSa to CSd are not divided into the partial display areas AR1 to AR8, the timing controllers TC1 to TC8 are gated at different timings.
  • the liquid crystal panel LCP may be damaged.
  • the timing controllers TC1 to TC8 detect an abnormality, all the timing controllers TC1 to TC8 operate in the free-running mode. Therefore, damage to the liquid crystal panel LCP can be prevented.
  • Timing controller TC1 changes its own self-running mode to a normal operation mode when normal operation becomes possible and the abnormal state is resolved. Further, the timing controller TC1 sets the in-board signal line port of the timing controller TC1 as an input port, and sets the in-board failsafe signal to DISABLE (invalid) (H level). When the timing controller TC2 detects that the in-board fail-safe signal of the display control board DC1 is DISABLE (invalid), the timing controller TC2 changes its own self-running mode to the normal operation mode.
  • the input / output switching unit IFS1 outputs an input / output control signal (L level) to the LVDS driver LD1 and the LVDS receiver LR1 when detecting that the in-board failsafe signal of the display control board DC1 is DISABLE (invalid).
  • LVDS driver LD1 to which an L level input / output control signal is input becomes inactive, and LVDS receiver LR1 becomes active. That is, the inter-substrate signal line side of the inter-substrate signal sharing circuit SH1 is set to the input mode. As a result, the LVDS driver LD1 is deactivated, and the inter-board fail safe signal is switched to DISABLE (invalid) (L level).
  • the LVDS receiver LR2 of the display control board DC2 in the input mode detects that the inter-board failsafe signal has been switched to DISABLE (invalid), and outputs an L level signal to the input / output switching unit IFS2.
  • the input / output switching unit IFS2 to which the L level signal is input from the LVDS receiver LR2 sets the in-board signal line side port of the inter-board signal sharing circuit SH2 as an input port, and the in-board fail-safe signal of the display control board DC2 To DISABLE (invalid) (H level).
  • timing controllers TC3 and TC4 When the timing controllers TC3 and TC4 detect that the in-board fail-safe signal of the display control board DC2 is DISABLE (invalid), the timing controllers TC3 and TC4 change their own free-running mode to the normal operation mode. Similarly, the self-running modes of the timing controllers TC5 to TC8 of the other display control boards DC3 to DC4 are also released.
  • the self-running mode of all timing controllers TC1 to TC8 is canceled, and normal video display is performed.
  • the return from the self-running mode when the abnormal state is resolved is also quickly performed in all the timing controllers TC1 to TC8 in the same manner as when the abnormal state occurs. Therefore, the period in the self-running mode can be minimized.
  • timing controllers TC1 and TC3 are in an abnormal state
  • a case where an abnormal state has occurred in the timing controller TC3 mounted on a different display control board DC2 from the state shown in FIG. 5 where the abnormal state has occurred in the timing controller TC1 will be described below. This is also the case when the abnormal state is detected almost simultaneously (TC1 is slightly faster) in the timing controllers TC1 and TC3.
  • the timing controller TC3 is in the free-running mode.
  • the timing controller TC3 changes the in-board signal line port of the timing controller TC3 from the input port to the output port, and displays
  • the in-board fail-safe signal of the control board DC2 is driven to ENABLE (valid) (L level). Since the input / output switching unit IFS2 originally drives the in-board fail-safe signal of the display control board DC2 to ENABLE (valid) (L level), there is no change in the in-board fail-safe signal.
  • the in-board signal lines are wired or connected, there is no problem even if any of the timing controller and the display control board individually outputs L level.
  • the timing controller nor the display control board outputs an L level signal to the in-board signal line, the in-board signal line is pulled up by the resistor and thus becomes the H level.
  • the input / output switching unit IFS2 has already set the in-board signal line side of the inter-board signal sharing circuit SH2 as an output port due to the abnormal state of the timing controller TC1. Therefore, the state does not change any more.
  • the timing controller TC3 of the display control board DC2 different from the timing controller TC1 of the display control board DC1 becomes in an abnormal state completely simultaneously, for example, the LVDS drivers LD1 and LD2 of both display control boards DC1 and DC2
  • the inter-board fail-safe signal ENABLE (valid) (H level) may be output.
  • the timing controllers TC1 to TC8 of all the display control boards DC1 to DC4 are in the free-running mode.
  • the inter-board signal line that transmits inter-board fail-safe signals is also wired-or-connected for differential signal characteristics (that is, using the Type-2 specification (with fail-safe function) of the M-LVDS type receiver). Therefore, there is no problem even if there is the same level output from both ends.
  • timing controllers TC1 and TC3 are both in the free-running mode.
  • Timing controller TC1 changes its own self-running mode to a normal operation mode once normal operation becomes possible and the abnormal state is resolved. Further, the timing controller TC1 sets the in-board signal line port of the timing controller TC1 as an input port, and sets the in-board failsafe signal to DISABLE (invalid) (H level). When the timing controller TC2 detects that the in-board fail-safe signal of the display control board DC1 is DISABLE (invalid), the timing controller TC2 changes its own self-running mode to the normal operation mode.
  • the input / output switching unit IFS1 outputs an input / output control signal (L level) to the LVDS driver LD1 and the LVDS receiver LR1 when detecting that the in-board failsafe signal of the display control board DC1 is DISABLE (invalid).
  • LVDS driver LD1 to which an L level input / output control signal is input becomes inactive, and LVDS receiver LR1 becomes active. That is, the inter-substrate signal line side of the inter-substrate signal sharing circuit SH1 is set to the input mode. As a result, the LVDS driver LD1 is deactivated, and the inter-board fail safe signal is switched to DISABLE (invalid) (L level).
  • the LVDS receiver LR2 of the display control board DC2 in the input mode detects that the inter-board failsafe signal has been switched to DISABLE (invalid), and outputs an L level signal to the input / output switching unit IFS2.
  • the input / output switching unit IFS2 to which the L level signal is input from the LVDS receiver LR2 sets the in-board signal line side port of the inter-board signal sharing circuit SH2 as an input port.
  • the in-board fail safe signal of the inter-board signal sharing circuit SH2 is driven to ENABLE (valid) (L level) by the timing controller TC3 in an abnormal state. Therefore, the input / output switching unit IFS2 detects that the in-board fail-safe signal of the inter-board signal sharing circuit SH2 is ENABLE (valid), and sends an input / output control signal (H level) to the LVDS driver LD2 and the LVDS receiver LR2. Is output.
  • LVDS driver LD2 to which an H level input / output control signal is input becomes active, and LVDS receiver LR2 becomes inactive. That is, the inter-substrate signal line side of the inter-substrate signal sharing circuit SH2 is set to the output mode.
  • the LVDS driver LD2 outputs an inter-board fail safe signal ENABLE (valid) (H level).
  • the LVDS receiver LR1 of the display control board DC1 that has been in the input mode detects that the inter-board failsafe signal is ENABLE (valid), and outputs an H level signal to the input / output switching unit IFS1.
  • the input / output switching unit IFS1 to which the H level signal is input from the LVDS receiver LR1 sets the in-board signal line side port of the inter-board signal sharing circuit SH1 as an output port, and the in-board fail-safe signal of the display control board DC1 Is driven to ENABLE (valid) (L level).
  • the timing controllers TC1 and TC2 When the timing controllers TC1 and TC2 detect that the in-board fail-safe signal of the display control board DC1 is ENABLE (valid), the timing controllers TC1 and TC2 change to the self-running mode. As described above, the timing controllers TC1 and TC2 receive the inter-board fail-safe signal ENABLE (valid) from the display control board DC2 in which the abnormal state continues even if the free-running mode is once canceled, and immediately enter the free-running mode. Return.
  • timing controllers TC5 to TC8 are similarly maintained in the self-running mode.
  • the states of the inter-substrate signal sharing circuit SH1 and the inter-substrate signal sharing circuit SH2 are as shown in the table of FIG.
  • the normal state is the same as when the abnormal state occurs only in the timing controller TC3.
  • the input / output switching units IFS1 to IFS4 transmit and receive the inter-board failsafe signal (LVDS drivers LD1 to LD4) according to the in-board failsafe signal indicating an abnormality in the board. And the input mode / output mode of the LVDS receivers LR1 to LR4) are switched. Therefore, the fail-safe signal can be quickly transmitted and received in both directions between the substrates and within the substrate. Therefore, if any of the timing controllers is in an abnormal state, all the timing controllers TC1 to TC8 are quickly controlled to perform self-running control.
  • timing controllers TC1 to TC8 are controlled to perform self-running control, and immediately after the abnormal state of all the timing controllers TC1 to TC8 is resolved, It is possible to cancel the self-running mode and perform normal video display.
  • the configuration in which the inter-board fail-safe signal is transmitted using the differential signal has been described.
  • the inter-board signal sharing circuit of different display control boards is connected by a single-end inter-board signal line.
  • An inter-fail safe signal may be transmitted.
  • the inter-substrate signal line is wired or connected in the same manner as the in-substrate signal line.
  • two timing controllers mounted on different display control boards can be directly connected by a single-ended signal line wired or connected to transmit a fail-safe signal in both directions. In this case, there is no need to switch the input / output mode, and the configuration is simplified.
  • liquid crystal display device was demonstrated above, this invention is applicable not only to this but a plasma panel display or an organic electroluminescent display.
  • FIG. 8 is a block diagram showing a detailed configuration of the display control board of the present embodiment.
  • FIG. 8 only the configuration of the four display control boards DC1 to DC4 is shown, and the other constituent members are not shown.
  • illustration of outputs from the timing controllers TC1 to TC8 to the outside of each display control board is omitted.
  • the display control board DC1 includes two video processing circuits EP1 and EP2, two timing controllers TC1 and TC2, and one inter-board signal sharing circuit SHA1.
  • the display control board DC2 includes two video processing circuits EP3 and EP4, two timing controllers TC3 and TC4, and one inter-substrate signal sharing circuit SHA2.
  • the display control board DC3 includes two video processing circuits EP5 and EP6, two timing controllers TC5 and TC6, and one inter-board signal sharing circuit SHA3.
  • the display control board DC4 includes two video processing circuits EP7 and EP8, two timing controllers TC7 and TC8, and one inter-substrate signal sharing circuit SHA4. Since the display control boards DC1 to DC4 are arranged close to the positions of the corresponding partial display areas AR1 to AR8 and the corresponding source driver chip J, they are separated from each other.
  • the inter-substrate signal sharing circuit SHA1 and the inter-substrate signal sharing circuit SHA2 are connected by a pair of inter-substrate signal lines for transmitting a differential signal from the inter-substrate signal sharing circuit SHA1 to the inter-substrate signal sharing circuit SHA2. (In FIG. 8, a single line is omitted).
  • the inter-substrate signal sharing circuit SHA2 and the inter-substrate signal sharing circuit SHA4 are connected by a pair of inter-substrate signal lines for transmitting a differential signal from the inter-substrate signal sharing circuit SHA2 to the inter-substrate signal sharing circuit SHA4. .
  • the inter-substrate signal sharing circuit SHA4 and the inter-substrate signal sharing circuit SHA3 are connected by a pair of inter-substrate signal lines for transmitting a differential signal from the inter-substrate signal sharing circuit SHA4 to the inter-substrate signal sharing circuit SHA3.
  • the inter-substrate signal sharing circuit SHA3 and the inter-substrate signal sharing circuit SHA1 are connected by a pair of inter-substrate signal lines for transmitting a differential signal from the inter-substrate signal sharing circuit SHA3 to the inter-substrate signal sharing circuit SHA1. .
  • These inter-substrate signal lines transmit signals only in one direction. It can be said that these inter-substrate signal lines are included in inter-substrate connection portions that connect the inter-substrate signal sharing circuits SHA1 to SHA4.
  • the timing controller TC1, the timing controller TC2, and the inter-board signal sharing circuit SHA1 mounted on the same display control board DC1 are connected by wired-or connection using a single-end in-board signal line.
  • the timing controller TC1, the timing controller TC2, and the inter-substrate signal sharing circuit SHA1 transmit and receive an in-board fail-safe signal via the in-board signal line.
  • the in-board fail-safe signal is DISABLE (invalid), that is, the voltage of the in-board signal line is maintained at the H level.
  • timing controllers TC1 and TC2 The operation of the timing controllers TC1 and TC2 is the same as that of the first embodiment.
  • the inter-board fail safe signal is DISABLE (invalid) (H level)
  • the inter-board fail safe signal from the inter-board signal sharing circuit SHA3 is DISABLE (invalid) (L level).
  • the inter-board signal sharing circuit SHA1 sets the inter-board fail safe signal to the inter-board signal sharing circuit SHA2 to DISABLE (invalid) (L level).
  • the inter-board signal sharing circuit SHA1 detects that the in-board fail-safe signal is ENABLE (valid) (L level)
  • the inter-board signal sharing circuit SHA1 detects the LVDS driver connected to one end of the inter-board signal line (
  • the inter-board fail-safe signal ENABLE (valid) (H level) is output to the inter-board signal sharing circuit SHA2 by an unshown).
  • the inter-substrate signal sharing circuit SHA1 detects that the inter-substrate fail-safe signal from the inter-substrate signal sharing circuit SHA3 is ENABLE (H level)
  • the inter-substrate signal sharing circuit SHA1 The inter-board fail safe signal ENABLE (valid) is output to the shared circuit SHA2, and the in-board signal line side port is set as an output port, and the intra-board fail safe signal ENABLE (valid) (L level) is sent to the timing controllers TC1 and TC2. ) Is output.
  • the inter-board signal sharing circuits SHA1 to SHA4 receive the inter-board fail-safe signal ENABLE (valid) from the other inter-board signal sharing circuits, the next inter-board signal sharing is connected in a ring shape by the inter-board signal line. Since the inter-board fail-safe signal ENABLE (valid) is output to the circuit, the abnormal state generated in any one of the display control boards DC1 to DC4 can be transmitted to all the display control boards DC1 to DC4. Therefore, all the timing controllers TC1 to TC8 are in the free-running mode.
  • any of the inter-substrate signal sharing circuits SHA1 to SHA4 makes the inter-board fail safe signal DISABLE (invalid) every predetermined period.
  • Each inter-board signal sharing circuit SHA1 to SHA4 sets the in-board signal line side port as an input port if the inter-board fail safe signal from the other inter-board signal sharing circuit is DISABLE (invalid), and the in-board fail Set the safe signal to DISABLE.
  • the inter-board signal sharing circuit of different display control boards is single-ended.
  • the board-to-board signal line may be connected to transmit a board-to-board fail-safe signal.
  • the inter-board fail-safe signal is also ENABLE (effective) when the L-level signal is also at the L level, the inter-board signal sharing circuit ANDs the input intra-board fail-safe signal and the input inter-board fail-safe signal. The above result may be output as an inter-board fail-safe signal.
  • FIG. 9 is a block diagram showing a detailed configuration of the display control board of the present embodiment.
  • FIG. 9 only the configuration of the four display control boards DC1 to DC4 is shown, and the other components are not shown.
  • illustration of outputs from the timing controllers TC1 to TC8 to the outside of each display control board is omitted.
  • the display control board DC1 includes two video processing circuits EP1 and EP2, two timing controllers TC1 and TC2, and one inter-board signal sharing circuit SHB1.
  • the display control board DC2 includes two video processing circuits EP3 and EP4, two timing controllers TC3 and TC4, and one inter-board signal sharing circuit SHB2.
  • the display control board DC3 includes two video processing circuits EP5 and EP6, two timing controllers TC5 and TC6, and one inter-board signal sharing circuit SHB3.
  • the display control board DC4 includes two video processing circuits EP7 and EP8, two timing controllers TC7 and TC8, and one inter-board signal sharing circuit SHB4. Since the display control boards DC1 to DC4 are arranged close to the positions of the corresponding partial display areas AR1 to AR8 and the corresponding source driver chip J, they are separated from each other.
  • a signal distribution unit (inter-substrate connection unit) CF is provided between the display control substrates DC1 to DC4.
  • the inter-substrate signal sharing circuits SHB1 to SHB4 and the signal distribution unit CF are a pair for transmitting differential signals (inter-board fail-safe signals) from the inter-substrate signal sharing circuits SHB1 to SHB4 to the signal distribution unit CF.
  • the inter-substrate signal line is connected to the inter-substrate signal sharing circuits SHB1 to SHB4 from the signal distribution unit CF by a pair of inter-substrate signal lines for transmitting a differential signal (inter-board fail-safe signal) ( In FIG. 9, each line is omitted by a single line). These inter-substrate signal lines transmit signals only in one direction.
  • the signal distribution unit CF may be mounted on any one of the display control boards DC1 to DC4.
  • the timing controller TC1, timing controller TC2, and inter-board signal sharing circuit SHB1 mounted on the same display control board DC1 are connected by wired-or connection using a single-end in-board signal line.
  • the timing controller TC1, the timing controller TC2, and the inter-substrate signal sharing circuit SHB1 transmit and receive an in-board fail-safe signal through the in-board signal line.
  • the in-board fail-safe signal is DISABLE (invalid), that is, the voltage of the in-board signal line is maintained at the H level.
  • timing controllers TC1 and TC2 The operation of the timing controllers TC1 and TC2 is the same as that of the first embodiment.
  • the inter-board signal sharing circuit SHB1 when the in-board fail safe signal is DISABLE (invalid) (H level), the inter-board signal sharing circuit SHB1 outputs the inter-board fail safe signal to the signal distribution unit CF. (L level).
  • the inter-board signal sharing circuit SHB1 when the in-board fail-safe signal is ENABLE (valid) (L level), the inter-board signal sharing circuit SHB1 is connected to one end of the inter-board signal line (not shown). ), The inter-board fail-safe signal ENABLE (effective) (H level) is output to the signal distribution unit CF.
  • the inter-board signal sharing circuit SHB1 detects that the inter-board fail safe signal from the signal distribution unit CF is ENABLE (valid) (H level)
  • the inter-substrate signal sharing circuit SHB1 The port is set as an output port, and the in-board fail-safe signal ENABLE (valid) (L level) is output to the timing controllers TC1 and TC2.
  • the signal distribution unit CF monitors the ENABLE (valid) / DISABLE (invalid) of the inter-board fail-safe signals from the inter-board signal sharing circuits SHB1 to SHB4. When the inter-board fail sharing signals from all the inter-board signal sharing circuits SHB1 to SHB4 are DISABLE (invalid), the signal distribution unit CF outputs the inter-board fail safe signals to the inter-board signal sharing circuits SHB1 to SHB4. (To disable.
  • the signal distribution unit CF detects that the inter-board fail-safe signal from one inter-board signal sharing circuit SHB1 is ENABLE (valid) (H level), for example, the other inter-substrate signal sharing circuits SHB2 to The inter-board fail safe signal ENABLE (valid) (H level) is output to SHB4. At this time, the signal distribution unit CF makes the inter-board fail safe signal DISABLE (invalid) for the inter-board signal sharing circuit SHB1 outputting the inter-board fail safe signal ENABLE (valid) to the signal distribution unit CF.
  • the display control board that outputs the inter-board fail-safe signal ENABLE (valid) to the signal distribution unit CF
  • one of the timing controllers is in an abnormal state, and the in-board fail-safe signal is already ENABLE (valid). This is because the timing controller has shifted to the self-running mode.
  • the inter-board fail-safe signal ENABLE (valid) is input to the signal distribution unit CF from a plurality of inter-board signal sharing circuits, the signal distribution unit CF is inter-substrate only for the other inter-board signal sharing circuits. Outputs a fail-safe signal ENABLE (valid).
  • the in-board fail-safe signal becomes DISABLE (invalid)
  • the corresponding inter-board signal sharing circuit of the display control board becomes the inter-board fail safe to the signal distribution unit CF.
  • the signal distribution unit CF outputs inter-board fail-safe signals to be output to the inter-board signal sharing circuits SHB1 to SHB4 to DISABLE ( To disable.
  • each inter-board signal sharing circuit and the signal distribution unit are configured as a single unit.
  • the board-to-board signal line may be connected to transmit a board-to-board fail-safe signal.
  • the signal distribution unit obtains the AND result of a plurality of inter-board fail-safe signals input from the inter-board signal sharing circuit.
  • the signal may be output as an inter-board fail-safe signal to each inter-board signal sharing circuit.
  • the signal distribution unit when an abnormal state has occurred in any of the display control boards, the signal distribution unit outputs the inter-board fail safe signal ENABLE (valid) to all the inter-board signal sharing circuits. Therefore, in order to return from the self-running mode, the signal distribution unit may once disable DISABLE (interval) the inter-board fail-safe signals to all the inter-board signal sharing circuits every predetermined period. As a result, if all timing controllers are recovered from the abnormal state, all inter-board fail-safe signals and in-board fail-safe signals become DISABLE (invalid), and all timing controllers operate normally from the free-running mode. Return to mode.
  • a display device includes a display portion including a first region and a second region, a first substrate provided with a first timing controller that performs display control of the first region, and the second region.
  • a second substrate provided with a second timing controller for performing display control, and an inter-substrate connecting portion for connecting the first substrate and the second substrate, wherein the first timing controller includes the first region.
  • the 1st timing controller and the 2nd timing controller can perform suitable treatment (for example, self-running control) to the above-mentioned abnormality.
  • the second timing controller transmits a fail-safe signal to the inter-board connection portion, and the first timing controller indicates that the abnormality has occurred. It may be configured to communicate to.
  • the first timing controller sets the display control of the first area to the fail-safe mode, and the abnormality occurs in the first timing controller.
  • the second timing controller may be configured to set the display control of the second area to the fail-safe mode.
  • the display device is mounted on the first substrate, and is mounted on the first substrate, the first interface unit connected to the first timing controller and the inter-substrate connection unit, and the second timing controller and A second interface unit connected to the inter-board connection unit, and when the first interface unit receives an in-board fail-safe signal from the first timing controller, the differential signal is transmitted via the inter-board connection unit.
  • the inter-board fail-safe signal is transmitted from the second interface unit to the second interface unit via the inter-board connection unit, the inter-board fail-safe signal is transmitted to the first timing controller.
  • An internal fail-safe signal is transmitted, and the second interface unit is When the in-board fail-safe signal is received from the second timing controller, the inter-board fail-safe signal is transmitted to the first interface unit using the differential signal via the inter-board connection unit, and the inter-board connection is performed. When the inter-board fail-safe signal is received from the first interface unit via the unit, the intra-board fail-safe signal may be transmitted to the second timing controller.
  • the first interface unit has a first differential signal transmission / reception having an output mode for outputting an inter-board fail-safe signal to the inter-board connection unit and an input mode for monitoring the inter-board fail-safe signal of the inter-board connection unit. And a first input / output switching unit that switches the output mode and the input mode of the first differential signal transmitting / receiving unit, and the second interface unit outputs an inter-board fail-safe signal to the inter-board connecting unit. And a second differential signal transmitting / receiving unit having an input mode for monitoring an inter-board fail-safe signal of the inter-board connection unit, and a second switching between the output mode and the input mode of the second differential signal transmitting / receiving unit.
  • An input / output switching unit wherein the first input / output switching unit is configured such that the first differential signal transmitting / receiving unit transmits the second differential signal via the inter-substrate connection unit.
  • the in-board fail-safe signal is transmitted to the first timing controller, and when the in-board fail-safe signal is received from the first timing controller, the first differential signal is transmitted.
  • the transmission / reception unit is switched from the input mode to the output mode, and the second input / output switching unit is configured such that the second differential signal transmission / reception unit fails from the first differential signal transmission / reception unit via the inter-board connection unit.
  • the in-board fail-safe signal is transmitted to the second timing controller, and when the in-board fail-safe signal is received from the second timing controller, the second differential signal transmitting / receiving unit is set to the input mode. May be configured to switch to the output mode.
  • the first input / output switching unit includes a first differential signal output unit and a first differential signal input unit that are multi-point connected, and the first input / output switching unit is configured to perform the above operation according to an in-board fail-safe signal from the first timing controller. Which one of the first differential signal output unit and the first differential signal input unit is activated is switched, and the second input / output switching unit includes a second differential signal output unit and a second multipoint-connected second differential signal output unit.
  • the display device includes three or more substrates including the first substrate and the second substrate, and three or more timings including the first timing controller and the second timing controller mounted on each substrate.
  • the inter-substrate connection portion connects the three or more interface portions in a ring shape, and each interface portion is connected to the substrate from another interface portion via the inter-substrate connection portion.
  • inter-board fail-safe signal When transmitting an inter-board fail-safe signal to another interface unit via the inter-board connection unit, and receiving an in-board fail-safe signal from the timing controller of the mounted board, The inter-board fail-safe signal is transmitted to the further interface unit via the inter-board connection unit, and each timing controller is configured to display the board when an abnormality occurs in display control of the corresponding area.
  • the configuration may be such that a fail safe signal is transmitted to the inter-connection portion, and the fact that the abnormality has occurred is transmitted to the other timing controllers.
  • the display device includes three or more substrates including the first substrate and the second substrate, and three or more timings including the first timing controller and the second timing controller mounted on each substrate.
  • Each interface unit includes a signal distribution unit, and when each interface unit receives the in-board fail-safe signal from the timing controller of the mounted board, the inter-board fail-safe signal is transmitted to the signal distribution unit, and the signal distribution When the board-to-board fail-safe signal is received from the When the inter-board fail-safe signal is received from at least one of the plurality of interface units, the signal distribution unit transmits the inter-board fail-safe signal to the operating controller.
  • An inter-board fail-safe signal may be transmitted to the other interface unit that is not.
  • the signal distribution unit may transmit the inter-board fail-safe signal to all the interface units when receiving the inter-board fail-safe signal from at least one of the plurality of interface units.
  • inter-board fail safe signal may be a differential signal.
  • timing controller and the interface unit mounted on the same board are connected to each other by a single-ended signal line that is wired or connected, and can transmit and receive an in-board fail-safe signal bidirectionally. It may be a configuration.
  • the present invention can be used for a large screen display type display device.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

Un dispositif d'affichage à cristaux liquides dans un mode de réalisation de la présente invention est pourvu des éléments suivants : une unité d'affichage ; une carte de commande d'affichage (DC1) sur laquelle un contrôleur de synchronisation (TC1) qui commande l'affichage d'une région d'affichage partielle (AR1) est prévu ; une carte de commande d'affichage (DC2) sur laquelle un contrôleur de synchronisation (TC3) qui commande l'affichage d'une autre région d'affichage partielle (AR3) est prévu ; et une unité de connexion entre cartes qui connecte lesdites cartes de commande d'affichage (DC1 et DC2). Si une anomalie est apparue dans la commande d'affichage de la première région d'affichage partielle (AR1), ce contrôleur de synchronisation (TC1) envoie à l'unité de connexion entre cartes un signal à sécurité intégrée.
PCT/JP2012/062432 2011-05-18 2012-05-15 Dispositif d'affichage WO2012157649A1 (fr)

Applications Claiming Priority (2)

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JP2011111910 2011-05-18
JP2011-111910 2011-05-18

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WO2012157649A1 true WO2012157649A1 (fr) 2012-11-22

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016190010A1 (fr) * 2015-05-28 2016-12-01 シャープ株式会社 Dispositif d'affichage et procédé de commande de dispositif d'affichage
WO2017002569A1 (fr) * 2015-06-30 2017-01-05 シャープ株式会社 Dispositif d'affichage à cristaux liquides
WO2019186746A1 (fr) * 2018-03-28 2019-10-03 三菱電機株式会社 Système d'affichage à del, dispositif de commande d'affichage à del, et dispositif d'affichage à del
JP2020016794A (ja) * 2018-07-26 2020-01-30 Ｔｉａｎｍａ Ｊａｐａｎ株式会社 表示装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006243565A (ja) * 2005-03-04 2006-09-14 Nec Lcd Technologies Ltd 表示パネルの駆動方法及びその装置
JP2009008891A (ja) * 2007-06-28 2009-01-15 Semiconductor Energy Lab Co Ltd 表示装置及び電子機器
JP2009145485A (ja) * 2007-12-12 2009-07-02 Oki Semiconductor Co Ltd 液晶パネル駆動装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006243565A (ja) * 2005-03-04 2006-09-14 Nec Lcd Technologies Ltd 表示パネルの駆動方法及びその装置
JP2009008891A (ja) * 2007-06-28 2009-01-15 Semiconductor Energy Lab Co Ltd 表示装置及び電子機器
JP2009145485A (ja) * 2007-12-12 2009-07-02 Oki Semiconductor Co Ltd 液晶パネル駆動装置

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016190010A1 (fr) * 2015-05-28 2016-12-01 シャープ株式会社 Dispositif d'affichage et procédé de commande de dispositif d'affichage
WO2017002569A1 (fr) * 2015-06-30 2017-01-05 シャープ株式会社 Dispositif d'affichage à cristaux liquides
CN107710321A (zh) * 2015-06-30 2018-02-16 夏普株式会社 液晶显示装置
US20180182313A1 (en) * 2015-06-30 2018-06-28 Sharp Kabushiki Kaisha Liquid crystal display device
US10685609B2 (en) 2015-06-30 2020-06-16 Sharp Kabushiki Kaisha Liquid crystal display device
WO2019186746A1 (fr) * 2018-03-28 2019-10-03 三菱電機株式会社 Système d'affichage à del, dispositif de commande d'affichage à del, et dispositif d'affichage à del
JP2020016794A (ja) * 2018-07-26 2020-01-30 Ｔｉａｎｍａ Ｊａｐａｎ株式会社 表示装置
JP7168368B2 (ja) 2018-07-26 2022-11-09 Ｔｉａｎｍａ Ｊａｐａｎ株式会社 表示装置

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