WO2012155426A1

WO2012155426A1 - Method and system for interleaving address parallel calculation

Info

Publication number: WO2012155426A1
Application number: PCT/CN2011/079999
Authority: WO
Inventors: 张彩虹; 陈月强; 吴枫
Original assignee: 中兴通讯股份有限公司
Priority date: 2011-05-16
Filing date: 2011-09-22
Publication date: 2012-11-22
Also published as: CN102324999B; CN102324999A

Abstract

Disclosed are a method and a system for interleaving address parallel calculation. The method comprises: pre-configuring and storing an interleaving address compression table; receiving to-be-decoded data, and judging decoding parallelism degree; reading the interleaving address compression table to acquire value and interleaving calculation intermediate value based on the packet length of the to-be-decoded data; generating an interleaving address and a reading address based on the decoding parallelism degree, the packet length of the to-be-decoded data, the value, and the interleaving calculation intermediate value, and reading the to-be-decoded data to accomplish interleaving operation based on the reading address. According to the technical scheme of the invention, the interleaving address parallel calculation in a decoder of a WiMAX system can be realized.

Description

Parallel computing method and system for interleaving address

The present invention relates to a Worldwide Interoperability for Microwave Access (WiMAX) system in the field of communications, and more particularly to a parallel computing method and system for interleaving addresses. Background technique

In order to resist the burst error in the transmission process, the interleaving technique is adopted in the encoder in the WiMAX system, and the decoding of the interleaving address/deinterleaving address is required when the receiving end performs decoding. Since the calculation of the interlaced address is complicated, in order to achieve a higher decoding throughput, the decoding is performed in parallel in the decoding process. The use of parallel decoding refers to the segmentation mode for storage, that is, the data sequence is equally divided into K segments (K is the decoding parallelism), and is stored in the K slice data buffer, which is in turn with the data in the encoding. The slice data buffer is stored in different ways. Therefore, the inner interleaving algorithm for parallel decoding is different from the inner interleaving algorithm for parallel encoding. In order to achieve row decoding, the decoding interleaver requires the inner interleaver to perform parallel interleaving calculation consistent with the decoding parallelism in real time, or store the interleaving address of the code block in advance, and read the stored interleaving address during decoding to obtain interleaving. Address, complete data interleaving, and decode.

Since the WiMAX system supports up to 17 types of packet lengths and the maximum packet length is 2400 bit pairs, if all the interleaved addresses are stored, 100Kbits of storage space is required, so the storage resources are relatively large, and it is also necessary to search according to the packet length. Different tables, the implementation method is more complicated. Summary of the invention

In view of this, the main object of the present invention is to provide a parallel computing method and system for interleaving addresses, which can realize parallel computing of interleaved addresses in a decoder in a WiMAX system. In order to achieve the above object, the technical solution of the present invention is achieved as follows:

The present invention provides a parallel computing system for interleaving addresses, including: an interleaving address buffer unit, a pre-processing buffer unit, and a control unit;

An interleave address buffer unit, configured to pre-configure and store an interleave address compression table;

Treatment before the cache unit for receiving data to be decoded, and decoding determines parallelism; and The length of the packet data to be decoded, read compressed interleaving address table, and acquires P _Q value interleaving calculates an intermediate value;

a control unit, configured to generate an interleave address and a read address according to the decoding parallelism, the length of the data packet of the data to be decoded, the P ₀ value, and the intermediate value of the interleaving calculation, and read the data to be decoded according to the read address, and complete the interleaving operation .

The present invention also provides a parallel computing method for interleaving addresses, including:

Pre-configuring and storing an interleave address compression table;

Receiving data to be decoded, and determining decoding parallelism;

The interleave address compression table is read according to the length of the data packet of the data to be decoded, and P is obtained. Value and interleaving calculate the intermediate value;

According to the degree of parallelism of decoding, the length of the data packet to be decoded, and P. The value and the interleave calculation intermediate value generate an interleave address and a read address, and read the data to be decoded according to the read address to complete the interleaving operation.

In the above method, the determining the decoding parallelism is:

According to the length N of the data packet of the data to be decoded, the decoding parallel degree K is judged, when 24 < N < 180, K = l; when 192 < Ν < 240, Κ = 2; when 480 < Ν < 2400 , Κ=4.

In the above method, the interleaving address and the read address are generated according to the decoding parallel degree, the length of the data packet of the data to be decoded, the Ρ ₀ value, and the intermediate value of the interleaving calculation:

Α Calculate the number of data to be decoded cached in each data buffer in the buffer unit before processing

Δ ;

Β, according to the degree of parallelism of decoding ^ the number of data to be decoded cached in each data buffer Δ And interleaving the calculation base address to generate K interleave addresses;

C. Mapping the generated K interleave addresses to corresponding data buffer numbers;

D. Generate a read address of the K data to be decoded in the respective data buffer, and the value of the read address is a minimum value among the K interleave addresses.

In the above method, the reading the data to be decoded according to the read address is:

E. Read data from the corresponding data buffer in the buffer unit before processing according to the generated K read addresses, and input the read K data to be decoded into the parallel decoder for decoding.

In the above method, the method further includes:

F, buffering the first interleave address of the K interleave addresses to the pre-processing buffer unit, denoted as temp;

G, selecting an accumulated value W required to calculate the next round of interleaving address calculation;

H. Calculate and update the base address of the next round of interleave address calculation according to the tem value and the accumulated value W; determine the size of the index value i and the number of data to be decoded cached in each data buffer, if less than, execute Step A, until the index value i is equal to the number of data to be decoded buffered in each data buffer.

In the above method, the step B is:

When K = l, interleaving address base address for the interleave calculation; when Κ = 2, base address 1 and calculated according to the interleaving P _Q recursive generating two interleaved addresses; when K = 4, in accordance with the calculated base interleaver Address 1 and P _{Q are} recursively generated into 4 interleaved addresses.

In the above method, the base address and P calculated according to the interleaving. Recursively generate K interleaved addresses as:

Among the K interleave addresses, the modulo processing is performed according to the length N of the data packet of the base address to be decoded, to obtain the first interleave address inter_addr0; P. Multiplying the number Δ of the data to be decoded buffered in each data buffer, and adding the product to the K-1 way interleave address inter_addrK-2, the length N of the data packet to be decoded according to the base address Adding results to the modulo To get the first interleaved address inter_addrK-1.

In the above method, the step C is:

When K=l, the data buffer number is 0; when Κ=2, the data buffer number is 0 and 1; when Κ=4, the data buffer number is 0, 1, 2, 3.

The parallel computing method and system for interleaving addresses provided by the present invention pre-configures and stores an interleave address compression table; receives data to be decoded, and determines decoding parallelism; and reads an interleave address according to the length of the data packet of the data to be decoded Compress the table and get Ρ. The value and interleaving calculate the intermediate value; according to the degree of parallelism of the decoding, the length of the data packet of the data to be decoded, Ρ. The intermediate value of the value and the interleaving calculation generates an interleave address and a read address, and reads the data to be decoded according to the read address to complete the interleaving operation, thereby enabling parallel calculation of the interleave address in the decoder in the WiMAX system; and, due to the use of the buffer interleaving The address compression table can reduce the consumption of storage resources. In addition, using the method proposed in the present invention can reduce the difficulty of parallel computing of interleaving addresses in the decoder in the WiMAX system, and has a very low implementation cost for the WiMAX system. Great meaning. DRAWINGS

1 is a schematic structural diagram of a parallel computing system for implementing an interleaved address according to the present invention;

2 is a schematic flow chart of a parallel computing method for implementing an interleaved address according to the present invention;

3 is a schematic flow chart of a method for implementing step 204 of FIG. 2 according to the present invention;

4 is a schematic diagram of recursively generating an interleave address in the present invention;

FIG. 5 is a schematic flowchart of Embodiment 1 of a parallel computing method for implementing an interleaved address according to the present invention; FIG. 6 is a schematic diagram of buffering data to be decoded in a data buffer of a pre-processing buffer unit. detailed description

The basic idea of the present invention is: pre-configure and store the interleave address compression table; receive the data to be decoded, and determine the degree of parallelism of decoding; and read the interleave address compression table according to the length of the data packet to be decoded, and obtain P. Value and interleaving calculation intermediate value; according to decoding parallelism, data to be decoded The length of the packet, P. The value and the interleave calculation intermediate value generate an interleave address and a read address, and read the data to be decoded according to the read address to complete the interleaving operation.

The invention will be further described in detail below with reference to the drawings and specific embodiments.

The present invention provides a parallel computing system for interleaving addresses. FIG. 1 is a schematic structural diagram of a parallel computing system for implementing an interleaved address according to the present invention. As shown in FIG. 1, the system includes: an interleaving address buffer unit 11, a pre-processing buffer unit 12, Control unit 13; wherein

The interleave address buffer unit 11 is configured to pre-configure and store an interleave address compression table; the pre-processing buffer unit 12 is configured to receive data to be decoded, and determine a decoding parallel degree; and according to the length of the data packet of the data to be decoded, Read the interleave address compression table and get P. Value and interleaving calculate the intermediate value;

The control unit 13 is configured to generate an interleave address and a read address according to the decoding parallelism, the length of the data packet of the data to be decoded, the P ₀ value, and the intermediate value of the interleaving calculation, and read the data to be decoded according to the read address to complete the interleaving. operating.

Based on the above system, the present invention further provides a parallel computing method for interleaving addresses. FIG. 2 is a schematic flowchart of a parallel computing method for implementing an interleaving address according to the present invention. As shown in FIG. 2, the method includes the following steps:

Step 201: Pre-configure and store an interleave address compression table.

Specifically, the interleave address buffer unit pre-configures the interleave address compression table, as shown in Table 1, the interleave address compression table is used to store the packet length and P of the data to be decoded. Correspondence between T ₀ , T Τ ₂ , and ; ₃ ; where, Τ. , Τ\, Τ ₂ , Τ ₃ are intermediate values of the interleaved address; and the interleave address compression table is stored in the interleave address buffer unit.

96 7 7 31 7 79

108 11 11 67 11 63

120 13 13 13 13 13

144 17 19 87 19 87

180 11 11 11 11 11

192 11 11 59 11 155

216 13 13 13 13 13

240 13 13 73 13 193

480 53 355 243 283 291

960 43 587 759 87 659

1440 43 43 403 943 223

1920 31 999 1007 983 975

2400 53 1319 1211 1231 1251 Table 1

Step 202: Receive data to be decoded, and determine a degree of parallelism of decoding;

Specifically, the pre-processing buffer unit receives the input data to be decoded, and buffers the data to be decoded. According to the length N of the data packet to be decoded, the pre-processing buffer unit determines the decoding parallel degree K. In the present invention, K The value is 1, 2 or 4, that is, when 24 < N < 180, K = l; when 192 < Ν < 240, Κ = 2; when 480 < Ν < 2400, Κ = 4.

Step 203: Read the interleave address compression table according to the length of the data packet of the data to be decoded, and obtain Ρ. Value and interleaving calculate the intermediate value;

Specifically, the pre-processing buffer unit reads the Ν corresponding to the length 数据 of the data packet of the data to be decoded in the interleave address compression table according to the length of the data packet of the input data to be decoded. The value and interleaving calculate the intermediate values Τ ₀ , Τ\, Τ ₂ , Τ ₃ .

Step 204, based on the decoded parallelism, length of the packet to be decoded data, P _Q value and the calculated intermediate value generating interleaver interleaving address and the read address, and reading data to be decoded according to the read address, complete interleaving operation. FIG. 3 is a schematic flowchart of a method for implementing step 204 in FIG. 2 according to the present invention. As shown in FIG. 3, the method includes the following steps:

Step 301: Calculate, according to the length N of the data packet of the data to be decoded and the decoding parallelism K, the number of data to be decoded, which is buffered in each data buffer in the buffer unit before processing, that is, the number is equal to the prison.

Step 302: Generate K interleave addresses according to the decoding parallelism, the number of data to be decoded buffered in each data buffer, and the interleaving calculation base address.

Specifically, when K=l, it means that the parallel interleaving calculation is not performed, and the interleaving address is the base address of the interleaving calculation; according to the provisions in the protocol, the base address of the interleaving calculation in the first round of calculation is 1, and the initialization index value i is 0. When K=2, the base addresses 1 and Ρ are calculated according to the interleaving. Recursively generates 2 interleaved addresses; when Κ=4, the base addresses 1 and 计算 are calculated according to the interleaving. Recursively generate 4 interlaced addresses;

4 is a schematic diagram of recursively generating an interleave address in the present invention. As shown in FIG. 4, the recursively generated interleave address is specifically:

In the interleave address, the length of the data packet of the base data to be decoded is subjected to modulo processing to obtain the first interleave address inter_addr0; P. Multiplying the number of data to be decoded buffered in each data buffer by Δ, adding the product to the first interleave address inter_addrO, and adding the length N pairs of the data packets to be decoded according to the base address modulo to give a second way interleaving address i _nter _addrl; and so on, the P. Multiply the number of data to be decoded buffered in each data buffer by eight, and add the product to the K-1 way interleave address inter_addrK-2, and the length N of the data packet to be decoded according to the base address The result of the addition is subjected to modulo processing to obtain a K-th interleave address inter_addrK-l.

Step 303: Map the generated K interleave addresses to corresponding data buffer numbers. Specifically, map the generated K interleave addresses to corresponding data buffer numbers. When K=l, the data buffer number is 0. ; when Κ = 2, the data buffer number is 0 and 1; when Κ = 4 The data buffer number is 0, 1, 2, 3; Here, the interleave address is divided by N/K to obtain the data buffer number.

Step 304: Generate a read address of the K data to be decoded in the respective data buffers, wherein the value of each read address is the minimum value of the K interleave addresses, that is, the value of the generated K read addresses.

Step 305: Read data from the corresponding data buffer in the buffer unit before processing according to the generated K read addresses, and read K data to be decoded in total, and input the K data to be decoded into parallel translation. The coder performs decoding processing.

Step 306: The first interleave address of the K interleave addresses in step 302 is buffered to the pre-processing buffer unit, denoted as temp, as an intermediate value for calculating the next round of interleave addresses.

Step 307, according to the index value i and the intermediate value T. , Τ\, Τ ₂ , Τ ₃ , select the accumulated value W needed to calculate the next round of interleaved address calculation.

Step 308, calculating and updating the base address of the next round of interleaving address calculation according to the temp value and the accumulated value W.

At this time, the index value i=l, if it is smaller than the number Δ of data to be decoded buffered in each data buffer, then the index value i is incremented by 1, and the loop is performed from step 302 to step 308 until the index value is equal to each data buffer. When the number of data to be decoded is Δ, the parallel interleaved address of the current data to be decoded is calculated.

FIG. 5 is a schematic flowchart of Embodiment 1 of a parallel computing method for implementing an interleaved address according to the present invention. In this embodiment, a length of a data packet of the data to be decoded, N=480, is taken as an example. As shown in FIG. 5, the method includes The following steps:

Step 501: Determine, according to the length N of the data packet of the data to be decoded, that the decoding parallelism K is 4; as shown in FIG. 6, the data to be decoded is buffered in the four data buffers of the pre-processing buffer unit.

Step 502: Read the interleave address compression table according to the length N of the data packet of the data to be decoded, and obtain P. =53, T ₀ = 355, 1\ = 243, T ₂ = 283, Τ ₃ = 291. Step 503: Calculate the number of data to be decoded buffered in each data buffer in the buffer unit before processing, Δ=Ν/Κ=480/4=120.

Step 504, according to the decoding parallel degree Κ=4, the number of data to be decoded buffered in each data buffer Δ=120, and the interleaving calculation base address 1 generate four interleaving addresses, respectively, inter_addrO=l, inter_addrl= 121, inter_addr2=241, inter_addr3=361; At this time, the index value i=0.

Step 505: Generate data buffer numbers corresponding to the four interleaved addresses: 0, 1, 2, 3. Step 506, generating a read address of the four data to be decoded in the respective buffer, where the read address is 1.

Step 507: Read data from a corresponding data buffer in the buffer unit before processing according to the generated four read addresses, and input the read four data to be decoded into a parallel decoder for decoding processing; Read address 1 of data buffer 0 reads the corresponding data to be decoded, and inputs the 0th channel of the parallel decoder;

Read the corresponding data to be decoded from the read address 1 of the data buffer 1 and send it to the parallel decoder 1st;

Read the corresponding data to be decoded from the read address 1 of the data buffer 2, and send it to the parallel decoder 2nd channel;

The corresponding data to be decoded is read from the read address 1 of the data buffer 3, and sent to the parallel decoder.

Step 508: Cache the first interleave address temp=l.

Step 509, selecting an accumulated value W required to calculate the next round of interleave address calculation is 355. In step 510, the base address calculated and updated for the next round of interleaving address calculation is 356.

In step 511, the index value i is incremented by 1, and the index value i=l is accumulated. Since the index value i<N=120, the process proceeds to step 502, where the next round of interleave address calculation is performed.

Step 512, generating four interleaving addresses according to the decoding parallelism K=4, the number of data to be decoded buffered in each data buffer Δ=120, and the interleaving calculation base address1, respectively Inter_addr0=356, inter_addr 1=476, inter_addr2=116, inter_addr3=236.

Step 513: Generate data buffer numbers corresponding to the four interleaved addresses: 2, 3, 0, 1. Step 514, generating a read address of the four data to be decoded in the respective buffer, where the read address is 116.

Step 515: Read data from a corresponding data buffer in the buffer unit before processing according to the generated four read addresses, and input the read four data to be decoded into a parallel decoder for decoding; specifically, The read address 116 of the data buffer 2 reads the corresponding data to be decoded, and inputs the 0th channel of the parallel decoder;

Read the corresponding data to be decoded from the read address 116 of the data buffer 3, and send it to the first decoder of the parallel decoder;

Read the corresponding data to be decoded from the read address 116 of the data buffer 0, and send it to the second channel of the parallel decoder;

The corresponding data to be decoded is read from the read address 116 of the data buffer 1 and sent to the third channel of the parallel decoder.

Step 516, buffering the first interleave address temp=356.

Step 517, selecting an accumulated value W required to calculate the next round of interleave address calculation is 243. Step 518: Calculate and update the base address of the next round of interleaving address calculation to be 119.

In step 519, the index value i is incremented by one, and the index value i=2 is accumulated. Since the index value i<N=120, the process proceeds to step 504, the next round of interleave address calculation is performed, and so on, until the index value i=N= 120.

The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included. Within the scope of protection of the present invention.

Claims

Claim

A parallel computing system for interleaving addresses, the system comprising: an interleaved address buffer unit, a pre-processing buffer unit, and a control unit;

2. A parallel computing method for interleaving addresses, the method comprising: pre-configuring and storing an interleave address compression table;

Receiving data to be decoded, and determining decoding parallelism;

The method according to claim 2, wherein the determining the decoding parallelism is: determining the decoding parallelism K according to the length N of the data packet to be decoded, when 24 < N <

At 180 o'clock, K = l; when 192 < Ν < 240, Κ = 2; when 480 < Ν < 2400, Κ = 4.

The method according to claim 2, wherein the decoding is based on a degree of parallelism, a length of a data packet of data to be decoded, and ρ. The intermediate value of the value and interleaving calculation generates the interleave address and the read address as:

Δ ; B. generating, according to the decoding parallelism K, the number of data to be decoded cached in each data buffer, and the interleaving calculation base address to generate an interleave address;

5. The method according to claim 3, wherein the reading the data to be decoded according to the read address is:

E. Read data from a corresponding data buffer in the buffer unit before processing according to the generated K read addresses, and input the read κ data to be decoded into a parallel decoder for decoding.

6. The method according to claim 5, wherein the method further comprises:

H. Calculate and update the base address of the next round of interleave address calculation according to the tem value and the accumulated value W; determine the size of the index value i and the number of data to be decoded cached in each data buffer, if less than, execute Step A, until the index value i is equal to the number Δ of data to be decoded buffered in each data buffer.

The method according to claim 4, wherein the step Β is: when K=l, the interleave address is the base address of the interleave calculation; when Κ=2, the base address 1 and the interleave calculation Hey. Recursively generates 2 interleaving addresses; when Κ=4, 4 interleaving addresses are recursively generated according to the base addresses 1 and P _Q calculated by the interleaving.

The method according to claim 4, wherein the base address and the P ₀ recursively generated K interleave addresses according to the interlace calculation are:

Among the K interleave addresses, the modulo processing is performed according to the length N of the data packet of the base address to be decoded, to obtain the first interleave address inter_addr0; P. And caching in each data buffer The number of data to be decoded is multiplied by Δ, and the product is added to the K-1th interleave address inter_addrK-2, and the result of the addition is performed according to the length N of the data packet of the base data to be decoded. , get the Kth interleave address inter_addrK-1.

9. The method according to claim 4, wherein the step C is: when K=l, the data buffer number is 0; when Κ=2, the data buffer number is 0 and

1 ; When Κ=4, the data buffer number is 0, 1, 2, 3.