JP4874312B2 - Turbo code decoding apparatus, turbo code decoding method, and communication system - Google Patents

Description

  The present invention relates to an error correction technique in digital information processing, and more particularly to a turbo code decoding apparatus, a turbo code decoding method, and a communication system for decoding a turbo code.

The decoding of the turbo code is performed by repeatedly calculating the path metric value for the non-interleaved sequence and the interleaved sequence by a forward process and a backward process of a trellis diagram called a BCJR (Bahl Cocke Jinek Raviv) algorithm.
As an ideal decoding method, there is a MAP (maximum a posteriori probabilistic) decoding method, and a Log-MAP decoding method, a Max-Log-MAP decoding method, and the like are widely known (for example, see Non-Patent Document 1).

When high-speed digital communication is performed using a turbo code, it is necessary to speed up the decoding process of the turbo code and reduce the processing delay amount.
In order to speed up the turbo code decoding process, when the turbo code decoding process is parallelized, the implementation complexity depends on the configuration of the internal interleaver.
For example, QPP (Quadratic Polynomial Permutation) defined in the standard of “3GPP TS36.212” (see, for example, Non-Patent Document 2) is an internal interleaver suitable for parallelization of decoding processing (for example, (Refer nonpatent literature 3).

For example, Non-Patent Document 4 discloses a method of performing turbo code decoding processing in parallel.
That is, Non-Patent Document 4 describes that the BCJR algorithm is divided into parallel numbers and processed at the same time. When the parallel number is divided and processed simultaneously, a path metric value that becomes a break between divisions is stored. By using the path metric value in the next calculation of the iterative process, decoding can be performed without causing deterioration in decoding performance.

Also, a sliding window method is known as a combination method with the above decoding method (see, for example, Non-Patent Document 5).
The sliding window method is also a method that can reduce the amount of memory by dividing the BCJR algorithm and calculating the path metric value.
At that time, decoding can be performed without degrading the decoding performance by starting the BCJR algorithm by tracing back the trellis at each process at the break of the division.
The period going back to the trellis is called “margin width” or “training width”. Hereinafter, in this specification, a period going back the trellis is referred to as a “margin width”.

Haruo Sugawara, “Basics of Turbo Codes”, Trikes, p.37-46, October 7, 1999 J.Sun, O.Y.Takeshita, "Interleavers for turbo codes using permutation polynomials over integer rings", IEEE Trans. Inform. Theory, vol.51, p.101-119, March 2005 M.K.Cheng, B.E.Moision, J.Hamkins, M.A.Nakashima, "An interleaver implementation for the serially concatenated pulse-position modulation decoder", IEEE Symposium on Circuits and Systems, Greece, May 21-24, 2006 Shunsuke Ochi, Tomoharu Shibuya, Yoshikazu Sakanai, Isao Yamada, "High-speed decoding of Turbo-Code by parallel processing of MAP algorithm", IEICE IT97-57, pp.1-6, 1998 S. Benedetto, D. Divsalar, G. Montorsi, F. Pollara, `` Algorithm for continuous decoding of turbo codes '', Electronics Letters Volume 32, Issue 4, 15 Feb 1996, p.314-315

  Since the conventional turbo code decoding apparatus is configured as described above, when the QPP method is adopted as an interleaver for turbo code, an interleave sequence is simply performed by performing addition / subtraction and comparison processing instead of complicated multiplication and remainder calculation. Can be generated (Non-Patent Document 2). However, in this case, since the interleaved sequence can be generated in order from the beginning, decoding can be performed simultaneously with the generation of the interleaved sequence in the forward processing, but the interleaved sequence is generated in the backward processing. It is necessary to store the data in a memory and perform processing while reading the interleaved sequence. For this reason, a memory for storing the interleaved sequence is required, and there is a problem that the amount of memory increases.

The decoding processing speed of the turbo code depends on the number of decoding repetitions and the number of parallel operations, and on the margin when the sliding window method is used. If the number of repetitions is reduced, the decoding process can be speeded up, but there is a problem that the decoding performance is deteriorated. Even if the number of parallel processing is increased, the speed of the decoding process can be increased, but there is a problem that the amount of memory is increased.
In addition, when memory reduction is performed using the sliding window method, particularly when the turbo code is short, there is a problem that the processing amount is greatly affected by the margin width and the processing speed is lowered.

  The present invention has been made to solve the above-described problems, and is provided with a turbo code decoding apparatus and turbo code decoding capable of parallelizing turbo code decoding processing without mounting a memory for storing an interleaved sequence. The object is to obtain a method and a communication system.

The turbo code decoding device according to the present invention performs forward / backward processing and backward processing by performing addition / subtraction processing and comparison calculation processing using the parameters held in the memory selection initial table and the coefficients held in the interleave address generation table. The arrangement order and address of the turbo code storage means are determined, each data stored in the address of the turbo code storage means is read out in the arrangement order determined by the information selection control means, and forward processing and backward processing are performed. An interleave sequence is generated.

According to the present invention, sequence generating means for generating the interleaved sequence and non-interleaved sequence of turbo code, when generating the interleaved sequence of turbo codes, the forward processing and comparison made computing the subtraction processing and backward processing Since the interleave position is obtained, it is possible to parallelize the decoding process of the turbo code without mounting the memory for storing the interleaved sequence, and the effect of reducing the amount of memory to be mounted There is.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a turbo code decoding apparatus according to Embodiment 1 of the present invention. In the figure, information memories 1 are installed in the same number as the parallel number P of element decoders 7, for example, “3GPP TS36. A reception signal corresponding to a turbo code information sequence (systematic sequence) defined in the “212” standard is stored.
The parity 1 memory 2 is installed in the same number as the parallel number P of the element decoder 7 and stores received signals corresponding to the parity 1 sequence of the turbo code.
The parity 2 memory 3 is installed in the same number as the parallel number P of the element decoders 7, and stores received signals corresponding to the parity 2 sequence of the turbo code.
The external information memory 4 is installed in the same number as the parallel number P of the element decoder 7 and stores the external information series output from the element decoder 7.
The information memory 1, the parity 1 memory 2, and the parity 2 memory 3 store tail bit received signals in the case of a turbo code with tail bits added to the trellis end.
The information memory 1, the parity 1 memory 2, the parity 2 memory 3, and the external information memory 4 constitute turbo code storage means.

The memory interface 5 reads out the received signal from the interleave position indicated by the control unit 6 among the received signals stored in the information memory 1, the parity 1 memory 2, and the parity 2 memory 3, and interleaves the turbo code and non-interleaved. A sequence is generated, and an interleave sequence and a non-interleave sequence of the turbo code are output to the element decoder 7 indicated by the control unit 6, and the external information sequence output from the element decoder 7 is output to the external information memory 4. Perform the output process.
The control unit 6 indicates the interleave position to the memory interface 5 and controls forward processing and reverse processing in the element decoder 7. The control unit 6 generates an interleave sequence of turbo codes by the memory interface 5. At this time, the interleave position of the forward process and the backward process is obtained only by performing the addition / subtraction process and the comparison calculation process.
The memory interface 5 and the control unit 6 constitute a sequence generation unit.

  The P element decoders 7 are installed in parallel. Under the instruction of the control unit 6, the forward processing and the backward processing for the interleaved sequence and the non-interleaved sequence generated by the memory interface 5 are repeatedly performed. A process of decoding the code and calculating the external information sequence is performed. The element decoder 7 constitutes a decoding means.

In the example of FIG. 1, the memory interface 5, the control unit 6, and the element decoder 7 that are components of the turbo code decoding device are each configured by dedicated hardware (for example, a semiconductor integrated circuit board on which an MPU is mounted). However, when the turbo code decoding device is configured by a computer, a program describing the processing contents of the memory interface 5, the control unit 6, and the element decoder 7 is stored in the memory of the computer. The CPU of the computer may execute a program stored in the memory.
FIG. 2 is a flowchart showing the processing contents of the turbo code decoding apparatus according to Embodiment 1 of the present invention.

Next, the operation will be described.
For example, a transmitter (not shown) that employs a QPP method that is a second-order polynomial on an integer ring as an internal interleaver of a turbo code generates a turbo code by turbo-coding an information source such as packet data, for example. Then, the turbo code is modulated and a modulated wave is transmitted.
In the communication path, noise is added to the modulated wave in accordance with the propagation environment, and the modulated wave to which noise is added is received by a receiving device (not shown).

When the receiving device receives the modulated wave transmitted from the transmitting device, the receiving device performs synchronous detection and demodulation processing on the modulated wave, and receives a received signal corresponding to a turbo code information sequence (systematic sequence), a parity of the turbo code A reception signal corresponding to one sequence and a reception signal corresponding to a parity 2 sequence of turbo codes are calculated.
The receiving apparatus incorporates the turbo code decoding apparatus shown in FIG. 1, and the turbo code decoding apparatus decodes the turbo code.
Hereinafter, the processing content of the turbo code decoding apparatus will be described in detail.

Here, it is assumed that the information length of the information sequence is K and the parallel number of the element decoders 7 is P.
In this case, the length of the parallelized unit processed in parallel by the P element decoders 7 is W = K / P, and the number of addresses is also K / P.
One word is n bits equal to the number of bits n of the received signal.

In the P information memories 1 in the turbo code decoding device, received signals corresponding to turbo code information sequences are respectively stored. However, the information is stored in the information memory 1 in the order of # 1 to #P from the top of the information series.
Also, the P parity 1 memory 2 in the turbo code decoding apparatus stores received signals corresponding to the parity 1 sequence of the turbo code, and the P parity 2 memory 3 stores the parity 2 sequence of the turbo code. Corresponding received signals are stored respectively.
However, they are stored in the parity 1 memory 2 in the order of # 1 to #P from the top of the parity 1 series, and are stored in the parity 2 memory 3 in the order of # 1 to #P from the top of the parity 2 series.

The control unit 6 controls the reception signal that the memory interface 5 reads from the information memory 1, the parity 1 memory 2, and the parity 2 memory 3, and the external information that the memory interface 5 reads from the external information memory 4 and the external information memory 4 External information to be written (for example, information indicating the probability that the decoding result by the element decoder 7 is “1” or “0”) is controlled.
However, when the memory interface 5 writes external information, control is performed so that the external information is written to the same memory as the external information to be read and has the same address as the external information to be read.

Although details will be described later, reading from the information memory 1 and the external information memory 4 is random access according to the interleave sequence in the interleave access, and is in order in the non-interleave access.
In addition, the reading from the parity 1 memory 2 and the parity 2 memory 3 is always performed in the order, and at the time of non-interleaved decoding, a received signal corresponding to the parity 1 series is read from the parity 1 memory 2 and sent to the element decoder 7. Is output. At the time of interleaving decoding, a received signal corresponding to the parity 2 sequence is read from the parity 2 memory 3 and output to the element decoder 7.
From the control unit 6, a control signal indicating the memory number B (t) to be read and the address A (t) to be read is output to the memory interface 5.

Here, the memory number B (t) and the address A (t) output from the control unit 6 to the memory interface 5 will be specifically described.
First, the t-th interleave sequence π (t) of the QPP interleaver generated by the memory interface 5 is expressed as follows.
π (t) = (f1 × t + f2 × t × t) mod K (1)
However, f1 and f2 are predetermined constants.
At this time, when the P element decoders 7 perform parallel processing, the memory number B (t) and the address A (t) accessed as data to be passed to the jth element decoder 7 in the i-th process are as follows: It is expressed as follows.
B (t) = π (i + W × j) / W (2)
A (t) = π (i + W × j) mod W (3)
However, P is a divisor of K for simplicity of explanation here.

Therefore, if the control unit 6 calculates the equations (1) to (3), the memory number B (t) and the address A (t) can be obtained, but the equations (1) to (3) are calculated. Then, multiplication and mod (remainder) calculation are required, and the implementation is highly complicated.
Therefore, in the first embodiment, as shown below, the control unit 6 performs the addition / subtraction process and the comparison calculation process to obtain the interleave position of the forward process and the backward process.
When calculating the memory number B (t) and the address A (t) to be accessed, β (t) and α (t) are prepared as auxiliary parameters.

However, since the following parameters β (0), α (0), γ, and δ have a large calculation amount, they are stored in the memory in advance.
β (0) = ceil ((f1 + f2) mod K) / W)
α (0) = (f1 + f2) mod W
γ = ceil (2 × f2 / W)
δ = (2 × f2 mod W)
Here, ceil (argument) is a function that returns the next largest integer from the arguments in parentheses.
Note that a large amount of memory is not required for calculating the parameters β (0), α (0), γ, and δ and holding the calculated values.

As shown below, the memory number B (t) and the address A (t) indicating the interleave position of the forward processing can be obtained by sequential operations in the forward direction.
[Update of B (t)] If (A (t) + α (t) ≧ W)
C = 1
Else
C = 0
B (t + 1) = B (t) + β (t) + C
If (B (t + 1) ≧ P)
B (t + 1) = B (t + 1) −P
[Update of β (t)] If (α (t) + δ ≧ W)
C = 1
Else
C = 0
β (t + 1) = β (t) + γ + C
If (β (t + 1) ≧ P)
β (t + 1) = β (t + 1) −P
[Update of A (t)] A (t + 1) = A (t) + α (t)
If (A (t + 1) ≧ W)
A (t + 1) = A (t + 1) −W
[Update of α (t)] α (t + 1) = α (t) + δ
If (α (t + 1) ≧ W)
α (t + 1) = α (t + 1) −W
(4)

The memory interface 5 starts from the interleave position indicated by the address A (t) output from the control unit 6 among the received signals stored in the information memory 1 indicated by the memory number B (t) output from the control unit 6. By reading the received signal for one word, a forward interleaved sequence π (t) can be generated.
When the information length K is equally divided by the parallel number P and the # 1 to #P element decoders 7 perform parallel processing, the starting point of the parallel processing in the # 1 to #P element decoders 7 is The tops of the QPP interleavers are 0, W, 2W,..., (P−1) × W, respectively.
Therefore, the control unit 6 uses parameters B (0), B (W), B (2W),. , Β (0), β (W), β (2W),..., Β ((P−1) × W), α (0), γ, δ are held.

When the memory interface 5 generates a forward interleave sequence π (t) and gives the interleave sequence π (t) to the element decoder 7, the memory interface 5 receives from the parity 2 memory 3 the parity 2 sequence corresponding to the turbo code. The signal is read and the received signal is given to the element decoder 7. The received signal stored in the # 1 parity 2 memory 3 is given to the # 1 element decoder 7, and the # 2 parity 2 memory 3 is given. The stored received signal is applied to the # 2 element decoder 7, and the received signal stored in the #P parity 2 memory 3 is applied to the #P element decoder 7.
At this time, the received signal is read in order from the initial position of the parity 2 memory 3 of # 1 to #P, but every time the received signal is read from the parity 2 memory 3 of # 1 to #P, the read address (initially The address of the position = the address indicating the received signal stored at the head of the W received signals stored in the parity 2 memory 3 of # 1 to #P is incremented by one.

As described above, the control unit 6 calculates the equation (4) when obtaining the interleave position for the forward processing, but the memory interface 5 generates a non-interleaved sequence for the forward processing, and the non-interleaved sequence is calculated. When given to the # 1 to #P element decoder 7, the received signal for one word is read in order from the initial position of the information memory 1 of # 1 to #P.
At this time, each time a received signal is read from the information memory 1 of # 1 to #P, a read address (initially, the address of the initial position = W received signals stored in the information memory 1 of # 1 to #P) Among them, the address indicating the received signal stored at the head is incremented by one.
The received signal stored in the # 1 information memory 1 is supplied to the # 1 element decoder 7, and the received signal stored in the # 2 information memory 1 is supplied to the # 2 element decoder 7. The received signal stored in the #P information memory 1 is supplied to the #P element decoder 7.

When the memory interface 5 generates a forward non-interleaved sequence and gives the non-interleaved sequence to the element decoder 7, the memory interface 5 reads the received signal corresponding to the parity 1 sequence of the turbo code from the parity 1 memory 2, and The received signal is supplied to the element decoder 7, but the received signal stored in the parity 1 memory 2 of # 1 is supplied to the element decoder 7 of # 1, and the received signal stored in the parity 1 memory 2 of # 2 Is supplied to the # 2 element decoder 7 and the received signal stored in the #P parity 1 memory 2 is supplied to the #P element decoder 7.
At this time, the received signals are read sequentially from the initial position of the parity 1 memory 2 of # 1 to #P, but each time the received signal is read from the parity 1 memory 2 of # 1 to #P, the read address (initially The address of the position = the address indicating the received signal stored in the head among the W received signals stored in the parity 1 memory 2 of # 1 to #P is incremented by one.

Next, as shown below, the memory number B (t) and the address A (t) indicating the interleave position of the backward processing can be obtained by sequential operations in the backward direction.
[Update of α (t)] If (α (t) ≧ δ)
α (t−1) = α (t) −δ
Else
α (t−1) = α (t) + W−δ
[Update of A (t)] If (A (t) ≧ α (t−1))
A (t−1) = A (t) −α (t−1)
Else
A (t-1) = A (t) + W- [alpha] (t-1)
[Update of β (t)] If (α (t) + δ ≧ W)
C = 1
Else
C = 0
If (β (t) ≧ γ + C)
β (t−1) = β (t) −γ-C
Else
β (t−1) = β (t + 1) + P−γ−C
[Update of B (t)] If (A (t) + α (t) ≧ W)
C = 1
Else
C = 0
If (B (t) ≧ β (t−1) + C)
B (t−1) = B (t) −β (t−1) −C
Else
B (t−1) = B (t) + P−β (t−1) −C
(5)

The memory interface 5 starts from the interleave position indicated by the address A (t) output from the control unit 6 among the received signals stored in the information memory 1 indicated by the memory number B (t) output from the control unit 6. By reading a received signal for one word, an interleaved sequence π (t) in the reverse direction can be generated.
When the information length K is equally divided by the parallel number P and the # 1 to #P element decoders 7 perform parallel processing, the starting point of the parallel processing in the # 1 to #P element decoders 7 is QPP interleaver has (P-1) × W,..., 2W, 1W, and leading 0.
Therefore, the control unit 6 uses parameters B (0), B (W), B (2W),. , Β (0), β (W), β (2W),..., Β ((P−1) × W), α (0), γ, δ are held.

When the memory interface 5 generates an interleave sequence π (t) in the reverse direction and supplies the interleave sequence π (t) to the element decoder 7, the memory interface 5 receives from the parity 2 memory 3 the parity 2 sequence corresponding to the turbo code. The signal is read and the received signal is given to the element decoder 7. The received signal stored in the # 1 parity 2 memory 3 is given to the # 1 element decoder 7, and the # 2 parity 2 memory 3 is given. The stored received signal is applied to the # 2 element decoder 7, and the received signal stored in the #P parity 2 memory 3 is applied to the #P element decoder 7.
At this time, the received signal is sequentially read from the final position of the parity 2 memory 3 of # 1 to #P, but each time the received signal is read from the parity 2 memory 3 of # 1 to #P, The address of the position = the address indicating the received signal stored at the tail of the W received signals stored in the parity 2 memory 3 of # 1 to #P) is decremented by one.

As described above, the control unit 6 calculates Equation (5) when obtaining the interleave position for the backward processing, but the memory interface 5 generates the non-interleaved sequence for the backward processing and generates the non-interleaved sequence. When given to the # 1 to #P element decoder 7, the received signal for one word is read in order from the final position of the information memory 1 of # 1 to #P.
At this time, every time a received signal is read from the information memories 1 of # 1 to #P, a read address (initially, the address of the final position = W received signals stored in the information memory 1 of # 1 to #P Among them, the address indicating the received signal stored at the end is decremented one by one.
The received signal stored in the # 1 information memory 1 is supplied to the # 1 element decoder 7, and the received signal stored in the # 2 information memory 1 is supplied to the # 2 element decoder 7. The received signal stored in the #P information memory 1 is supplied to the #P element decoder 7.

When the memory interface 5 generates a forward non-interleaved sequence and gives the non-interleaved sequence to the element decoder 7, the memory interface 5 reads the received signal corresponding to the parity 1 sequence of the turbo code from the parity 1 memory 2, and The received signal is supplied to the element decoder 7, but the received signal stored in the parity 1 memory 2 of # 1 is supplied to the element decoder 7 of # 1, and the received signal stored in the parity 1 memory 2 of # 2 Is supplied to the # 2 element decoder 7 and the received signal stored in the #P parity 1 memory 2 is supplied to the #P element decoder 7.
At this time, the received signal is sequentially read from the last position of the parity 1 memory 2 of # 1 to #P, but each time the received signal is read from the parity 1 memory 2 of # 1 to #P, The address of the position = the address indicating the received signal stored at the end of the W received signals stored in the parity 1 memory 2 of # 1 to #P is decremented one by one.

The operation of the control unit 6 when the memory interface 5 generates an interleaved sequence and a non-interleaved sequence is as described above.
Hereinafter, a process in which the control unit 6 controls the memory interface 5 to generate an interleaved sequence and a non-interleaved sequence in order, and the element decoder 7 decodes the turbo code will be described with reference to FIG.
2 shows an example in which iterative decoding is performed in the order of non-interleaving, interleaving, non-interleaving, interleaving,..., Non-interleaving, and interleaving, but non-interleaving and interleaving may be reversed. Further, the processing is performed in the order of the forward direction, the reverse direction, the forward direction, and the reverse direction, but the forward direction and the reverse direction may be reversed.

First, the control unit 6 initializes the path metric value stored in the memory of the element decoder 7.
Next, the control unit 6 uses parameters (α (0), γ, δ) specific to the information length as parameters relating to the generation of the interleave sequence π (t), and a parameter ( B (0), B (W), B (2W),..., B ((P-1) × W), β (0), β (W), β (2W),. ((P-1) × W) is set.
In FIG. 2, in order to clarify parallel processing, the number of parallel processes is represented by P, and forward processing and backward processing are represented by # 1 to #P.

In addition, the control unit 6 initializes the number of repetitions of forward processing and reverse processing and initial setting of memory access, and initializes path metric calculation in the element decoder 7.
In FIG. 2, the path metric value calculated by the element decoder 7 is described as “end path metric value”. In particular, in order to clarify the storage and reading of the path metric value, the non-interleaved forward direction is described. The case is denoted by F1, the non-interleaved reverse direction is denoted by B1, the interleave forward direction is denoted by F2, and the interleave reverse direction is denoted by B2. These path metric values are overwritten when a new value is calculated.

In the first iteration, the control unit 6 performs the forward processing of the non-interleaved sequence, so that the address indicating the position of the forward non-interleaved sequence given to the # 1 to #P element decoders 7 and the memory number are stored in the memory interface. 5 is output.
When the memory interface 5 receives the address and memory number from the control unit 6, it reads out the received signal from the information memories 1 of # 1 to #P according to the address and memory number, respectively, and sends each received signal to # 1 to ##. The received signal is supplied to the P element decoder 7 and the received signal is read from the parity 1 memory 2, and each received signal is supplied to the # 1 to #P element decoder 7.
Upon receiving the received signal from the memory interface 5, the # 1 to #P element decoders 7 perform forward processing on the received signal, calculate a decoding result, and obtain a non-interleaved forward path metric value. The path metric value is calculated and stored in the internal memory as the end path metric value F1. The forward processing for the received signal, the method of calculating the decoding result and the path metric value are known techniques, and are disclosed in Non-Patent Document 1, for example.
The forward process in the # 1 to #P element decoders 7 requires W steps.

Next, in order to perform reverse processing of the non-interleaved sequence in the first iteration, the control unit 6 assigns an address indicating the position of the reverse non-interleaved sequence to be supplied to the # 1 to #P element decoder 7 and a memory number. Output to the memory interface 5.
When the memory interface 5 receives the address and memory number from the control unit 6, it reads out the received signal from the information memories 1 of # 1 to #P according to the address and memory number, respectively, and sends each received signal to # 1 to ##. The received signal is supplied to the P element decoder 7 and the received signal is read from the parity 1 memory 2, and each received signal is supplied to the # 1 to #P element decoder 7.
Upon receiving the received signal from the memory interface 5, the # 1 to #P element decoders 7 perform reverse processing on the received signal, calculate the decoding result, and calculate the path metric value in the non-interleaved reverse direction. The path metric value is calculated and stored in the internal memory as the end path metric value B1.
Also, the # 1 to #P element decoder 7 uses the path metric value in the non-interleaved reverse direction to determine the probability that the decoding result by the element decoder 7 is “1” or “0”. Information) is calculated, and the external information is stored in the external information memories 4 of # 1 to #P. The reverse processing for the received signal and the method for calculating the external information are known techniques, and are disclosed in Non-Patent Document 1, for example.
The backward process in the # 1 to #P element decoders 7 requires W steps.

Next, the control unit 6 calculates the memory number B (t) and the address A (t) using the above equation (4) in order to perform forward processing of the interleaved sequence in the first repetition, and the memory The number B (t) and the address A (t) are output to the memory interface 5.
When the memory interface 5 receives the memory number B (t) and the address A (t) from the control unit 6, the information memory 1 of # 1 to #P according to the memory number B (t) and the address A (t). The received signals are respectively read from and supplied to the # 1 to #P element decoders 7, and the received signals are read from the parity 2 memory 3, and the received signals are # 1 to #P decoded. Give to vessel 7.
Also, the external information is read from the external information memories 4 of # 1 to #P, and the external information is given to the element decoder 7 of # 1 to #P.
When receiving the received signal and the external information from the memory interface 5, the # 1 to #P element decoders 7 perform forward processing on the received signal using the external information and calculate the decoding result. The path metric value in the interleave forward direction is calculated, and the path metric value is stored in the internal memory as the end path metric value F2.

Next, the control unit 6 calculates the memory number B (t) and the address A (t) using the above equation (5) in order to perform reverse processing of the interleaved sequence in the first iteration, and the memory The number B (t) and the address A (t) are output to the memory interface 5.
When the memory interface 5 receives the memory number B (t) and the address A (t) from the control unit 6, the information memory 1 of # 1 to #P according to the memory number B (t) and the address A (t). The received signals are respectively read from and supplied to the # 1 to #P element decoders 7, and the received signals are read from the parity 2 memory 3, and the received signals are # 1 to #P decoded. Give to vessel 7.
Also, the external information is read from the external information memories 4 of # 1 to #P, and the external information is given to the element decoder 7 of # 1 to #P.
When receiving the received signal and the external information from the memory interface 5, the # 1 to #P element decoder 7 performs reverse processing on the received signal using the external information and calculates the decoding result. The path metric value in the reverse direction of interleaving is calculated, and the path metric value is stored in the internal memory as the end path metric value B2.
Also, the # 1 to #P element decoder 7 calculates external information using the path metric value in the reverse direction of interleaving, and stores the external information in the external information memory 4 of # 1 to #P (external information). The newly calculated external information is overwritten on the external information stored in the memory 4).

In the second iteration, the control unit 6 performs the forward processing of the non-interleaved sequence, so that the address indicating the position of the forward non-interleaved sequence given to the # 1 to #P element decoder 7 and the memory number are stored in the memory interface. 5 is output.
When the memory interface 5 receives the address and memory number from the control unit 6, it reads out the received signal from the information memories 1 of # 1 to #P according to the address and memory number, respectively, and sends each received signal to # 1 to ##. The received signal is supplied to the P element decoder 7 and the received signal is read from the parity 1 memory 2, and each received signal is supplied to the # 1 to #P element decoder 7.
Also, the external information is read from the external information memories 4 of # 1 to #P, and the external information is given to the element decoder 7 of # 1 to #P.
Upon receiving the received signal and the external information from the memory interface 5, the # 1 to #P element decoders 7 receive the end path metric value F1 stored in the internal memory (the non-interleaved sequence forward processing in the first iteration). Is read out, and the end path metric value F1 is set as an initial value for forward processing.
Then, forward processing is performed on the received signal using the external information to calculate a decoding result and a path metric value in the interleaved forward direction.
The element decoders # 1 to #P use the path metric value as the end path metric value F1, and update the end path metric value F1 stored in the internal memory (the end metric stored in the internal memory). The newly calculated path metric value is overwritten on the path metric value F1).

Next, in order to perform reverse processing of the non-interleaved sequence in the second iteration, the control unit 6 assigns an address and a memory number indicating the position of the reverse non-interleaved sequence to be supplied to the # 1 to #P element decoders 7. Output to the memory interface 5.
When the memory interface 5 receives the address and memory number from the control unit 6, it reads out the received signal from the information memories 1 of # 1 to #P according to the address and memory number, respectively, and sends each received signal to # 1 to ##. The received signal is supplied to the P element decoder 7 and the received signal is read from the parity 1 memory 2, and each received signal is supplied to the # 1 to #P element decoder 7.
Also, the external information is read from the external information memories 4 of # 1 to #P, and the external information is given to the element decoder 7 of # 1 to #P.
Upon receiving the received signal and the external information from the memory interface 5, the # 1 to #P element decoders 7 receive the end path metric value B1 stored in the internal memory (reverse processing of the non-interleaved sequence in the first iteration) Is read out, and the end path metric value B1 is set as the initial value of the backward processing.
Then, using the external information, reverse processing is performed on the received signal to calculate a decoding result and a non-interleaved reverse path metric value.
The element decoders # 1 to #P update the end path metric value B1 stored in the internal memory with the path metric value as the end path metric value B1.
Further, external information is calculated using the path metric value in the non-interleaved reverse direction, and the external information is stored in the external information memory 4 of # 1 to #P.

Next, the control unit 6 calculates the memory number B (t) and the address A (t) using the above equation (4) in order to perform forward processing of the interleaved sequence in the second repetition, and the memory The number B (t) and the address A (t) are output to the memory interface 5.
When the memory interface 5 receives the memory number B (t) and the address A (t) from the control unit 6, the information memory 1 of # 1 to #P according to the memory number B (t) and the address A (t). The received signals are respectively read from and supplied to the # 1 to #P element decoders 7, and the received signals are read from the parity 2 memory 3, and the received signals are # 1 to #P decoded. Give to vessel 7.
Also, the external information is read from the external information memories 4 of # 1 to #P, and the external information is given to the element decoder 7 of # 1 to #P.
Upon receipt of the received signal and external information from the memory interface 5, the # 1 to #P element decoders 7 receive the end path metric value F2 stored in the internal memory (in the first iteration of the interleaved sequence forward processing). The calculated end path metric value F2) is read, and the end path metric value F2 is set as the initial value of the forward processing.
Then, forward processing is performed on the received signal using the external information to calculate a decoding result and a path metric value in the interleaved forward direction.
The element decoders # 1 to #P update the end path metric value F2 stored in the internal memory with the path metric value as the end path metric value F2.

Next, the control unit 6 calculates the memory number B (t) and the address A (t) using the above equation (5) in order to perform the backward process of the interleaved sequence in the second iteration, and the memory The number B (t) and the address A (t) are output to the memory interface 5.
When the memory interface 5 receives the memory number B (t) and the address A (t) from the control unit 6, the information memory 1 of # 1 to #P according to the memory number B (t) and the address A (t). The received signals are respectively read from and supplied to the # 1 to #P element decoders 7, and the received signals are read from the parity 2 memory 3, and the received signals are # 1 to #P decoded. Give to vessel 7.
Also, the external information is read from the external information memories 4 of # 1 to #P, and the external information is given to the element decoder 7 of # 1 to #P.
Upon receipt of the received signal and external information from the memory interface 5, the # 1 to #P element decoders 7 receive the end path metric value B2 stored in the internal memory (reverse processing of the interleaved sequence in the first iteration). The calculated end path metric value B2) is read, and the end path metric value B2 is set as the initial value of the backward processing.
Then, using the external information, reverse processing is performed on the received signal to calculate a decoding result and a path metric value in the interleave reverse direction.
The # 1 to #P element decoders 7 update the end path metric value B2 stored in the internal memory using the path metric value as the end path metric value B2.
Further, external information is calculated using the path metric value in the reverse direction of interleaving, and the external information is stored in the external information memory 4 of # 1 to #P.

Thereafter, similarly to the second iteration, the non-interleaved forward process and backward process and the interleaved forward process and backward process are repeated a predetermined number of times.
When the # 1 to #P element decoders 7 are repeatedly executed a predetermined number of times, they output the finally calculated decoding result.

As apparent from the above, according to the first embodiment, when the memory interface 5 generates the interleaved sequence of the turbo code, the control unit 6 simply performs the addition / subtraction process and the comparison calculation process, and reverses the forward process. Since the configuration is such that the interleave position of the direction processing is obtained, it becomes possible to parallelize the decoding process of the turbo code without mounting the memory for storing the interleaved sequence, thereby reducing the amount of memory to be mounted. There is an effect that can be done.
That is, since memory access depending on the interleaved sequence can be obtained sequentially with a simple calculation, a memory for holding the interleaved sequence becomes unnecessary, and the memory capacity and circuit scale can be reduced. .

In the first embodiment, the element decoder 7 performs forward processing and backward processing in order. However, the element decoder 7 performs forward processing and backward processing at the same time. May be.
However, when the element decoder 7 performs the forward processing and the backward processing simultaneously, if the length W of the parallelization unit is an odd number, the start of either the forward processing or the backward processing is advanced by one step. Alternatively, it is delayed by one step.

That is, when the element decoder 7 performs forward processing and backward processing at the same time, the forward processing proceeds while storing the path metric value from the beginning of the unit, and the backward processing starts with the path metric value from the end of the unit. Proceed while saving.
Since the trellises that have advanced from both directions cross each other, the mutual path metric values can be read out, so that external information can be calculated.
However, if the length W of the parallelization unit is an odd number, the start of either the forward process or the backward process is delayed by one step or delayed by one step.
The reason is that when the parallelization unit length W is an odd number, the positions at which the trellis crosses are the same, so that there is a position where no path metric value is stored, and external information is calculated. Because you can't.
By delaying any start by one step or delaying one step, external information can be calculated in any case without contradiction to the processing timing.

Embodiment 2. FIG.
In the first embodiment, the information memory 1, the parity 1 memory 2, the parity 2 memory 3, and the external information memory 4 are mounted on each of the P pieces. However, as shown in FIG. One parity 1 memory 2, one parity 2 memory 3, and one external information memory 4 may be mounted.
In this case, reading and writing of data when parallelizing the decoding process can be performed by controlling the rearrangement of the address to be accessed and the read data.
For example, if the parallel number is P, the number of addresses is K / P, and one word is n × P bits, which is P times the number of bits n of the received signal, and the read n × P bits are divided into n bits and rearranged. Like that.

The control unit 6 controls the reception signal that the memory interface 5 reads from the information memory 1, the parity 1 memory 2, and the parity 2 memory 3, and the external information that the memory interface 5 reads from the external information memory 4 and the external information memory 4 Control external information to be written. However, when the memory interface 5 writes external information, control is performed so that the external information is written to the same address as the external information to be read.
In addition, the control unit 6 controls a data rearrangement pattern that is a received signal read by the memory interface 5.

Hereinafter, control of the data rearrangement pattern in the control unit 6 will be described.
Here, auxiliary parameters β (t) and α (t) are prepared, assuming that the address accessed by the memory interface 5 is A (t) and the parameter indicating the data rearrangement order is B (t).
However, since the following parameters β (0), α (0), γ, and δ have a large calculation amount, they are stored in the memory in advance.
β (0) = ceil ((f1 + f2) mod K) / W)
α (0) = (f1 + f2) mod W
γ = ceil (2 × f2 / W)
δ = (2 × f2 mod W)
Note that a large amount of memory is not required for calculating the parameters β (0), α (0), γ, and δ and holding the calculated values.

If the information length K is equally divided by the parallel number P and the # 1 to #P element decoders 7 perform parallel processing, the starting point of the parallel processing in the # 1 to #P element decoders 7 is QPP, respectively. The top of the interleaver is 0, W, 2W,..., (P-1) × W.
Therefore, the control unit 6 uses parameters B (0), B (W), B (2W),. , Β (0), β (W), β (2W),..., Β ((P−1) × W), α (0), γ, δ are held.

B (t) and A (t) can be obtained using the above equation (4) in a sequential operation during forward interleaving, and in a sequential operation during backward interleaving, (5) can be obtained. In the first embodiment, B (t) in the above equations (4) and (5) represents a memory number. In this second embodiment, B in the equations (4) and (5) It is assumed that (t) represents the data rearrangement order.
As for the address at the time of non-interleaving, the address may be changed one by one from the initial position or the final position as in the first embodiment.

In the information memory 1, the parity 1 memory 2, the parity 2 memory 3, and the external information memory 4, one word is composed of n × P bits, and FIG. 4 shows the read n × P bits as P element decoders 7 Shows the procedure for reordering for delivery.
When the information memory 1, the parity 1 memory 2, the parity 2 memory 3 and the external information memory 4 are mounted one by one, values having the same remainder (i mod P) at P with respect to the data number i are stored at the same address. If parallel processing is performed, the same combination is processed simultaneously even during interleaving.
However, since the element decoder 7 for transferring data changes, it is necessary to rearrange the data. In FIG. 4, data rearrangement is performed using B (t) obtained from the above equations (4) and (5).

Hereinafter, a process in which the control unit 6 controls the memory interface 5 to generate an interleaved sequence and a non-interleaved sequence in order, and the element decoder 7 decodes the turbo code will be described with reference to FIG.
2 shows an example in which iterative decoding is performed in the order of non-interleaving, interleaving, non-interleaving, interleaving,..., Non-interleaving, and interleaving, but non-interleaving and interleaving may be reversed. Further, the processing is performed in the order of the forward direction, the reverse direction, the forward direction, and the reverse direction, but the forward direction and the reverse direction may be reversed.

First, the control unit 6 initializes the path metric value stored in the memory of the element decoder 7.
Next, the control unit 6 uses parameters (α (0), γ, δ) specific to the information length as parameters relating to the generation of the interleave sequence π (t), and a parameter ( B (0), B (W), B (2W),..., B ((P-1) × W), β (0), β (W), β (2W),. ((P-1) × W) is set.
In FIG. 2, in order to clarify parallel processing, the number of parallel processes is represented by P, and forward processing and backward processing are represented by # 1 to #P.
In addition, the control unit 6 initializes the number of repetitions of forward processing and reverse processing and initial setting of memory access, and initializes path metric calculation in the element decoder 7.

In the first iteration, the control unit 6 calculates the rearrangement order parameter B (t) using the above-described equation (4) in order to perform the forward processing of the non-interleaved sequence, and the rearrangement order parameter B ( t) and an address indicating the position of the forward non-interleaved sequence are output to the memory interface 5.
When the memory interface 5 receives the address and the rearrangement order parameter B (t) from the control unit 6, the memory interface 5 reads the received signal from the information memory 1 according to the address, and receives the received signal according to the rearrangement order parameter B (t). The signals are rearranged, and the rearranged received signals are output to the # 1 to #P element decoders 7. Also, the received signal is read from the parity 1 memory 2 and the received signal is supplied to the # 1 to #P element decoder 7.
Upon receiving the received signal from the memory interface 5, the # 1 to #P element decoders 7 perform forward processing on the received signal, calculate a decoding result, and obtain a non-interleaved forward path metric value. The path metric value is calculated and stored in the internal memory as the end path metric value F1.
The forward process in the # 1 to #P element decoders 7 requires W steps.

Next, in order to perform reverse processing of the non-interleaved sequence in the first iteration, the control unit 6 calculates the rearrangement order parameter B (t) using the above equation (5), and the rearrangement order parameter. B (t) and an address indicating the position of the non-interleaved sequence in the reverse direction are output to the memory interface 5.
When the memory interface 5 receives the address and the rearrangement order parameter B (t) from the control unit 6, the memory interface 5 reads the received signal from the information memory 1 according to the address, and receives the received signal according to the rearrangement order parameter B (t). The signals are rearranged, and the rearranged received signals are output to the # 1 to #P element decoders 7. Also, the received signal is read from the parity 1 memory 2 and the received signal is supplied to the # 1 to #P element decoder 7.
Upon receiving the received signal from the memory interface 5, the # 1 to #P element decoders 7 perform reverse processing on the received signal, calculate the decoding result, and calculate the path metric value in the non-interleaved reverse direction. The path metric value is calculated and stored in the internal memory as the end path metric value B1.
Also, the # 1 to #P element decoders 7 calculate external information using the path metric value in the non-interleaved reverse direction, and store the external information in the external information memory 4.
The backward process in the # 1 to #P element decoders 7 requires W steps.

Next, the control unit 6 calculates the address A (t) and the rearrangement order parameter B (t) using the above equation (4) in order to perform the forward process of the interleave sequence in the first iteration. The address A (t) and the rearrangement order parameter B (t) are output to the memory interface 5.
Upon receiving the address A (t) and the rearrangement order parameter B (t) from the control unit 6, the memory interface 5 reads the received signal from the information memory 1 according to the address A (t), and the rearrangement order parameter B The received signals are rearranged according to (t), and the rearranged received signals are output to the # 1 to #P element decoders 7.
Also, the received signal is read from the parity 2 memory 3, the received signal is given to the # 1 to #P element decoder 7, the external information is read from the external information memory 4, and the external information is sent from # 1 to #P. To the element decoder 7.
When receiving the received signal and the external information from the memory interface 5, the # 1 to #P element decoders 7 perform forward processing on the received signal using the external information and calculate the decoding result. The path metric value in the interleave forward direction is calculated, and the path metric value is stored in the internal memory as the end path metric value F2.

Next, the control unit 6 calculates the address A (t) and the rearrangement order parameter B (t) using the above equation (5) in order to perform the backward processing of the interleaved sequence in the first iteration. The address A (t) and the rearrangement order parameter B (t) are output to the memory interface 5.
Upon receiving the address A (t) and the rearrangement order parameter B (t) from the control unit 6, the memory interface 5 reads the received signal from the information memory 1 according to the address A (t), and the rearrangement order parameter B The received signals are rearranged according to (t), and the rearranged received signals are output to the # 1 to #P element decoders 7.
Also, the received signal is read from the parity 2 memory 3, the received signal is given to the # 1 to #P element decoder 7, the external information is read from the external information memory 4, and the external information is sent from # 1 to #P. To the element decoder 7.
When receiving the received signal and the external information from the memory interface 5, the # 1 to #P element decoder 7 performs reverse processing on the received signal using the external information and calculates the decoding result. The path metric value in the reverse direction of interleaving is calculated, and the path metric value is stored in the internal memory as the end path metric value B2.
Also, the # 1 to #P element decoders 7 calculate external information using path metric values in the reverse direction of interleaving, and store the external information in the external information memory 4 (stored in the external information memory 4). The newly calculated external information is overwritten on the existing external information).

In the second iteration, the control unit 6 calculates the rearrangement order parameter B (t) using the above equation (4) in order to perform the forward processing of the non-interleaved sequence, and the rearrangement order parameter B ( t) and an address indicating the position of the forward non-interleaved sequence are output to the memory interface 5.
When the memory interface 5 receives the address and the rearrangement order parameter B (t) from the control unit 6, the memory interface 5 reads the received signal from the information memory 1 according to the address, and receives the received signal according to the rearrangement order parameter B (t). The signals are rearranged, and the rearranged received signals are output to the # 1 to #P element decoders 7.
Also, the received signal is read from the parity 1 memory 2, the received signal is applied to the # 1 to #P element decoder 7, the external information is read from the external information memory 4, and the external information is converted to # 1 to #P. To the element decoder 7.
Upon receiving the received signal and the external information from the memory interface 5, the # 1 to #P element decoders 7 receive the end path metric value F1 stored in the internal memory (the non-interleaved sequence forward processing in the first iteration). Is read out, and the end path metric value F1 is set as an initial value for forward processing.
Then, forward processing is performed on the received signal using the external information to calculate a decoding result and a path metric value in the interleaved forward direction.
The element decoders # 1 to #P use the path metric value as the end path metric value F1, and update the end path metric value F1 stored in the internal memory (the end metric stored in the internal memory). The newly calculated path metric value is overwritten on the path metric value F1).

Next, the control unit 6 calculates the rearrangement order parameter B (t) using the above equation (5) in order to perform the reverse processing of the non-interleaved sequence in the second iteration, and the rearrangement order parameter. B (t) and an address indicating the position of the non-interleaved sequence in the reverse direction are output to the memory interface 5.
When the memory interface 5 receives the address and the rearrangement order parameter B (t) from the control unit 6, the memory interface 5 reads the received signal from the information memory 1 according to the address, and receives the received signal according to the rearrangement order parameter B (t). The signals are rearranged, and the rearranged received signals are output to the # 1 to #P element decoders 7.
Also, the received signal is read from the parity 1 memory 2, the received signal is applied to the # 1 to #P element decoder 7, the external information is read from the external information memory 4, and the external information is converted to # 1 to #P. To the element decoder 7.
Upon receiving the received signal and the external information from the memory interface 5, the # 1 to #P element decoders 7 receive the end path metric value B1 stored in the internal memory (reverse processing of the non-interleaved sequence in the first iteration) Is read out, and the end path metric value B1 is set as the initial value of the backward processing.
Then, using the external information, reverse processing is performed on the received signal to calculate a decoding result and a non-interleaved reverse path metric value.
The element decoders # 1 to #P update the end path metric value B1 stored in the internal memory with the path metric value as the end path metric value B1.
Further, external information is calculated using the path metric value in the non-interleaved reverse direction, and the external information is stored in the external information memory 4.

Next, the control unit 6 calculates the address A (t) and the rearrangement order parameter B (t) using the above equation (4) in order to perform the forward process of the interleave sequence in the second iteration. The address A (t) and the rearrangement order parameter B (t) are output to the memory interface 5.
Upon receiving the address A (t) and the rearrangement order parameter B (t) from the control unit 6, the memory interface 5 reads the received signal from the information memory 1 according to the address A (t), and the rearrangement order parameter B The received signals are rearranged according to (t), and the rearranged received signals are output to the # 1 to #P element decoders 7.
Also, the received signal is read from the parity 2 memory 3, the received signal is given to the # 1 to #P element decoder 7, the external information is read from the external information memory 4, and the external information is sent from # 1 to #P. To the element decoder 7.
Upon receipt of the received signal and external information from the memory interface 5, the # 1 to #P element decoders 7 receive the end path metric value F2 stored in the internal memory (in the first iteration of the interleaved sequence forward processing). The calculated end path metric value F2) is read, and the end path metric value F2 is set as the initial value of the forward processing.
Then, forward processing is performed on the received signal using the external information to calculate a decoding result and a path metric value in the interleaved forward direction.
The element decoders # 1 to #P update the end path metric value F2 stored in the internal memory with the path metric value as the end path metric value F2.

Next, the control unit 6 calculates the address A (t) and the rearrangement order parameter B (t) using the above equation (5) in order to perform the backward processing of the interleaved sequence in the second iteration. The address A (t) and the rearrangement order parameter B (t) are output to the memory interface 5.
Upon receiving the address A (t) and the rearrangement order parameter B (t) from the control unit 6, the memory interface 5 reads the received signal from the information memory 1 according to the address A (t), and the rearrangement order parameter B The received signals are rearranged according to (t), and the rearranged received signals are output to the # 1 to #P element decoders 7.
Also, the received signal is read from the parity 2 memory 3, the received signal is given to the # 1 to #P element decoder 7, the external information is read from the external information memory 4, and the external information is sent from # 1 to #P. To the element decoder 7.
Upon receipt of the received signal and external information from the memory interface 5, the # 1 to #P element decoders 7 receive the end path metric value B2 stored in the internal memory (reverse processing of the interleaved sequence in the first iteration). The calculated end path metric value B2) is read, and the end path metric value B2 is set as the initial value of the backward processing.
Then, using the external information, reverse processing is performed on the received signal to calculate a decoding result and a path metric value in the interleave reverse direction.
The # 1 to #P element decoders 7 update the end path metric value B2 stored in the internal memory using the path metric value as the end path metric value B2.
Further, external information is calculated using the path metric value in the reverse direction of interleaving, and the external information is stored in the external information memory 4 of # 1 to #P.

Thereafter, similarly to the second iteration, the non-interleaved forward process and backward process and the interleaved forward process and backward process are repeated a predetermined number of times.
When the # 1 to #P element decoders 7 are repeatedly executed a predetermined number of times, they output the finally calculated decoding result.

  As apparent from the above, according to the second embodiment, memory access depending on the interleave sequence can be obtained sequentially with a simple calculation, so that a memory for holding the interleave sequence becomes unnecessary. There is an effect that the amount of memory and the circuit scale can be reduced.

In the second embodiment, the element decoder 7 performs forward processing and backward processing in order. However, the element decoder 7 performs forward processing and backward processing at the same time. May be.
However, when the element decoder 7 performs the forward processing and the backward processing simultaneously, if the length W of the parallelization unit is an odd number, the start of either the forward processing or the backward processing is advanced by one step. Alternatively, it is delayed by one step.

That is, when the element decoder 7 performs forward processing and backward processing at the same time, the forward processing proceeds while storing the path metric value from the beginning of the unit, and the backward processing starts with the path metric value from the end of the unit. Proceed while saving.
Since the trellises that have advanced from both directions cross each other, the mutual path metric values can be read out, so that external information can be calculated.
However, if the length W of the parallelization unit is an odd number, the start of either the forward process or the backward process is delayed by one step or delayed by one step.
The reason is that when the parallelization unit length W is an odd number, the positions at which the trellis crosses are the same, so that there is a position where no path metric value is stored, and external information is calculated. Because you can't.
By delaying any start by one step or delaying one step, external information can be calculated in any case without contradiction to the processing timing.

Embodiment 3 FIG.
FIG. 5 is a block diagram showing a turbo code decoding apparatus according to Embodiment 3 of the present invention. In the figure, a parallel turbo decoder 10 is a turbo code decoding apparatus corresponding to FIG. 1 or FIG.
The decoding scheme control unit 11 determines the parallel number P of the element decoders 7 according to the information length K of the turbo code, controls the element decoders 7 for the parallel number, and responds to the information length K of the turbo code. Thus, the number of repetitions I and the margin width M of the forward processing and the backward processing in the element decoder 7 are controlled. The decoding scheme control unit 11 constitutes a control means.
FIG. 7 is a flowchart showing the processing contents of the turbo code decoding apparatus according to Embodiment 3 of the present invention.

Next, the operation will be described.
In order to increase the speed of the turbo code decoding process, a method of increasing the operation clock or a method of increasing the parallel number P of the element decoders 7 can be considered.
However, when using a method of increasing the operation clock, for example, power consumption and device cost increase.
Therefore, in this third embodiment, a method of increasing the parallel number P of the element decoders 7 is adopted, and a decoding method suitable for the processing speed required by the system is selected according to the information length K, which is effective for implementation. Set the operating clock within a certain range.

For example, when the sliding window method is adopted as a turbo code decoding method, if the information length K is short, the margin width M becomes a width close to the information length K, and throughput (bits / sec: bits to be decoded within a unit time) Number) is significantly reduced.
In the decoding process of the turbo code, W steps are required for the forward process and the reverse process, respectively, and (W + W) × 2 × I steps are required in consideration of the non-interleaved and interleaved decoding repetition count I. However, tail bit processing is not considered here for the sake of simplicity.
Considering the margin width M in the forward processing and the backward processing, the required number of steps is (W + M + W + M) × 2 × I steps. When W is small, the influence of the margin width M is large.

FIG. 6 is a graph showing the result of the comparison simulation of the decoding performance depending on the difference between the information length K and the decoding repetition count I.
In FIG. 6, the horizontal axis represents the information length K, and the vertical axis represents Eb / N0 [dB] at which the block error rate BLER (Block Error Rate) reaches 1%.
The turbo code uses a turbo code defined by the standard of “3GPP TS36212”, and the code length is 3K + 12.
As a simulation condition, an additive white Gaussian channel and BPSK modulation are assumed, and the “Max Log MAP decoding method” is used for decoding the turbo code.
The decoding performance increases as the number of repetitions I increases, and the performance difference increases as the information length K increases. In the decoding of the turbo code that performs repetition, the number of repetitions required to converge to a correct result depends on the information length K. When the information length K is short, it converges with a smaller number of repetitions than when the information length K is long.

As described above, the characteristics of turbo code decoding vary greatly depending on the information length K.
In the third embodiment, the parallel number P of the element decoders 7, the margin width M, and the number of decoding repetitions according to the information length K so as to satisfy the processing speed required in the communication system and obtain high decoding performance. I is controlled.
For example, in the graph of FIG. 6, if the communication performance using the turbo code is acceptable up to a deterioration of about 0.5 dB with respect to 8 repetitions, the number of repetitions is 2 when the information length K is less than 100 bits. When the information length K is less than 1000 bits, the number of repetitions is 3 times, and when the information length K is 1000 bits or more, the number of repetitions is 4 times.

Hereinafter, the processing content of the turbo code decoding apparatus will be described with reference to FIG.
In the third embodiment, the parallel number P and the margin width M of the element decoders 7 set in advance to satisfy the processing speed required by the communication system are tabulated, and the table is used as the decoding scheme control unit 11. Is held in.
When receiving the information length K (step ST1), the decoding scheme control unit 11 reads the parallel number P and the margin width M of the element decoder 7 from the held table, and sets the parallel number P and the margin width M. (Steps ST2 and ST3). However, the parallel number P and the margin width M are set to values equal to or less than the maximum value of the mounted circuit.

Next, the decoding scheme control unit 11 sets the decoding repetition count I. The number of decoding iterations I is set to the maximum value satisfying the system request from the number of steps and the operation clock.
Note that the number of decoding iterations I may be reduced by reducing the number of iterations until the decoding performance required by the system is satisfied.
The decoding method control unit 11 performs turbo decoding with the setting contents set by the decoding method control unit 11 (steps ST5 and ST6), and outputs the decoding result (step ST7).

As is apparent from the above, according to the third embodiment, the parallel number P of the element decoder 7, the number of repetitions I of forward processing and backward processing, and the margin width M according to the information length K of the turbo code. Therefore, it is possible to satisfy the processing speed required by the communication system for all the information lengths K possessed by the communication system.
Since the operation time of the decoding circuit is proportional to the number of decoding iterations I, the effect of reducing power consumption can be enhanced by controlling the number of iterations I according to the decoding performance required by the communication system. In addition, since the system requirements are satisfied with an operation clock within a range effective for implementation, development costs can be suppressed.

Embodiment 4 FIG.
FIG. 8 is a block diagram showing a communication system according to Embodiment 4 of the present invention. The communication system is composed of a transmission device 20 and a reception device 30.
In the figure, the transmitting apparatus 20 has a turbo encoder 21 using QPP as an internal interleaver, and uses the turbo encoder 21 to turbo-encode an information source to generate a turbo code, The turbo code is modulated and a modulated wave is transmitted.
The receiving device 30 is mounted with the turbo code decoding device 31 of FIG. 1, FIG. 3 or FIG. 5, receives the modulated wave transmitted from the transmitting device 20, and demodulates the turbo code from the modulated wave. The decoder 31 is used to decode the turbo code.
Note that the communication path between the transmission device 20 and the reception device 30 may be wireless or wired, and can be applied to all digital communication systems using turbo codes.
FIG. 9 is a flowchart showing the processing contents of the communication system according to Embodiment 4 of the present invention.

Next, the operation will be described.
For example, when an information source that is packet data to be subjected to data communication is input (step ST11), the transmitting device 20 uses the turbo encoder 21 that is installed to turbo-encode the information source, (Turbo coded sequence) is generated (step ST12).
When generating the turbo code, the transmission device 20 modulates the turbo code and transmits the modulated wave (step ST13).
In the communication path, noise is added to the modulated wave according to the propagation environment.

The receiving device 30 receives the modulated wave transmitted from the transmitting device 20 (step ST14), and demodulates the turbo code by performing synchronous detection processing and demodulation processing on the modulated wave.
When demodulating the turbo code, receiving apparatus 30 uses the turbo code decoding apparatus of FIG. 1, FIG. 3, or FIG. 5 to decode the turbo code (step ST15), and outputs the decoding result to, for example, a reproduction apparatus. .
As a result, the reproduction device performs reproduction processing of the decoding result (step ST16), and the information source is reproduced.

  According to the fourth embodiment, since the receiving device 30 is equipped with the turbo code decoding device 31 of FIG. 1, FIG. 3 or FIG. 5, the communication system maintains a stable communication speed with respect to the information length K. Thus, the power consumption and circuit scale of the receiving device 30 can be reduced.

Embodiment 5 FIG.
10 is a block diagram showing a communication system according to Embodiment 5 of the present invention. The communication system includes a mobile terminal 40 corresponding to the transmission apparatus 20 in FIG. 8 and a base station 50 corresponding to the reception apparatus 30 in FIG. It consists of and.
In the figure, a mobile terminal 40 is equipped with a turbo encoder 41 defined by the “3GPP TS36.212” standard, and the turbo encoder 41 is used to turbo-encode an information source to turbocharge the information source. A code is generated, the turbo code is modulated, and a modulated wave is transmitted.
In the mobile terminal 40, among the data to be transmitted to the base station 50, a data sequence assigned to a channel (for example, Uplink Shared Channel) using a turbo code is turbo-coded, and the turbo code is generated and transmitted. To do.
The base station 50 is mounted with the turbo code decoding device 51 of FIG. 1, FIG. 3, or FIG. 5, receives the modulated wave transmitted from the mobile terminal 40, and demodulates the turbo code from the modulated wave. The code decoding device 51 is used to decode the turbo code.

  Also in the case of the fifth embodiment, since the base station 50 is mounted with the turbo code decoding device 51 of FIG. 1, FIG. 3 or FIG. 5, the communication system has the information length K as in the fourth embodiment. On the other hand, a stable communication speed can be maintained, and the power consumption and circuit scale of the base station 50 can be suppressed.

  In the first to fifth embodiments, the turbo code decoding device decodes the turbo code when performing wireless communication. However, the present invention is not limited to this, and general digital information processing is performed. In doing so, the turbo code decoding device may decode the turbo code.

Embodiment 6 FIG.
In the first to fifth embodiments, when the decoding process is parallelized, the control unit 6 sequentially calculates the memory number B (t) and the address A (t) of the information memory 1 accessed by the memory interface 5. It was. FIG. 11 is a block diagram showing the turbo code decoding apparatus according to Embodiments 1 to 5, and particularly shows the internal configuration of the control unit 6 in detail. Although described as the control unit 6 in the first to fifth embodiments (FIGS. 1 and 3), the control unit (sequence generation means) 6 is an interleave address generation table for calculating the address A (t). 61, an address generation unit 62, an information selection control unit 63 for calculating a memory number B (t), a memory selection initial table 65, and an operation control unit 64 for controlling the operations of these units.

For example, when realizing the decoding process of the first embodiment, the interleave address generation table 61 holds the coefficients f1 and f2 specific to the information length in the second order polynomial (1) for determining the interleave. The interleave address generation table 61 also holds information α-specific parameters α (0) and δ necessary for the sequential calculation of the address A (t). At the time of interleaving, the address generation unit 62 calculates an expression (4) or an expression (5) using a coefficient and a parameter corresponding to the information length K held in the interleave address generation table 61 to obtain an address A (t). .
The memory selection initial table 65 includes parameters B (0), B (W), B (2W),..., B ((P− 1) × W), β (0), β (W), β (2W),..., Β ((P−1) × W), γ are held. The information selection control unit 63 calculates the equation (4) or (5) using the parameters held in the memory selection initial table 65 to obtain the memory number B (t). Then, the memory interface 5 generates an interleaved sequence according to the memory number B (t) and the address A (t) and passes it to the element decoder (decoding means) 7. The memory interface 5 also performs a process of outputting the external information series output from the element decoder 7 to the external information memory 4.
The operation control unit 64 initializes the number of repetitions of forward processing and backward processing and memory access, and initializes path metric calculation in the element decoder 7. However, in the third embodiment, the operation control unit 64 corresponds to the decoding method control unit 11.

In the case of this configuration, the control unit 6 includes the memory selection initial table 65, and the information selection control unit 63 sequentially calculates the memory number B (t) using the parameters of the memory selection initial table 65. In this configuration, a memory selection initial table 65 corresponding to a memory for storing parameters is required.
Therefore, in the sixth embodiment, the information selection control unit (information selection control means) 66 of the control unit 6 uses the value of the interleave address generation table 61 instead of the parameter of the memory selection initial table 65 to change the memory number B (T) is obtained.

FIG. 12 is a block diagram showing a turbo code decoding apparatus according to Embodiment 6 of the present invention. The same or corresponding parts as those in FIGS. Here, it is assumed that the information length of the information sequence is N and the parallel number of the element decoders 7 is M.
In this case, the length of the parallelized unit processed in parallel by the M element decoders 7 is W = N / M, and the number of addresses is also N / M.

FIG. 13 is an explanatory diagram schematically showing a memory configuration of the information memory 1 and a memory access method during interleaving. FIG. 13 shows a configuration in which the information length N is 32 and the parallel number M is 4 as an example. In this case, four element decoders 7 are mounted in the turbo code decoding device, and four information memories 1, parity 1 memories 2, parity 2 memories 3 and external information memories 4 are also mounted. The memory interface 5 receives the received information sequence, the parity 1 sequence, the parity 2 sequence, and the external information sequence from the address 0 of the information memory 1, the parity 1 memory 2, the parity 2 memory 3, and the external information memory 4 in order from the address N / M- Store up to 1.
At the time of interleaving, the correspondence changes between the information memory 1 and the element decoder 7 to which the data written in the information memory 1 is transferred, so that the data must be rearranged. In FIG. 13, data rearrangement is performed using a memory number B (t) obtained from Expression (10) described later.

When the interleave address of the data stored in the information memory 1 in the t-th stage in the parallel stage number M is π (t), the data to be simultaneously decoded by the element decoder 7 when the interleaver satisfies the following formula (6) Since the combination is the same for non-interleaving and interleaving, a plurality of pieces of data to be simultaneously processed are stored as one word in one address of one memory, and can be read and written.
π (t + k × N / M) = π (t) + k × fx × N / M mod N (6)
Here, t = 0, 1,..., N / M−1, k = 0, 1,.
At this time, the memory number B (t) and the address (t) of the information memory 1 to be accessed when the M element decoders 7 perform parallel processing are expressed as follows.
B (t) = ceil (π (t) / W) (7)
A (t) = π (t) mod W (8)
Here, t = 0, 1,..., W−1, W = N / M, and M is a divisor of N.

Therefore, if the address generation unit 62 and the information selection control unit 66 of the control unit 6 calculate the equations (6) to (8), the memory number B (t) and the address A (t) can be obtained. In calculations (6) to (8), multiplication and mod (remainder) calculation are required, and the complexity of implementation is high.
Therefore, in the sixth embodiment, the controller 6 sequentially calculates the address A (t) by simple calculation as in the first to fifth embodiments, and the memory number B (t) is also calculated by the address calculation. It is made to calculate using the parameter for this.

As shown in FIG. 12, the control unit 6 includes an interleave address generation table 61, an address generation unit 62, an information selection control unit 66, and an operation control unit 64. The interleave address generation table 61, the address generation unit 62, and the operation control unit 64 are the same as those shown in FIG.
Note that the interleave address generation table 61 in FIG. 11 holds the coefficients f1 and f2 according to the information length K. However, the interleave address generation table 61 in this embodiment holds the coefficient fx according to the information length N. It shall be.

The information selection control unit 66 uses the coefficient fx of the interleave address generation table 61 to calculate the remaining memory number (arrangement order of the turbo code storage means) based on any one of the memory numbers # 1 to #M. Obtained by sequential operation and output to the memory interface 5.
In this embodiment, since the interleave address is expressed by the following equation (9), the memory number B (t) of the information memory 1 accessed by the memory interface 5 is set in the information selection control unit 66 as shown below. It can be obtained by sequential operations in the forward direction.
π (t + W) = π (t) + fx × W (9)
B (t) = A + (k−1) × fx mod M (10)
Here, A is one memory number B (t) used as a reference, and the data stored in the information memory 1 of this memory number B (t) is passed to the # 1 element decoder 7 in the first process. . However, the reference memory number A is an arbitrary value, and may be any of # 1 to #M.
For example, when the element decoder 7 of # 1 receives data from the information memory 1 of #A (A = 1, 2,..., M), the element decoder 7 of # 2 receives # (A + fx) ( data is received from the information memory 1 of (mod M). Similarly, the #k element decoder 7 receives data from the information memory 1 of # (A + (k−1) × fx) (mod M).

  As described above, the information selection control unit 66 calculates the equation (10) when obtaining the interleave sequence for the forward processing. As in the forward processing, the information selection control unit 66 uses the fx of the interleave address generation table 61 to determine one item. Based on the memory number, the remaining memory number B (t) in the backward processing can also be obtained.

  FIG. 14 is a flowchart showing the processing contents of the turbo code decoding apparatus according to the sixth embodiment. The method by which the address generation unit 62 (control unit 6) calculates the address A (t) is the same as that in the first to fifth embodiments, and thus the description thereof is omitted below. In FIG. 14, in order to clarify parallel processing, the number of parallel processes is represented by M, and forward processing and backward processing are represented by # 1 to #M.

  First, the operation control unit 64 initializes the number of repetitions of forward processing and reverse processing and initial settings of memory access, and initializes the path metric value stored in the memory of the element decoder 7. Further, the operation control unit 64 sets parameters (α (0), δ) specific to the information length in the interleave address generation table 61 as parameters relating to the generation of the interleave sequence π (t).

Reading from the information memory 1 is an orderly access in a non-interleaved access. That is, in order to perform forward processing or reverse processing of a non-interleaved sequence, the address generation unit 62 receives an address indicating the position of a forward or reverse non-interleaved sequence to be given to the # 1 to #M element decoders 7 as information The selection control unit 66 outputs the memory numbers to the memory interface 5 respectively.
When the memory interface 5 receives the address from the address generation unit 62 and the memory number from the information selection control unit 66, the memory interface 5 reads the received signals from the information memories 1 of # 1 to #M according to the address and the memory number, Each received signal is supplied to the # 1 to #M element decoder 7.
On the other hand, the access during interleaving is random access according to an interleave sequence. That is, in order to perform forward processing or backward processing of the interleaved sequence, the address generation unit 62 uses the calculation formulas related to A (t) and α (t) in Expression (4) or Expression (5) to calculate the address A (t ) And the address A (t) is output to the memory interface 5. Further, the information selection control unit 66 calculates the memory number B (t) using the equation (10), and outputs the memory number B (t) to the memory interface 5.
When the memory interface 5 receives the address A (t) from the address generation unit 62 and the memory number B (t) from the information selection control unit 66, the memory interface 5 ## according to the address A (t) and the memory number B (t). The received signals are respectively read from the 1 to #M information memories 1 and given to the # 1 to #M element decoder 7.

Further, the reading from the parity 1 memory 2 and the parity 2 memory 3 is always performed in the same order in both interleaving and non-interleaving as in the first to fifth embodiments. That is, at the time of non-interleaved decoding, the memory interface 5 reads out the received signals corresponding to the parity 1 series from the parity 1 memory 2 of # 1 to #M, and converts each received signal into the element decoder 7 of # 1 to #M. To give.
On the other hand, at the time of interleaving decoding, the memory interface 5 reads out the received signals corresponding to the parity 2 series from the parity 2 memory 3 of # 1 to #M, and sends the received signals to the element decoder 7 of # 1 to #M. give.
Note that the process of decoding turbo codes by the # 1 to #M element decoders 7 is the same as in the first to fifth embodiments, and a description thereof will be omitted.

  14 shows an example in which iterative decoding is performed in the order of non-interleaving, interleaving, non-interleaving, interleaving,..., Non-interleaving, and interleaving, but non-interleaving and interleaving may be in reverse order. Further, the processing is performed in the order of the forward direction, the reverse direction, the forward direction, and the reverse direction, but the forward direction and the reverse direction may be reversed.

As is apparent from the above, according to the sixth embodiment, the control unit 6 includes the interleave address generation table 61 that holds in advance the coefficient fx corresponding to the information length N of the turbo code, and the interleave address generation table 61. Using the coefficient fx stored in the information memory 1 for the number of parallel M, and the coefficient fx stored in the interleave address generation table 61 to determine the address of each data stored in the information memory 1 An information selection control unit 66 for determining the arrangement order of the information memory 1, and data stored in the information memory 1 is read in the arrangement order determined by the information selection control unit 66, and the address determined by the address generation unit 62 And a memory interface 5 for generating an interleaved sequence by reading from. Therefore, as in the first to fifth embodiments, memory access depending on the interleaved sequence can be obtained sequentially with a simple calculation, so that a memory for holding the interleaved sequence becomes unnecessary, and the amount of memory and The circuit scale can be kept small.
In addition, since the information selection control unit 66 generates the memory number using the information stored in the interleave address generation table 61, a memory corresponding to the memory selection initial table 65 of the first to fifth embodiments is unnecessary. As a result, the memory amount and circuit scale can be further reduced.

In the sixth embodiment, the element decoder 7 performs forward processing and backward processing in order. However, the element decoder 7 performs forward processing and backward processing at the same time. May be.
That is, when the element decoder 7 performs forward processing and backward processing at the same time, the forward processing proceeds from the beginning of the parallelization unit while saving the path metric value, and the backward processing is performed at the end of the parallelization unit. The process proceeds while saving the path metric value from.
Since the trellises that have advanced from both directions cross each other, the mutual path metric values can be read out, so that external information can be calculated.

Embodiment 7 FIG.
In Embodiment 6 described above, the turbo code decoding apparatus using an interleaved sequence generated by a general polynomial is shown. However, in the turbo code decoding apparatus shown in FIG. 12, a second-order polynomial is used instead of the general polynomial. A QPP method may be adopted, and the number of parallel stages M may be four or two. Hereinafter, a configuration in which the number M of parallel stages is four will be described.
In this case, if the information length is N, the t-th interleave sequence π (t) of the QPP interleaver is expressed by the following equation (11).
π (t) = f1 × t + f2 × t × t mod N (11)
However, f1 is an odd constant, and f2 is an even constant.
At this time, the memory number B (t) and the address (t) of the information memory 1 to be accessed when the four element decoders 7 perform parallel processing are expressed as follows.
B (t) = ceil (π (t) / W) (12)
A (t) = π (t) mod W (13)
Here, t = 0, 1,..., W−1, W = N / M, and M is a divisor of N.

Therefore, if the address generation unit 62 and the information selection control unit 66 of the control unit 6 calculate the equations (11) to (13), the memory number B (t) and the address A (t) can be obtained. In the calculations of (11) to (13), multiplication and mod (remainder) calculation are required, and the complexity of implementation is high.
Therefore, in the seventh embodiment, the memory number B (t) and the address A (t) are sequentially calculated as in the first to sixth embodiments. When calculating the access address A (t), α (t) is prepared as an auxiliary parameter.

However, since the following parameters α (0) and δ have a large calculation amount, they are stored in the interleave address generation table 61 in advance.
α (0) = f1 + f2 mod W
δ = 2 × f2 mod W
Note that a large amount of memory is not required for calculating the parameters α (0) and δ and holding the calculated values.

The address A (t) of the information memory 1 accessed by the memory interface 5 can be obtained by sequential operation in the forward direction in the address generation unit 62 as shown below.
[Update of α (t)] α (t + 1) = α (t) + δ
If (α (t + 1) ≧ W)
α (t + 1) = α (t + 1) −W
[Update of A (t)] A (t + 1) = A (t) + α (t)
If (A (t + 1) ≧ W)
A (t + 1) = A (t + 1) −W
(14)
The address generation unit 62 calculates the above equation (14) at the time of interleaving to obtain the address A (t), and at the time of non-interleaving, the address generating unit 62 may change the address A (t) one by one from the initial position.

Further, the memory number B (t) of the information memory 1 accessed by the memory interface 5 can be obtained by sequential operation in the forward direction in the information selection control unit 66 as shown below.
B (t) = A + (k−1) × f1 mod M (15)
Here, A is one memory number B (t) used as a reference, and the data stored in the information memory 1 of this memory number B (t) is passed to the # 1 element decoder 7 in the first process. . However, the reference memory number A is an arbitrary value and may be any of # 1 to # 4, and the equation (12) may be calculated as in the past.
For example, when the # 1 element decoder 7 receives data from the information memory 1 #A (A = 1, 2,..., M), the # 2 element decoder 7 # (A + f1) ( data is received from the information memory 1 of (mod M). Similarly, the # 3 element decoder 7 uses the # (A + 2 × f1) (mod M) information memory 1, and the # 4 element decoder 7 uses the # (A + 3 × f1) (mod M) information memory 1. 1 receives data from each.
In this embodiment, parallel processing is performed in which the number M of parallel stages is four. In this case, the remainder obtained by dividing the value of the coefficient f1 by 4 becomes an odd number, and there are cases of 1 and 3. FIG. 15 shows a pattern of the memory number B (t) that the element decoder 7 accesses through the memory interface 5 in the case of the remainders 1 and 3. FIG. 15 shows the correspondence between the # 1 to # 4 element decoders 7 that perform parallel processing and the # 1 to # 4 information memories 1 that pass data to the element decoder 7.

Further, the address A (t) of the information memory 1 accessed by the memory interface 5 can be obtained by sequential operation in the reverse direction in the address generation unit 62 as shown below.
[Update of α (t)] If (α (t) ≧ δ)
α (t−1) = α (t) −δ
Else
α (t−1) = α (t) + W−δ
[Update of A (t)] If (A (t) ≧ α (t−1))
A (t−1) = A (t) −α (t−1)
Else
A (t-1) = A (t) + W- [alpha] (t-1)
(16)
The address generator 62 calculates the above equation (16) at the time of interleaving to obtain the address A (t), and at the time of non-interleaving, the address generating unit 62 may change the address A (t) one by one from the initial position.

  The memory number B (t) of the information memory 1 accessed by the memory interface 5 is also stored in one memory by the information selection control unit 66 using f1 of the interleave address generation table 61 in the same manner as the forward sequential operation. Based on the number, it can be obtained by sequential operation in the reverse direction.

  Hereinafter, a process in which the control unit 6 controls the memory interface 5 to generate an interleaved sequence and a non-interleaved sequence in order and the element decoder 7 decodes the turbo code will be described with reference to FIG.

  First, the operation control unit 64 initializes the number of repetitions of forward processing and reverse processing and initial settings of memory access, and initializes the path metric value stored in the memory of the element decoder 7. Further, the operation control unit 64 sets parameters (α (0), δ) specific to the information length in the interleave address generation table 61 as parameters relating to the generation of the interleave sequence π (t).

Reading from the information memory 1 is an orderly access in a non-interleaved access. That is, in order to perform forward processing or reverse processing of a non-interleaved sequence, the address generation unit 62 receives an address indicating the position of a forward or reverse non-interleaved sequence to be given to the element decoders 7 of # 1 to # 4 as information The selection control unit 66 outputs the memory numbers to the memory interface 5 respectively.
When the memory interface 5 receives the address from the address generation unit 62 and the memory number from the information selection control unit 66, the memory interface 5 reads the received signal from the information memories 1 of # 1 to # 4 according to the address and the memory number, Each received signal is given to the element decoder 7 of # 1 to # 4.
On the other hand, the access during interleaving is random access according to an interleave sequence. That is, in order to perform forward processing or backward processing of the interleave sequence, the address generation unit 62 calculates the address A (t) using the equation (14) or the equation (16), and stores the address A (t) in the memory. Output to interface 5. Further, the information selection control unit 66 calculates the memory number B (t) using the equation (15), and outputs the memory number B (t) to the memory interface 5.
When the memory interface 5 receives the address A (t) from the address generation unit 62 and the memory number B (t) from the information selection control unit 66, the memory interface 5 ## according to the address A (t) and the memory number B (t). The received signals are read from the information memories 1 to # 4, respectively, and are supplied to the element decoders 7 to # 1 to # 4.

In addition, reading from the parity 1 memory 2 and the parity 2 memory 3 is always performed in the order both in interleaving and non-interleaving. That is, at the time of non-interleaved decoding, the memory interface 5 reads out received signals corresponding to the parity 1 series from the parity 1 memory 2 of # 1 to # 4, and converts each received signal into the element decoder 7 of # 1 to # 4. To give.
On the other hand, at the time of interleaving decoding, the memory interface 5 reads out the received signals corresponding to the parity 2 series from the parity 2 memory 3 of # 1 to # 4, and sends the received signals to the element decoder 7 of # 1 to # 4. give.
The process of decoding turbo codes by the # 1 to # 4 element decoders 7 is the same as in the first to fifth embodiments, and a description thereof will be omitted.

As is apparent from the above, according to the seventh embodiment, the turbo code decoding apparatus adopts the QPP method as the turbo code interleaver, sets the parallel number to 2 or 4, and the information selection control unit 66 generates the interleave address. The arrangement order of the information memories 1 is determined based on the memory number of one information memory 1 using the coefficient f1 corresponding to the information length N held in the table 61. Therefore, as in the first to sixth embodiments, the memory access depending on the interleaved sequence can be obtained sequentially with a simple calculation, so that a memory for holding the interleaved sequence becomes unnecessary, the amount of memory and The circuit scale can be kept small.
In addition, since the information selection control unit 66 generates the memory number using the information stored in the interleave address generation table 61, the memory selection in the first to fifth embodiments is also performed in the turbo code decoding apparatus using the QPP method. A memory corresponding to the initial table 65 becomes unnecessary, and the memory amount and circuit scale can be further reduced.

In the seventh embodiment, the element decoder 7 performs forward processing and backward processing in order. However, the element decoder 7 performs forward processing and backward processing at the same time. May be.
That is, when the element decoder 7 performs forward processing and backward processing at the same time, the forward processing proceeds from the beginning of the parallelization unit while saving the path metric value, and the backward processing is performed at the end of the parallelization unit. The process proceeds while saving the path metric value from.
Since the trellises that have advanced from both directions cross each other, the mutual path metric values can be read out, so that external information can be calculated.

  Further, the turbo code decoding apparatus according to the sixth and seventh embodiments may be applied to the parallel turbo decoder 10 (FIG. 5) according to the third embodiment, or the receiving apparatus 30 according to the fourth embodiment. (FIG. 8) may be mounted, and furthermore, it may be mounted on the base station 50 (FIG. 10) according to the fifth embodiment. Even if it is a case where it is set as such a structure, there exists the effect mentioned above.

It is a block diagram which shows the turbo code decoding apparatus by Embodiment 1 of this invention. It is a flowchart which shows the processing content of the turbo code decoding apparatus by Embodiment 1 of this invention. It is a block diagram which shows the turbo code decoding apparatus by Embodiment 2 of this invention. It is explanatory drawing which shows the procedure which rearranges in order to pass the read nxP bit to P element decoders. It is a block diagram which shows the turbo code decoding apparatus by Embodiment 3 of this invention. It is a graph which shows the result of the comparison simulation of the decoding performance by the difference in the information length K and the decoding repetition frequency I. It is a flowchart which shows the processing content of the turbo code decoding apparatus by Embodiment 3 of this invention. It is a block diagram which shows the communication system by Embodiment 4 of this invention. It is a flowchart which shows the processing content of the communication system by Embodiment 4 of this invention. It is a block diagram which shows the communication system by Embodiment 5 of this invention. It is a block diagram which shows the turbo code decoding apparatus which concerns on Embodiment 1-5 of this invention, and shows a control part in detail especially. It is a block diagram which shows the turbo code decoding apparatus by Embodiment 6 of this invention. It is explanatory drawing which shows typically the memory structure of the information memory 1 of the turbo code decoding apparatus by Embodiment 6 of this invention, and the memory access method at the time of interleaving. It is a flowchart which shows the processing content of the turbo code decoding apparatus by Embodiment 6 of this invention. The pattern of the memory number which the memory interface 5 accesses in the turbo code decoding apparatus by Embodiment 7 of this invention is shown.

Explanation of symbols

  1 information memory (turbo code storage means), 2 parity 1 memory (turbo code storage means), 3 parity 2 memory (turbo code storage means), 4 external information memory (turbo code storage means), 5 memory interface (sequence generation means) ), 6 control unit (sequence generation unit), 7 element decoder (decoding unit), 10 parallel turbo decoder, 11 decoding scheme control unit (control unit), 20 transmission device, 21 turbo encoder, 30 reception device , 31 Turbo code decoder, 40 Mobile terminal, 41 Turbo encoder, 50 Base station, 51 Turbo code decoder, 61 Interleave address generation table, 62 Address generator, 63, 66 Information selection controller, 64 Operation control 65, memory selection initial table.

Claims (14)

Turbo code storage means for dividing a turbo code received sequence into a number of parallel numbers and storing it,
Sequence generating means for generating an interleaved sequence and a non-interleaved sequence of turbo codes stored by the turbo code storing unit ;
In a turbo code decoding apparatus comprising: a parallel number of decoding means for decoding turbo codes in parallel by repeatedly performing forward processing and backward processing on interleaved sequences and non-interleaved sequences generated by the sequence generating means ,
The series generation means includes
A memory selection initial table holding parameters for determining the arrangement order of the turbo code storage means;
An interleave address generation table that holds in advance a coefficient corresponding to the information length of a turbo code in a polynomial for generating an interleave sequence;
Using the parameters held in the memory selection initial table and the coefficients held in the interleave address generation table, addition / subtraction processing and comparison calculation processing are performed, and forward processing and backward processing of the turbo code storage means Information selection control means for determining the arrangement order and address;
A memory interface that reads out each data stored in the address of the turbo code storage unit in the arrangement order determined by the information selection control unit and generates an interleaved sequence of forward processing and backward processing; The turbo code decoding apparatus characterized by the above-mentioned.   The control means for determining the parallel number of the decoding means for performing the forward processing and the backward processing according to the information length of the turbo code, and controlling the decoding means for the parallel number. 1. The turbo code decoding device according to 1.   2. The turbo code decoding apparatus according to claim 1, further comprising a control unit that controls the number of repetitions of forward processing and backward processing in the decoding unit in accordance with the information length of the turbo code.   4. The turbo code decoding device according to claim 1, wherein the plurality of decoding units have a function of simultaneously performing forward processing and backward processing. 5.   5. The turbo according to claim 4, wherein the decoding means delays the start of one of the forward process and the backward process by one step ahead or one step when performing the forward process and the backward process simultaneously. Code decoding apparatus.   The sequence generation means generates an interleaved sequence and a non-interleaved sequence of a turbo code defined in the standard of “3GPP TS36.212”, according to any one of claims 1 to 5. Turbo code decoding apparatus.   The turbo code decoding apparatus according to any one of claims 1 to 5, wherein the sequence generation means employs a QPP method as a turbo code interleaver. A sequence generation step in which the sequence generation means generates an interleaved sequence and a non-interleaved sequence of the turbo code; and
A turbo code decoding method comprising: a decoding step in which a plurality of decoding means repeatedly perform forward processing and reverse processing on the interleaved sequence and non-interleaved sequence generated by the sequence generating unit, and decode turbo codes in parallel In
The series generation step includes
A storage step in which the memory interface divides the reception sequence of the turbo code into a number of parallel numbers and stores it in the turbo code storage means;
Parameters for determining the order of arrangement of the turbo code storage means stored in the memory selection initial table in advance by the information selection control means, and polynomials for generating an interleave sequence held in advance in the interleave address generation table Information selection control step for determining the arrangement order and address of the turbo code storage means of forward processing and backward processing by performing addition / subtraction processing and comparison calculation processing using a coefficient corresponding to the information length of the turbo code in When,
An interleaving in which the memory interface reads out each data stored at the address of the turbo code storage means in the arrangement order determined in the information selection control step, and generates an interleave sequence of forward processing and backward processing; A turbo code decoding method comprising: a sequence generation step. A turbo code is generated by turbo-coding an information source, a transmitter that modulates the turbo code and transmits a modulated wave, a modulated wave transmitted from the transmitter is received, and a turbo code is demodulated from the modulated wave In the communication system comprising the receiving device, the receiving device stores turbo code storage means for the number of parallel stores of the demodulated turbo code, and interleave sequences and non-interleaved turbo codes stored by the turbo code storage means. A sequence generation unit that generates a sequence, and a forward number process and a reverse direction process for the interleaved sequence and the non-interleaved sequence generated by the sequence generation unit are repeatedly performed, and a plurality of parallel codes for decoding the turbo code in parallel A turbo code decoding device including decoding means,
The sequence generation means of the turbo code decoding device comprises:
A memory selection initial table holding parameters for determining the arrangement order of the turbo code storage means;
An interleave address generation table that holds in advance a coefficient corresponding to the information length of a turbo code in a polynomial for generating an interleave sequence;
Using the parameters held in the memory selection initial table and the coefficients held in the interleave address generation table, addition / subtraction processing and comparison calculation processing are performed, and forward processing and backward processing of the turbo code storage means Information selection control means for determining the arrangement order and address;
A memory interface that reads out each data stored in the address of the turbo code storage unit in the arrangement order determined by the information selection control unit and generates an interleaved sequence of forward processing and backward processing; communication system, characterized in that.   The communication system according to claim 9, wherein the transmitting device is a mobile terminal and the receiving device is a base station. The information selection control means obtains a parameter for determining the arrangement order of the turbo code storage means using the coefficient held in the interleave address generation table, and performs addition / subtraction processing and comparison calculation processing using the parameter and the coefficient. 2. The turbo code decoding apparatus according to claim 1, wherein the turbo code decoding apparatus determines the arrangement order and addresses of the turbo code storage means for forward processing and backward processing. The turbo code storage means for the parallel number M includes information series and check series data of information length N for each N / M word in order from the head, from address 0 to address N / M− of each turbo code storage means. 1 and store
The information selection control means uses the coefficient fx corresponding to the information length N held in the interleave address generation table when the polynomial that generates the interleave sequence is expressed by the following formula and the coefficient fx is a value that does not depend on t. 12. The turbo code decoding apparatus according to claim 11, wherein the order of arrangement of the turbo code storage means is determined on the basis of one turbo code storage means.
π (t + k × N / M) = π (t) + k × fx × (N / M) mod N
Here, t = 0, 1,..., N / M−1, k = 0, 1,. When QPP method is adopted as an interleaver for turbo code and the parallel number is 2 or 4,
The information selection control means uses a coefficient f1 corresponding to the information length N held in the interleave address generation table as a reference for one turbo code storage means when the polynomial for generating the interleave sequence is expressed by the following equation: 13. The turbo code decoding apparatus according to claim 12, wherein the arrangement order of the turbo code storage means for 2 minutes in parallel or 4 minutes in parallel is determined.
π (t) = f1 × t + f2 × t × t mod N
Here, t = 0, 1,..., N−1, f1 is an odd constant, and f2 is an even constant. In the information selection control step, the information selection control means obtains a parameter for determining the arrangement order of the turbo code storage means using the coefficient held in advance in the interleave address generation table, and uses the parameter and the coefficient. 9. The turbo code decoding method according to claim 8, wherein the addition / subtraction process and the comparison calculation process are executed to determine the arrangement order and address of the turbo code storage means for the forward process and the reverse process.

Images