WO2012155425A1

WO2012155425A1 - Parallel computing method and system of interleaving address

Info

Publication number: WO2012155425A1
Application number: PCT/CN2011/079997
Authority: WO
Inventors: 张彩虹; 陈月强; 马龙龙
Original assignee: 中兴通讯股份有限公司
Priority date: 2011-05-17
Filing date: 2011-09-22
Publication date: 2012-11-22
Also published as: CN102170333B; CN102170333A

Abstract

The invention provides a parallel computing method and a system of an interleaving address. The method comprises the following steps: pre-configuring and storing an interleaving address compression table; receiving the data to be coded, and reading the interleaving address compression table based on the length of a data packet of the data to be coded to acquire the PO value and the intermediate value of interleaving calculation; determining the value of the code parallelism degree K, generating an interleaving address and a read address based on the code parallelism degree, the length of the data packet of the data to be coded, the PO value, and the intermediate value of the interleaving calculation, reading the data to be coded based on the read address, and completing the interleaving operation. According to the technical solution of the invention, the parallel calculation of the interleaving address in an encoder of the WiMAX system can be realized.

Description

Parallel computing method and system for interleaving address

The present invention relates to a Worldwide Interoperability for Microwave Access (WiMAX) system in the field of communications, and more particularly to a parallel computing method and system for interleaving addresses in an encoder. Background technique

In order to resist burst errors during transmission, interleaving techniques are employed in the encoder in WiMAX systems. Since the calculation of the interleaved address is complicated, in order to achieve a higher encoding throughput, the encoding is performed in parallel using the encoding process. The structure of the encoder requires that the inner interleaver can complete the parallel interleaving calculation consistent with the coding parallelism in real time, or store the interleaving address of the code block in advance, and read the stored interleaving address during encoding, thereby obtaining the interleaving address, and completing the interleaving calculation of the data. , coding.

Since the WiMAX system supports up to 17 types of packet lengths and the maximum packet length is 2400 bit pairs, if all the interleaved addresses are stored, 100Kbits of storage space is required, so the storage resources are relatively large, and it is also necessary to search according to the packet length. Different tables, the implementation method is more complicated. Summary of the invention

In view of this, the main object of the present invention is to provide a parallel computing method and system for interleaving addresses, which can implement parallel computing of interleaved addresses in an encoder in a WiMAX system.

In order to achieve the above object, the technical solution of the present invention is achieved as follows:

The present invention provides a parallel computing system for interleaving addresses, including: an interleaving address buffer unit, a pre-processing buffer unit, and a control unit;

An interleave address buffer unit, configured to pre-configure and store an interleave address compression table; The pre-processing buffer unit is configured to receive data to be encoded, and read the interleave address compression table according to the length of the data packet to be encoded to obtain P. Value and interleaving calculate the intermediate value;

The control unit is configured to determine the value of the coding parallelism K, and according to the coding parallelism, the length of the data packet to be encoded, and P. The value and the interleave calculation intermediate value generate an interleave address and a read address, and the data to be encoded is read according to the read address to complete the interleaving operation.

The present invention also provides a parallel computing method for interleaving addresses, including:

Pre-configuring and storing an interleave address compression table;

The data to be encoded is received, and according to the length of the data packet of the data to be encoded, the interleave address compression table is read to obtain P. Value and interleaving calculate the intermediate value;

The value of the coding parallelism K is judged according to the degree of coding parallelism, the length of the data packet to be encoded, and P. The value and the intermediate value of the interleaving calculation generate an interleave address and a read address, and the data to be encoded is read according to the read address to complete the interleaving operation.

In the above method, the value of the judgment coding parallel degree K is:

The value of the coding parallelism K is judged based on the pre-configured throughput rate in the WiMAX system. In the above method, the interleaving address and the read address are generated according to the coding parallel degree, the length of the data packet to be encoded, the P ₀ value, and the intermediate value of the interleaving calculation:

A. Calculate the number of data to be encoded buffered in each data buffer in the buffer unit before processing

Δ ;

B. Recursively generating an interleave address according to the coding parallelism K, the number of data to be encoded buffered in each data buffer, and the interleaving calculation base address;

C. The generated K-way interleaving addresses respectively modulo K, and obtain data buffer numbers of the data to be encoded corresponding to the K interleave addresses;

D. The generated K-way interleaving addresses respectively round up K to obtain the read addresses of the respective data buffers of the data to be encoded corresponding to the K interleave addresses.

In the above method, the reading the data to be encoded according to the read address is: E. Read data from the data buffer corresponding to the data to be encoded in the buffer unit before processing according to the generated K read addresses, and input the read data to be encoded into the parallel encoder for encoding processing.

In the above method, the method further includes:

F. Cache the first interleave address of the K interleave addresses to the pre-processing buffer unit, and record it as temp;

G. Multiply the coding parallelism K by P _Q , and then add it to temp, and the obtained result is the number of data to be encoded buffered in each data buffer. As the base address of the next round of interleaving calculations.

In the above method, the method further includes:

H. Determine the size of the index value i and the number of data to be encoded Δ buffered in each data buffer. If the index value i is smaller than the number Δ of data to be encoded buffered in each data buffer, perform step A. Until the index value i is equal to the number of data to be encoded buffered in each data buffer.

In the above method, the step B is:

Among the K interleave addresses, the K-1th interleave address inter_addrK-2 and Τ are used. Add one of Τ\, Τ ₂ and Τ ₃ , and modulate the addition result to obtain the second interleaving address inter_addrK-l.

The parallel computing method and system for interleaving addresses provided by the present invention pre-configure and store an interleave address compression table; receive data to be encoded, and read an interleave address compression table according to the length of the data packet to be encoded to obtain P. The value and the interleave calculate the intermediate value; determine the value of the encoding parallelism K, and according to the encoding parallelism, the length of the data packet to be encoded, P. The intermediate value of the value and the interleaving calculation generates an interleave address and a read address, reads the data to be encoded according to the read address, completes the interleaving operation, and can implement parallel calculation of the interleave address in the encoder in the WiMAX system; and, because the buffered interleave address is used to compress the table Therefore, the consumption of the storage resources can be reduced; in addition, the method proposed in the present invention can reduce the difficulty in realizing the parallel computing of the interleave addresses in the encoder in the WiMAX system, and has great significance for the reduction of the implementation cost of the WiMAX system. DRAWINGS

1 is a schematic structural diagram of a parallel computing system for implementing an interleaved address according to the present invention;

2 is a schematic flow chart of a parallel computing method for implementing an interleaved address according to the present invention;

3 is a schematic flow chart of a method for implementing step 203 of FIG. 2 according to the present invention;

4 is a schematic diagram of a recursively generated interleaving address when the coding parallelism K is 4; FIG. 5 is a schematic flowchart of Embodiment 1 of a parallel computing method for implementing an interleaved address according to the present invention; FIG. 6 is a buffer for data to be encoded. Schematic diagram of the data buffer of the cache unit before processing. detailed description

The basic idea of the present invention is: pre-configuring and storing an interleave address compression table; receiving data to be encoded, and reading an interleave address compression table according to the length of the data packet to be encoded, obtaining a Po value and interleaving calculation intermediate value; The value of the degree of parallelism K, and according to the degree of coding parallelism, the length of the data packet to be encoded, P. The value and the interleave calculation intermediate value generate an interleave address and a read address, and the data to be encoded is read according to the read address to complete the interleaving operation.

The invention will be further described in detail below with reference to the drawings and specific embodiments.

The present invention provides a parallel computing system for interleaving addresses. FIG. 1 is a schematic structural diagram of a parallel computing system for implementing an interleaved address according to the present invention. As shown in FIG. 1, the system includes: an interleaving address buffer unit 11, a pre-processing buffer unit 12, Control unit 13; wherein

The interleave address buffer unit 11 is configured to pre-configure and store the interleave address compression table. The pre-processing buffer unit 12 is configured to receive data to be encoded, and read the interleave address compression table according to the length of the data packet to be encoded, to obtain P. . Value and interleaving calculate the intermediate value;

The control unit 13 is configured to determine the value of the coding parallelism K, and according to the coding parallelism, the length of the data packet to be encoded, and P. The value and the interleave calculation intermediate value generate an interleave address and a read address, and the data to be encoded is read according to the read address to complete the interleaving operation.

Based on the foregoing system, the present invention further provides a parallel computing method for interleaving addresses, and FIG. 2 is a schematic flowchart of a parallel computing method for implementing an interleaved address according to the present invention. As shown in FIG. 2, the method is Includes the following steps:

Step 201: Pre-configure and store an interleave address compression table.

Specifically, the interleave address buffering unit pre-configures the interleave address compression table, as shown in Table 1, the interleave address compression table is used to store the packet length of the data to be encoded and P ₀ , τ. Correspondence between τ τ ₂ and τ ₃ ; where τ. τ τ ₂ and τ ₃ are intermediate values of the interleave address; and the interleave address compression table is stored in the interleave address buffer unit.

Table 1

Step 202: Receive data to be encoded, and read according to the length of the data packet of the data to be encoded. Specifically, the pre-processing buffer unit receives the input data to be encoded, and buffers the data to be encoded. The pre-processing buffer unit reads the data to be encoded in the interleave address compression table according to the length N of the input data packet to be encoded. The length of the packet N corresponds to P. The value and interleaving calculate the intermediate values Τ ₀ , Τ ₂ , Τ ₃ .

Step 203: Determine a value of the coding parallel degree ,, and according to the coding parallel degree, the length of the data packet to be encoded, and Ρ. The value and the intermediate value of the interleaving calculation generate an interleave address and a read address, and the data to be encoded is read according to the read address to complete the interleaving operation.

FIG. 3 is a schematic flowchart of a method for implementing step 203 in FIG. 2 according to the present invention. As shown in FIG. 3, the method includes the following steps:

Step 301: Determine a value of the coding parallel degree Κ;

Specifically, the value of the coding parallelism K is determined according to the pre-configured throughput rate in the WiMAX system. If the configured throughput rate is high, the value of the coding parallelism K is large, for example, the coding parallelism K is equal to 8; If the throughput is low, the value of the coding parallelism K is small, for example, the coding parallelism K is equal to 4.

Step 302: Calculate, according to the length N of the data packet to be encoded and the coding parallelism K, the number Δ of data to be encoded buffered in each data buffer in the buffer unit before processing, that is, the number is equal to the prison.

Step 303: Recursively generate K interleave addresses according to coding parallelism, number of data to be encoded buffered in each data buffer, and interleaving calculation base address;

Specifically, K interleave addresses are generated according to the base address of the interleave calculation and the intermediate value of the interleave calculation. For example, when K=4, the intermediate value T is calculated according to the base address and the interlace calculated by the interleave. TT ₂ recursively generates 4 interleaving addresses; when Κ=8, the intermediate value Τ is calculated according to the base address and interleaving calculated by the interleaving. , Τ\, Τ ₂ , Τ ₃ recursively generate 8 interleaved addresses;

4 is a schematic diagram of a recursively generated interleave address when the coding parallel degree Κ is 4 in the present invention. As shown in FIG. 4, the recursively generated interleave address is specifically: Among the K interleave addresses, the length of the data packet of the base data to be encoded is subjected to modulo processing to obtain a first interleave address inter_addr0; and the first interleave address inter_addr0 and T are obtained. After adding, the modulo result is modulo, and the second interleave address inter_addrl is obtained; after the second interleave address inter_addrl is added to 1\, the addition result is modulo, and the third interleave address inter_addr2 is obtained; After the three-way interleave address inter_addr2 is added to T ₂ , the addition result is modulo, and the fourth interleave address inter_addr3 is obtained; for the case of K=4, the four-way interleave address is obtained, and the calculation can be stopped, for Κ=8 case, also need to continue calculation, i.e. with the fourth way interleaving address inter_addr3 Τ ₃ after the addition of modulo addition result, to obtain a fifth way interleaving address inter_addr4; the fifth passage and the interleaving address inter_addr4 T. After adding, the modulo result is modulo, and the sixth interleave address inter_addr5 is obtained; and so on, the K-1 way interleave address inter_addrK-2 is added to one of T ₀ , Τ ₂ , Τ ₃ , The result of the addition is 4, and the second interleaving address inter_addrK-l is obtained.

Step 304: The generated K-way interleaving addresses respectively modulo K, and obtain data buffer numbers of the data to be encoded corresponding to the K interleaved addresses.

Step 305: The generated K-way interleaving addresses respectively round up K to obtain read addresses of respective data buffers of the data to be encoded corresponding to the K interleaved addresses.

Step 306: Read data from the data buffer corresponding to the data to be encoded in the buffer unit before processing according to the generated K read addresses, and read K data to be encoded, and input the K data to be encoded. The parallel encoder performs encoding processing.

Step 307: The first interleave address of the K interleave addresses in step 302 is buffered to the pre-processing buffer unit, denoted as temp, as an intermediate value for calculating the next round of interleave addresses.

Step 308, encoding the parallel degrees K and P. After multiplying, it is added to temp, and the obtained result is modulo the number of data to be encoded Δ buffered in each data buffer, and the modulo result is used as the base address of the next round of interleaving calculation.

At this time, the index value is i=l, if it is less than the number of data to be encoded buffered in each data buffer. Δ , then the index value i is incremented by one, and the steps 302 to 308 are looped until the index value is equal to the number Δ of the data to be encoded buffered in each data buffer, and the parallel interleaving address of the current data to be encoded is calculated. .

FIG. 5 is a schematic flowchart of the first embodiment of the method for implementing the interleaving address in the parallel computing method. In this embodiment, the length of the data packet to be encoded is N=36. As shown in FIG. 5, the method includes the following steps. Steps:

Step 501: Determine, according to the pre-configured throughput rate in the WiMAX system, that the coding parallelism κ is 4; as shown in FIG. 6, the data to be encoded is buffered in four data buffers of the pre-processing buffer unit.

Step 502: Read the interleave address compression table according to the length N of the data packet of the data to be encoded, and obtain p. =ll, T. =ll, 1\=11, T ₂ =ll, T ₃ =ll.

Step 503: Calculate the number of data to be encoded buffered in each data buffer in the buffer unit before processing Δ=Ν/Κ=36/4=9.

Step 504: Generate four interleave addresses according to the coding parallel degree Κ=4, the number of data to be encoded buffered in each data buffer=9, and the base address 1 of the interleave calculation, respectively, inter_addrO=l, inter_addrl=12 Inter_addr2=23, inter_addr3=34; At this time, the index value i=0.

Step 505: Generate data buffer numbers corresponding to the four interleaved addresses: 1, 0, 3, and 2. Step 506, generating a read address of the four data to be encoded in the respective buffers: 0, 3, 5, 8. Step 507, according to the generated four read addresses, read data from the corresponding data buffer in the pre-processing buffer unit, and input the read four data to be encoded into the parallel encoder for encoding processing; specifically, the data buffer Reading address 2 of 1 reads the corresponding data to be encoded, and inputs the parallel encoder 0th channel;

Read the corresponding data to be encoded from the read address 5 of the data buffer 0, and send it to the parallel encoder 1st;

Read the corresponding data to be encoded from the read address 7 of the data buffer 3, and send it to the parallel encoder. Second road;

The corresponding data to be encoded is read from the read address 1 of the data buffer 2, and sent to the parallel encoder 3rd.

Step 508: Cache the first interleave address temp=l.

Step 509: Calculate the base address of the next round of interleaving address calculation: 1+ ( 4*11 ) =45, and modulo 45 pairs of 36, equal to 9.

In step 510, the index value i is incremented by 1, and the index value i=l is accumulated. Since the index value i<N=9, the process proceeds to step 504, where the next round of interleave address calculation is performed.

Step 511: Generate four interleave addresses according to the coding parallelism K=4, the number of data to be encoded buffered in each data buffer Δ=9, and the interleave calculation base address 9, which are respectively inter_addr0=9, inter_addrl=20, Inter_addr2=31, inter_addr3=6.

Step 512: Generate data buffer numbers corresponding to the four interleaved addresses: 1, 0, 3, and 2. Step 513, generating a read address of the four data to be encoded in the respective buffers: 2, 5, 7, and 1. Step 514, according to the generated four read addresses, read data from the corresponding data buffer in the pre-processing buffer unit, and input the read four data to be encoded into the parallel encoder for encoding processing; specifically, the data buffer Reading address 2 of 1 reads the corresponding data to be encoded, and inputs the parallel encoder 0th channel;

Read the corresponding data to be encoded from the read address 7 of the data buffer 3, and send it to the parallel encoder 2nd channel;

Step 515, buffering the first interleave address temp=9.

In step 516, the base address calculated by the next round of interleave address calculation is 17. In step 517, the index value i is incremented by one, and the index value i=2 is accumulated. Since the index value i<N=9, the process proceeds to step 504, where the next round of interleave address calculation is performed, and so on, until the index value i=N= 9.

The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included. Within the scope of protection of the present invention.

Claims

Claim

A parallel computing system for interleaving addresses, the system comprising: an interleaved address buffer unit, a pre-processing buffer unit, and a control unit;

An interleave address buffer unit, configured to pre-configure and store an interleave address compression table;

The pre-processing buffer unit is configured to receive data to be encoded, and read the interleave address compression table according to the length of the data packet to be encoded to obtain P. Value and interleaving calculate the intermediate value;

2. A parallel computing method for interleaving addresses, the method comprising: pre-configuring and storing an interleave address compression table;

3. The method according to claim 2, wherein the value of the judgment coding parallelism K is:

The value of the coding parallelism K is judged based on the pre-configured throughput rate in the WiMAX system.

4. The method according to claim 2, wherein the length of the data packet according to the coding parallelism, the data to be encoded, P. The intermediate value of the value and interleaving calculation generates the interleave address and the read address as:

Δ ;

B, according to the degree of coding parallelism ^ the number of data to be encoded cached in each data buffer Δ And interleaving the base address, and recursively generating K interleave addresses;

5. The method according to claim 2, wherein the reading the data to be encoded according to the read address is:

E. Read data from the data buffer corresponding to the data to be encoded in the buffer unit before processing according to the generated K read addresses, and input the read K data to be encoded into the parallel encoder for encoding processing.

6. The method according to claim 5, wherein the method further comprises:

F, buffering the first interleave address of the K interleave addresses to the pre-processing buffer unit, denoted as temp;

G, the coding parallelism K and P (^3⁄4 multiplied, and then added to temp, the result will be the number of data to be encoded buffered in each data buffer Δ ear 4, will be modulo The result is the base address of the next round of interleaving calculations.

The method according to claim 6, wherein the method further comprises:

8. The method according to claim 4, wherein the step B is:

Among the K interleave addresses, the K-1th interleave address inter_addrK-2 and T are used. Add one of T Τ ₂ and Τ ₃ , and modulate the addition result to obtain the second interleaving address inter_addrK-l.