CN102769471B - A kind of Turbo code coding method and encoder - Google Patents

A kind of Turbo code coding method and encoder Download PDF

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CN102769471B
CN102769471B CN201210216116.XA CN201210216116A CN102769471B CN 102769471 B CN102769471 B CN 102769471B CN 201210216116 A CN201210216116 A CN 201210216116A CN 102769471 B CN102769471 B CN 102769471B
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CN102769471A (en
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廖晓强
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CICT Mobile Communication Technology Co Ltd
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Beijing Northern Fiberhome Technologies Co Ltd
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Abstract

The embodiment of the present application provides a kind of Turbo code coding method.The method comprises: receive the first parameter for characterizing block to be encoded size; According to the first parameter, the second parameter and the 3rd calculation of parameter interleaving address, described second parameter, the 3rd parameter are the preset parameter corresponding with the first parameter; The data of the block to be encoded of buffer memory are read according to described interleaving address; Export by the data of the block to be encoded of the buffer memory of order reading with after carrying out Recursive Systematic Convolutional coding according to the data of the block to be encoded of interleaving address reading.The embodiment of the present application additionally provides a kind of Turbo code encoder.By the technical scheme of the embodiment of the present application, the Turbo code encoded question of the not reciprocity situation of input and output speed can be solved.

Description

A kind of Turbo code coding method and encoder
Technical field
The application relates to wireless communication technology field, particularly relates to a kind of Turbo code coding method and encoder.
Background technology
The relative wire communication of radio communication, the limited bandwidth resources of its transfer of data, and transmission channel environment is comparatively severe.For improving data transmission efficiency, usually needing during transfer of data to encode to the data flow in channel, to reduce the error rate, and then strengthening channel reliability.Turbo code is a kind of important novel radio channel coding method proposed nineteen nineties, and this coding is superior performance under the high-noise environment that channel SNRs is lower not only, but also has stronger anti-fading, jamproof ability.Based on the advantage of these uniquenesses, Turbo code becomes the heat subject of wireless communication technology field research day by day.
In prior art, the coding of Turbo code realizes generally including two kinds of modes: one is adopt DSP (DigitalSignalProcessing Digital Signal Processing) to carry out serial code, two is adopt FPGA (FieldProgrammableGateArray, field programmable gate array) to carry out parallel encoding.Although parallel encoding processing speed is faster than serial process, its input and output speed must be symmetrical, the normal realization of guarantee Turbo code coding.See Fig. 1, the figure shows in LTE (LongTermEvolution, long-term project evolution) system the existing encoder realizing Turbo code coding.C in this figure krepresent that up-stream module is input to the input code flow of Turbo code encoder, c ' krepresent c kcode stream after the interleaver in Turbo code encoder, x krepresent the system code stream that Turbo code encoder exports, z kand z ' krepresent the first check code that Turbo code encoder exports and the second check code respectively.In this encoder encodes process, its up-stream module must be symmetrical to the input rate of encoder and encoder to the output speed of downstream module, i.e. c kwith x k, z kand z ' kdata bits must be consistent, such as input code flow is 4bit, and output code flow is also 4bit, otherwise, incapability is realized the normal encoding of Turbo code.
But due to a variety of causes, there is difference in the requirement of upstream and downstream module to encoder data speed of encoder, namely occurs the asymmetric phenomenon of encoder constrained input speed.Under this situation, existing encoder cannot realize Turbo code coding.
Summary of the invention
Because prior art can not realize the problem of the Turbo code coding under asymmetric rate behavior, the embodiment of the present application provides a kind of Turbo code coding method and encoder, with the Turbo code coding under the asymmetric rate behavior of upstream and downstream module realizing encoder.
The Turbo code coding method that the embodiment of the present application provides comprises:
Receive the first parameter for characterizing block to be encoded size;
According to the first parameter, the second parameter and the 3rd calculation of parameter interleaving address, described second parameter, the 3rd parameter are the preset parameter with the first parameter with corresponding relation;
The data of the block to be encoded of buffer memory are read according to described interleaving address;
Export by the data of the block to be encoded of the buffer memory of order reading with after carrying out Recursive Systematic Convolutional coding according to the data of the block to be encoded of interleaving address reading.
Preferably, after receiving the first parameter, trigger the data buffer storage operation of block to be encoded.
Further preferably, after the data buffer storage of block to be encoded, interleaving address calculating operation is triggered.
Preferably, describedly specifically to comprise according to the first parameter, the second parameter and the 3rd calculation of parameter interleaving address:
Obtain recursion initial value;
Calculate i-th data after interweaving according to the following formula and the recurrence relation of the individual data of front Π (i+m) that interweave:
Π(i+m)＝mod((Π(i)+mod((mf 1+m 2f 2),K)+mod(2mi·f 2,K)),K)
In formula: the span of i is 0 to (K-1), and m is the data amount check of parallel processing, and Π (0) be the recursion initial value obtained, and K is the first parameter of sign block to be encoded size, f 1be the second parameter, f 2it is the 3rd parameter;
According to above-mentioned recurrence relation determination interleaving address.
Further preferably, to the mod ((mf in recurrence relation 1+ m 2f 2), K) numerical value store.
Preferably, the data rate of described buffer memory block to be encoded and the data output rate after Recursive Systematic Convolutional is encoded meet following relation:
Data output rate after Recursive Systematic Convolutional coding and the ratio of the data rate of buffer memory block to be encoded are the integer power of 2.
The embodiment of the present application additionally provides a kind of Turbo encoder.This encoder comprises: receiving element, interleave unit, reading unit and coding unit, and for the buffer unit of buffer memory block to be encoded data, wherein:
Described receiving element, for receiving the first parameter characterizing block to be encoded size;
Described interleave unit, for according to the first parameter, the second parameter and the 3rd calculation of parameter interleaving address, described second parameter, the 3rd parameter are the preset parameter with the first parameter with corresponding relation;
Described reading unit, the data of the data reading the block to be encoded of buffer memory for order and the block to be encoded reading buffer memory according to interleaving address;
Described coding unit, for the data of the block to be encoded of buffer memory that order read with carry out Recursive Systematic Convolutional coding according to the data of block to be encoded that interleaving address reads, and exports.
Preferably, trigger buffer unit after receiving element reception characterizes the first parameter of block to be encoded size and carry out data buffer storage operation.
Further preferably, trigger interleave unit after the data of the complete block to be encoded of buffer unit buffer memory and carry out interleaving address calculating operation.
Preferably, described buffer unit comprises two sub-buffer units, and two sub-buffer units are alternately for buffer memory and read operation.
The technical scheme of the embodiment of the present application by receive characterize block to be encoded size the first parameter after, according to the first parameter and second, third calculation of parameter interleaving address, the data of the encoding block of buffer memory are carried out order read and read according to interleaving address, export after then two groups of data being carried out Recursive Systematic Convolutional coding.Compared with prior art, the embodiment of the present application reads data according to interleaving address again by after block to be encoded buffer memory, by the regulating action of buffer memory, data storage procedure and interleaving address computational process are separated, number data cached in unit interval can not be equal to the interleaving address number calculated, still normally can carry out Turbo code coding under ensure that encoder accepts data rate and the asymmetric situation of output data rate, thus efficiently solve the problem of prior art.In addition, the embodiment of the present application also can adopt Synchronous data dispose mode to realize Turbo code coding, and under identical clock frequency, transmitted data rates is faster than the serial data processing time, improves Turbo code code efficiency.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present application or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, the accompanying drawing that the following describes is only some embodiments recorded in the application, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the Turbo coder structure figure based on LTE system in prior art;
Fig. 2 is the flow chart of the embodiment of the method one of the application;
The flow chart of the embodiment of the method two that Fig. 3 (a) is the application;
Fig. 3 (b) is single-bit Recursive Systematic Convolutional coding schematic diagram;
Fig. 4 is the structure chart of the encoder embodiment one of the application;
The structure chart of the encoder embodiment two that Fig. 5 (a) is the application;
The particular value that Fig. 5 (b) is the interleaving block of embodiment two stores schematic diagram;
The memory module hardware designs figure that Fig. 5 (c) is embodiment two.
Embodiment
Technical scheme in the application is understood better in order to make those skilled in the art person, below in conjunction with the accompanying drawing in the embodiment of the present application, technical scheme in the embodiment of the present application is clearly and completely described, obviously, described embodiment is only some embodiments of the present application, instead of whole embodiments.Based on the embodiment in the application, those of ordinary skill in the art are not making the every other embodiment obtained under creative work prerequisite, all should belong to the scope of the application's protection.
For enabling above-mentioned purpose, the feature and advantage of the application more become apparent, below in conjunction with the drawings and specific embodiments, the application is described in further detail.
See Fig. 2, the figure shows the flow process of the embodiment of the present application one.This embodiment comprises:
Step S201: receive the first parameter for characterizing block to be encoded size;
As previously mentioned, the object of carrying out Turbo code coding to transmission channel is to submit data transmission efficiency to.Therefore, chnnel coding is in critical role in a wireless communication system, and it and other upstream and downstream modules realize radio communication jointly.The operating upstream of chnnel coding generally includes CRC interpolation, code block segmentation etc., large code block can be divided into by these operations the code block size that encoder can process.According to the difference of wireless communication system, the magnitude range of code block is also different.Such as, in LTE system, be generally used for parameter K (first parameter of the present embodiment) span of mask block size between 40 to 6144.After the operating upstream such as code block segmentation, this parameter can be obtained.
Step S202: according to the first parameter, the second parameter and the 3rd calculation of parameter interleaving address, described second parameter, the 3rd parameter are the preset parameter corresponding with the first parameter;
Obtained the first parameter K of mask block size by abovementioned steps after, the calculating of interleaving address can be carried out on this basis.Need in computational process to use second parameter f with the first parameter K with incidence relation 1with the 3rd parameter f 2, the second parameter f 1with the 3rd parameter f 2it is the preset parameter depending on the first parameter K.In LTE system, there is following corresponding relation in these three parameters:
[table 1: the first parameter K and the second parameter f 1, the 3rd parameter f 2comparison table]
idx K f 1 f 2 idx K f 1 f 2 idx K f 1 f 2 idx K f 1 f 2
1 40 3 10 48 416 25 52 95 1120 67 140 142 3200 111 240
2 48 7 12 49 424 51 106 96 1152 35 72 143 3264 443 204
3 56 19 42 50 432 47 72 97 1184 19 74 144 3328 51 104
4 64 7 16 51 440 91 110 98 1216 39 76 145 3392 51 212
5 72 7 18 52 448 29 168 99 1248 19 78 146 3456 451 192
6 80 11 20 53 456 29 114 100 1280 199 240 147 3520 257 220
7 88 5 22 54 464 247 58 101 1312 21 82 148 3584 57 336
8 96 11 24 55 472 29 118 102 1344 211 252 149 3648 313 228
9 104 7 26 56 480 89 180 103 1376 21 86 150 3712 271 232
10 112 41 84 57 488 91 122 104 1408 43 88 151 3776 179 236
11 120 103 90 58 496 157 62 105 1440 149 60 152 3840 331 120
12 128 15 32 59 504 55 84 106 1472 45 92 153 3904 363 244
13 136 9 34 60 512 31 64 107 1504 49 846 154 3968 375 248
14 144 17 108 61 528 17 66 108 1536 71 48 155 4032 127 168
15 152 9 38 62 544 35 68 109 1568 13 28 156 4096 31 64
16 160 21 120 63 560 227 420 110 1600 17 80 157 4160 33 130
17 168 101 84 64 576 65 96 111 1632 25 102 158 4224 43 264
18 176 21 44 65 592 19 74 112 1664 183 104 159 4288 33 134
19 184 57 46 66 608 37 76 113 1696 55 954 160 4352 477 408
20 192 23 48 67 624 41 234 114 1728 127 96 161 4416 35 138
21 200 13 50 68 640 39 80 115 1760 27 110 162 4480 233 280
22 208 27 52 69 656 185 82 116 1792 29 112 163 4544 357 142
23 216 11 36 70 672 43 252 117 1824 29 114 164 4608 337 480
24 224 27 56 71 688 21 86 118 1856 57 116 165 4672 37 146
25 232 85 58 72 704 155 44 119 1888 45 354 166 4736 71 444
26 240 29 60 73 720 79 120 120 1920 31 120 167 4800 71 120
27 248 33 62 74 736 139 92 121 1952 59 610 168 4864 37 152
28 256 15 32 75 752 23 94 122 1984 185 124 169 4928 39 462
29 264 17 198 76 768 217 48 123 2016 113 420 170 4992 127 234
30 272 33 68 77 784 25 98 124 2048 31 64 171 5056 39 158
31 280 103 210 78 800 17 80 125 2112 17 66 172 5120 39 80
32 288 19 36 79 816 127 102 126 2176 171 136 173 5184 31 96
33 296 19 74 80 832 25 52 127 2240 209 420 174 5248 113 902
34 304 37 76 81 848 239 106 128 2304 253 216 175 5312 41 166
35 312 19 78 82 864 17 48 129 2368 367 444 176 5376 251 336
36 320 21 120 83 880 137 110 130 2432 265 456 177 5440 43 170
37 328 21 82 84 896 215 112 131 2496 181 468 178 5504 21 86
38 336 115 84 85 912 29 114 132 2560 39 80 179 5568 43 174
39 344 193 86 86 928 15 58 133 2624 27 164 180 5632 45 176
40 352 21 44 87 944 147 118 134 2688 127 504 181 5696 45 178
41 360 133 90 88 960 29 60 135 2752 143 172 182 5760 161 120
42 368 81 46 89 976 59 122 136 2816 43 88 183 5824 89 182
43 376 45 94 90 992 65 124 137 2880 29 300 184 5888 323 184
44 384 23 48 91 1008 55 84 138 2944 45 92 185 5952 47 186
45 392 243 98 92 1024 31 64 139 3008 157 188 186 6016 23 94
46 400 151 40 93 1056 17 66 140 3072 47 96 187 6080 47 190
47 408 155 102 94 1088 171 204 141 3136 13 28 188 6144 263 480
In embody rule, after obtaining the first parameter K, by acquisition second parameter f of tabling look-up 1, the 3rd parameter f 2.Then according to these three calculation of parameter interleaving address.Computing formula can be carried out in the following way:
C ' i=c Π (i), i=0,1 ..., (K-1) (formula 1)
Π (i)=(f 1i+f 2i 2) modK (formula 2)
In above formula: c ' ifor i-th data after interweaving, c Π (i)for the individual data of ∏ (i) before intertexture.Because address and data sequence number have corresponding relation, in actual application, data sequence number can be carried out interleaving address calculating as address, also can directly calculate usage data address.When calculating interleaving address, can select according to actual needs to calculate one by one, also can the simultaneously multiple interleaving address of parallel computation, the former is applicable to the situation of serial process usually, and the latter uses the situation of parallel processing.
Step S203: the data reading the block to be encoded of buffer memory according to described interleaving address;
After going out interleaving address according to above-mentioned formulae discovery, corresponding data can be read according to this interleaving address from the code block data of buffer memory, the data of reading are passed to subsequent step.Here it should be noted that: the buffer memory rate (input rate of up-stream module) during buffer memory encoding block can be identical with the reading rate (speed exported after Recursive Systematic Convolutional is encoded) reading data according to interleaving address, also can be different, as long as the data of the encoding block of buffer memory take address realm meet the interleaving address scope reading data.
Step S204: export by the data of the block to be encoded of the buffer memory of order reading with after carrying out Recursive Systematic Convolutional coding according to the data of the block to be encoded of interleaving address reading;
When reading the data in encoding block by the interleaving address calculated, read the data of block to be encoded in order, then these two groups of data are carried out Recursive Systematic Convolutional coding (RSC, RecursiveSystemCode), and the result after coding is exported.Recursive Systematic Convolutional coding has been prior art, does not do too much introduction herein.
The technical scheme of the present embodiment by receive characterize block to be encoded size the first parameter after, according to the first parameter and second, third calculation of parameter interleaving address, the data of the encoding block of buffer memory are carried out order read and read according to interleaving address, export after then two groups of data being carried out Recursive Systematic Convolutional coding.Compared with prior art, the present embodiment reads data according to interleaving address again by after block to be encoded buffer memory, by the regulating action of buffer memory, data storage procedure and interleaving address computational process are separated, number data cached in unit interval can not be equal to the interleaving address number calculated, still normally can carry out Turbo code coding under ensure that encoder accepts speed and the asymmetric situation of output speed, thus efficiently solve the problem of prior art.In addition, the embodiment of the present application adopts Synchronous data dispose mode to realize Turbo code coding, and under identical clock frequency, transmitted data rates is faster than the serial data processing time.
For more clearly understanding the technical scheme of the application, with an embodiment, technique scheme is further described again below.The flow process of the embodiment of the present application is shown see Fig. 3, Fig. 3 (a); Fig. 3 (b) is single-bit recursive systematic convolutional code coding schematic diagram.This embodiment comprises:
Step S301: monitor encoder and whether be in idle condition, if so, then performs step S301; If not, then proceed to monitor;
Step S302: produce write enable signal after receiving the first parameter K of the sign block to be encoded size of operating upstream transmission;
Step S303: carry out buffer memory to the data of block to be encoded after receiving write enable signal, produces write end signal after buffer memory;
Step S304: after receiving write end signal, according to the first parameter K and with this first parameter K, there is the second parameter f of corresponding relation 1, the 3rd parameter f 2calculate interleaving address, and produce address valid signal;
The recursion multidigit that goes out the present embodiment parallel work-flow the interleaving address of data can be exported according to aforementioned formula (1), formula (2).For 8 OPADD, its recurrence relation is as follows:
Π(i+1)＝(f 1·(i+1)+f 2·(i+1) 2)modK
＝mod((Π(i)+mod((f 1+f 2),K)+mod(2i·f 2,K)),K)
Π(i+2)＝(f 1·(i+2)+f 2·(i+2) 2)modK
＝mod((Π(i)+mod((2f 1+4f 2),K)+mod(4i·f 2,K)),K)
Π(i+3)＝(f 1·(i+3)+f 2·(i+3) 2)modK
＝mod((Π(i)+mod((3f 1+9f 2),K)+mod(6i·f 2,K)),K)
Π(i+4)＝(f 1·(i+4)+f 2·(i+4) 2)modK
＝mod((Π(i)+mod((4f 1+16f 2),K)+mod(8i·f 2,K)),K)
Π(i+5)＝(f 1·(i+5)+f 2·(i+5) 2)modK
＝mod((Π(i)+mod((5f 1+25f 2),K)+mod(10i·f 2,K)),K)
Π(i+6)＝(f 1·(i+6)+f 2·(i+6) 2)modK
＝mod((Π(i)+mod((6f 1+36f 2),K)+mod(12i·f 2,K)),K)
Π(i+7)＝(f 1·(i+7)+f 2·(i+7) 2)modK
＝mod((Π(i)+mod((7f 1+49f 2),K)+mod(14i·f 2,K)),K)
Π (i+8)=(f 1(i+8)+f 2(i+8) 2) modK (formula 3)
＝mod((Π(i)+mod((8f 1+64f 2),K)+mod(16i·f 2,K)),K)
From above-mentioned formula 3: i-th data after intertexture and the interweave individual data of front Π (i+m) and the first parameter, relation between the second parameter and the 3rd parameter can be expressed as:
Π (i+m)=mod ((Π (i)+mod ((mf 1+ m 2f 2), K)+mod (2mif 2, K)), K) (formula 4)
In formula: the span of i is 0 to (K-1), m is the data amount check of parallel processing, such as, need parallel processing 8 data in parallel processing, one time recursion goes out 8 interleaving address, then m value is 1 to 8, as i=0, Π (0) is for realizing the recursion initial value of above-mentioned recursion, and this initial value can carry out initialization before native system brings into operation, K is the first parameter characterizing block to be encoded size, f 1be the second parameter, f 2it is the 3rd parameter.The interleaving address after interweaving can be determined under the recurrence relation of formula 4.
Such understanding (with parallel processing 8 data instances) can be obtained: 1. in each treatment cycle by above formula, as long as know known address Π (i), can carry out by Π (i) address that simple XOR releases Π (i+1) ~ Π (i+8), next treatment cycle releases the address of Π (i+9) ~ Π (i+16) by Π (i+8).In actual applications, before and after data interlacing, its first data is identical with the address of last data, therefore, using the address of first data as known address, can carry out the reckoning of other interleaving address according to above-mentioned relation.2. above-mentioned formula four comprises three data item altogether, wherein: Section 2 is mod ((f such as 1+ f 2), K), mod ((2f 1+ 4f 2), K), mod ((3f 1+ 9f 2), K), mod ((4f 1+ 16f 2), K), mod ((5f 1+ 25f 2), K), mod ((6f 1+ 36f 2), K), mod ((7f 1+ 49f 2), K) and mod ((8f 1+ 64f 2), K) etc. only relevant with K value, when K value is determined, its analog value can be determined, therefore, these values can be stored after calculating first, and need not all calculate, thus save time, raise the efficiency, before carrying out Turbo code coding, even can also carry out the calculating of these data in advance; at every turn directly transfer in an encoding process, thus improve code efficiency further; Section 3 is both relevant to K value, relevant to i value again, in each treatment cycle, need interim calculating, for after completing interleaving address recursion without the need to preserving.
Step S305: after receiving address valid signal, reads block to be encoded data and the order reading block to be encoded data of buffer memory according to interleaving address;
In actual applications, in order to save memory latency time, two memories can be adopted, one for read operation, namely block to be encoded data and the order reading block to be encoded data of buffer memory are read according to interleaving address, one for write operation, namely for buffer memory block to be encoded data, these two memories under control of the control signal can alternately for realize read-write.The parallel bit wide of the write sense data of memory can be the same or different; when difference; when clock source is identical; usually there will be a memory data to run through; the situation that the data of another memory also do not write, owing to there is the irregular feature of interleaving address during read-write, for ensureing that data do not misplace; need the principle following " write-then-read writes readable ".
Step S306: the data of reading are carried out Recursive Systematic Convolutional coding, generation system code, the first check code and the second check code, and exported.
Can input/output relation be obtained by Recursive Systematic Convolutional cataloged procedure:
Z k＝C k+D 2+D 1
D 1＝C k+D 3+D 2,D 2＝D 1,D 3＝D 2
Coding when can release parallel output long numeric data according to above-mentioned formula.For 8 bit data, as follows according to the parallel RSC relation that above-mentioned relation is derived:
Z N＝C N+D 2+D 1
Z N+1＝C N+C N+1+D 2+D 1+D 3
Z N+2＝C N+C N+1+C N+2+D 1+D 3
Z N+3＝C N+C N+1+C N+2+C N+3+D 3
Z N+4＝C N+1+C N+2+C N+3+C N+4+D 2
Z N+5＝C N+2+C N+3+C N+4+C N+5+D 1
Z N+6＝C N+C N+3+C N+4+C N+5+C N+6+D 2+D 3
Z N+7＝C N+1+C N+4+C N+5+C N+6+C N+7+D 1+D 2
D 1 = C N + C N + 3 + C N + 4 + C N + 5 + C N + 7 + D 2 0 + D 3 0
D 2 = C N + 2 + C N + 3 + C N + 4 + C N + 6 + D 1 0
D 3 = C N + 1 + C N + 2 + C N + 3 + C N + 5 + D 2 0
Wherein, with represent the initial value of shift register.After being encoded by the block to be encoded of said process to buffer memory, coding result can be exported.
Above-described embodiment describes the embodiment of the method for the application in detail, correspondingly, present invention also provides a kind of Turbo code encoder.See Fig. 4, the figure shows the structured flowchart of the encoder embodiment one of the application.This encoder embodiment 400 comprises: receiving element 401, interleave unit 402, reading unit 403 and coding unit 404, and for the buffer unit 405 of buffer memory block to be encoded data, wherein:
Receiving element 401, for receiving the first parameter characterizing block to be encoded size;
Interleave unit 402, for according to the first parameter, the second parameter and the 3rd calculation of parameter interleaving address, described second parameter, the 3rd parameter are the preset parameter with the first parameter with corresponding relation;
Reading unit 403, reads the block to be encoded data of buffer memory for order and reads the block to be encoded data of buffer memory according to interleaving address;
Coding unit 404, for the data of the block to be encoded of buffer memory that order read with carry out Recursive Systematic Convolutional coding according to the data of block to be encoded that interleaving address reads, and exports coding result.
The course of work of this encoder embodiment is: after receiving element receives the first parameter characterizing block to be encoded size, by interleave unit 402 according to the first parameter and the second parameter, the 3rd calculation of parameter interleaving address, then, reading unit 403 order reads the block to be encoded data of buffer memory and reads the block to be encoded data of buffer memory according to interleaving address, coding unit 404 carries out Recursive Systematic Convolutional coding by the data of the block to be encoded of the buffer memory of order reading with according to the data of the block to be encoded of interleaving address reading, and is exported by coding result.
The technical scheme of this encoder embodiment by receive characterize block to be encoded size the first parameter after, according to the first parameter and second, third calculation of parameter interleaving address, the data of the encoding block of buffer memory are carried out order read and read according to interleaving address, export after then two groups of data being carried out Recursive Systematic Convolutional coding.Compared with prior art, the embodiment of the present application reads data according to interleaving address again by after block to be encoded buffer memory, by the data regulating action of buffer unit, still normally can carry out Turbo code coding under ensure that encoder accepts speed and the asymmetric situation of output speed, thus efficiently solve the problem of prior art.In addition, the embodiment of the present application adopts Synchronous data dispose mode to realize Turbo code coding, and under identical clock frequency, transmitted data rates is faster than the serial data processing time.
Present invention also provides another embodiment of Turbo code encoder, see Fig. 5 (a), the figure shows the structure of encoder embodiment two.This encoder comprises control module 501, interleaving block 502, memory module 503 and output module 504.The above-mentioned modules of the present embodiment can individualism, also integrated as a whole by FPGA.Discuss the Design and Features of each module below successively.
(1) control module.This module comprises the receiving element of previous embodiment, in addition also a series of signal controlling is responsible for, such as, receive the first parameter K and by K and the second parameter, the 3rd parameter transmission to interleaving block after, produce a write enable signal, and this signal is sent to memory module, control store module stores the module to be encoded that up-stream module is transmitted; After memory module data store, what receive memory module writes end signal, then sends enable signal according to this write end signal to interleaving block, starts interleaving block and carries out address computation.
(2) interleaving block.Interleaving block in the present embodiment can comprise two unit: interleaving address recursion unit and particular value memory cell, wherein: interleaving address recursion unit carries out recursion according to the formula of foregoing description to interleaving address.As previously mentioned, recursion interleaving address out all comprises only relevant with a K value middle entry, and for these middle entries, the embodiment of the present application is stored it by particular value memory cell.In actual application, the data 13bits of memory cell, the degree of depth is 1692bits, and address width is 11bits.Wherein address 0 ~ 187 corresponding stored mod ((f 1+ f 2), K) value, address 188 ~ 375 corresponding stored mod ((2f 1+ 4f 2), K) value, address 376 ~ 563 corresponding stored mod ((3f 1+ 9f 2), K) value, address 564 ~ 751 corresponding stored mod ((4f 1+ 16f 2), K) value, address 752 ~ 939 corresponding stored mod ((5f 1+ 25f 2), K) value, address 940 ~ 1127 corresponding stored mod ((6f 1+ 36f 2), K) value, address 1128 ~ 1315 corresponding stored mod ((7f 1+ 49f 2), K) value, address 1316 ~ 1503 corresponding stored mod ((8f 1+ 64f 2), K) value, the value of the f2 that address 1504 ~ 1691 corresponding stored is corresponding with K, its concrete storing process can refer to shown in Fig. 5 (b).
(3) memory module.The memory module of the present embodiment completes the storage enclosure to whole data.In actual application, memory module can comprise two and store RAM group, two structures storing RAM group are identical, it is 1bit that each RAM group comprises 8 width, the degree of depth is that the twoport DRAM of 768bits is (if use BRAM to realize, then each RAM group comprises 2 width is 4bits, and the degree of depth is the twoport BRAM of 768bits), each RAM group can store the data of a K value size.During write operation, if input data are 4bits, produce RAM select signal by control module, each stores processor cycle selects 4 bits to store data, the data of write-once 4bits.During read operation, 8 bits of RAM are simultaneously enable, and twoport DRAM has two output ports, and a port exports the system data of 8bits, and another port exports the interleaving data of 8bits.The concrete pin configuration of memory module see shown in Fig. 5 (c), can the figure shows the dual port RAM structure (left figure) adopting DRAM to realize and the dual port RAM structure (right figure) adopting BRAM to realize.In left figure, D is for writing FPDP, and A is write address port, and DPRA is for reading address port, and CLK is synchronised clock input port, and WE is for writing enable port, and SPO is data reading port.In right figure, DINA is for writing FPDP, and ADDRA is write address port, and ADDRB is for reading address port, and CLKA/CLKB is synchronised clock input port, and WEA is for writing enable port, and ENB is for reading enable port, and DOUTA is data reading port.
(4) output module.The output module of the present embodiment can adopt the mode of recursive systematic convolutional code to realize exporting.If need parallel output long numeric data, can adopt the recursive systematic convolutional code coding unit of multiple single-bit, the detailed process of single-bit recursive systematic convolutional code coding can refer to the description of aforementioned manner embodiment simultaneously, no longer goes to live in the household of one's in-laws on getting married chat at this.It should be noted that: the embodiment of the present application does not limit the concrete asymmetrical relationship between input rate and output speed, it can be applicable to process the not reciprocity situation of any upstream and downstream module transfer data.However, in actual application, for simplicity, usually require to there is certain relation between input rate and output speed, such as: the data output rate after Recursive Systematic Convolutional coding and the ratio of the data rate of buffer memory block to be encoded are the integer power of 2.
The technical scheme of the embodiment of the present application is when in the face of upstream and downstream transmitted data rates is not reciprocity, can the process of easy and flexible, relative to the Turbo encoder scheme only supporting upstream and downstream module output data rate equity, can play upstream and downstream module and more fully support.
The foregoing is only the preferred embodiment of the application, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., within the protection range that all should be included in invention.

Claims (8)

1. a Turbo code coding method, described method is applied to LTE system, it is characterized in that, the method comprises:
Receive the first parameter for characterizing block to be encoded size;
According to the first parameter, the second parameter and the 3rd calculation of parameter interleaving address, described second parameter, the 3rd parameter are the preset parameter with the first parameter with corresponding relation;
The data of the block to be encoded of buffer memory are read according to described interleaving address;
Export by the data of the block to be encoded of the buffer memory of order reading with after carrying out Recursive Systematic Convolutional coding according to the data of the block to be encoded of interleaving address reading;
Describedly specifically to comprise according to the first parameter, the second parameter and the 3rd calculation of parameter interleaving address:
Obtain recursion initial value;
Determine the recurrence relation of i-th data after interweaving and the individual data of front Π (i+m) that interweave according to the following formula:
Π(i+m)＝mod((Π(i)+mod((mf 1+m 2f 2),K)+mod(2mi·f 2,K)),K)
In formula: the span of i is 0 to (K-1), and m is the data amount check of parallel processing, and Π (0) be the recursion initial value obtained, and K is the first parameter of sign block to be encoded size, f 1be the second parameter, f 2it is the 3rd parameter;
According to above-mentioned recurrence relation determination interleaving address;
The data rate of described buffer memory block to be encoded and the data output rate after Recursive Systematic Convolutional is encoded meet following relation:
Data output rate after Recursive Systematic Convolutional coding and the ratio of the data rate of buffer memory block to be encoded are the integer power of 2.
2. method according to claim 1, is characterized in that, triggers the data buffer storage operation of block to be encoded after receiving the first parameter.
3. method according to claim 2, is characterized in that, triggers interleaving address calculating operation after the data buffer storage of block to be encoded.
4. method according to claim 1, is characterized in that, to the mod ((mf in recurrence relation 1+ m 2f 2), K) numerical value store.
5. a Turbo code encoder, described encoder applies, in LTE system, is characterized in that, this encoder comprises: receiving element, interleave unit, reading unit and coding unit, and for the buffer unit of buffer memory block to be encoded data, wherein:
Described receiving element, for receiving the first parameter characterizing block to be encoded size;
Described interleave unit, for according to the first parameter, the second parameter and the 3rd calculation of parameter interleaving address, described second parameter, the 3rd parameter are the preset parameter with the first parameter with corresponding relation;
Described reading unit, the data of the data reading the block to be encoded of buffer memory for order and the block to be encoded reading buffer memory according to interleaving address;
Described coding unit, for the data of the block to be encoded of buffer memory that order read with carry out Recursive Systematic Convolutional coding according to the data of block to be encoded that interleaving address reads, and exports;
Described interleave unit is specifically for obtaining recursion initial value; Determine the recurrence relation of i-th data after interweaving and the individual data of front Π (i+m) that interweave according to the following formula:
Π(i+m)＝mod((Π(i)+mod((mf 1+m 2f 2),K)+mod(2mi·f 2,K)),K)
In formula: the span of i is 0 to (K-1), and m is the data amount check of parallel processing, and Π (0) be the recursion initial value obtained, and K is the first parameter of sign block to be encoded size, f 1be the second parameter, f 2it is the 3rd parameter;
According to above-mentioned recurrence relation determination interleaving address;
The data rate of described buffer memory block to be encoded and the data output rate after Recursive Systematic Convolutional is encoded meet following relation:
Data output rate after Recursive Systematic Convolutional coding and the ratio of the data rate of buffer memory block to be encoded are the integer power of 2.
6. encoder according to claim 5, is characterized in that, receiving element triggers buffer unit after receiving the first parameter characterizing block to be encoded size and carries out data buffer storage operation.
7. encoder according to claim 6, is characterized in that, triggers interleave unit and carry out interleaving address calculating operation after the data of the complete block to be encoded of buffer unit buffer memory.
8. encoder according to claim 5, is characterized in that, described buffer unit comprises two sub-buffer units, and two sub-buffer units are alternately for buffer memory and read operation.
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