CN102104387A - Decoder and decoding method - Google Patents

Decoder and decoding method Download PDF

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CN102104387A
CN102104387A CN2009102582133A CN200910258213A CN102104387A CN 102104387 A CN102104387 A CN 102104387A CN 2009102582133 A CN2009102582133 A CN 2009102582133A CN 200910258213 A CN200910258213 A CN 200910258213A CN 102104387 A CN102104387 A CN 102104387A
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mod
data
buffer address
interweaves
initial value
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邱伟
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ZTE Corp
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ZTE Corp
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Abstract

The invention provides a decoder and a decoding method. The decoder comprises an interleaver which comprises a buffer module, a shunting module, a first reading module, an interleaving processing module and a second reading module, wherein the buffer module is used for buffering data to be interleaved; the shunting module is used for uniformly dividing the data to be interleaved into N paths of subdata according to the code block length of the data to be interleaved; the first reading module is used for reading the pre-interleaving buffer addresses of the N paths of subdata; the interleaving processing module is used for respectively interleaving and processing the pre-interleaving buffer address of the N paths of subdata to acquire post-interleaving buffer addresses of the N paths of subdata; and the second reading module is used for reading data from the buffer module according to the interleaved buffer addresses to acquire the interleaved data. By using the method, the interleaving efficiency of the interleaver can be effectively improved to further improve the decoding efficiency of the decoder.

Description

Decoder and interpretation method
Technical field
The present invention relates to communication technical field, relate in particular to a kind of decoder and interpretation method.
Background technology
Turbo code is a kind of channel coding method effective and commonly used, because it still can obtain the lower error rate under near the low signal-to-noise ratio of the Shannon limit, thereby in the multiple scheme of 3-G (Generation Three mobile communication system), consider Turbo code as one of coding standard of wireless channel.
Interleaver is the important composition parts in Turbo code encoder and the decoder, and it makes two sub-cataloged procedures be tending towards relatively independent in cataloged procedure, and at the decoding end, then is the bridge that connects two sub-decoders.Owing to used interleaver, make at the decoding end, the error event that for some sub-decoders, can not entangle, and in another sub-decoder, separated, become and can entangle mistake.
Interleaver roughly can be divided into two classes, and a class is a random interleaving, and another kind of is that certainty interweaves.Theoretically, the random interleaving performance is optimum, but because random interleaving when decoding, need be sent to whole interleaver information of coding side the decoding end, thereby take system bandwidth, has reduced coding and efficiency of transmission, is not suitable for practical application.Certainty interweaves and is meant that coding side and decoding end all know mutual interleaving mode in advance, need not mutual interleaving mode information, thereby, have higher coding and efficiency of transmission, be adapted at using in the mobile communication system.
In 3GPP LTE agreement, the interleaver of Turbo code coding side has adopted a kind of special interleaving mode that is different from other standards, is specially: being input as of interleaver: c 0, c 1, c 2, c 3..., c K-1, wherein, K is a code block length, its span is: 40≤K≤6144, interleaver is output as: c ' 0, c ' 1..., c ' K-1, satisfy following relation between the input and output of interleaver:
c′ i＝c ∏(i)，(i＝0，...，K-1)
∏(i)＝mod(f 1×i+f 2×i 2，K)
Wherein, mod is for getting surplus operation, parameter f 1And f 2Value change parameter f according to the variation of code block length K 1, f 2As shown in table 1 with the corresponding relation of K.
Table 1
i Ki f 1 f 2 i Ki f 1 f 2 i Ki f 1 f 2 i Ki f 1 f 2
1 40 3 10 48 416 25 52 95 1120 67 140 142 3200 111 240
2 48 7 12 49 424 51 106 96 1152 35 72 143 3264 443 204
3 56 19 42 50 432 47 72 97 1184 19 74 144 3328 51 104
4 64 7 16 51 440 91 110 98 1216 39 76 145 3392 51 212
5 72 7 18 52 448 29 168 99 1248 19 78 146 3456 451 192
6 80 11 20 53 456 29 114 100 1280 199 240 147 3520 257 220
7 88 5 22 54 464 247 58 101 1312 21 82 148 3584 57 336
8 96 11 24 55 472 29 118 102 1344 211 252 149 3648 313 228
9 104 7 26 56 480 89 180 103 1376 21 86 150 3712 271 232
10 112 41 84 57 488 91 122 104 1408 43 88 151 3776 179 236
11 120 103 90 58 496 157 62 105 1440 149 60 152 3840 331 120
12 128 15 32 59 504 55 84 106 1472 45 92 153 3904 363 244
13 136 9 34 60 512 31 64 107 1504 49 846 154 3968 375 248
14 144 17 108 61 528 17 66 108 1536 71 48 155 4032 127 168
15 152 9 38 62 544 35 68 109 1568 13 28 156 4096 31 64
16 160 21 120 63 560 227 420 110 1600 17 80 157 4160 33 130
17 168 101 84 64 576 65 96 111 1632 25 102 158 4224 43 264
18 176 21 44 65 592 19 74 112 1664 183 104 159 4288 33 134
19 184 57 46 66 608 37 76 113 1696 55 954 160 4352 477 408
20 192 23 48 67 624 41 234 114 1728 127 96 161 4416 35 138
21 200 13 50 68 640 39 80 115 1760 27 110 162 4480 233 280
22 208 27 52 69 656 185 82 116 1792 29 112 163 4544 357 142
23 216 11 36 70 672 43 252 117 1824 29 114 164 4608 337 480
24 224 27 56 71 688 21 86 118 1856 57 116 165 4672 37 146
25 232 85 58 72 704 155 44 119 1888 45 354 166 4736 71 444
26 240 29 60 73 720 79 120 120 1920 31 120 167 4800 71 120
27 248 33 62 74 736 139 92 121 1952 59 610 168 4864 37 152
28 256 15 32 75 752 23 94 122 1984 185 124 169 4928 39 462
29 264 17 198 76 768 217 48 123 2016 113 420 170 4992 127 234
30 272 33 68 77 784 25 98 124 2048 31 64 171 5056 39 158
31 280 103 210 78 800 17 80 125 2112 17 66 172 5120 39 80
32 288 19 36 79 816 127 102 126 2176 171 136 173 5184 31 96
33 296 19 74 80 832 25 52 127 2240 209 420 174 5248 113 902
34 304 37 76 81 848 239 106 128 2304 253 216 175 5312 41 166
35 312 19 78 82 864 17 48 129 2368 367 444 176 5376 251 336
36 320 21 120 83 880 137 110 130 2432 265 456 177 5440 43 170
37 328 21 82 84 896 215 112 131 2496 181 468 178 5504 21 86
38 336 115 84 85 912 29 114 132 2560 39 80 179 5568 43 174
39 344 193 86 86 928 15 58 133 2624 27 164 180 5632 45 176
40 352 21 44 87 944 147 118 134 2688 127 504 181 5696 45 178
41 360 133 90 88 960 29 60 135 2752 143 172 182 5760 161 120
42 368 81 46 89 976 59 122 136 2816 43 88 183 5824 89 182
43 376 45 94 90 992 65 124 137 2880 29 300 184 5888 323 184
44 384 23 48 91 1008 55 84 138 2944 45 92 185 5952 47 186
45 392 243 98 92 1024 31 64 139 3008 157 188 186 6016 23 94
46 400 151 40 93 1056 17 66 140 3072 47 96 187 6080 47 190
47 408 155 102 94 1088 171 204 141 3136 13 28 188 6144 263 480
In 3GPP LTE agreement, stipulate, interleaver in encoder and the decoder adopts the certainty interleaving mode to interweave, be that interleaver in the decoder also will adopt above-mentioned interleaving mode to interweave, in the prior art and the unexposed specific implementation that interweaves at above-mentioned interleaving mode.
Summary of the invention
In view of this, the invention provides a kind of decoder and interpretation method, can effectively improve the efficient that interweaves of interleaver, thereby further improved the decoding efficiency of decoder.
For addressing the above problem, the invention provides a kind of decoder, comprise interleaver, described interleaver comprises:
Cache module is used for buffer memory and treats interleaving data;
Shunt module is used for the code block length for the treatment of interleaving data according to described, and the described interleaving data for the treatment of is divided into N way data;
First read module is used to read the preceding buffer address that interweaves of described N way data;
The interleaving treatment module is used for respectively buffer address before the interweaving of described N way data is carried out interleaving treatment, obtains the back buffer address that interweaves of described N way data;
Second read module is used for according to the described back buffer address that interweaves, reading of data from described cache module, the data after obtaining interweaving.
Buffer address and the described back buffer address that interweaves satisfy following formula before described interweaving:
c′ i＝c ∏(i)，(i＝0，...，K-1)
∏(i)＝mod(f 1×i+f 2×i 2，K)
Wherein, c iBe the described preceding buffer address that interweaves, c ' iBe the described back buffer address that interweaves, K is the described code block length for the treatment of interleaving data, and the span of K is 40≤K≤6144, and mod is for getting surplus operation, parameter f 1And f 2Value change according to the variation of K.
Described decoder adopts the MAP algorithm to decipher, and described interleaver also comprises:
Memory module is used to store the required correlation computations parameter of the required correlation computations parameter of beta reverse recursion formula, alpha forward recursive formula and the beta computing initial value and the required correlation computations parameter of the vertical recurrence formula of alpha computing initial value of each way data;
Described interleaving treatment module comprises:
Beta reverse recursion module, be used for the back buffer address that interweaves, calculate the buffer address afterwards that interweaves of other data except that described beta computing initial value in the described N way data respectively according to the beta computing initial value of required correlation computations parameter of described beta reverse recursion formula and described N way data;
Alpha forward recursive module, be used for the back buffer address that interweaves, calculate the buffer address afterwards that interweaves of other data except that described alpha computing initial value in the described N way data respectively according to the alpha computing initial value of required correlation computations parameter of described alpha forward recursive formula and described N way data;
Vertical recursion module, be used for interweave back buffer address and the required correlation computations parameter of described vertical recurrence formula according to the beta computing initial value of the definite first via subdata of described beta reverse recursion module, the back buffer address that interweaves of the beta computing initial value of calculating other each way data except that described first via subdata, and, feed back to described beta reverse recursion module with the back buffer address that interweaves of the beta computing initial value of described other each way data; And according to interweave the back buffer address and the required correlation computations parameter of described vertical recurrence formula of the alpha computing initial value of the first via subdata of determining in the described alpha forward recursive module, the back buffer address that interweaves of the alpha computing initial value of calculating other each way data except that described first via subdata, and, feed back to described alpha forward recursive module with the back buffer address that interweaves of the alpha computing initial value of described other each way data.
Described beta reverse recursion formula is:
∏(k-1)＝mod((∏(k)+mod((mod(f 2-f 1，K)-mod(2f 2×k，K))，K))，K)；
Described alpha forward recursive formula is:
∏(k+1)＝mod((∏(k)+mod((mod(f 1+f 2，K)+mod(2f 2×k，K))，K))，K)；
Described vertical recurrence formula is:
∏(k+Δ)＝mod((∏(k)+mod((mod(Δ×f 1+Δ 2×f 2，K)+mod(2f 2×Δ×k，K))，K))，K)。
In the described span for the treatment of the code block length of interleaving data is 40≤K≤512 o'clock, and described N is 1;
In the span of described code block length is 512＜K≤1024 o'clock, and described N is 2;
In the span of described code block length is 1024＜K≤6144 o'clock, and described N is 8.
The present invention also provides a kind of interpretation method, and described interpretation method may further comprise the steps:
The decoder buffer memory is treated interleaving data;
Described decoder is divided into N way data according to the described code block length for the treatment of interleaving data with the described interleaving data for the treatment of;
Described decoder reads the preceding buffer address that interweaves of described N way data;
Described decoder carries out interleaving treatment to buffer address before the interweaving of described N way data respectively, obtains the back buffer address that interweaves of described N way data;
Described decoder reads the described interleaving data for the treatment of of buffer memory, the data after obtaining interweaving according to the described back buffer address that interweaves.
Buffer address and the described back buffer address that interweaves satisfy following formula before described interweaving:
c′ i＝c ∏(i)，(i＝0，...，K-1)
∏(i)＝mod(f 1×i+f 2×i 2，K)
Wherein, c iBe the described preceding buffer address that interweaves, c ' iBe the described back buffer address that interweaves, K is the described code block length for the treatment of interleaving data, and the span of K is 40≤K≤6144, and mod is for getting surplus operation, parameter f 1And f 2Value change according to the variation of K.
Described decoder adopts the MAP algorithm to decipher, and described decoder carries out interleaving treatment to buffer address before the interweaving of described N way data respectively, obtains the back buffer address that interweaves of described N way data, is specially:
Required required correlation computations parameter and the beta computing initial value of each way data and the required correlation computations parameter of vertical recurrence formula of alpha computing initial value of correlation computations parameter, alpha forward recursive formula of described decoder storage beta reverse recursion formula;
Described decoder calculates the back buffer address that interweaves of the beta computing initial value of other each way data except that described first via subdata according to interweave the back buffer address and the required correlation computations parameter of described vertical recurrence formula of the beta computing initial value of first via subdata;
Described decoder calculates the back buffer address that interweaves of the alpha computing initial value of other each way data except that described first via subdata according to interweave the back buffer address and the required correlation computations parameter of described vertical recurrence formula of the alpha computing initial value of first via subdata;
Described decoder calculates the buffer address afterwards that interweaves of other data except that described beta computing initial value in the described N way data respectively according to the back buffer address that interweaves of the beta computing initial value of required correlation computations parameter of described beta reverse recursion formula and described N way data;
Described decoder calculates the buffer address afterwards that interweaves of other data except that described alpha computing initial value in the described N way data respectively according to the back buffer address that interweaves of the alpha computing initial value of required correlation computations parameter of described alpha forward recursive formula and described N way data.
Described beta reverse recursion formula is:
∏(k-1)＝mod((∏(k)+mod((mod(f 2-f 1，K)-mod(2f 2×k，K))，K))，K)；
Described alpha forward recursive formula is:
∏(k+1)＝mod((∏(k)+mod((mod(f 1+f 2，K)+mod(2f 2×k，K))，K))，K)；
Described vertical recurrence formula is:
∏(k+Δ)＝mod((∏(k)+mod((mod(Δ×f 1+Δ 2×f 2，K)+mod(2f 2×Δ×k，K))，K))，K)。
In the described span for the treatment of the code block length of interleaving data is 40≤K≤512 o'clock, and described N is 1;
In the span of described code block length is 512＜K≤1024 o'clock, and described N is 2;
In the span of described code block length is 1024＜K≤6144 o'clock, and described N is 8.
The present invention has following beneficial effect:
Can be according to the code block length for the treatment of interleaving data, Dynamic Selection will treat that interleaving data is divided into N way data, walk abreast described N way data are carried out interleaving treatment, because each road treats that the data volume of interleaving data is all less, therefore, can effectively improve the efficient that interweaves of interleaver, thereby further improve the decoding efficiency of decoder, meet the requirement of handling the business of high speed, large data capacity in the 3GPP LTE standard.
When decoder adopts the MAP algorithm to decipher, can be by the mode of beta reverse recursion, calculate the back buffer address that interweaves of the beta operational data of N way data correspondence fast, mode by the alpha forward recursive, calculate the back buffer address that interweaves of the alpha operational data of N way data correspondence fast, and the mode by vertical recursion, calculate the beta computing initial value of each way data correspondence and the back buffer address that interweaves of alpha computing initial value fast, thereby can reduce the computation complexity of interleaver, save the consumption of hardware resource.
Device is realized simple, and clear in structure adopts general low-cost circuit devcie to realize, guaranteeing cheaply simultaneously, can increase substantially the felt properties of interleaver, thereby improve the decoding efficiency of decoder.
Description of drawings
Fig. 1 is the operation principle schematic diagram of the Turbo decoder of the embodiment of the invention;
Fig. 2 is a structural representation of the decoder of the embodiment of the invention;
Fig. 3 for the embodiment of the invention be used to store interweave before the structural representation of buffer area of data;
Fig. 4 is the structural representation of the beta reverse recursion circuit of the embodiment of the invention;
Fig. 5 is the structural representation of the alpha forward recursive circuit of the embodiment of the invention;
Fig. 6 is each way data recurrence relation schematic diagram of the embodiment of the invention;
Fig. 7 is another structural representation of the decoder of the embodiment of the invention;
Fig. 8 is a concrete application scenarios schematic diagram of the decoder of the embodiment of the invention;
Fig. 9 is the single channel s operation control signal timing diagram of the embodiment of the invention;
Figure 10 is the two-way s operation control signal timing diagram of the embodiment of the invention;
Figure 11 is eight tunnel s operation control signal timing diagrams of the embodiment of the invention;
Figure 12 is a flow process schematic diagram of the interpretation method of the embodiment of the invention;
Figure 13 is another schematic flow sheet of the interpretation method of the embodiment of the invention.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.
Understand for convenient, at first the operation principle of the Turbo decoder of the embodiment of the invention is simply introduced, be illustrated in figure 1 as the operation principle schematic diagram of the Turbo decoder of the embodiment of the invention, the Turbo decoder is made up of two soft input and output sub-decoder polyphones, in the embodiment of the invention, two sub-decoders adopt MAX-LOG-MAP (logarithm maximum a posteriori probability) algorithm to decipher, and when carrying out decoding, first MAP sub-decoder is to the original information bits x of input kWith the first check code y 1kDecipher, produce the likelihood information of information bit, and after will external information wherein interweaving, send into second MAP sub-decoder through interleaver.Second MAP sub-decoder with this information as prior information, to the information bit x after interweaving through interleaver 2kWith the second check code y 2kDecipher, produce the likelihood information of information bit, and first MAP sub-decoder will be fed back to after the external information deinterleaving wherein, decipher next time, through after the iteration repeatedly, the external information of first MAP sub-decoder and second MAP sub-decoder tends towards stability, and at last likelihood ratio is carried out hard decision, obtains decoding information.
In Turbo decoder for decoding process, interleaver is the critical component that improves Turbo decoder for decoding performance, at the interleaver in the Turbo decoder, proposes a kind of new interleaving mode in the embodiment of the invention, can effectively improve the decoding efficiency of decoder, will be described in detail below.
Be illustrated in figure 2 as a structural representation of the decoder of the embodiment of the invention, described decoder can be applied to integrated circuit (IC) design field, FPGA (field programmable gate array) design field and moving communicating field.
Described decoder comprises: two sub-decoders, two interleavers, two deinterleavers and a hard decision module, the annexation between the module as shown in Figure 1.
Described interleaver comprises:
Cache module 201 is used for buffer memory and treats interleaving data; The interleaving data for the treatment of that is about to input is cached in the pre-assigned buffer area successively.
Shunt module 202 is used for the code block length for the treatment of interleaving data according to described, and the described interleaving data for the treatment of is divided into N way data; Described N is the integer more than or equal to 1;
First read module 203 is used to read the preceding buffer address that interweaves of described N way data; Promptly read and treat the buffer address of interleaving data in above-mentioned buffer area.
Interleaving treatment module 204 is used to adopt default interleaving mode, respectively buffer address before the interweaving of described N way data is carried out interleaving treatment, obtains the back buffer address that interweaves of described N way data; When being applied to 3GPP LTE communication system, the interleaving mode that described default interleaving mode can adopt for the interleaver of the Turbo code encoder stipulated in the 3GPP LTE agreement.
Second read module 205 is used for according to the described back buffer address that interweaves, reading of data from described cache module, the data after obtaining interweaving.
Adopting the interleaving mode of stipulating in the 3GPP LTE agreement with described interleaver below is example, and the decoder of the embodiment of the invention is elaborated.
The default interleaving mode that described interleaver adopts is as follows:
c′ i＝c ∏(i)，(i＝0，...，K-1)....................................(1)
∏(i)＝mod(f 1×i+f 2×i 2，K)....................................(2)
Wherein, c 0, c 1, c 2, c 3..., c K-1Be the input data of interleaver, K is a code block length, and the span of K is 40≤K≤6144, c ' 0, c ' 1..., c ' K-1The dateout of interleaver, mod is for getting surplus operation, parameter f 1And f 2Value change parameter f according to the variation of code block length K 1, f 2As shown in table 1 with the corresponding relation of K.
Regulation according to agreement, the code block length K that treats interleaving data is 6144 to the maximum, therefore, the described size that is used to store the buffer area for the treatment of interleaving data is set to 6144 usually, buffer address is from 0～6143, interleaver can be cached to a described K data in the buffer area from buffer address 0 successively receiving code block length when being the data of K.
The operation principle of described interleaver be will input the order of data sequence rearrange back output, in embodiments of the present invention, promptly be that buffer address interweaves before treating the interweaving of interleaving data, the back buffer address obtains interweaving, and according to buffer address reading of data after interweaving and output, the data after obtaining interweaving.
When the code block length K that treats interleaving data is big, for example be 4096 o'clock, if interweave these 4096 buffer address for the treatment of interleaving data simultaneously,, will certainly influence the efficient that interweaves owing to treat that the data volume of interleaving data is bigger.
In the embodiment of the invention, can be when the code block length K that treats interleaving data be big, the described interleaving data for the treatment of is divided into the less subdata of N circuit-switched data amount, walk abreast the less subdata of described N circuit-switched data amount is carried out interleaving treatment, then can effectively improve the efficient that interweaves of interleaver, thereby further improve the decoding efficiency of decoder.
Value according to the code block length K of record in the table 1, in the embodiment of the invention, can will treat that interleaving data is divided into 1 tunnel, 2 tunnel, 4 road or 8 way data, promptly the value of N can be 1,2,4 or 8, below so that the value of N can be example describe the decoder of the embodiment of the invention for 1,2,8.
In the span of the code block length K that treats interleaving data is 40≤K≤512 o'clock, and can set N is 1, at this moment, owing to treat that the data volume of interleaving data is less, therefore, does not need to treat interleaving data parallel processing along separate routes.
In the span of the code block length K that treats interleaving data is 512＜K≤1024 o'clock, and can set N is 2, at this moment, owing to treat that the data volume of interleaving data is bigger, therefore, will treat that interleaving data is divided into the 2 tunnel parallel interleaving treatment of carrying out.
In the span of the code block length K that treats interleaving data is 1024＜K≤6144 o'clock, and can set N is 8, at this moment, owing to treat that the data volume of interleaving data is very big, therefore, will treat that interleaving data is divided into the 8 tunnel parallel interleaving treatment of carrying out.
Handle for convenience, as shown in Figure 3, in the embodiment of the invention, can treat that it is 768 that the buffer area of interleaving data is divided into 8 degree of depth with being used for buffer memory, bit wide is sub-buffer area mem0～mem7 of 8bit, in the span of the code block length K that treats interleaving data is 40≤K≤512 o'clock, only need to get final product with treating that interleaving data is buffered among the mem0, in the span of the code block length K that treats interleaving data is 512＜K≤1024 o'clock, 2 way data can be buffered in respectively among mem0 and the mem1, in the span of the code block length K that treats interleaving data is 1024＜K≤6144 o'clock, 8 way data can be buffered among mem0～mem7 respectively.For example, suppose to treat that the code block length K of interleaving data is 4096, then described 4096 data are divided into 8 tunnel length and are 512 subdata, and be respectively that 512 subdata is buffered among mem0～mem7 respectively with this 8 tunnel length, concrete, first via subdata is stored among the mem0, and in mem1, the rest may be inferred with the second way storage.
The decoder that provides by the foregoing description, can be according to the code block length for the treatment of interleaving data, Dynamic Selection will treat that interleaving data is divided into N way data, walk abreast described N way data are carried out interleaving treatment, because each road treats that the data volume of interleaving data is all less, therefore, can effectively improve the efficient that interweaves of interleaver, thereby further improved the decoding efficiency of decoder, met the requirement of handling the business of high speed, large data capacity in the 3GPP LTE standard.
Mention in the foregoing, the Turbo decoder can adopt the MAX-LOG-MAP algorithm to decipher, adopting the MAX-LOG-MAP algorithm with described decoder below is example, decoder to the embodiment of the invention is further detailed, certainly, decoder in the foregoing description also can adopt other decoding algorithms to decipher, for example, and soft output Viterbi algorithm (SOVA) etc.
In the embodiment of the invention, sub-decoder in the decoder is the MAP sub-decoder, when the MAP sub-decoder is carried out decoding, need to calculate respectively gamma (branched measurement value), beta (back is to metric) and the alpha (forward metrics value) of input data, calculate the LLR (log-likelihood ratio) of input data then.Because the back data that interweave that described interleaver obtains need be imported the MAP sub-decoder and decipher, therefore, the back data that interweave that interleaver obtains need satisfy the beta operational data in the MAP sub-decoder and the feature of alpha operational data.
At first introduce the computational methods of the back buffer address that interweaves of the beta operational data for the treatment of the interleaving data correspondence.
Calculating treat the interleaving data correspondence the beta operational data interweave the back during buffer address, usually at first calculate the described back buffer address that interweaves for the treatment of the beta computing initial value of interleaving data correspondence, suppose to treat that the beta computing initial value of interleaving data correspondence is k, interleaving mode according to above-mentioned formula (1) and formula (2) record, can obtain, treat that the back buffer address that interweaves of the beta computing initial value k of interleaving data correspondence is:
∏(k)＝mod(f 1×k+f 2×k 2，K)；
And the described back buffer address that interweaves of other data except that described beta computing initial value in the interleaving data for the treatment of is followed successively by:
∏(k-1)＝mod(f 1×(k-1)+f 2×(k-1) 2，K)；
∏(k-2)＝mod(f 1×(k-2)+f 2×(k-2) 2，K)；
……
From the aforementioned calculation formula as can be seen, comprise a large amount of multiplyings in the computing formula of beta operational data, a large amount of multiplyings will increase the computation complexity of interleaver greatly.
In the embodiment of the invention,, the multiplying in the computing formula of described beta operational data can be converted to comparatively simple addition of computing or subtraction, will be described in detail below in order to reduce the computation complexity of interleaver.
To formula ∏ (k-1)=mod (f 1* (k-1)+f 2* (k-1) 2, K) derive, can obtain a beta reverse recursion formula:
∏(k-1)＝mod(f 1×(k-1)+f 2×(k-1) 2，K)
＝mod((f 1×k-f 1+f 2×k 2-2f 2×k+f 2)，K)
＝mod((mod(f 1×k+f 2×k 2，K)+mod(f 2-f 1，K)-mod(2f 2×k，K))，K)
＝mod((∏(k)+mod(f 2-f 1，K)-mod(2f 2×k，K))，K)
＝mod((∏(k)+mod((mod(f 2-f 1，K)-mod(2f 2×k，K))，K))，K)
Only comprise addition or subtraction in the above-mentioned beta reverse recursion formula, therefore, can effectively reduce the computation complexity of interleaver.
When code block length K is known, the f in the above-mentioned beta reverse recursion formula 2-f 1And 2f 2* k all can be by inquiring about above-mentioned table 1 and calculating, therefore, and the mod ((f in the above-mentioned beta reverse recursion formula 2-f 1), K) and mod (2f 2* k K) then can find the solution out.
In concrete the application, can be with the correlation computations parameter in the above-mentioned beta reverse recursion formula, as: ∏ (k), mod ((f 2-f 1), K) and mod (2f 2* k, K) etc., be stored in advance in the buffer memory, according to code block length K value question blank 1, and by the required correlation computations parameter of the beta reverse recursion formula of above-mentioned storage, calculate the back buffer address that interweaves of the beta operational data for the treatment of the interleaving data correspondence fast, the aforementioned calculation process can be finished by the circuit with beta reverse recursion structure shown in Figure 4, among the figure, + be adder,-be subtracter, MUX is a selector, reg is a register; Wherein:
E＝{[(2f 2i?mod?k)add((f 2?sub?f 1?mod?k?add-2f 2init?mod?k)mod?k)]}mod?k
M＝(f 2?sub?f 1?add-2f 2init?mod?k)mod?k
N＝[(f 2?sub?f 1?mod?k?add?2f 2?init?mod?k)mod?k]sub?k。
For example the reverse recursion process of the back buffer address that interweaves of above-mentioned beta operational data is elaborated below.
Suppose to treat the code block length K=4096 of interleaving data, before interweaving, described data are divided into 8 way data, the preceding buffer address that interweaves of first via subdata is 0～511, the preceding buffer address that interweaves of the second way data is: 511～1023......, the preceding buffer address that interweaves of the 8th way data is: 3584～4095.
Be example with the beta operational data of obtaining first via subdata correspondence below:
At first determine the beta computing initial value of first via subdata: k=511+32=543; Wherein, 32 data lengths for initial value calculating selection;
Obtain back buffer address: ∏ (the k)=∏ (543)=513 that interweaves of the beta computing initial value of first via subdata; The back buffer address that interweaves of the beta computing initial value of first via subdata can be stored in the buffer memory in advance, also can pass through formula ∏ (k)=mod (f 1* k+f 2* k 2, K) calculate in real time;
K=4096 corresponding parameters f in the question blank 1 1, f 2, and according to the f that inquires 1, f 2Value and the correlation computations parameter in the above-mentioned beta reverse recursion formula, calculate in the first via subdata buffer address afterwards that interweaves of other data except that beta computing initial value, in the aforementioned calculation process, when occurring overflowing, to get surplusly, concrete computational process is as follows:
∏(k-1)＝∏(542)＝mod((∏(543)+mod((64-31，4096)-mod(2×64×543，4096))，4096))，4096)＝674
∏(k-2)＝∏(541)＝mod((∏(542)+mod((64-31，4096)-mod(2×64×542，4096))，4096))，4096)＝963
……
The rest may be inferred, until reverse recursion go out all data correspondences in the first via subdata the beta operational data interweave the back buffer address.
Introduce the computational methods of the back buffer address that interweaves of the alpha operational data for the treatment of the interleaving data correspondence below.
Calculating treat the interleaving data correspondence the alpha operational data interweave the back during buffer address, usually at first calculate the described back buffer address that interweaves for the treatment of the alpha computing initial value of interleaving data correspondence, suppose to treat that the alpha computing initial value of interleaving data correspondence is k, interleaving mode according to above-mentioned formula (1) and formula (2) record, can obtain, treat that the back buffer address that interweaves of the alpha computing initial value k of interleaving data correspondence is:
∏(k)＝mod(f 1×k+f 2×k 2，K)；
And the described back buffer address that interweaves of other data except that described alpha computing initial value in the interleaving data for the treatment of is followed successively by:
∏(k+1)＝mod(f 1×(k+1)+f 2×(k+1) 2，K)；
∏(k+2)＝mod(f 1×(k+2)+f 2×(k+2) 2，K)；
……
From the aforementioned calculation formula as can be seen, comprise a large amount of multiplyings in the computing formula of alpha operational data, a large amount of multiplyings will increase the computation complexity of interleaver greatly.
In the embodiment of the invention,, the multiplying in the computing formula of described alpha operational data can be converted to comparatively simple addition of computing or subtraction, will be described in detail below in order to reduce the computation complexity of interleaver.
To formula ∏ (k+1)=mod (f 1* (k+1)+f 2* (k+1) 2, K) derive, can obtain an alpha forward recursive formula:
∏(k+1)＝mod(f 1×(k+1)+f 2×(k+1) 2，K)
＝mod((f 1×k+f 1+f 2×k 2+2f 2×k+f 2)，K)
＝mod((mod(f 1×k+f 2×k 2，K)+mod(f 1+f 2，K)+mod(2f 2×k，K))，K)
＝mod((∏(k)+mod(f 1+f 2，K)+mod(2f 2×k，K))，K)
＝mod((∏(k)+mod((mod(f 1+f 2，K)+mod(2f 2×k，K))，K))，K)
Only comprise addition or subtraction in the above-mentioned alpha forward recursive formula, therefore, can effectively reduce the computation complexity of interleaver.
When code block length K is known, the f in the above-mentioned alpha forward recursive formula 1+ f 2And 2f 2* k all can be by inquiring about above-mentioned table 1 and calculating, therefore, and the mod (f in the above-mentioned alpha forward recursive formula 1+ f 2, K) and mod (2f 2* k K) then can find the solution out.
In concrete the application, can be with the correlation computations parameter in the above-mentioned alpha forward recursive formula, as: ∏ (k), mod (f 1+ f 2, K) and mod (2f 2* k, K), be stored in advance in the buffer memory, according to code block length K value question blank 1, and by the required correlation computations parameter of the alpha forward recursive formula of above-mentioned storage, calculate the back buffer address that interweaves of the alpha operational data for the treatment of the interleaving data correspondence fast, the aforementioned calculation process can be finished by the circuit with alpha forward recursive structure shown in Figure 5, among the figure, + be adder,-be subtracter, MUX is a selector, reg is a register; Wherein:
E＝{[(2f 22i?mod?k)add((f 1?add?f 2?mod?k?add?2f 2init?mod?k)mod?k)]}mod?k
M＝(f 1?add?f 2?mod?k?add?2f 2init?mod?k)mod?k
N＝[(f 1?add?f 2?mod?k?add?2f 2init?mod?k)mod?k]sub?k。
For example the forward recursive process of the back buffer address that interweaves of above-mentioned alpha operational data is elaborated below.
Suppose to treat the code block length K=4096 of interleaving data, before interweaving, described data are divided into 8 way data, the preceding buffer address that interweaves of first via subdata is 0～511, the preceding buffer address that interweaves of the second way data is: 511～1023......, the preceding buffer address that interweaves of the 8th way data is: 3584～4095.
The back buffer address that interweaves with the alpha operational data of obtaining the second way data correspondence is that example describes below.
At first determine the alpha computing initial value of the second way data: k=512-32=480; Wherein, 32 data lengths for initial value calculating selection;
Obtain back buffer address: ∏ (the k)=∏ (480)=2592 that interweaves of the alpha computing initial value of the second way data; The back buffer address that interweaves of the alpha computing initial value of the second way data can be stored in the buffer memory in advance, also can pass through formula ∏ (k)=mod (f 1* k+f 2* k 2, K) calculate in real time;
K=4096 corresponding parameters f in the question blank 1 1, f 2, and according to the f that inquires 1, f 2Value and the required correlation computations parameter of above-mentioned alpha forward recursive formula, calculate in the second way data back buffer address that interweaves of other data except that alpha computing initial value, in the aforementioned calculation process, when occurring overflowing, to get surplusly, concrete computational process is as follows:
∏(k+1)＝∏(481)＝mod((∏(480)+mod((31+64，4096)+mod(2×64×480，4096))，4096))，4096)＝2687
∏(k+2)＝∏(482)＝mod((∏(481)+mod((31+64，4096)+mod(2×64×482，4096))，4096))，4096)＝2910
……
The rest may be inferred, until forward recursive go out all data correspondences in the described second way data the alpha operational data interweave the back buffer address.
From the foregoing description as can be seen, treat interweaving during the buffer address of back of the beta operational data of interleaving data correspondence and alpha operational data in calculating, need at first determine to treat the beta computing initial value and the alpha computing initial value of interleaving data, then could be according to described initial value corresponding cache address, calculate and treat in the interleaving data buffer address afterwards that interweaves of other data correspondences except that described initial value.
In the embodiment of the invention, can be at the beta of known first via subdata computing initial value and alpha computing initial value interweave the back during buffer address, mode by vertical recursion, recursion goes out the beta computing initial value of other way data and the back buffer address that interweaves of alpha computing initial value fast, will be described in detail below.
Be illustrated in figure 6 as each way data recurrence relation schematic diagram of the embodiment of the invention, as can be seen from the figure, the beta computing initial value of first via subdata to the seven way data is respectively: 543,1055,1567,2079,2591,3103,3615, interval between the adjacent initial value is Δ=K/8=512, yet, the beta computing initial value that it should be noted that the 8th way data is 4095, and the interval between the beta computing initial value 3615 of the 7th way data is not equal to 512.In addition, the alpha computing initial value of the second way data to the, eight way data is respectively: 480,992,1504,2016,2526,3040,3552, interval between the adjacent initial value is Δ=K/8=512, yet, it should be noted that, the alpha computing initial value of first via subdata is 0, and the interval between the alpha computing initial value 480 of the second way data is not equal to 512.
Vertical recursion with the back buffer address that interweaves of the beta computing initial value of each way data correspondence is that example describes below.
The beta computing initial value of supposing first via subdata is k, and the interleaving mode according to above-mentioned formula (1) and formula (2) record can obtain, and the back buffer address that interweaves of the beta computing initial value k correspondence of first via subdata is:
∏(k)＝mod(f 1×k+f 2×k 2，K)；
Owing to be spaced apart Δ=K/8=512 between the beta computing initial value of the beta computing initial value of the second way data and first via subdata, therefore, can go out the computing formula of the beta computing initial value of the second way data according to the beta computing initial value recursion of first via subdata, as follows:
∏(k+Δ)＝mod(f 1×(k+Δ)+f 2×(k+Δ) 2，K)
＝mod((f 1×k+Δ×f 1+f 2×Δ 2+2f 2×Δ
＝mod((∏(k)+mod((mod(Δ×f 1+Δ 2×f 2，K)+mod(2f 2×Δ×k，K))，K))，K)
When code block length K is known, the Δ * f in above-mentioned vertical recurrence formula 1+ Δ 2* f 2And 2f 2* Δ * k all can be by inquiring about above-mentioned table 1 and calculating, therefore, and the mod (Δ * f in above-mentioned vertical recurrence formula 1+ Δ 2* f 2, K) and mod (2f 2* Δ * k K) then can find the solution out.
In concrete the application, correlation computations parameter that can above-mentioned vertical recurrence formula is required, as: ∏ (k), mod (Δ * f 1+ Δ 2* f 2, K) and mod (2f 2* Δ * k, K), be stored in advance in the buffer memory, according to code block length K value question blank 1, and, calculate the back buffer address that interweaves of the beta computing initial value of other subdatas fast according to the back buffer address that interweaves of the beta computing initial value of the required correlation computations parameter of vertical recurrence formula of storage and first via subdata.
In like manner, can calculate the back buffer address that interweaves of the alpha computing initial value of other subdatas fast according to the back buffer address that interweaves of the alpha computing initial value of required correlation computations parameter of described vertical recurrence formula and first via subdata.
For example above-mentioned vertical recursive process is described below.
Suppose to treat the code block length K=4096 of interleaving data, before interweaving, the described interleaving data for the treatment of is divided into 8 way data, the preceding buffer address that interweaves of first via subdata is 0～511, the preceding buffer address that interweaves of the second way data is: 511～1023......, the preceding buffer address that interweaves of the 8th way data is: 3584～4095.
The back buffer address that interweaves with the alpha computing initial value that calculates each way data correspondence is that example describes below.
At first determine the alpha computing initial value of the second way data: k=512-32=480;
Obtain back buffer address: ∏ (the k)=∏ (480)=2592 that interweaves of the alpha computing initial value of the second way data; The back buffer address that interweaves of described alpha computing initial value can be stored in the buffer memory in advance, also can pass through ∏ (k)=mod (f 1* k+f 2* k 2, K) calculate in real time;
K=4096 corresponding parameters f in the question blank 1 1, f 2, according to the f that inquires 1, f 2Value and the required correlation computations parameter of above-mentioned vertical recurrence formula, calculate the back buffer address that interweaves of the alpha computing initial value of Third Road subdata, in the aforementioned calculation process, when occurring overflowing, to get surplusly, concrete computational process is as follows:
The back buffer address that interweaves of the alpha computing initial value of Third Road subdata is:
∏(992)＝mod((∏(480)+mod(512×31+512 2×64，4096)+mod(2×64×512×31，4096))，4096))，4096)
……
The rest may be inferred, until the back buffer address that interweaves of the alpha computing initial value that calculates the 8th way data.Because the alpha computing initial value of first via subdata is 0, and the interval between the alpha computing initial value 480 of the second way data is not equal to 512, and therefore, the back buffer address that interweaves of the alpha computing initial value of first via subdata is according to formula ∏ (k)=mod (f 1* k+f 2* k 2, K) calculate separately, perhaps also can be stored in advance in the buffer memory.
According to the content of foregoing description as can be known, when the sub-decoder in decoder adopted the MAP algorithm to decipher, as shown in Figure 7, described interleaver also comprised:
Memory module 206 is used to store required correlation computations parameter and the beta computing initial value of each way data and the required correlation computations parameter of vertical recurrence formula of alpha computing initial value of forward recursive formula of the required correlation computations parameter of beta reverse recursion formula, alpha operational data;
At this moment, described interleaving treatment module 204 comprises:
Beta reverse recursion module 2041, be used for the back buffer address that interweaves, calculate the buffer address afterwards that interweaves of other data except that described beta computing initial value in the described N way data respectively according to the beta computing initial value of required correlation computations parameter of described beta reverse recursion formula and described N way data;
Alpha forward recursive module 2042, be used for the back buffer address that interweaves, calculate the buffer address afterwards that interweaves of other data except that described alpha computing initial value in the described N way data respectively according to the alpha computing initial value of required correlation computations parameter of described alpha forward recursive formula and described N way data;
Vertical recursion module 2043, be used for interweave back buffer address and the required correlation computations parameter of described vertical recurrence formula according to the beta computing initial value of the definite first via subdata of described beta reverse recursion module, the back buffer address that interweaves of the beta computing initial value of calculating other each way data except that described first via subdata, and, feed back to described beta reverse recursion module with the back buffer address that interweaves of the beta computing initial value of described other each way data; And according to interweave the back buffer address and the required correlation computations parameter of described vertical recurrence formula of the alpha computing initial value of the first via subdata of determining in the described alpha forward recursive module, the back buffer address that interweaves of the alpha computing initial value of calculating other each way data except that described first via subdata, and, feed back to described alpha forward recursive module with the back buffer address that interweaves of the alpha computing initial value of described other each way data.
Wherein, described beta reverse recursion formula is:
∏(k-1)＝mod((∏(k)+mod((mod(f 2-f 1，K)-mod(2f 2×k，K))，K))，K)；
Described alpha forward recursive formula is:
∏(k+1)＝mod((∏(k)+mod((mod(f 1+f 2，K)+mod(2f 2×k，K))，K))，K)；
Described vertical recurrence formula is:
∏(k+Δ)＝mod((∏(k)+mod((mod(Δ×f 1+Δ 2×f 2，K)+mod(2f 2×Δ×k，K))，K))，K)。
The decoder that provides by the foregoing description, when decoder adopts the MAP algorithm to decipher, can be by the mode of beta reverse recursion, calculate the back buffer address that interweaves of the beta operational data of N way data correspondence fast, mode by the alpha forward recursive, calculate the back buffer address that interweaves of the alpha operational data of N way data correspondence fast, and the mode by vertical recursion, calculate the beta computing initial value of each way data correspondence and the back buffer address that interweaves of alpha computing initial value fast, thereby can reduce the computation complexity of interleaver, save the consumption of hardware resource.
For example the course of work of the decoder in the foregoing description is elaborated below.
Be illustrated in figure 8 as a concrete application scenarios schematic diagram of the decoder of the embodiment of the invention, the structure of described decoder as shown in Figure 1, described decoder comprises an interleaver, described interleaver is connected with second MAP sub-decoder with first MAP sub-decoder respectively, and described interleaver mainly comprises: master control module (interleaver_decoder_ctrl), single channel computing module (oneline), two-way computing module (twoline), eight road computing modules (eightline), mem address selection module and mem sequence number are selected module.
Wherein, the single channel computing module is responsible for calculating the interweave back buffer address for the treatment of interleaving data of code block length between 40 and 512, because only adopt a mem storage to treat interleaving data, so in the process of calculating beta operational data and alpha operational data, all need not calculate initial value.When utilizing recursive algorithm calculating to interweave the back buffer address, mem_num is appointed as 0 always, and the control signal of input single channel computing module as shown in Figure 9.
The two-way computing module is responsible for calculating the interweave back buffer address for the treatment of interleaving data of code block length between 512 and 1024, in the process of first via subdata calculating alpha operational data, do not need to calculate alpha computing initial value, and in the process of the second way data computation beta operational data, do not need to calculate beta computing initial value.When utilizing recursive algorithm calculating to interweave the back buffer address, mem_num selects 0 or 1 according to the difference of address, and the control signal of input two-way computing module as shown in figure 10.
Eight road computing modules are responsible for calculating the interweave back buffer address for the treatment of interleaving data of code block length between 1024 and 6144, in the process of first via subdata calculating alpha operational data, do not need to calculate alpha computing initial value, and in the process of the 8th way data computation beta operational data, do not need to calculate beta computing initial value, when calculating beta, the alpha operational data on other roads, all need to calculate initial value, the back buffer address that interweaves of the beta of each way data and alpha computing initial value can be obtained by vertical recursion.When utilizing recursive algorithm to calculate to interweave the back buffer address, mem_num selects number between 0～7 according to the difference of address, and the control signal of importing eight road computing modules as shown in figure 11.
The concrete course of work of described decoder is:
Described interleaver receives some control signals of first MAP sub-decoder input, and described control signal comprises: data_cal_en0 (beta calculation control signal), data_cal_en1 (alpha calculation control signal), init_cal_en0 (beta initial value calculation control signal) and init_cal_en1 (alpha initial value calculation control signal).
In addition, the signal of importing described interleaver also comprises clk (clock control signal), rst (zero clearing control signal) and the code block length K that treats interleaving data.
Behind system power-on reset, described master control module is selected to adopt single channel computing module, two-way computing module or eight road computing modules according to the code block length K that treats interleaving data, treats interleaving data and interweaves.
When described master control module is selected to adopt several roads computing module to treat interleaving data to interweave, also produce simultaneously corresponding to the reading the address, read to enable and beta, alpha calculation control signal of the correlation computations parameter of this road computing module, and import this road computing module; Described correlation computations parameter comprises: the correlation computations parameter of vertical recurrence formula of the correlation computations parameter of the correlation computations parameter of beta reverse recursion formula, alpha fortune forward recursive formula and the beta computing initial value of each way data and alpha computing initial value.
After single channel computing module, two-way computing module or eight road computing modules are selected, reading the address, read to enable and beta, alpha calculation control signal according to master control module input corresponding to the correlation computations parameter of this road computing module, buffer address interweaves before treating the interweaving of interleaving data, the back buffer address obtains interweaving, use binary tree algorithm that the back buffer address that interweaves is carried out computing then, obtain mem_addr (buffer address that needs the data of output) and mem_num (the buffer memory sequence number that needs the data place of output).
Concrete, when adopting the single channel computing module to carry out interleaving treatment, the span of mem_addr is 0～512, the scope of mem_num is 0.When adopting the two-way computing module to carry out interleaving treatment, the span of mem_addr is 0～512, and the scope of mem_num is 0～1.When adopting eight road computing modules to carry out interleaving treatment, the span of mem_addr is 0～768, and the scope of mem_num is 0～7.
At last, utilize the mem_addr and the mem_num that calculate, read the data of mem_num mem_addr address in the buffer memory, the data after promptly can obtaining interweaving.
In the foregoing description, single channel computing module, two-way computing module and eight road computing module branches are arranged, in specific implementation, also can not separatedly be provided with, but a computing module with eight road circuit is set, can be simultaneously to the eight way data interleaving treatment that walks abreast, at N is 1 o'clock, only utilize a road in eight road circuit to treat interleaving data and carry out interleaving treatment, at N is 2 o'clock, utilizing two-way in eight road circuit to treat interleaving data and carry out interleaving treatment, is 8 o'clock at N, utilizes whole eight road circuit to treat interleaving data and carries out interleaving treatment.
Decoder device in the foregoing description is realized simple, and clear in structure adopts general low-cost circuit devcie to realize, guaranteeing cheaply simultaneously, can increase substantially the felt properties of interleaver, thereby improve the decoding efficiency of decoder.
Be 4096 to be example with the code block length K that treats interleaving data below, the implementation method of the decoder shown in above-mentioned Fig. 8 is described.
The concrete job step of described decoder is as follows:
Step 1, the master control module receives associated control signal, described control signal comprises: code block length K=4096, cycle are the data_cal_en0 that 32 init_cal_en0 and init_cal_en1, cycle is K/8=512 and data_cal_en1 etc., according to code block length K=4096, determine to adopt eight road computing modules to treat interleaving data and carry out interleaving treatment, the mem that produces the correlation computations parameter of eight road computing module correspondences simultaneously reads the address, and described mem is read the address import described eight road computing modules.
Step 2, eight road computing modules are read the address according to the described mem of input, read the correlation computations parameter, as: ∏ (k), mod ((f 2-f 1), K), mod ((2f 2* k), K), mod ((f 1+ f 2), K), mod ((512f 1+ 512 2f 2), K) and mod (2f 2* 512 * k, K) etc.
Step 3, eight road computing modules are under the cooperation of control signal bata_en_eightline_line0to6, beta_en_eightline7, alpha_en_eightline_line0 and alpha_en_eightlinelto7, vertical recursion of carrying out between beta reverse recursion, alpha forward recursive and each road of single channel is calculated, utilize binary tree algorithm to obtain to interweave the mem address and the mem sequence number of back data at last, the mem address of the back data that interweave that eight road computing modules will calculate and mem sequence number input mem address selection module and mem sequence number are selected module;
Step 4, mem address selection module and mem sequence number are selected mem address and the mem sequence number of module according to the described back data that interweave, and data reads after interweaving.
Be a flow process schematic diagram of the interpretation method of the embodiment of the invention as shown in figure 12, described interpretation method may further comprise the steps:
Step 1201, the decoder buffer memory is treated interleaving data; The interleaving data for the treatment of that is about to input is cached in the pre-assigned buffer area successively.
Step 1202, described decoder are divided into N way data according to the described code block length for the treatment of interleaving data with the described interleaving data for the treatment of; Described N is the integer more than or equal to 1;
Step 1203, described decoder read the preceding buffer address that interweaves of described N way data; Promptly read and treat the buffer address of interleaving data in above-mentioned buffer area.
Step 1204, described decoder adopt default interleaving mode, respectively buffer address before the interweaving of described N way data are carried out interleaving treatment, obtain the back buffer address that interweaves of described N way data; When being applied to 3GPP LTE communication system, the interleaving mode that described default interleaving mode can adopt for the interleaver of the Turbo code encoder stipulated in the 3GPP LTE agreement.
Step 1205, described decoder read the described interleaving data for the treatment of of buffer memory, the data after obtaining interweaving according to the described back buffer address that interweaves.
Adopting the interleaving mode of stipulating in the 3GPP LTE agreement with described interleaver below is example, and the decoder of the embodiment of the invention is elaborated.
The default interleaving mode that described interleaver adopts is:
c′ i＝c ∏(i)，(i＝0，...，K-1)
∏(i)＝mod(f 1×i+f 2×i 2，K)
Wherein, c 0, c 1, c 2, c 3..., c K-1Be the input data of interleaver, K is a code block length, and the span of K is 40≤K≤6144, c ' 0, c ' 1..., c ' K-1The dateout of interleaver, mod is for getting surplus operation, parameter f 1And f 2Value change parameter f according to the variation of code block length K 1, f 2As shown in table 1 with the corresponding relation of K.
Value according to the code block length K of record in the table 1, in the embodiment of the invention, can will treat that interleaving data is divided into 1 tunnel, 2 tunnel, 4 road or 8 way data, promptly the value of N can be 1,2,4 or 8, below so that the value of N can be example describe the decoder of the embodiment of the invention for 1,2,8.
In the span of the code block length K that treats interleaving data is 40≤K≤512 o'clock, and can set N is 1, at this moment, owing to treat that the data volume of interleaving data is less, therefore, does not need to treat interleaving data parallel processing along separate routes.
In the span of the code block length K that treats interleaving data is 512＜K≤1024 o'clock, and can set N is 2, at this moment, owing to treat that the data volume of interleaving data is bigger, therefore, will treat that interleaving data is divided into the 2 tunnel parallel interleaving treatment of carrying out.
In the span of the code block length K that treats interleaving data is 1024＜K≤6144 o'clock, and can set N is 8, at this moment, owing to treat that the data volume of interleaving data is very big, therefore, will treat that interleaving data is divided into the 8 tunnel parallel interleaving treatment of carrying out.
The interpretation method that provides by the foregoing description, can be according to the code block length for the treatment of interleaving data, Dynamic Selection will treat that interleaving data is divided into N way data, walk abreast described N way data are carried out interleaving treatment, because each road treats that the data volume of interleaving data is all less, therefore, can effectively improve the efficient that interweaves of interleaver, thereby further improved the decoding efficiency of decoder, met the requirement of handling the business of high speed, large data capacity in the 3GPP LTE standard.
Described decoder can adopt the MAX-LOG-MAP algorithm to decipher, and adopting the MAX-LOG-MAP algorithm with described decoder below is example, and the interpretation method of the embodiment of the invention is further detailed.
In the embodiment of the invention, sub-decoder in the decoder is the MAP sub-decoder, when the MAP sub-decoder is carried out decoding, need to calculate respectively gamma (branched measurement value), beta (back is to metric) and the alpha (forward metrics value) of input data, calculate the LLR (log-likelihood ratio) of input data then.Because the back data that interweave that described interleaver obtains need be imported the MAP sub-decoder and decipher, therefore, the back data that interweave that interleaver obtains need satisfy the beta operational data in the MAP sub-decoder and the feature of alpha operational data.
Be another schematic flow sheet of the interpretation method of the embodiment of the invention as shown in figure 13, described interpretation method may further comprise the steps:
Step 1301, the decoder buffer memory is treated interleaving data;
Step 1302, described decoder are divided into N way data according to the described code block length for the treatment of interleaving data with the described interleaving data for the treatment of;
Step 1303, described decoder read the preceding buffer address that interweaves of described N way data;
Step 1304, required required correlation computations parameter and the beta computing initial value of each way data and the required correlation computations parameter of vertical recurrence formula of alpha computing initial value of correlation computations parameter, alpha forward recursive formula of described decoder storage beta reverse recursion formula;
Described beta reverse recursion formula is:
∏(k-1)＝mod((∏(k)+mod((mod(f 2-f 1，K)-mod(2f 2×k，K))，K))，K)；
The required correlation computations parameter of described beta reverse recursion formula is: ∏ (k), mod ((f 2-f 1), K) and mod (2f 2* k, parameter such as K).
Described alpha forward recursive formula is:
∏(k+1)＝mod((∏(k)+mod((mod(f 1+f 2，K)+mod(2f 2×k，K))，K))，K)；
The required correlation computations parameter of the forward recursive formula of described alpha operational data is: ∏ (k), mod (f 1+ f 2, K) and mod (2f 2* k, parameter such as K).
Described vertical recurrence formula is:
∏(k+Δ)＝mod((∏(k)+mod((mod(Δ×f 1+Δ 2×f 2，K)+mod(2f 2×Δ×k，K))，K))，K)。
The required correlation computations parameter of vertical recurrence formula of the beta computing initial value of described each way data and alpha computing initial value is: ∏ (k), mod (Δ * f 1+ Δ 2* f 2, K) and mod (2f 2* Δ * k, parameter such as K).
Step 1305, described decoder calculates the back buffer address that interweaves of the beta computing initial value of other each way data except that described first via subdata according to interweave the back buffer address and the required correlation computations parameter of described vertical recurrence formula of the beta computing initial value of first via subdata;
Step 1306, described decoder calculates the buffer address afterwards that interweaves of other data except that described beta computing initial value in the described N way data respectively according to the back buffer address that interweaves of the beta computing initial value of required correlation computations parameter of described beta reverse recursion formula and described N way data;
Step 1307, described decoder calculates the back buffer address that interweaves of the alpha computing initial value of other each way data except that described first via subdata according to interweave the back buffer address and the required correlation computations parameter of described vertical recurrence formula of the alpha computing initial value of first via subdata;
Step 1308, described decoder calculates the buffer address afterwards that interweaves of other data except that described alpha computing initial value in the described N way data respectively according to the back buffer address that interweaves of the alpha computing initial value of required correlation computations parameter of described alpha forward recursive formula and described N way data.
The method that provides by the foregoing description, when decoder adopts the MAP algorithm to decipher, can be by the mode of beta reverse recursion, calculate the back buffer address that interweaves of the beta operational data of N way data correspondence fast, mode by the alpha forward recursive, calculate the back buffer address that interweaves of the alpha operational data of N way data correspondence fast, and the mode by vertical recursion, calculate the beta computing initial value of each way data correspondence and the back buffer address that interweaves of alpha computing initial value fast, thereby can reduce the computation complexity of interleaver, save the consumption of hardware resource.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims (10)

1. a decoder comprises interleaver, it is characterized in that, described interleaver comprises:
Cache module is used for buffer memory and treats interleaving data;
Shunt module is used for the code block length for the treatment of interleaving data according to described, and the described interleaving data for the treatment of is divided into N way data;
First read module is used to read the preceding buffer address that interweaves of described N way data;
The interleaving treatment module is used for respectively buffer address before the interweaving of described N way data is carried out interleaving treatment, obtains the back buffer address that interweaves of described N way data;
Second read module is used for according to the described back buffer address that interweaves, reading of data from described cache module, the data after obtaining interweaving.
2. decoder according to claim 1 is characterized in that, buffer address and the described back buffer address that interweaves satisfy following formula before described interweaving:
c′ ic ∏(i)，(i＝0，…，K-1)
∏(i)＝mod(f 1×i+f 2×i 2，K)
Wherein, c iBe the described preceding buffer address that interweaves, c ' iBe the described back buffer address that interweaves, K is the described code block length for the treatment of interleaving data, and the span of K is 40≤K≤6144, and mod is for getting surplus operation, parameter f 1And f 2Value change according to the variation of K.
3. decoder according to claim 2 is characterized in that, described decoder adopts the MAP algorithm to decipher, and described interleaver also comprises:
Memory module is used to store the required correlation computations parameter of the required correlation computations parameter of beta reverse recursion formula, alpha forward recursive formula and the beta computing initial value and the required correlation computations parameter of the vertical recurrence formula of alpha computing initial value of each way data;
Described interleaving treatment module comprises:
Beta reverse recursion module, be used for the back buffer address that interweaves, calculate the buffer address afterwards that interweaves of other data except that described beta computing initial value in the described N way data respectively according to the beta computing initial value of required correlation computations parameter of described beta reverse recursion formula and described N way data;
Alpha forward recursive module, be used for the back buffer address that interweaves, calculate the buffer address afterwards that interweaves of other data except that described alpha computing initial value in the described N way data respectively according to the alpha computing initial value of required correlation computations parameter of described alpha forward recursive formula and described N way data;
Vertical recursion module, be used for interweave back buffer address and the required correlation computations parameter of described vertical recurrence formula according to the beta computing initial value of the definite first via subdata of described beta reverse recursion module, the back buffer address that interweaves of the beta computing initial value of calculating other each way data except that described first via subdata, and, feed back to described beta reverse recursion module with the back buffer address that interweaves of the beta computing initial value of described other each way data; And according to interweave the back buffer address and the required correlation computations parameter of described vertical recurrence formula of the alpha computing initial value of the first via subdata of determining in the described alpha forward recursive module, the back buffer address that interweaves of the alpha computing initial value of calculating other each way data except that described first via subdata, and, feed back to described alpha forward recursive module with the back buffer address that interweaves of the alpha computing initial value of described other each way data.
4. decoder according to claim 3 is characterized in that:
Described beta reverse recursion formula is:
∏(k-1)＝mod((∏(k)+mod((mod(f 2-f 1，K)-mod(2f 2×k，K))，K))，K)；
Described alpha forward recursive formula is:
∏(k+1)＝mod((∏(k)+mod((mod(f 1+f 2，K)+mod(2f 2×k，K))，K))，K)；
Described vertical recurrence formula is:
∏(k+Δ)＝mod((∏(k)+mod((mod(Δ×f 1+Δ 2×f 2，K)+mod(2f 2×Δ×k，K))，K))，K)。
5. according to each described decoder of claim 1 to 4, it is characterized in that:
In the described span for the treatment of the code block length of interleaving data is 40≤K≤512 o'clock, and described N is 1;
In the span of described code block length is 512＜K≤1024 o'clock, and described N is 2;
In the span of described code block length is 1024＜K≤6144 o'clock, and described N is 8.
6. an interpretation method is characterized in that, may further comprise the steps:
The decoder buffer memory is treated interleaving data;
Described decoder is divided into N way data according to the described code block length for the treatment of interleaving data with the described interleaving data for the treatment of;
Described decoder reads the preceding buffer address that interweaves of described N way data;
Described decoder carries out interleaving treatment to buffer address before the interweaving of described N way data respectively, obtains the back buffer address that interweaves of described N way data;
Described decoder reads the described interleaving data for the treatment of of buffer memory, the data after obtaining interweaving according to the described back buffer address that interweaves.
7. interpretation method according to claim 6 is characterized in that, buffer address and the described back buffer address that interweaves satisfy following formula before described interweaving:
c′ i＝c ∏(i)，(i＝0，…，K-1)
∏(i)＝mod(f 1×i+f 2×i 2，K)
Wherein, c iBe the described preceding buffer address that interweaves, c ' iBe the described back buffer address that interweaves, K is the described code block length for the treatment of interleaving data, and the span of K is 40≤K≤6144, and mod is for getting surplus operation, parameter f 1And f 2Value change according to the variation of K.
8. interpretation method according to claim 7, it is characterized in that described decoder adopts the MAP algorithm to decipher, described decoder carries out interleaving treatment to buffer address before the interweaving of described N way data respectively, obtain the back buffer address that interweaves of described N way data, be specially:
Required required correlation computations parameter and the beta computing initial value of each way data and the required correlation computations parameter of vertical recurrence formula of alpha computing initial value of correlation computations parameter, alpha forward recursive formula of described decoder storage beta reverse recursion formula;
Described decoder calculates the back buffer address that interweaves of the beta computing initial value of other each way data except that described first via subdata according to interweave the back buffer address and the required correlation computations parameter of described vertical recurrence formula of the beta computing initial value of first via subdata;
Described decoder calculates the back buffer address that interweaves of the alpha computing initial value of other each way data except that described first via subdata according to interweave the back buffer address and the required correlation computations parameter of described vertical recurrence formula of the alpha computing initial value of first via subdata;
Described decoder calculates the buffer address afterwards that interweaves of other data except that described beta computing initial value in the described N way data respectively according to the back buffer address that interweaves of the beta computing initial value of required correlation computations parameter of described beta reverse recursion formula and described N way data;
Described decoder calculates the buffer address afterwards that interweaves of other data except that described alpha computing initial value in the described N way data respectively according to the back buffer address that interweaves of the alpha computing initial value of required correlation computations parameter of described alpha forward recursive formula and described N way data.
9. interpretation method according to claim 8 is characterized in that:
Described beta reverse recursion formula is:
∏(k-1)＝mod((∏(k)+mod((mod(f 2-f 1，K)-mod(2f 2×k，K))，K))，K)；
Described alpha forward recursive formula is:
∏(k+1)＝mod((∏(k)+mod((mod(f 1+f 2，K)+mod(2f 2×k，K))，K))，K)；
Described vertical recurrence formula is:
∏(k+Δ)＝mod((∏(k)+mod((mod(Δ×f 1+Δ 2×f 2，K)+mod(2f 2×Δ×k，K))，K))，K)。
10. according to each described interpretation method of claim 6 to 9, it is characterized in that:
In the described span for the treatment of the code block length of interleaving data is 40≤K≤512 o'clock, and described N is 1;
In the span of described code block length is 512＜K≤1024 o'clock, and described N is 2;
In the span of described code block length is 1024＜K≤6144 o'clock, and described N is 8.
CN2009102582133A 2009-12-17 2009-12-17 Decoder and decoding method Pending CN102104387A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102739358A (en) * 2012-06-01 2012-10-17 武汉邮电科学研究院 Method for realizing parallel Turbo code interweaver and used in LTE (Long Term Evolution)
CN102882634A (en) * 2012-06-20 2013-01-16 华为技术有限公司 Llr processing method and receiving equipment
CN112395214A (en) * 2016-06-30 2021-02-23 联发科技股份有限公司 Time de-interleaving circuit and method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102739358A (en) * 2012-06-01 2012-10-17 武汉邮电科学研究院 Method for realizing parallel Turbo code interweaver and used in LTE (Long Term Evolution)
CN102882634A (en) * 2012-06-20 2013-01-16 华为技术有限公司 Llr processing method and receiving equipment
CN102882634B (en) * 2012-06-20 2015-02-04 华为技术有限公司 Llr processing method and receiving equipment
CN112395214A (en) * 2016-06-30 2021-02-23 联发科技股份有限公司 Time de-interleaving circuit and method

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