CN112395214A

CN112395214A - Time de-interleaving circuit and method

Info

Publication number: CN112395214A
Application number: CN202011337016.3A
Authority: CN
Inventors: 王俊杰
Original assignee: MediaTek Inc
Current assignee: MediaTek Inc
Priority date: 2016-06-30
Filing date: 2016-06-30
Publication date: 2021-02-23
Also published as: CN107562638A

Abstract

The time de-interleaving circuit and the time de-interleaving method perform time de-interleaving by writing and reading a plurality of time-interleaved data into and out of a first memory and a second memory. The time de-interleaving method comprises the following steps: selecting a first time staggered data and a second time staggered data from the plurality of time staggered data, wherein the first time staggered data and the second time staggered data have the same delay length; writing the first time-interleaved data into the first memory; writing the second time staggered data into the second memory; wherein the first memory has a bit width as an access unit, and the second memory has an access unit smaller than the bit width.

Description

Time de-interleaving circuit and method

The present application is a divisional application of a patent application having an application date of 2016, 30/06, and an application number of 201610504245.7, entitled "time deinterleaving circuit and method".

Technical Field

The present invention relates to a time de-interleaving circuit and method, and more particularly, to a time de-interleaving circuit and method in a convolutional (convolutional) mode.

Background

The receiving end of ISDB-T (Integrated Services Digital Broadcasting) signal adopts a convolution time deinterleaving method, generally speaking, time interleaved data (i.e. data generated after preceding stage frequency deinterleaving) is divided into 13 groups, each group can be subdivided into n sections (different transmission modes have different n values, as shown in table 1) according to different delay lengths, multiple data in the same section experience the same delay, 13 groups of time interleaved data can be divided into three layers (layers), and each Layer uses an independent time interleaving length I. Fig. 1 is a block diagram illustrating a time de-interleaving process performed at a receiving end. As shown in the figure, 13 sets of time interleaved data respectively correspond to 13 convolutional deinterleavers 110, each convolutional deinterleaver is used to process a set of data, n paths respectively correspond to the above n segments of data, and according to the specification, the delay length d of the path i_iThe following can be expressed (taking transmission mode 1 as an example, i is 0 to 95):

d_i＝I×(95-((i×5)mod 96)) (1)

i is a time interleaving length (time interleaving length), and each transmission mode provides a plurality of time interleaving lengths I (as shown in table 1). In practice, the time de-interleaving process of the convolutional de-interleaving units 110 can be implemented by reading and writing a memory, and the size of the memory corresponding to each path is proportional to the delay length of the path. Suppose each data DX_p，q(X is the number of the convolutional deinterleaver 110, p is the path number In a convolutional deinterleaver 110, q represents the sequence of the data In the segment), the data amount (i.e., the code-word length) of the convolutional deinterleaver 110 is 21 bits (e.g., the In-phase (In-phase) component of Orthogonal Frequency Division Multiplexing (OFDM) occupies 7 bits, the Quadrature (Quadrature) component occupies 7 bits, and the CSI (channel state information) occupies 7 bits), and when the memory is implemented by a Dynamic Random Access Memory (DRAM) or a Synchronous Dynamic Random Access Memory (SDRAM) with a bit width of 128 bits, each data is written In_p,qIn practice, 107 (128-21) bits are wasted in memory. This becomes a serious problem in an integrated system where memory resources are expensive.

Table 1: (different transmission modes have different parameters, e.g. modulation, code rate, etc.)

Transmission mode	n	Length of time interleaving I
			1	96	0,4,8,16
2	192	0,2,4,8
			3	384	0,1,2,4

TABLE 1

Disclosure of Invention

In view of the foregoing, it is an object of the present invention to provide a time de-interleaving circuit and method for more efficiently using memory.

The invention discloses a time de-interleaving method, which writes and reads a plurality of time-interleaved data into and out of a storage unit to perform time de-interleaving processing, and comprises the following steps: selecting K time-interleaved data from the plurality of time-interleaved data, wherein the K time-interleaved data have the same delay length, and K is an integer greater than 1; generating data to be written, wherein the data to be written comprises the K time staggered data; writing the data to be written into the storage unit in the same writing program; wherein a bit width of the storage unit is greater than or equal to a data amount of the data to be written.

The present invention further discloses a time de-interleaving circuit, comprising: a buffer unit for buffering multiple time-interleaved data; a storage unit; and a control unit, coupled to the buffer unit and the storage unit, for selecting K time-interleaved data from the buffer unit to form a data to be written, and writing the data to be written into the storage unit in the same writing procedure; the K time-interleaved data have the same delay length, K is an integer greater than 1, and the width of one bit of the storage unit is greater than or equal to the data size of the data to be written.

The present invention further discloses a time de-interleaving method for performing time de-interleaving by writing and reading a plurality of time-interleaved data into and from a first memory and a second memory, the method comprising: selecting a first time staggered data and a second time staggered data from the plurality of time staggered data, wherein the first time staggered data and the second time staggered data have the same delay length; writing the first time-interleaved data into the first memory; writing the second time staggered data into the second memory; wherein the first memory has a bit width as an access unit, and the second memory has an access unit smaller than the bit width.

The present invention further discloses a time de-interleaving circuit, comprising: a buffer unit for buffering multiple time-interleaved data; a first memory having a bit width as an access unit; a second memory having an access unit smaller than the bit width; and a control unit, coupled to the buffer unit, the first memory and the second memory, for selecting a first time-interleaved data and a second time-interleaved data from the buffer unit, writing the first time-interleaved data into the first memory and writing the second time-interleaved data into the second memory; the first time staggered data and the second time staggered data have the same delay length.

The time de-interleaving circuit and the time de-interleaving method form a plurality of time-interleaved data with the same delay length into data to be written, and write the data to be written into the memory in the same writing operation, so that the memory can be more efficiently accessed, the memory can be more effectively used, and the waste of memory space is reduced. In addition, the invention uses 2 memories to store time-interleaved data, wherein the access unit of one of the memories is a fixed data volume, and the other access unit is not limited.

The features, implementations and functions of the present invention will be described in detail with reference to the drawings.

Drawings

FIG. 1 is a block diagram of a temporal deinterlacing process;

FIG. 2 is a block diagram of an embodiment of a time de-interlacing circuit according to the present invention; and

fig. 3-4 are flow charts of a time de-interleaving method according to an embodiment of the present invention.

Description of the symbols

100 time de-interleaving circuit

110 convolutional deinterleaving unit

210 frequency de-interleaving circuit

220 time de-interleaving circuit

222. 223 buffer unit

224 control unit

225 storage unit

226 first memory

228 second memory

S310 to S340, S342 to S346 steps

Detailed Description

The present disclosure includes time deinterleaving circuits and methods, and those skilled in the art can select equivalent elements or steps to implement the present invention according to the disclosure of the present specification, where possible, i.e., the implementation of the present invention is not limited to the embodiments described below.

Fig. 2 is a functional block diagram of a time de-interleaving circuit according to an embodiment of the present invention, and fig. 3 and 4 are flowcharts of a time de-interleaving method according to an embodiment of the present invention. The time de-interleaving circuit 220 receives time-interleaved data (i.e., the aforementioned data DX) from the frequency de-interleaving circuit 210_p,q) Then, the data is buffered in the buffer unit 222 (step S310), the control unit 224 writes the data into and reads the data from the storage unit 225 to complete time de-interleaving, the data read from the storage unit 225 is buffered in the buffer unit 223, and the data is output according to the normal time de-interleaving sequence. The storage unit 225 includes a first memory 226 and a second memory 228, the first memory 226 must have a bit width unit (e.g., DRAM, SDRAM) for each access, and the second memory 228 may be DRAM or SDRAM having a bit width smaller than that of the first memory 226 or a memory without a minimum access unit limitation (e.g., Static Random Access Memory (SRAM)).

With continued reference to fig. 1, several of the 13 convolutional deinterleaving units 110 have the same time interleaving length I. For example, assuming that the 0 th convolutional deinterleaver 110-0 and the 1 st convolutional deinterleaver 110-1 have the same time interleaving length I, the data D0 is based on equation (1)_0,qAnd data D1_0,qWill experience the same delay length, data D0_1,qAnd data D1_1,qThe same delay length will be experienced and so on. Furthermore, data having the same q value are generated simultaneously, i.e., corresponding to all data D0 having p values of 0 to (n-1)_p,0Data D1_p,0… and data D12_p,0All data D0 corresponding to p values 1 to (n-1) are generated simultaneously_p,1Data D1_p,1…, data D12_p,1Are generated simultaneously, and so on. Therefore, the control unit 224 can simultaneously fetch the data D0 from the buffer unit 222_0,0And data D1_0,0And both correspond to the same delay length, i.e. data D0_0,0And data D1_0,0Can be written by the control unit 224 at the same timeThe storage unit 225 and the reading-out storage unit 225 at the same time to complete the time de-interleaving, so the control unit 224 can use the two data as a set of data to be written when writing into the first memory 226, thereby saving the memory space. In more detail, the control unit 224 first determines the bit width W of the first memory 226 and the data DX_p,qThe length C of the code word can be calculated to obtain a group of data to be written

Pen data DX_p,q(step S320), then according to the k value, k data DXs with the same delay length are selected_p,qBecomes the set of data to be written (step S330), and then writes the set of data to be written to the storage unit 225 (step S340), in more detail, at this time, writes the set of data to be written to the first memory 226. The following table 2 lists several W values and k values (for example, 21 bits)

Table 2:

bit width W (bit)	The number k of data strokes contained in a group of data to be written
		64	3
128	6
		256	12

Taking the actual number as an example (scenario 1), it is assumed that the transmission mode of the 13 sets of time-interleaved data is 1 and has the same time-interleaving length I16, the bit width W of the first memory 226 is 128 bits, and the data DX_p,qThe code word length C is 21 bits, the memory size required by the conventional time de-interleaving method is (bits):

the time de-interlacing method of the present invention is to

Data DX_p,qAs a set of data to be written, the required memory size is (bits):

the memory size required by the present invention in this case is only about 3/13 in the conventional case.

In detail, in the foregoing embodiment, D0_p,q、D1_p,q、D2_p,q、D3_p,q、D4_p,qAnd D5_p,qCan be used as a group of data to be written T0_p,q，D6_p,q、D7_p,q、D8_p,q、D9_p,q、D10_p,qAnd D11_p,qCan be used as a group of data to be written T1_p,q，D12_pCan be used as a group of data to be written T2_p,qWherein data DX_p,qThe data DX can be obtained through the cache unit 222_p,qThe control unit 224 can generate the appropriate control signal to store the data DX according to the (x 108+ p) data at the p-th time of the buffer unit 222_p，qAnd written into storage cell 225. According to each data DX_p，qCorresponding delay length d_iThe control unit 224 sends data DX from the storage unit 225 according to the corresponding time_p，qAnd (6) reading. In the foregoing embodiment, data DX_p，qIs output in the storage unit 225 in the late 16 × (95- (p × 5) mod 96) induction room, i.e., T0_0，qThe output is performed after a unit time of 1520 × 16 (95- (0 × 5) mod 96) in the storage unit 225. At time q ═1520, T0_0，0Is outputted, and T0_0，1520Can be written in original T0_0，0At the location of the storage unit 225. When T0_1，80When outputted, T0_1，1520Can be written in original T0_1，80At the location of the storage unit 225. And so on when T0_{p，1520-16*(95-(p*5)mod96)}When outputted, and T0_p，1520Written at original T0_{p，1520-16*(95-(p*5)mod96)}At the location of the storage unit 225.

The control unit 224 receives data DX from the storage unit 225_p，qAfter being read out, the data is stored in the buffer unit 223, and DX is known from the read-out sequence_p，qThe data in the buffer unit 223 are: d0_0，0、D1_0，0、D2_0，0、D3_0，0、D4_0，0、D5_0，0、D0_1，80、D1_1，80、D2_1，80、D3_1，80、D4_1，80、D5_1，80、…、D0_{p，1520-16*(95-(p*5)mod96)}、D1_{p，1520-16*(95-(p*5)mod96)}、D2_{p，1520-16*(95-(p*5)mod96)}、D3_{p，1520-16*(95-(p*5)mod96)}、D4_{p，1520-16*(95-(p*5)mod96)}、D5_{p，1520-16*(95-(p*5)mod96)}、…、D12_0，0、D12_1，80、…、D12_{p，1520-16*(95-(p*5)mod96)}、…、D12_94，1376、D12_95，1456. Finally, the control unit 224 adjusts the data DX_p，qData DX from output order of buffer unit 223_p，qThe output is in the following sequence: d0_0，0、D0_1，80、D0_2，160、…、D0_{p，1520-16*(95-(p*5)mod96)}、…、D0_94，1376、D0_95，1456、D1_0，0、D1_1，80、D1_2，160、…、D1_{p，1520-16*(95-(p*5)mod96)}、…、D1_94，1376、D1_95，1456、D2_0，0、D2_1，80、D2_2，160、…、D2_{p，1520-16*(95-(p*5)mod96)}、…、D11_94，1376、D11_95，1456、D12_0，0、D12_1，80、D12_2，160、…、D12_{p，1520-16*(95-(p*5)mod96)}、…、D12_94，1376、D12_95，1456。

If 13 sets of time-interleaved data may correspond to multiple time-interleaved lengths I (scenario 2), for example, 4 sets of I values are 16, 8 sets of I values are 8, and the remaining 1 set of I values are 4, the control unit 224 determines a set of data to be written (step S330) (i.e., k is 6), and the 4 sets of I is 16 data DX_p，qCan be formed into

Set data A to be written, 8 sets of data DX with I being 8_p，qCan be formed into

Sets of data to be written (data to be written B (including 6 data) and data to be written C (including 2 data)), and the remaining 1 set of data DX_p，qSelf-forming

And (5) grouping the data D to be written. It can be seen that 2 of the 4 sets of data to be written (data to be written C and data to be written D) actually contain only 1 and 2 time-interleaved data DX respectively_p，qThis situation still causes a waste of the first memory 226. Therefore, the control unit 224 further includes the detailed process shown in fig. 4 when writing the set of data to be written into the storage unit 225 (step S340).

In step S342, the control unit 224 determines whether the difference between the bit width W of the first memory 226 and the data amount of the set of data to be written is greater than a time-interleaved data DX_p,qIf yes, the group of data to be written is written into the first memory 226 or the second memory 228 according to a judgment condition (step S346), and if no, the group of data to be written is written into the first memory 226 (step S344). In the case of scenario 2, the data B to be written is written into the first memory 226 (step S344), and the control unit 224 determines to write the data C to be written into the first memory 226 or the second memory 228 according to the determination condition. For example, the determination condition may be (1) the set of data to be writtenWhether the actual data amount in (a) exceeds half the bit width W; or (2) the group of data to be written only contains 1 data DX_p,q. With the condition (1), the actual data amount of the data a to be written exceeds half of the bit width W, and is therefore written into the first memory 226, while the data C and D to be written are written into the second memory 228; for the condition (2), the data a and C to be written are written into the first memory 226, and the data D to be written is written into the second memory 228. In either condition (1) or condition (2), as long as the second memory 228 is a DRAM or SDRAM with a bit width smaller than that of the first memory 226, or even an SRAM, memory space saving effect can be achieved. Furthermore, in case 1, no matter whether the condition (1) or (2) is used for determination, the control unit 224 will include the set of data DX_p,qThe data to be written is written into the second memory 228 (here, taking SRAM as an example), and the space used by the first memory 226 is (bit):

the space used by the second memory 228 is (bits):

it is equal to replacing the 9,338,880 (28, 016,640 and 18,677,760) bits of the first memory 226 with 1,532,160 bits of space in the second memory 228. The design can effectively improve the use efficiency of the memory.

In detail, in the embodiment of scenario 2, D0_p,q、D1_p,q、D2_p,qAnd D3_p,qCan be used as a group of data to be written T0_p,q，D4_p,q、D5_p,q、D6_p,q、D7_p,q、D8_p,qAnd D9_p,qCan be used as a group of data to be written T1_p,q，D10_p、D11_p,qCan be used as a group of data to be written T2_p,q，D12_pCan be used as a group to be treatedWrite data T3_p,qWherein data DX_p,qThe data DX can be obtained through the cache unit 222_p,qThe (x × 108+ p) pen data at the p-th time of the buffer unit 222. Similarly, the control unit 224 is configured to control the operation according to the data DX_p,qCorresponding delay length d_iData DX from the storage unit 225 corresponding to the time_p，qAnd (6) reading. D0-3_p，qIs output after a delay of 16 × (95- (p × 5) mod 96) time units in the storage unit 225, i.e., T0_0，qThe time unit of 16 × (95- (0 × 5) mod 96) ═ 1520 will be output after the storage unit 225 will elapse. D4-11_p，qIs output after the storage unit 225 delays by 8 × (95- (p × 5) mod 96), i.e., T1_0，qAnd T2_0，qThe time unit of 8 × (95- (0 × 5) mod 96) ═ 760 will elapse in the storage unit 225 and be output. D12_p，qIs delayed by 4 × (95- (p × 5) mod 96) in the storage unit 225 and then output, i.e., T3_0，qThe time unit of 4 × (95- (0 × 5) mod 96) ═ 380 will elapse in the storage unit 225 and then be output. The control unit 224 receives data DX from the storage unit 225_p，qAfter being read out, the data is stored in the buffer unit 223. Finally, the control unit 224 adjusts the data DX_p，qData DX from output order of buffer unit 223_p，qOutput to complete the temporal deinterlacing process.

Possible footprints of the first memory 226 and the second memory 228 at different bit widths W for the first memory 226 are listed below (case 1 as an example):

bit width W of 64 bits

Bit width W of 128 bits

Bit width W of 256 bits

While the present invention has been described with reference to particular examples and embodiments thereof, the present invention will be understood by those skilled in the art from a consideration of the disclosure of the apparatus of FIG. 2 and a consideration of the disclosure of the method of FIGS. 3-4, which are not intended to limit the present invention.

Claims

1. A time de-interleaving method for performing time de-interleaving by writing and reading a plurality of time-interleaved data into and out of a storage unit, the method comprising:

selecting K time-interleaved data from the plurality of time-interleaved data, wherein the K time-interleaved data have the same delay length, and K is an integer greater than 1;

generating data to be written, wherein the data to be written comprises the K time staggered data; and

writing the data to be written into the storage unit in the same writing program;

wherein a bit width of the storage unit is greater than or equal to a data amount of the data to be written.

2. The time deinterleaving method as claimed in claim 1, wherein the K time interleaved data are respectively selected from K time interleaved data sets, and the K time interleaved data sets correspond to the same time interleaving length.

3. The time deinterleaving method as recited in claim 1, further comprising:

the value K is determined according to a data amount of the time-interleaved data and the bit width of the storage unit.

4. The method of claim 3, wherein the K is a maximum integer less than a quotient of the bit width divided by an amount of the time-interleaved data.

5. The time deinterleaving method as claimed in claim 1, wherein the storage unit includes a first memory and a second memory, the first memory stores the data to be written in the unit of access of the bit width, the unit of access of the second memory is smaller than the bit width, the method further comprising:

selecting a piece of target time staggered data, wherein the target time staggered data and the K pieces of time staggered data have the same delay length; and

and writing the target time staggered data into the second memory.

6. A time deinterleaving circuit comprising:

a buffer unit for buffering multiple time-interleaved data;

a storage unit; and

a control unit, coupled to the buffer unit and the storage unit, for selecting K time-interleaved data from the buffer unit to form a data to be written, and writing the data to be written into the storage unit in the same writing procedure;

the K time staggered data have the same delay length, K is an integer greater than 1, and the width of one bit of the storage unit is greater than or equal to the data size of the data to be written.