CN107562638A - Time release of an interleave circuit and method - Google Patents
Time release of an interleave circuit and method Download PDFInfo
- Publication number
- CN107562638A CN107562638A CN201610504245.7A CN201610504245A CN107562638A CN 107562638 A CN107562638 A CN 107562638A CN 201610504245 A CN201610504245 A CN 201610504245A CN 107562638 A CN107562638 A CN 107562638A
- Authority
- CN
- China
- Prior art keywords
- data
- time
- time interleaving
- memory
- interleaving data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0207—Addressing or allocation; Relocation with multidimensional access, e.g. row/column, matrix
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0607—Interleaved addressing
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Error Detection And Correction (AREA)
Abstract
Time release of an interleave circuit and time de-interlace method, it is by by more time interleaving data write-ins and reading a first memory and a second memory to carry out time release of an interleave processing.Time de-interlace method includes：A very first time intercrossed data and a second time interleaving data are chosen from the more time interleaving data, this very first time intercrossed data with pen the second time interleaving data there is identical one to postpone length；This very first time intercrossed data is write into the first memory；And pen the second time interleaving data are write into the second memory；Wherein, the first memory system is using a bit width as access unit, and the access unit of the second memory is less than the bit width.
Description
Technical field
The present invention is on time release of an interleave (time de-interleaving) circuit and method, especially with respect to convolution
(convolutional) the time release of an interleave circuit and method of mode.
Background technology
ISDB-T (Integrated Services Digital Broadcasting, integrated services digital broadcast) signal
Receiving terminal using convolution time de-interlace method, it is however generally that, time interleaving data (are produced after prime frequency release of an interleave
Raw data) be divided into 13 groups, every group and can be subdivided into according to different delay length n sections (different transmission mode have difference
N values, as shown in table 1), more pen datas experience identical delay in same section, 13 groups of time interleaving data are segmented into three
Each stratum (Layer), each stratum use independent time interleaving length I.Fig. 1 is that receiving terminal carries out time release of an interleave processing
Block schematic diagram.As illustrated, 13 groups of time interleaving data systems correspond to 13 convolution release of an interleave units 110, each convolution respectively
Release of an interleave unit is used for handling one group of data, and n path corresponds to foregoing n segment datas respectively, according to specification, path i delay
Length diIt can represent following (by taking transmission mode 1 as an example, i=0~95)：
di=I × (95- ((i × 5) mod 96)) (1)
I is time interleaving length (time interleaving length), and each transmission mode provides multiple time interleavings
Length I (as shown in table 1).In fact, the time release of an interleave processing of those convolution release of an interleave units 110 can be by the storage of read-write one
Device realizes that the size of the memory corresponding to each path is directly proportional to the delay length in the path.Assuming that per pen data
DXp,q(X is the numbering of convolution release of an interleave unit 110, and p is the path number in a certain convolution release of an interleave unit 110, and q is represented should
The order of pen data in this paragraph) data volume (i.e. code word length (code-word length)) be 21 (such as orthogonal frequency divisions
Same phase (In-phase) component of multiplexing (OFDM) account for 7, orthogonal (Quadrature) component account for 7 and CSI (channel
State information, channel condition information) account for 7), when memory with bit width (bit width) is 128 dynamic
When state random access memory (DRAM) or Synchronous Dynamic Random Access Memory (SDRAM) implementation, then write per pen data
DXp,qWhen, the waste of 107 (=128-21) positions is actually just caused in memory.This is in the valuable integration system of memory resource
In system turn into one it is serious the problem of.
Table 1：(different transmission modes has different parameters, such as modulation mode, code check (code rate) etc.)
| Transmission mode | n | Time interleaving length I |
| 1 | 96 | 0,4,8,16 |
| 2 | 192 | 0,2,4,8 |
| 3 | 384 | 0,1,2,4 |
Table 1
The content of the invention
In view of the deficiency of prior art, a purpose of the invention is to provide a kind of time release of an interleave circuit and method, with
More efficiently use memory.
The invention discloses a kind of time de-interlace method, by more time interleaving data write-ins and the storage of reading one are single
To carry out time release of an interleave processing, this method includes member：K pens, the K time interleaving are chosen from the more time interleaving data
There is data identical one to postpone length, and K is the integer more than 1；A data to be written are produced, the packet to be written contains the K
Time interleaving data；And in write-in program once, the data to be written are write into the storage element；The wherein storage
One bit width of memory cell is more than or equal to the data volume of the data to be written.
The present invention separately discloses a kind of time release of an interleave circuit, comprising：One buffer unit, for caching more time interleaving numbers
According to；One storage element；And a control unit, the buffer unit and the storage element are coupled, is to choose K from the buffer unit
Time interleaving data write the data to be written to form a data to be written, and in write-in program once
The storage element；Wherein, there is identical one to postpone length for the K time interleaving data system, and K is integer more than 1, and the storage
One bit width of memory cell is more than or equal to the data volume of the data to be written.
The present invention separately discloses a kind of time de-interlace method, and one first is write and read by by more time interleaving data
To carry out time release of an interleave processing, this method includes for memory and a second memory：Selected from the more time interleaving data
A very first time intercrossed data and a second time interleaving data are taken, when this very first time intercrossed data is with the pen the second
Between intercrossed data have identical one postpone length；This very first time intercrossed data is write into the first memory；And will
Pen the second time interleaving data write the second memory；Wherein, the first memory system using a bit width as access unit,
And the access unit of the second memory is less than the bit width.
The present invention separately discloses a kind of time release of an interleave circuit, comprising：One buffer unit, for caching more time interleaving numbers
According to；One first memory, it is using a bit width as access unit；One second memory, it accesses unit and is less than the bit width；With
And a control unit, the buffer unit, the first memory and the second memory are coupled, is to choose one from the buffer unit
A pen very first time intercrossed data and second time interleaving data, and this very first time intercrossed data is write this and first deposited
Reservoir and pen the second time interleaving data are write into the second memory；Wherein, this very first time intercrossed data is with being somebody's turn to do
There is the second time interleaving data of pen identical one to postpone length.
The time release of an interleave circuit of the present invention forms multiple time interleaving data with same delay length with method
Data to be written, and the data to be written are write into memory in a write operation together, therefore access the memory and incite somebody to action
Become more efficiently, and the memory also can be used more effectively, reduce the waste of storage space.In addition, present invention profit
With 2 memories come storage time intercrossed data, the access unit of one of them is fixed data volume, another access unit
It is then unrestricted.
Feature, implementation and effect for the present invention, schema is hereby coordinated to make embodiment detailed description as follows.
Brief description of the drawings
Fig. 1 is the block schematic diagram of time release of an interleave processing；
Fig. 2 is the functional block diagram of an embodiment of time release of an interleave circuit of the invention；And
Fig. 3~Fig. 4 is the flow chart of an embodiment of time de-interlace method of the invention.
Symbol description
100 time release of an interleave circuits
110 convolution release of an interleave units
210 frequency release of an interleave circuits
220 time release of an interleave circuits
222nd, 223 buffer unit
224 control units
225 storage elements
226 first memories
228 second memories
S310~S340, S342~S346 steps
Embodiment
The present invention disclosure include time release of an interleave circuit and method, be embodied as it is possible under the premise of, this technology
Field tool usually intellectual can select equivalent element or step to realize the present invention according to the disclosure of this specification,
That is, the implementation of the present invention be not limited to after the embodiment chatted.
Fig. 2 is the functional block diagram of an embodiment of time release of an interleave circuit of the invention, and Fig. 3 and Fig. 4 are the time of the invention
The flow chart of one embodiment of de-interlace method.Time release of an interleave circuit 220 receives time interleaving from frequency release of an interleave circuit 210
Data (i.e. foregoing data DXp,q) after, buffer unit 222 (step S310) is first buffered in, control unit 224 again writes data
Enter and read 225 deadline of storage element release of an interleave, the data read from storage element 225 are first buffered in buffer unit
223, then according to normal time deinterleaved order output data.Storage element 225 includes first memory 226 and second memory
228, access must be in units of a bit width (such as DRAM, SDRAM) every time for first memory 226, and second memory
228 can be the DRAM or SDRAM of the bit width that bit width is less than first memory 226, or could be used without minimum access list
The memory (such as static RAM (SRAM)) of position limitation.
It is several in this 13 convolution release of an interleave units 110 that there is identical time interleaving length I with continued reference to Fig. 1.Citing
For, it is assumed that the 0th convolution release of an interleave unit 110-0 and the 1st convolution release of an interleave unit 110-1 have identical time interleaving length
I, then according to equation (1), data D00,qWith data D10,qWill experience identical delay length, data D01,qWith data D11,qWill
Identical delay length is undergone, by that analogy.Furthermore produced simultaneously with the data system of same q-value, that is, correspond to p value be 0~
(n-1) all data D0p,0, data D1p,0... and data D12p,0System produces simultaneously, and corresponding p value is all of 1~(n-1)
Data D0p,1, data D1p,1..., data D12p,1System produces simultaneously, by that analogy.Therefore, control unit 224 can be from caching
Unit 222 obtains data D0 simultaneously0,0And data D10,0, and both corresponding identical delay length, i.e. data D00,0And data
D10,0Storage element 225 can be write in identical time controlled unit 224, and same time reads storage element 225 with complete
Into time release of an interleave, so control unit 224 when writing first memory 226, can be treated this two pen data as one group
Data are write, to save storage space.In more detail, control unit 224 first according to first memory 226 bit width W and
Data DXp,qThe long C of code word, one group can be calculated and treat that data packets containPen data DXp,q(step S320), connect
Again according to k values, choosing k pens has the data DX of same delay lengthp,qAs group data (step S330) to be written, then
By group data write-in storage element 225 (step S340) to be written, in more detail, group data to be written are now write first
Memory 226.Lower section table 2 enumerates the corresponding relation of several W values and k values (by taking C=21 positions as an example)
Table 2：
| Bit width W (position) | One group of data stroke count k for treating that data packets contain |
| 64 | 3 |
| 128 | 6 |
| 256 | 12 |
By taking the numeral of reality as an example (situation 1), it is assumed that the transmission mode of 13 groups of time interleaving data is 1 and has identical
Time interleaving length I=16, the bit width W=128 positions of first memory 226, data DXp,qThe long C=21 positions of code word, then practise
The memory size needed for time de-interlace method known is (position)：
And the time de-interlace method of the present invention willIndividual data DXp,qAs one group of number to be written
According to so required note memory size is (position)：
Required memory size of present invention is only about known in this 3/13.
Specifically, in previous embodiment, D0p,q、D1p,q、D2p,q、D3p,q、D4p,qAnd D5p,qOne group of number to be written can be used as
According to T0p,q, D6p,q、D7p,q、D8p,q、D9p,q、D10p,qAnd D11p,qOne group of data T1 to be written can be used asp,q, D12pOne group can be used as
Data T2 to be writtenp,q, wherein data DXp,qBuffer unit 222 is can pass through to obtain, and data DXp,qSystem is positioned at buffer unit 222
(x × 108+p) pen data of pth time, control unit 224 can produce appropriate control signal accordingly by data DXp,qWrite-in storage
Memory cell 225.According to each pen data DXp,qCorresponding delay length di, control unit 224 is in the corresponding time from storage element
225 by data DXp,qRead.In previous embodiment, data DXp,q16 × (95- (p × 5) mod of delay in storage element 225
96) Single Wei Time Inter Hous are output, this means, T00,q16 × (95- (0 × 5) mod 96)=1520 of experience in storage element 225
It is output after unit interval.In time q=1520, T00,0It is output, and T00,1520Original T0 can be write on0,0It is single positioned at storage
The position of member 225.Work as T01,80When being output, T01,1520Original T0 can be write on1,80Positioned at the position of storage element 225.Class according to this
Push away, work as T0p,1520-16*(95-(p*5)mod96)When being output, and T0p,1520Write on original T0p,1520-16*(95-(p*5)mod96)It is single positioned at storage
The position of member 225.
Control unit 224 is from storage element 225 by data DXp,qIt is to be stored in buffer unit 223 after reading, by foregoing
Knowable to the order of reading, DXp,qData are sequentially in buffer unit 223：D00,0、D10,0、D20,0、D30,0、D40,0、D50,0、
D01,80、D11,80、D21,80、D31,80、D41,80、D51,80、…、D0p,1520-16*(95-(p*5)mod96)、D1p,1520-16*(95-(p*5)mod96)、
D2p,1520-16*(95-(p*5)mod96)、D3p,1520-16*(95-(p*5)mod96)、D4p,1520-16*(95-(p*5)mod96)、
D5p,1520-16*(95-(p*5)mod96)、…、D120,0、D121,80、…、D12p,1520-16*(95-(p*5)mod96)、…、D1294,1376、
D1295,1456.Finally, the system of control unit 224 is adjusted by data DXp,qFrom the output order of buffer unit 223 by data
DXp,qExport into one sequence：D00,0、D01,80、D02,160、…、D0p,1520-16*(95-(p*5)mod96)、…、D094,1376、D095,1456、
D10,0、D11,80、D12,160、…、D1p,1520-16*(95-(p*5)mod96)、…、D194,1376、D195,1456、D20,0、D21,80、
D22,160、…、D2p,1520-16*(95-(p*5)mod96)、…、D1194,1376、D1195,1456、D120,0、D121,80、D122,160、…、
D12p,1520-16*(95-(p*5)mod96)、…、D1294,1376、D1295,1456。
13 groups of time interleaving data may correspond to multiple time interleaving length I (situation 2), such as wherein 4 groups of I values are
16,8 groups of I values are 8, and remaining 1 group I values are 4, then control unit 224 (step S330) when determining one group of data to be written (is held
Upper example, k=6), the data DX of 4 groups of I=16p,qIt may be constructedGroup data A to be written, the data of 8 groups of I=8
DXp,qIt may be constructedGroup data to be written (are respectively that data B (including 6 pen datas) to be written and data C to be written (are included
2 pen datas)), the data DX of 1 group of the residuep,qSelf-containedGroup data D to be written.It can be found that 4 groups of data to be written
Wherein 2 groups (data C to be written and data D to be written) actually only include 1 and 2 time interleaving data DX respectivelyp,q, this feelings
Condition still causes the waste of first memory 226.Therefore group data to be written are being write storage element 225 by control unit 224
When (step S340), further include the thin portion flow shown in Fig. 4.
In step S342, control unit 224 judges the bit width W of first memory 226 and the number of group data to be written
Whether it is more than a time interleaving data DX according to the difference of amountp,qData volume (i.e. the long C of code word), if it is, according to one judge
Group data to be written are write first memory 226 or second memory 228 (step S346) by condition, if it is not, then write-in the
One memory 226 (step S344).Above-mentioned situation 2 is held, data B to be written can be written into first memory 226 (step S344), control
Unit 224 processed can determine data C to be written writing first memory 226 or second memory 228 according to Rule of judgment again.Citing
For, the Rule of judgment can be the half whether actual amount of data in (1) group data to be written exceedes bit width W；Or
(2) group data to be written only include 1 pen data DXp,q.For condition (1), data A to be written actual amount of data exceedes bit wide
W half is spent, so first memory 226 can be written into, and data C to be written and data D to be written are then written into second memory
228；For condition (2), data A to be written and data C to be written can be written into first memory 226, and data D to be written is then write
Enter second memory 228.Whether condition (1) or condition (2), as long as second memory 228 is to be less than first using bit width
The DRAM or SDRAM of the bit width of memory 226, or SRAM is even used, it all can reach the effect for saving storage space
Fruit.Furthermore above-mentioned situation 1 is held, is whether made a decision with condition (1) or condition (2), control unit 224 all can only wrap the group
Containing a pen data DXp,qData to be written write-in second memory 228 (this is sentenced exemplified by SRAM), the now institute of first memory 226
The space used is (position)：
Space used in second memory 228 is (position)：
Exchanged in fact with the space of the second memory 228 of 1,532,160 9,338,880 in first memory 226
(=28,016,640-18,677,760) position space.The service efficiency of memory can effectively be lifted by being so designed that.
Specifically, in the embodiment of situation 2, D0p,q、D1p,q、D2p,qAnd D3p,qOne group of data to be written can be used as
T0p,q, D4p,q、D5p,q、D6p,q、D7p,q、D8p,qAnd D9p,qOne group of data T1 to be written can be used asp,q, D10p、D11p,qOne can be used as
Group data T2 to be writtenp,q, D12pOne group of data T3 to be written can be used asp,q, wherein data DXp,qBuffer unit 222 is can pass through to obtain,
And data DXp,qPositioned at (x × 108+p) pen data of the pth time of buffer unit 222.Similarly, control unit 224 is according to each
Pen data DXp,qCorresponding delay length diIn the corresponding time from storage element 225 by data DXp,qRead.D0~3p,qNumber
It is output according in storage element 225 after 16 × (95- (p × 5) mod 96) chronomeres of delay, this means, T00,qIt is single in storage
It is output after the chronomere that member 225 will undergo 16 × (95- (0 × 5) mod 96)=1520.And D4~11p,qData storing up
Memory cell 225 is output after postponing 8 × (95- (p × 5) mod 96), this means, T10,qAnd T20,qWill be through in storage element 225
It is output after going through the chronomere of 8 (95- (0 × 5) mod 96)=760.D12p,qData will postpone 4 in storage element 225
It is output after × (95- (p × 5) mod 96), this means, T30,q4 × (95- (0 × 5) mod 96) will be undergone in storage element 225
It is output after=380 chronomere.Control unit 224 is from storage element 225 by data DXp,qIt is to be stored in caching after reading
In unit 223.Finally, the system of control unit 224 is adjusted by data DXp,qFrom the output order of buffer unit 223 by data
DXp,qOutput is handled with deadline release of an interleave.
First memory 226 is exemplified below under not bit widths W, first memory 226 and second memory 228 may
Space-consuming (by taking situation 1 as an example)：
Bit width W=64 positions
Bit width W=128 positions
Bit width W=256 positions
The disclosure and figure that can be invented due to the art tool usually intellectual by the device of interaction reference picture 2
The disclosure of 3~Fig. 4 method invention carrys out Liao and solves respective implementation detail and change, thus while embodiments of the invention are such as
It is upper described, but those embodiments are not used for limiting the present invention, the art tool usually intellectual can be according to the present invention
The content expressed or implied change is imposed to the technical characteristic of the present invention, all this kind change may belong to of the invention and be sought
The patent protection category asked, in other words, scope of patent protection of the invention must regard the as defined in claim of this specification as
It is accurate.
Claims (20)
1. a kind of time de-interlace method, by by more time interleaving data write-ins and reading a storage element to carry out the time
Release of an interleave processing, this method include：
K pens are chosen from the more time interleaving data, there is the K time interleaving data identical one to postpone length, and K is big
In 1 integer；
A data to be written are produced, the packet to be written contains the K time interleaving data；And
In with write-in program once, the data to be written are write into the storage element；
Wherein a bit width of the storage element is more than or equal to the data volume of the data to be written.
2. time de-interlace method as claimed in claim 1, it is characterised in that the K time interleaving data are respectively selected from K groups
Time interleaving data group, the K group time interleaving data groups correspond to identical time interleaving length.
3. time de-interlace method as claimed in claim 1, it is characterised in that further include：
The data volume of one time interleaving data of foundation and the bit width of the storage element determine the K values.
4. time de-interlace method as claimed in claim 3, it is characterised in that the K values are less than the bit width divided by one
The maximum integer of business obtained by the data volume of the time interleaving data.
5. time de-interlace method as claimed in claim 1, it is characterised in that the storage element include a first memory and
One second memory, the first memory as access unit and store the data to be written, the second memory using the bit width
Access unit be less than the bit width, this method further includes：
An object time intercrossed data is chosen, the object time intercrossed data has identical with the K time interleaving data
The delay length；And
The object time intercrossed data is write into the second memory.
6. a kind of time release of an interleave circuit, comprising：
One buffer unit, for caching more time interleaving data；
One storage element；And
One control unit, couple the buffer unit and the storage element, from the buffer unit choose K time interleaving data with
A data to be written are formed, and in write-in program once, the data to be written are write into the storage element；
Wherein, there is the K time interleaving data identical one to postpone length, and K is integer more than 1, and the storage element
One bit width is more than or equal to the data volume of the data to be written.
7. time release of an interleave circuit as claimed in claim 6, it is characterised in that the K time interleaving data are not selected from K groups
Time interleaving data group, the K group time interleaving data groups correspond to identical time interleaving length.
8. time release of an interleave circuit as claimed in claim 6, it is characterised in that the control unit is more handed over according to the time
The data volume of wrong data and the bit width of the storage element determine the K values.
9. time release of an interleave circuit as claimed in claim 8, it is characterised in that the K is should less than the bit width divided by one
The maximum integer of business obtained by the data volume of time interleaving data.
10. time release of an interleave circuit as claimed in claim 6, it is characterised in that the storage element includes：
One first memory, using the bit width as access unit, for storing the data to be written；And
One second memory, it accesses unit and is less than the bit width；
Wherein, the control unit more chooses an object time intercrossed data from the buffer unit, and the object time is interlocked
Data write the second memory, and the object time intercrossed data with the K time interleaving data there is the identical delay to grow
Degree.
11. a kind of time de-interlace method, by by more time interleaving data write-ins and reading a first memory and one the
To carry out time release of an interleave processing, this method includes two memories：
A very first time intercrossed data and a second time interleaving data, the pen are chosen from the more time interleaving data
Very first time intercrossed data with pen the second time interleaving data there is identical one to postpone length；
This very first time intercrossed data is write into the first memory；And
Pen the second time interleaving data are write into the second memory；
Wherein, the first memory is using a bit width as access unit, and the access unit of the second memory is less than the bit wide
Degree.
12. time de-interlace method as claimed in claim 11, it is characterised in that this very first time intercrossed data and the pen
Second time interleaving data produce simultaneously.
13. time de-interlace method as claimed in claim 11, it is characterised in that further include：
(K-1) pen is chosen from the more time interleaving data, (K-1) time interleaving data is somebody's turn to do and interlocks the very first time with this
Data have the identical delay length, and K is the integer more than 1；
Wherein, this very first time intercrossed data writes the first memory simultaneously with being somebody's turn to do (K-1) time interleaving data, and should
The summation of data volume of the pen very first time intercrossed data with being somebody's turn to do (K-1) time interleaving data is less than the bit width.
14. time de-interlace method as claimed in claim 13, it is characterised in that this very first time intercrossed data and should
(K-1) a time interleaving data is respectively selected from K group time interleaving data groups, when the K group time interleaving data groups correspond to identical
Between staggeredly length.
15. time de-interlace method as claimed in claim 13, it is characterised in that further include：
The data volume of one time interleaving data of foundation and the bit width determine the K values, and the K is less than the bit width divided by is somebody's turn to do
The maximum integer of business obtained by the data volume of time interleaving data.
16. a kind of time release of an interleave circuit, comprising：
One buffer unit, for caching more time interleaving data；
One first memory, using a bit width as access unit；
One second memory, it accesses unit and is less than the bit width；And
One control unit, the buffer unit, the first memory and the second memory are coupled, one is chosen from the buffer unit
A pen very first time intercrossed data and second time interleaving data, and this very first time intercrossed data is write this and first deposited
Reservoir and pen the second time interleaving data are write into the second memory；
Wherein, this very first time intercrossed data with pen the second time interleaving data there is identical one to postpone length.
17. time release of an interleave circuit as claimed in claim 16, it is characterised in that this very first time intercrossed data and the pen
Second time interleaving data produce simultaneously.
18. time release of an interleave circuit as claimed in claim 16, it is characterised in that the control unit is more from the buffer unit
(K-1) time interleaving data are chosen, and in this very first time intercrossed data is same with being somebody's turn to do (K-1) time interleaving data
When write the first memory, should (K-1) time interleaving data with this very first time intercrossed data there is identical this prolong
Slow length, K be integer more than 1, and this very first time intercrossed data with should (K-1) time interleaving data data volume
Summation is less than the bit width.
19. time release of an interleave circuit as claimed in claim 18, it is characterised in that this very first time intercrossed data and should
(K-1) a time interleaving data is respectively selected from K group time interleaving data groups, when the K group time interleaving data groups correspond to identical
Between staggeredly length.
20. time de-interlace method as claimed in claim 18, it is characterised in that the control unit is more according to the time
The data volume of intercrossed data and the bit width determine the K values, and the K is the data less than the bit width divided by the time interleaving data
Measure the maximum integer of the business of gained.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011337016.3A CN112395214A (en) | 2016-06-30 | 2016-06-30 | Time de-interleaving circuit and method |
| CN201610504245.7A CN107562638A (en) | 2016-06-30 | 2016-06-30 | Time release of an interleave circuit and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610504245.7A CN107562638A (en) | 2016-06-30 | 2016-06-30 | Time release of an interleave circuit and method |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011337016.3A Division CN112395214A (en) | 2016-06-30 | 2016-06-30 | Time de-interleaving circuit and method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107562638A true CN107562638A (en) | 2018-01-09 |
Family
ID=60969701
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610504245.7A Pending CN107562638A (en) | 2016-06-30 | 2016-06-30 | Time release of an interleave circuit and method |
| CN202011337016.3A Withdrawn CN112395214A (en) | 2016-06-30 | 2016-06-30 | Time de-interleaving circuit and method |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011337016.3A Withdrawn CN112395214A (en) | 2016-06-30 | 2016-06-30 | Time de-interleaving circuit and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN107562638A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101237240A (en) * | 2008-02-26 | 2008-08-06 | 北京海尔集成电路设计有限公司 | A method and device for realizing cirrocumulus interweaving/de-interweaving based on external memory |
| US20100197302A1 (en) * | 2009-01-30 | 2010-08-05 | Freescale Semiconductor, Inc. | Techniques for extracting a control channel from a received signal in a wireless communication system |
| TW201421914A (en) * | 2012-11-23 | 2014-06-01 | Mstar Semiconductor Inc | Convolutional deinterleaving apparatus and convolutional deinterleaving method |
| CN105099599A (en) * | 2014-04-16 | 2015-11-25 | 澜起科技（上海）有限公司 | Interleaving method, de-interleaving method and corresponding devices |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100699491B1 (en) * | 2005-07-19 | 2007-03-26 | 삼성전자주식회사 | Interleaving Method and System therof |
| US8127199B2 (en) * | 2007-04-13 | 2012-02-28 | Rgb Networks, Inc. | SDRAM convolutional interleaver with two paths |
| CN102104387A (en) * | 2009-12-17 | 2011-06-22 | 中兴通讯股份有限公司 | Decoder and decoding method |
-
2016
- 2016-06-30 CN CN201610504245.7A patent/CN107562638A/en active Pending
- 2016-06-30 CN CN202011337016.3A patent/CN112395214A/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101237240A (en) * | 2008-02-26 | 2008-08-06 | 北京海尔集成电路设计有限公司 | A method and device for realizing cirrocumulus interweaving/de-interweaving based on external memory |
| US20100197302A1 (en) * | 2009-01-30 | 2010-08-05 | Freescale Semiconductor, Inc. | Techniques for extracting a control channel from a received signal in a wireless communication system |
| TW201421914A (en) * | 2012-11-23 | 2014-06-01 | Mstar Semiconductor Inc | Convolutional deinterleaving apparatus and convolutional deinterleaving method |
| CN105099599A (en) * | 2014-04-16 | 2015-11-25 | 澜起科技（上海）有限公司 | Interleaving method, de-interleaving method and corresponding devices |
Non-Patent Citations (1)
| Title |
|---|
| 顾朝奇等: "用于视讯解交错的先进影像处理器", 《现代显示》 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112395214A (en) | 2021-02-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105490776B (en) | Deinterleaving method and interleaver | |
| CN107241288A (en) | The method and device of occupied resource is indicated under service integration scene | |
| CN107220187A (en) | A kind of buffer memory management method, device and field programmable gate array | |
| CN103581055B (en) | The order-preserving method of message, flow scheduling chip and distributed memory system | |
| CN104407809A (en) | Multi-channel FIFO (First In First Out) buffer and control method thereof | |
| CN108304347A (en) | A kind of Fast Fourier Transform (FFT) treating method and apparatus | |
| CN104246723A (en) | Management method and apparatus for on-chip shared cache | |
| CN101697491B (en) | Method for realizing convolution interleaving and de-interleaving of time domain by using SDRAM | |
| CN108092738A (en) | A kind of method and apparatus for deinterleaving solution rate-matched | |
| DE102007007546A1 (en) | Error correction code striping | |
| TWI601424B (en) | Time de-interleaving circuit and method thereof | |
| CN105550220B (en) | A kind of method and device of the access of heterogeneous system | |
| US7363552B2 (en) | Method and apparatus for convolutional interleaving/de-interleaving technique | |
| CN107562638A (en) | Time release of an interleave circuit and method | |
| CN114116600A (en) | Chip power consumption reduction design method and chip | |
| CN105955996A (en) | Image processing method and device | |
| CN104598391A (en) | Partitioning linear storage and reading method and system for two-dimensional matrix to be transposed | |
| CN107609161A (en) | A kind of data write-in, read method and system | |
| CN113169811B (en) | Data processing method and matrix memory | |
| KR101558172B1 (en) | The method and device for interleaving for error distribution and the recording medium for performing the method | |
| CN107368258B (en) | Method for screening damaged data row of data storage medium | |
| CN106528598B (en) | A kind of management method and physical equipment of chain | |
| CN105099599B (en) | Interleaving and deinterleaving method and corresponding device | |
| CN102006087B (en) | Convolutional interleaving method and device based on static random access memory (SRAM) | |
| CN109635929A (en) | Convolution implementation method and acoustic convolver based on FPGA |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20200331 Address after: No.1, Duhang 1st Road, Hsinchu City, Hsinchu Science Park, Taiwan, China Applicant after: MEDIATEK Inc. Address before: Taiwan Hsinchu County Tai Yuan Street China jhubei City, No. 26 4 floor 1 Applicant before: MStar Semiconductor, Inc. |
|
| TA01 | Transfer of patent application right | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20180109 |
|
| WD01 | Invention patent application deemed withdrawn after publication |