WO2017000682A1

WO2017000682A1 - Decoding method and apparatus and storage medium

Info

Publication number: WO2017000682A1
Application number: PCT/CN2016/081993
Authority: WO
Inventors: 王华勇
Original assignee: 深圳市中兴微电子技术有限公司
Priority date: 2015-06-30
Filing date: 2016-05-13
Publication date: 2017-01-05
Also published as: CN106330206A

Abstract

A decoding method comprises: reading input data of decoding at a first semi-window stage of decoding, and processing the read input data to obtain a processing result (101); decoding the processing result at a second semi-window stage of decoding to obtain a decoding result (102); and packaging and outputting the decoding result when the decoding result confirms that the decoding is ended (103). Also disclosed are a corresponding decoding apparatus and a storage medium.

Description

Decoding method, device and storage medium

Technical field

The present invention relates to the field of wireless communications technologies, and in particular, to a decoding method, apparatus, and storage medium.

Background technique

In wireless communication, 2G, 3G, 4G, and even 5G will coexist for a long time to meet the different needs of different users; therefore, multi-mode of wireless communication equipment is an inevitable trend in the development of wireless communication equipment.

As a channel coding technology, Turbo is widely used in wireless communication systems with 3G and 4G systems. The schematic diagram of the encoding principle of Turbo encoders is shown in Figure 1. The Turbo encoder passes two simple component encoders through a pseudo-random interleaver. Parallel cascading to construct long codes with pseudo-random characteristics to maximize the randomness of data and the amount of information per bit, making its capacity closer to the limit of Shannon's theory, in a noisy environment with low signal-to-noise ratio The performance is superior and has stronger anti-fading and anti-interference ability.

Turbo decoder realizes pseudo-random decoding by performing multiple iterations between two soft-in/soft-out decoders; schematic diagram of decoding principle of Turbo decoder, as shown in Fig. 2, two decoders MAP0 And MAP1 form a loop iterative structure. Under the action of external information, the bit error rate of a certain signal-to-noise ratio will decrease with the increase of the number of cycles, and the confidence will gradually increase. At the same time, the correlation of external information will also follow. As the number of decodings increases, the error correction capability provided by the external information is also weakened. After a certain number of cycles, the decoding performance of the Turbo decoder will not be improved. The Turbo decoder not only adopts an iterative loop process, but also adopts an algorithm that not only can decode each bit, but also provides a priori information for each bit of decoding along with decoding; therefore, the Turbo decoder has complex implementation. Disadvantages; here, MAP1 is the solution for interleaving The coder, MAP0, is a decoder that performs non-interleaving processing.

The only difference between the Turbo algorithm used in the 3G system and the 4G system is the interleaver. The implementation of the interleaver is usually done by controlling the address of the access data. The multi-level (MIL) interleaver used in the 3G system is constructed by constructing the RxC matrix. Multi-step steps such as permutation and inter-row permutation are implemented. The address is irregular and the possibility of parallel operation is small. The 4G system adopts a quadratic polynomial permutation (QPP) interleaver. The address is regular and can be realized. Conflict access and easy to operate.

At the same time, because the key technologies used in the 3G system and the 4G system are different, the interference type and the interference cancellation target are different; the 3G standard is to ensure the reliability, usually adopts the hard bit interference cancellation algorithm, and does not need to output soft symbols; In order to obtain greater gain, the soft symbol interference cancellation algorithm is usually used, so that the soft symbol information needs to be buffered in the Turbo decoding process for output to the external module for interference cancellation.

In order to improve the system throughput rate, the 3G system and the 4G system usually use the base 4 Turbo decoding algorithm, that is, decoding 4 bits of data at a time; however, due to the difference in the interleaver algorithms used in the 3G system and the 4G system, Affects the way of its decoding implementation and the overhead of the storage space; the decoding implementation, as shown in Figure 3: For the 4G system, due to the regularity of interleaving, the Turbo decoder can be conveniently divided into parallel processing units (PU). Parallel, serial serial processing unit (WIN) serial; for 3G system, due to the irregularity of interleaving, MAP1 can only be divided into WIN serial. The traditional MAP pipeline, as shown in Figure 4, for MP0, because the latter half of the window needs to read and write LE, there is a read and write LE conflict; and for MAP1, in addition to reading and writing LE conflict, 3G system due to the conflict of interleaved addresses, There are 4 bit read conflicts and write conflicts; therefore, the implementation architecture of the multimode Turbo decoder in the prior art is as shown in FIG. 5: the front window is read and written by the front window buffer and the back window. LE conflicts; 4-bit read conflicts and write conflicts supported by 3G are solved by 4 copies; however, this method can not fully share the storage resources of 4G standard soft symbols, resulting in relatively large storage resource overhead.

At the same time, in order to improve the decoding performance, the Turbo decoder usually uses a certain overlap window to train the sequence by fixing the default initial value, thereby improving the accuracy and correctness of the decoding; using a fixed default initial value, The overlap window requires at least 16 to meet the general performance requirements of the decoding. This greatly increases the useless overhead of resources.

It can be seen that the traditional Turbo decoder has 4G parallel and 3G serial, the storage resources are limited to 3G, the logic resources are limited to 4G, and the resource sharing is insufficient, resulting in low resource utilization. Both hardware overhead and power consumption are large. For the 3G system, the system throughput is also low due to insufficient use of logical resources.

Summary of the invention

In view of this, embodiments of the present invention are directed to providing a decoding method, apparatus, and storage medium, which can improve resource utilization and throughput, and reduce system overhead and power consumption.

The technical solution of the embodiment of the present invention is implemented as follows:

An embodiment of the present invention provides a decoding method, where the method includes:

Reading the decoded input data in the first half window stage of decoding, and processing the read input data to obtain a processing result;

Decoding the processing result in a second half of the decoding stage to obtain a decoding result;

When the decoding is confirmed based on the decoding result, the decoding result is encapsulated and output.

In the foregoing solution, before the confirming that the received external data is the first half of the window data, the method further includes:

Receiving a decoding parameter packet, and acquiring a decoding parameter according to the decoding parameter packet;

The decoded input data is received, the input data is processed according to the zero padding value PadNum calculated by the decoding parameter, and the processed data is stored.

In the above solution, the reading and decoding input data includes:

For the 3G system, in the first window of the interleaving processing stage of the decoded input data, the two sets of decoded input data are read first, and in the first half window stage, the two sets of decoded inputs are read. Data, obtaining four sets of decoded input data; or,

For the 3G system, the four sets of decoded input data are directly read in the non-interleaved processing stage of the decoded input data; or

For the 4G system, four sets of decoded input data are directly read during the non-interleaving process of the decoded input data and the interleaving process of the decoded input data.

In the above solution, the processing of the read input data to obtain a decoding result includes:

The gamma calculation is performed on the read input data to obtain a gamma value.

In the above solution, the decoding the processing result includes:

The forward and backward collision calculation is performed on the gamma value to obtain hard bit information, a priori information, and soft symbol information.

An embodiment of the present invention further provides a decoding apparatus, where the apparatus includes: a first processing module, a decoding module, and an output module;

The first processing module is configured to read the decoded input data in a first half window stage of decoding, and process the read input data to obtain a processing result;

The decoding module is configured to decode the processing result in a second half of the decoding stage to obtain a decoding result;

The output module is configured to, when the decoding is completed according to the decoding result, encapsulate and output the decoding result.

In the foregoing solution, the device further includes: a second processing module, configured to receive a decoding parameter packet, and obtain a decoding parameter according to the decoding parameter packet;

In the above solution, the first processing module is configured to, for the 3G system, read the two sets of decoded input data in the first window of the interleaving processing stage of the decoded input data, in the first half window In the stage, the two sets of decoded input data are read, and four sets of decoded input data are obtained; Or, for the 3G system, directly reading the four sets of decoded input data during the non-interleaving processing stage of the decoded input data; or

In the above solution, the first processing module is configured to perform gamma calculation on the read input data to obtain a gamma value.

In the above solution, the decoding module is configured to perform forward and backward collision calculation on the gamma value to obtain hard bit information, a priori information, and soft symbol information.

The embodiment of the present invention further provides a computer storage medium storing a computer program configured to perform the above decoding method of the embodiment of the present invention.

The decoding method, device and storage medium provided by the embodiments of the present invention read the decoded input data in the first half window stage of decoding, and process the read input data to obtain a processing result; In the second half window stage, the processing result is decoded to obtain a decoding result; when the decoding end is confirmed according to the decoding result, the decoding result is encapsulated and output; thus, the read data of the first half window stage can be obtained. The write data separation in the half window stage solves the problem of read and write conflicts and reduces the power consumption of resources. At the same time, 3G MAP0, 4G MAP0 and 4G MAP1 are merged into conflict-free channels by data alignment of the decoded input data. Unified parallel processing, 3G MAP1 is a collision channel, and serial processing is performed separately, which improves throughput.

DRAWINGS

1 is a schematic diagram of a coding principle of a prior art Turbo encoder;

2 is a schematic diagram of a decoding principle of a prior art Turbo decoder;

3 is a schematic diagram of a decoding implementation manner of a prior art turbo decoder;

4 is a schematic diagram of a prior art MAP pipeline;

5 is a schematic diagram of an implementation architecture of a prior art multimode Turbo decoder;

6 is a schematic flowchart of a basic processing process of a decoding method according to an embodiment of the present invention;

FIG. 7 is a schematic diagram showing the principle of initializing alpha inheritance history values according to an embodiment of the present invention; FIG.

FIG. 8 is a schematic diagram of a principle of initializing a beta inheritance history value according to an embodiment of the present invention; FIG.

9 is a schematic diagram of reading and writing data according to an embodiment of the present invention;

FIG. 10 is a schematic flowchart of detailed processing of a decoding method according to an embodiment of the present invention; FIG.

11 is a schematic structural diagram of a decoding apparatus according to an embodiment of the present invention;

FIG. 12 is a schematic diagram of implementation of a decoding apparatus according to an embodiment of the present invention.

detailed description

The basic processing flow of a decoding method in the embodiment of the present invention, as shown in FIG. 6, includes the following steps:

Step 101: In the first half window stage of decoding, reading the decoded input data, and processing the read input data to obtain a processing result;

The first processing module of the decoding device reads the decoded input data in a first half window stage of decoding;

1) For the 3G system, before interleaving the decoded input data, the first window of the MAP1 phase is read, and the two sets of decoded input data are read from the buffer, in the first half window stage, and then from the cache. Reading two sets of decoded input data, and obtaining four sets of decoded input data; each time before MAP1 iteration, there is a pre-reading phase of half window, and the latter half window is used as a pre-reading stage of the latter window;

Here, the input data of each group of decoding includes: a priori value LE, system data S, and check value P1; thus, by advancing half window reading, that is, adding one level before each iteration of 3G MAP1 Pre-read the pipeline ahead of time, take 2 bits of data from the 4-bit data for pre-reading and buffering, and the remaining 2 bits are read in the first half of the normal flow, and complete the data with 2 bits ahead of the pre-read; due to 3G MAP1 uses copying to resolve conflicts. Read and write will not exist in the same storage resource space at the same time. Therefore, there is no read/write conflict at all. The pre-reading pipeline can coincide with the second half of other windows. In this way, by adding a small amount of overhead, it is possible to reduce the simultaneous reading of 4 data to read 2 data at the same time, so that the corresponding copy number is also reduced from 4 copies to 2 copies, and the storage resources can completely share the storage of 4G soft symbols. Resources to reduce storage resources Source overhead and the purpose of improving shared resource utilization;

2) For the 3G system, the four sets of decoded input data are directly read in the non-interleaved processing MAP0 phase of the decoded input data; here, the input data of each set of decoding includes: LE, S, and P0;

3) for the 4G system, the non-interleaving processing stage of the decoded input data and the interleaving processing stage of the decoded input data are directly read four sets of decoded input data; here, Each set of decoded input data includes: LE, S, and P0, or LE, S, and P1.

Processing the read input data refers to performing gamma calculation on the input data to obtain a gamma value, and buffering the gamma value to gamma_ram; here, the gamma calculation adopts the scheme of (1, 0); the theory by Turbo algorithm The equation for the gamma calculation that is pushed up is:

among them,

Represents the gamma value from state S _2k to S _2k+2 ;

Indicates the encoding system bit SYS,

Representing the code check bit P0 or P1;

Indicates the received soft system symbol,

Indicates the received soft check symbol;

La(χ _2k ), La(χ _2k+1 ) represents the a priori soft information Le.

The hard bit symbol x is only +1,-1 in the sense of communication, and 0 means no signal, ±1 can increase the discrimination between two different signals; therefore, the calculation of gamma is usually adopted (1,- 1) Scheme; gamma calculation scheme comparison value, as shown in Table 1:

Table 1

It can be seen from Table 1 that the probability difference between the gamma(1,-1) and gamma(1,0) algorithms differs by an integer multiple, which is due to the result of using the gamma simplification algorithm; if a floating-point algorithm is used, The results of the two decoding algorithms are the same; however, if the fixed-point algorithm is used, the gamma(1,-1) algorithm will have a loss in accuracy due to the fixed-point accuracy problem; at the same time, from the implementation point of view, the gamma(1,0) algorithm It is also relatively simplified; therefore, the gamma(1,0) algorithm can not only reduce the overhead of logic resources, but also improve the decoding performance. Moreover, since the first half of the window needs to be cached, the overhead of the cache storage resource can also be reduced; and, since the gamma value is subsequently Whether it is used for hard bit symbols, for a priori information, or for soft symbol information, different combinations of probability differences are used. Therefore, gamma is calculated using the (1,0) scheme, and Does not cause any performance loss.

In the embodiment of the present invention, if it is not the first window of the MAP1 phase in the 3G system, the alpha or beta needs to be initialized before performing this step; if it is the first window of the MAP1 phase in the 3G system, it is in the cache. After reading the two sets of decoded input data, initialize alpha or beta;

Here, if the input data is decoded for the first time, that is, the first iteration, the alpha or beta is initialized with a fixed default value; otherwise, the alpha or beta is initialized with the cached historical value; wherein the cached history value is the last translation The value generated and cached by the code;

Since the Turbo collision decoding algorithm improves the decoding performance by increasing the size of the overlap training window, the initial value selected for training not only determines the size of the training window WIN, but also determines its decoding performance; the training window is theoretical. It is useless for the sake of training, and does not produce effective decoding output; therefore, the present application initializes alpha or beta by using inheritance history values, and can effectively reduce the decoding performance. The size of the training window WIN, This reduces useless overhead; and the reduction in useless overhead will inevitably increase system throughput and reduce dynamic power consumption.

The principle of alpha inheritance history value initialization, as shown in Figure 7: Since alpha uses forward calculation, each window can smoothly transition, except for the other windows outside the first window without overlapping training, the rear window can directly use the calculation result of the front window. As the training result continues processing, so alpha only the first window of each PU needs to be initialized. At the first iteration, the traditional default fixed value is initialized, and the alpha intermediate calculated value from the length of the WIN window at the end of each PU is saved for initialization of the next iteration; other iterations except the first iteration , use the intermediate value saved in the last iteration as the initial value of alpha, and save the intermediate value of this calculation for the next iteration.

The principle of beta inheritance history value initialization is shown in Figure 8. Since beta uses reverse computation, there is no continuity in data between windows. Therefore, each window needs to be initialized independently. At the first iteration, each window is initialized with the traditional default fixed value, and the beta intermediate calculation value from the WIN length point of each window header overlap window is saved for initialization of the next iteration; except for the first iteration The other iterations use the intermediate value saved in the last iteration as the initial value of beta, and save the intermediate value of this calculation for the next iteration.

In the embodiment of the present invention, before performing step 101, the method further includes:

Step 100a: Receive a decoding parameter packet, and obtain a decoding parameter according to the decoding parameter packet.

The second processing module in the decoding device receives the externally transmitted decoding parameter packet, and parses the decoding parameter packet; if the decoding parameter packet is parsed into a 3G system, the PadNum is calculated according to the zero-padding formula;

For the 3G system, since MAP0 uses sequential addresses and there is no conflict between addresses, MAP0 can operate in parallel; however, due to the irregularity of the interleaver in 3G system, the interleaved address when MAP1 reads and writes data is prone to conflict, so MAP1 It is impossible to operate in parallel; for the 4G system, the interleaver adopts Quadratic Polynomial Permutation (QPP). Therefore, both MAP0 and MAP1 in the 4G system can operate in parallel. So put 3G MAP0, 4G MAP0 and 4G MAP1 are merged into a collision-free channel and unified parallel processing; while 3G MAP1 is a collision channel, serial processing is performed separately by the principle of fixed window length. In this way, the logical resources can be shared to the maximum extent, and the resource utilization can be maximized. At the same time, the 3G MAP0 can be processed in parallel, which can greatly improve the throughput of the 3G system.

The Turbo code block size K specified by the 4G protocol is 188 possible values in the [40, 6144] interval, and each value is an integer multiple of N (N=8, 16, 32, 64) in each interval. Therefore, it can be easily divided into PU x WIN aliquots for parallel processing; and the Turbo code block size K specified in the 3G protocol can be any value of [40, 5114], not exactly an integer multiple of PU x WIN For 4G-compatible multi-PU parallel processing, the 3G input data needs to be padded at the end to the closest code block size K to 4G; the specific zero-padding formula is as follows:

PadNum=(8-k%8)%8,k∈[40,512] (2)

(16-k%16)%16,k∈(512,1024]

(32-k%32)%32,k∈(1024,2048]

(64-k%64)%64,k∈(2048,5114];

According to the decoding fast size k and PadNum, the number of parallel processing units (PuNum), serial processing unit number (WinNum) and serial processing unit size (WinSize), K', PuNum, WinNum, which are required for MAP0 and MAP1 operations, respectively, are calculated. The relationship with WinSize, as shown in Table 2:

K’＝k+PuNumK’=k+PuNum	PuNumPuNum	WinNumWinNum	WinSizeWinSize
[40，376][40,376]	11	11	K’％2K’%2
(376，752](376,752]	22	11	K’％4K’%4
(752，1504](752,1504)	44	11	K’％8K’%8
(1504，3072](1504,3072)	88	11	K’％16K’%16
(3072，6144](3072,6144]	88	22	K’％32K’%32

Table 2

Step 100b, receiving decoded input data, processing the input data according to PadNum, and storing the processed data;

Here, the second processing module of the decoding device receives the external decoded input data, parses p0, p1, and S in the input data, and stores the buffer to the cache after the received data is zero-padded according to the size of the PadNum. At the same time, the second processing module generates an interleave address according to k, and buffers the generated interleave address to addr_ram, the interleave address is used for reading and writing data in the MAP1 phase; after performing this step, performing initialization of alpha or beta operating.

Step 102: Decode the processing result in a second half of the decoding stage to obtain a decoding result.

Here, the decoding module in the decoding apparatus performs the forward-back collision calculation on the gamma value calculated in step 101 based on the base 4 collision MAP algorithm to obtain a decoding result, and caches the decoding result;

The decoding result includes: hard bit information, LE, and soft symbol information;

Correspondingly, the hard bit information is stored to hd_ram, the 4G check bit p1 soft symbol is stored to p1_le_ram, the 4G check bit p0 soft symbol is stored to p0_le_ram, the 4G system bit soft symbol is stored to llrs_scpy_ram, and the LE is stored to le_ram;

For non-conflicting channels, the four sets of decoding results are written to le_ram in parallel. If it is a conflicting channel, if an address conflict is encountered during the process of writing the decoding result, the conflicting address and data are first buffered to delay_ram. In the absence of an address conflict, the already cached conflicting address and data are written to le_ram along with other decoded results.

In the embodiment of the present invention, in order to solve the write conflict of the 4-bit data, the delayed write method is adopted. Since the decoding result data of the MAP only occurs in the second half window, the delay can be extended to the first half window, which is equivalent to writing only 2 at each moment. Bit data, and when there is no address conflict, multi-bit data can be written at the same time, thereby fundamentally eliminating the problem of write conflict.

Meanwhile, in the embodiment of the present invention, as shown in FIG. 9, the first half window is read from the shared storage resource. All the required data signals of the window are taken, and the data is cached by gamma calculation. In the latter half of the window, only the corresponding gamma value is read from the cache for decoding, and the decoding result is written back to the shared storage resource. In this way, the read/write of the shared storage resource is completely separated, and the read/write conflict is solved; at the same time, since it is not necessary to repeatedly read the data from the larger shared storage resource and perform the secondary calculation of the gamma value, only Obtaining the gamma value directly from the smaller cache reduces the read/write probability of large RAM and the flip rate of logical resources, effectively reducing dynamic power consumption.

Step 103, according to the decoding result, confirming that the decoding ends, encapsulating and outputting the decoding result;

The output module in the decoding device performs a Cyclic Redundancy Check (CRC) on the hard bit information in the decoding result, or the hard bit information in the current decoding result and the last iteration result. Comparing the hard bit information, determining whether the iteration ends according to the iterative early stop criterion and the CRC result or the comparison result; if the iteration is not finished, repeating steps 101 to 103; if the iteration ends, the decoded hard bit information is decoded. Or soft bit information is encapsulated and output to the outside;

It should be noted that the iteration in the embodiment of the present invention refers to performing multiple decoding on the input decoded data.

A detailed processing flow of a decoding method according to an embodiment of the present invention, as shown in FIG. 10, includes the following steps:

Step 201: Receive a decoding parameter packet, and obtain a decoding parameter according to the decoding parameter packet.

For the 3G system, since MAP0 uses sequential addresses and there is no conflict between addresses, MAP0 can operate in parallel; however, due to the irregularity of the interleaver in 3G system, the interleaved address when MAP1 reads and writes data is prone to conflict, so MAP1 Can not operate in parallel; for 4G system, the interleaver adopts collision-free QPP, therefore, MAP0 and MAP1 in 4G system can operate in parallel Work. Therefore, 3G MAP0, 4G MAP0 and 4G MAP1 are merged into a collision-free channel for unified parallel processing; while 3G MAP1 is a collision channel, serial processing is performed separately by the principle of fixed window length. In this way, the logical resources can be shared to the maximum extent, and the resource utilization can be maximized. At the same time, the 3G MAP0 can be processed in parallel, which can greatly improve the throughput of the 3G system.

PadNum=(8-k%8)%8,k∈[40,512] (2)

(16-k%16)%16,k∈(512,1024]

(32-k%32)%32,k∈(1024,2048]

(64-k%64)%64,k∈(2048,5114];

K’＝k+PuNumK’=k+PuNum	PuNumPuNum	WinNumWinNum	WinSizeWinSize
[40，376][40,376]	11	11	K’％2K’%2
(376，752](376,752]	22	11	K’％4K’%4
(752，1504](752,1504)	44	11	K’％8K’%8
(1504，3072](1504,3072)	88	21twenty one	K’％16K’%16
(3072，6144](3072,6144]	88	1212	K’％32K’%32

Table 2

Step 202: Receive decoded input data, process the input data according to PadNum, and store the processed data.

The second processing module of the decoding device receives the external decoded input data, parses p0, p1, and S in the input data, and stores the buffer to the buffer after the zero-order alignment of the received data according to the size of the PadNum; The second processing module generates an interleave address according to k, and buffers the generated interleave address to addr_ram, where the interleave address is used for MAP1 phase read and write data usage.

Step 203, it is determined whether it is necessary to enter the early pre-reading stage, when the determination result is yes, step 204 is performed, and if the determination result is no, step 205 is performed;

The first processing module of the decoding device determines that the 3G system is, and when the first window of the MAP1 phase is interleaved for the decoded input data, it is confirmed that the advance pre-reading phase needs to be entered; otherwise, the advance pre-reading is not required. Reading stage.

Step 204, pre-reading data in advance;

Here, two sets of input data to be decoded are first read from the cache;

Here, the input data of each group of decoding includes: a priori value LE, system data S, and check value P1; thus, by advancing half window reading, that is, adding one level before each iteration of 3G MAP1 Pre-read the pipeline ahead of time, take 2 bits of data from the 4-bit data for pre-reading and buffering, and the remaining 2 bits are read in the first half of the normal flow, and complete the data with 2 bits ahead of the pre-read; due to 3G MAP1 uses copying to resolve conflicts. Read and write will not exist in the same storage resource space at the same time. Therefore, there is no read/write conflict at all. The pre-reading pipeline can coincide with the second half of other windows. In this way, by adding a small amount of overhead, it is possible to reduce the simultaneous reading of 4 data to read 2 data at the same time, so that the corresponding copy number is also reduced from 4 copies to 2 copies, and the storage resources can completely share the storage of 4G soft symbols. Resources, to achieve the purpose of reducing storage resource overhead and increasing the utilization of shared resources.

Step 205, in the first half window stage of decoding, reading the decoded input data, and reading the input The data is processed to obtain the processing result;

Here, the first processing module of the decoding device reads the decoded input data in the first half window stage of decoding;

1) For the 3G system, the first window of the MAP1 phase is interleaved on the decoded input data, and in the first half window phase, the two sets of decoded input data are read from the buffer, and the step 204 is advanced in advance. The two sets of data read together constitute four sets of decoded input data; here, the input data of each set of decoding includes: LE, S, and P1; each time before the MAP1 iteration, there is a half-reading stage of the window, The second half window serves as the pre-reading stage of the latter window;

among them,

Represents the gamma value from state S _2k to S _2k+2 ;

Indicates the encoding system bit SYS,

Representing the code check bit P0 or P1;

Indicates the received soft system symbol,

Indicates the received soft check symbol;

La(χ _2k ), La(χ _2k+1 ) represents the a priori soft information Le.

In the embodiment of the present invention, the gamma calculation is performed by using the gamma (1, 0) algorithm.

In the embodiment of the present invention, if it is not the first window of the MAP1 phase in the 3G system, the alpha or beta needs to be initialized before performing this step; if it is the first bed of the MAP1 phase in the 3G system, it is in the cache. After reading the two sets of decoded input data, initialize alpha or beta;

Here, if the input data is decoded for the first time, that is, the first iteration, the alpha or beta is initialized with a fixed default value; otherwise, the alpha or beta is initialized with the cached historical value; wherein the cached history value is the last translation The value generated and cached by the code; the principle of alpha inheritance history value initialization, as shown in Figure 7, the principle of beta inheritance history value initialization, as shown in Figure 8, is described above, and will not be described here.

Step 206: Decode the processing result in a second half of the decoding stage to obtain a decoding result.

Here, the decoding module in the decoding device performs the forward-back collision calculation on the gamma value calculated in step 203 based on the base 4 collision MAP algorithm to obtain a decoding result, and caches the decoding result;

In the embodiment of the present invention, in order to solve the write conflict of the 4-bit data, the delayed write method is adopted, and since the decoding result data of the MAP only occurs in the second half window, the delay can be extended to the first half window, When only 2 bits of data are written at each moment, and when there is no address conflict, multi-bit data can be written at the same time, thereby fundamentally eliminating the problem of write conflict.

Step 207, it is determined whether all the windows are processed, and if the determination result is yes, step 208 is performed, and if the determination result is no, step 205 is performed;

Step 208, according to the decoding result to determine whether the decoding is over, the determination result is yes, step 209 is performed, and if the determination result is no, step 203 is performed;

Here, the output module in the decoding device performs a Cyclic Redundancy Check (CRC) on the hard bit information in the decoding result, or the hard bit information in the current decoding result and the last iteration. The hard bit information in the result is compared, and it is determined whether the iteration ends according to the iterative early stop criterion and the CRC result or the comparison result.

Step 209, encapsulating and outputting the decoding result;

The output module in the decoding device encapsulates and outputs the decoded hard bit information or soft bit information to the outside;

In order to achieve the above decoding method, an embodiment of the present invention provides a decoding apparatus. The composition of the apparatus, as shown in FIG. 11, includes: a first processing module 10, a decoding module 20, and an output module 30; ,

The first processing module 10 is configured to read the decoded input data in the first half window stage of the decoding, and process the read input data to obtain a processing result;

The decoding module 20 is configured to decode the processing result in a second half of the decoding stage to obtain a decoding result;

The output module 30 is configured to, when the decoding is completed according to the decoding result, encapsulate and output the decoding result.

In the embodiment of the present invention, the device further includes: a second processing module 40 configured to receive the translation a code parameter packet, which acquires a decoding parameter according to the decoding parameter packet;

The decoded input data is received, the input data is processed according to PadNum in the decoding parameter, and the processed data is stored.

In the embodiment of the present invention, the first processing module 10 is configured to, for the 3G system, read the two sets of decoded input data in the first window of the interleaving processing stage of the decoded input data. In the first half window stage, two sets of decoded input data are read, and four sets of decoded input data are obtained; or

In the embodiment of the present invention, the first processing module 10 is configured to perform gamma calculation on the read input data to obtain a gamma value.

In the embodiment of the present invention, the decoding module 30 is configured to perform forward and backward collision calculation on the gamma value to obtain hard bit information, LE, and soft symbol information.

Here, if the input data is decoded for the first time, that is, the first iteration, the alpha or beta is initialized with a fixed default value; otherwise, the alpha or beta is initialized with the cached historical value; wherein the cached history value is the last translation The value that the code generates and caches.

In the embodiment of the present invention, the second processing module 40 is configured to receive external decoding input data, parse p0, p1, and S in the input data, and fill zero in the tail of the received data according to the size of the PadNum. Aligning and storing to the cache; at the same time, the second processing module generates an interleave address according to k, and buffers the generated interleave address to addr_ram, where the interleave address is used MAP1 stage read and write data usage.

In the embodiment of the present invention, the decoding module 30 is configured to perform a forward-back collision calculation on the gamma value based on the base 4 collision MAP algorithm, obtain a decoding result, and cache the decoding result.

Here, for the non-conflicting channel, the four sets of decoding results are written in parallel to le_ram. If it is a conflicting channel, if an address conflict is encountered during the process of writing the decoding result, the conflicting address and data are first buffered. To delay_ram, when there is no address conflict, write the conflicted address and data that has been cached together with other decoding results to le_ram;

Correspondingly, the hard bit information is stored to hd_ram, the 4G check bit p1 soft symbol is stored to p1_le_ram, the 4G check bit p0 soft symbol is stored to p0_le_ram, the 4G system bit soft symbol is stored to llrs_scpy_ram, and the LE is stored to le_ram; A schematic diagram of the implementation of the decoding apparatus in the embodiment of the present invention is shown in FIG.

Meanwhile, in the embodiment of the present invention, all the required data messages of the window are read from the shared storage resource in the first half window, and the data is cached after gamma calculation, and only the corresponding data is read from the cache in the second half window. The gamma value is decoded, and the decoding result is written back to the shared storage resource; thus, the read/write of the shared storage resource is completely separated, and the read/write conflict is solved; at the same time, since the shared storage resource is not required from the larger The data is read twice and the second calculation of the gamma value is performed. The gamma value is directly obtained from the smaller buffer, which reduces the read/write probability of the large RAM and the flip rate of the logical resource, thereby effectively reducing the dynamic power consumption.

It should be noted that, in practical applications, the first processing module 10, the decoding module 20, And the functions performed by output module 30 and second processing module 40 may be by a central processing unit (CPU), or a microprocessor (MPU), or a digital signal processor (DSP), or a programmable gate array located on the decoding device ( FPGA) implementation.

In the embodiment of the present invention, if the above decoding method is implemented in the form of a software function module and sold or used as a stand-alone product, it may also be stored in a computer readable storage medium. Based on such understanding, the technical solution of the embodiments of the present invention may be embodied in the form of a software product in essence or in the form of a software product stored in a storage medium, including a plurality of instructions. A computer device (which may be a personal computer, server, or network device, etc.) is caused to perform all or part of the methods described in various embodiments of the present invention. The foregoing storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read only memory (ROM), a magnetic disk, or an optical disk. Thus, embodiments of the invention are not limited to any specific combination of hardware and software.

Correspondingly, the embodiment of the present invention further provides a computer storage medium, where the computer storage medium stores a computer program, and the computer program is used to execute the above decoding method in the embodiment of the present invention.

The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention.

Industrial applicability

In the embodiment of the present invention, in the first half window stage of decoding, the decoded input data is read, and the read input data is processed to obtain a processing result; in the second half of the decoding stage, the processing result is performed. Decoding, to obtain a decoding result; according to the decoding result, when decoding is completed, the decoding result is encapsulated and output; thus, the read data of the first half window stage and the write data of the second half window stage are separated, thereby solving the reading. Write conflicts, reduce the power consumption of resources; at the same time, by aligning the decoded input data, 3G MAP0, 4G MAP0 and 4G MAP1 are merged into a collision-free channel, unified parallel processing, 3G MAP1 is a conflict channel, separate Serial processing High throughput.

Claims

A decoding method, the method comprising:

Reading the decoded input data in the first half window stage of decoding, and processing the read input data to obtain a processing result;

Decoding the processing result in a second half of the decoding stage to obtain a decoding result;

When the decoding is confirmed based on the decoding result, the decoding result is encapsulated and output.
The method of claim 1, wherein before the confirming that the received external data is the first half of the window data, the method further comprises:

Receiving a decoding parameter packet, and acquiring a decoding parameter according to the decoding parameter packet;

The decoded input data is received, the input data is processed according to the zero padding value PadNum calculated by the decoding parameter, and the processed data is stored.
The method of claim 1 or 2, wherein said reading the decoded input data comprises:

For the 3G system, in the first window of the interleaving processing stage of the decoded input data, the two sets of decoded input data are read first, and in the first half window stage, the two sets of decoded input data are read. Obtaining four sets of decoded input data; or,

For the 3G system, the four sets of decoded input data are directly read in the non-interleaved processing stage of the decoded input data; or

For the 4G system, four sets of decoded input data are directly read during the non-interleaving process of the decoded input data and the interleaving process of the decoded input data.
The method according to claim 1 or 2, wherein said processing the read input data to obtain a decoded result comprises:

The gamma calculation is performed on the read input data to obtain a gamma value.
The method of claim 4 wherein said decoding said processing result comprises:

The forward and backward collision calculation is performed on the gamma value to obtain hard bit information, a priori information, and soft symbol information.
A decoding device, the device comprising: a first processing module, a decoding module, and an output module; wherein

The first processing module is configured to read the decoded input data in a first half window stage of decoding, and process the read input data to obtain a processing result;

The decoding module is configured to decode the processing result in a second half of the decoding stage to obtain a decoding result;

The output module is configured to, when the decoding is completed according to the decoding result, encapsulate and output the decoding result.
The apparatus according to claim 6, wherein the apparatus further comprises: a second processing module configured to receive a decoding parameter packet, and obtain a decoding parameter according to the decoding parameter packet;

The decoded input data is received, the input data is processed according to the zero padding value PadNum calculated by the decoding parameter, and the processed data is stored.
The apparatus according to claim 6 or 7, wherein said first processing module is configured to, for the 3G system, read the first two groups of the interleaving processing stage of said decoded input data Decoding input data, in the first half window stage, reading two sets of decoded input data to obtain four sets of decoded input data; or, for 3G system, performing non-interleaving processing on the decoded input data The stage directly reads four sets of decoded input data; or,

For the 4G system, four sets of decoded input data are directly read during the non-interleaving process of the decoded input data and the interleaving process of the decoded input data.
The apparatus according to claim 6 or 7, wherein said first processing module is configured to perform gamma calculation on the read input data to obtain a gamma value.
The apparatus according to claim 9, wherein the decoding module is configured to perform forward and backward collision calculation on the gamma value to obtain hard bit information, a priori information, and a soft symbol. information.
A computer storage medium having stored therein computer executable instructions for performing the decoding method of any one of claims 1 to 5.