CN101515805A - Turbo encoder and encoding method thereof - Google Patents
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Abstract
Turbo encoder and encoding method thereof are disclosed in the embodiment of the invention, which relates to the information communication field and can improve the performance and throughput of the Turbo encoder. The method comprises: when a data ping cache element is empty, inputting data into the data ping cache element, generating an interleaving table according to the data length, and storing the interleaving table into an interleaving table ping cache element; or when a data pong cache element is empty, inputting data into the data pong cache element, generating an interleaving table according to the data length, and storing the interleaving table into an interleaving table pong cache element; iteratively computing the data stored in the data ping cache element according to the interleaving table stored in the interleaving table ping cache element to obtain the encoding result; or iteratively computing the data stored in the data pong cache element according to the interleaving table stored in the interleaving table pong cache element to obtain the encoding result.
Description
Technical field
The present invention relates to the communications field, relate in particular to a kind of Turbo decoder and interpretation method thereof.
Background technology
Turbo code is after 1993 are proposed by people such as C.Berrou, communication educational circles has started the climax of research Turbo code, Turbo code is constructed the long code with pseudo-random characteristics with two simple component codes by the pseudo random interleaver parallel cascade dexterously, and has realized pseudorandom decoding by carry out repeatedly iteration between two SISO (Soft In Soft Out is soft go into soft go out module) decoder.
Be specially: after data to decode is distributed to input-buffer, start the interleaver of Turbo inside, interleaver starts the Turbo decoder after generating the table that interweaves automatically.Data distribution like this, the table that interweaves generates and the decoding serial is carried out.
Realization in SISO inside all is to adopt sliding window to add alpha training module or the realization of beta training module.The alpha training module and the beta training module of every window can be realized in SISO inside, also can only realize the alpha training module or the beta training module of every window, and the selection of training length scale can influence the decoding performance of Turbo decoder.
Realize that at the Turbo decoder in the process of above-mentioned decoding, the inventor finds that there are the following problems at least in the prior art:
The input of decoding data, the calculating of interleaver has taken a large amount of time, causes Turbo decoder performance and throughput lower.
Summary of the invention
Embodiments of the invention provide a kind of Turbo decoder and interpretation method thereof, can improve the performance and the throughput of Turbo decoder.
For achieving the above object, embodiments of the invention adopt following technical scheme:
A kind of Turbo decoder comprises:
Data ping-pong buffer unit is respectively applied for the buffer memory data to decode;
The table ping-pong buffer unit that interweaves is used for the buffer memory table that interweaves;
Input Control Element is used for when data table tennis buffer unit free time and data pang buffer unit take, and to data table tennis buffer unit input data to decode, and informs data to decode length to interleave unit; Perhaps when data pang buffer unit free time and data table tennis buffer unit takies,, and inform data to decode length to interleave unit to data pang buffer unit input data to decode;
Interleave unit is used to receive the data to decode length of the data table tennis buffer unit of informing from Input Control Element, generates to interweave table and deposit the table table tennis buffer unit that interweaves in; Perhaps receive the data to decode length of data pang the buffer unit of informing from Input Control Element, generating interweaves shows and deposits in table pang the buffer unit that interweaves;
Softly go into the soft SISO unit that goes out, be used for the data to decode of data table tennis buffer unit storage being carried out iterative computation, obtain decode results according to the table that interweaves of the table table tennis buffer unit storage that interweaves; Perhaps the data to decode of data pang buffer unit being stored according to the table that interweaves of table pang the buffer unit storage that interweaves carries out iterative computation, obtains decode results.
A kind of Turbo decoder for decoding method comprises: data ping-pong buffer unit is set and interweaves table ping-pong buffer unit;
When data table tennis buffer unit free time and data pang buffer unit take,,, generate and interweave table and deposit the table table tennis buffer unit that interweaves in according to data to decode length to data table tennis buffer unit input data to decode; Perhaps when data pang buffer unit free time and data table tennis buffer unit takies,,, generate and interweave table and deposit table pang the buffer unit that interweaves in according to data to decode length to data pang buffer unit input data to decode;
When there is data to decode in data table tennis buffer unit and the table table tennis buffer unit that interweaves stores when interweaving table accordingly, show the data to decode of data table tennis buffer unit storage is carried out iterative computation according to the interweaving of table table tennis buffer unit storage that interweave, obtain decode results; Perhaps there is data to decode and table pang the buffer unit that interweaves stores when table of interweaving accordingly when data pang buffer unit, the data to decode of data pang buffer unit being stored according to the table that interweaves of table pang the buffer unit storage that interweaves carries out iterative computation, obtains decode results.
Turbo decoder and interpretation method that the embodiment of the invention provides, adopt data ping-pong buffer unit and interweaved table ping-pong buffer unit, when data table tennis buffer unit free time and data pang buffer unit take, to data table tennis buffer unit input data, and show the table tennis buffer unit to interweaving and inform data length; Perhaps when data pang buffer unit free time and data table tennis buffer unit takies,, and inform data length to table pang the buffer unit that interweaves to data pang buffer unit input data; Therefore, can the ping-pong buffer data, and start the table ping-pong buffer unit that the interweaves table that becomes to interweave.The time has been saved in the input of this data and distribution, has improved degree of parallelism, thereby has improved efficient and throughput.
Description of drawings
Fig. 1 is the structural representation of Turbo encoder in the prior art;
Fig. 2 is the structural representation of Turbo decoder in the prior art;
The structured flowchart one of the Turbo decoder that Fig. 3 provides for the embodiment of the invention;
The structured flowchart two of the Turbo decoder that Fig. 4 provides for the embodiment of the invention;
The schematic diagram that the SISO unit internal algorithm of the Turbo decoder that Fig. 5 provides for the embodiment of the invention realizes;
The realization circuit diagram of three memory modules in the Turbo decoder that Fig. 6 provides for the embodiment of the invention;
The structured flowchart three of the Turbo decoder that Fig. 7 provides for the embodiment of the invention;
The FB(flow block) one of the Turbo decoder for decoding method that Fig. 8 provides for the embodiment of the invention;
The FB(flow block) two of the Turbo decoder for decoding method that Fig. 9 provides for the embodiment of the invention.
Embodiment
Embodiments of the invention provide a kind of Turbo decoder and interpretation method thereof, can improve the performance and the throughput of Turbo decoder.
Below in conjunction with accompanying drawing the embodiment of the invention is described in detail.
What the Turbo decoder was realized is the inverse process of Turbo coding, as shown in Figure 1, is the Turbo encoder block diagram in the agreement.
Wherein, the Turbo encoder is output as:
x
1，z
1，z′
1，x
2，z
2，z′
2，......，x
K，z
K，z′
K，
x
K+1，z
K+1，x
K+2，z
K+2，x
K+3，z
K+3，x′
K+1，z′
k+1，x′
K+2，z′
K+2，x′
K+3，z′
K+3
What the Turbo decoder that the present invention realizes adopted is basic 4 algorithms, therefore the data of decoder being distributed to input-buffer, four buffer memory: A, B, Y1W1, Y2W2 buffer memory is for example arranged, and reads for the Turbo decoder, as follows:
A buffer memory: x
1, x
2..., x
k, x
K+1, x
K+2, x
K+3, x '
K+1, x '
K+2, x '
K+3
B buffer memory: x
1, x
2..., x
k, x
K+1, x
K+2, x
K+3, x '
K+1, x '
K+2, x '
K+3
Y1W1 buffer memory: z
1, z
2... .., z
k, z
K+1, z
K+2, z
K+3
Y2W2 buffer memory: z '
1, z '
2..., z '
k, z '
K+1, z '
K+2, z '
K+3
Block diagram is realized as shown in Figure 2 in the inside of decoder, after A, B, Y1W1, Y2W2 buffer memory input data, the length of data is informed interleaver, generates the table that interweaves, and softly goes into the soft SISO of going out module and interweaves according to this and show to carry out iterative decoding.
The Turbo decoder that embodiments of the invention provide as shown in Figure 3, comprising:
Data ping-pong buffer unit 301 is respectively applied for the buffer memory data to decode;
The table ping-pong buffer unit 302 that interweaves is used for the buffer memory table that interweaves;
Softly go into the soft SISO unit 305 that goes out, be used for the data to decode of data table tennis buffer unit storage being carried out iterative computation, obtain decode results according to the table that interweaves of the table table tennis buffer unit storage that interweaves; Perhaps the data to decode of data pang buffer unit being stored according to the table that interweaves of table pang the buffer unit storage that interweaves carries out iterative computation, obtains decode results.
Wherein, data ping-pong buffer unit 301 can be specially A, B, Y1W1, Y2W2 buffer memory in practice.
The Turbo decoder that the embodiment of the invention provides, adopt data ping-pong buffer unit and interweaved table ping-pong buffer unit, when data table tennis buffer unit free time and data pang buffer unit take,, and inform data length to the table table tennis buffer unit that interweaves to data table tennis buffer unit input data; Perhaps when data pang buffer unit free time and data table tennis buffer unit takies,, and inform data length to table pang the buffer unit that interweaves to data pang buffer unit input data; Therefore, can the ping-pong buffer data, and start the table ping-pong buffer unit that the interweaves table that becomes to interweave.The time has been saved in the input of this data and distribution, has improved degree of parallelism, thereby has improved efficient and throughput.
Further, in another embodiment of the present invention, as shown in Figure 4, data ping-pong buffer unit 301 specifically comprises:
Data table tennis cache module 301A, data pang cache module 301B;
Have, the table ping-pong buffer unit 302 that interweaves also specifically comprises again:
Interweave and show table tennis cache module 302A, table pang cache module 302B interweaves.
The Turbo decoder that further embodiment of this invention provides, as shown in Figure 5, the iterative decoding that carries out in SISO unit 303 is to adopt sliding window algorithm to add gama computing module, beta training module, alpha computing module, beta computing module to realize that so-called sliding window algorithm also is by limiting the maximum number of cell that can receive in each time window traffic carrying capacity to be controlled.In addition, alpha computing module, beta training module, beta computing module, gama computing module and input data computing relation are as follows:
The gama computing module need be used A, B, Y1W1, Y2W2 buffer memory;
Alpha computing module and beta training module, beta computing module all to use the gama computing module the result;
The alpha computing module order and the gama computing module of each window, the computation sequence of beta computing module, beta training module is opposite;
The input data of N window need be finished in the time of N+2 window.
Its SISO is inner to be realized as shown in Figure 5, the gama computing module calculates window since N+1, calculate the 0th always and calculate window, calculate the result of calculation that each window obtains each window, the beta training module will use the gama computing module to calculate the result who works as front window, the alpha computing module will use the gama computing module to calculate the computer result of next window gained, and the beta computing module will use the gama computing module to calculate the result of calculation of two windows down.
Therefore, as shown in Figure 7, SISO provided by the invention unit 305 comprises:
Gama computing module 305A is used for obtaining data from data ping-pong buffer unit 301, calculates result of calculation, deposits result of calculation in memory module 305B, and sends this result of calculation to Bata training module 305C;
Memory module 305B, the result of calculation that is used to store Gama computing module 305A;
Bata training module 305C is used for obtaining the result of calculation of Gama computing module from the Gama computing module or from memory module, calculates;
Alpha computing module 305D is used for obtaining from memory module 305B the result of calculation of Gama computing module 305A, calculates;
Bata computing module 305E is used for obtaining from memory module 305B the result of calculation of Gama computing module 305A, calculates.
Wherein, memory module 305B is three, and first memory module 305B1 storage is when the result of calculation of the Gama computing module of front window; The second memory module 305B2 stores the result of calculation of the Gama computing module of next window; The 3rd memory module 305B3 storage is the result of calculation of the Gama computing module of two windows down, every calculating one window of Gama computing module just deposits data in a memory module, when three memory modules all deposit in after one time, once more since the first memory module 305B1, the circulation storage; It realizes circuit as shown in Figure 6;
Concrete, Bata training module 305C can directly obtain result of calculation when front window from Gama computing module 305A, also can obtain the result of calculation when front window from the first memory module 305B1, calculates;
Alpha computing module 305D calculates from the result of calculation that the second memory module 305B2 obtains the Gama computing module 305A of next window;
Bata computing module 305E calculates from the result of calculation that the 3rd memory module 305B3 obtains down the Gama computing module 305A of two windows.
Further, Bata training module 305C, Alpha computing module 305D and Bata computing module 305E parallel processing.
Three memory modules in the present embodiment can realize with memories such as RAM in practice.
The Turbo decoder that the embodiment of the invention provides, in the SISO internal configurations three memory modules, be used for storing respectively the result of calculation of Gama computing module when front window, next window and following two windows, therefore, Bata training module, Alpha computing module and Bata computing module can get access to the result of calculation of required Gama computing module from three memory modules, thereby can realize parallel processing, save and calculated the time, improve efficient and throughput.
The Turbo decoder for decoding method that the embodiment of the invention provides comprises: data ping-pong buffer unit is set and interweaves table ping-pong buffer unit; As shown in Figure 8, the step of this method comprises:
S801, when data table tennis buffer unit free time and data pang buffer unit take, to data table tennis buffer unit input data to decode,, generate and interweave table and deposit the table table tennis buffer unit that interweaves in according to data to decode length; Perhaps when data pang the buffer unit free time, and data table tennis buffer unit is when taking, and to data pang buffer unit input data to decode, according to data to decode length, generates and interweaves table and deposit table pang the buffer unit that interweaves in;
S802, there is data to decode and the table table tennis buffer unit that interweaves stores when interweaving table accordingly when data table tennis buffer unit, show the data to decode of data table tennis buffer unit storage is carried out iterative computation according to the interweaving of table table tennis buffer unit storage that interweave, obtain decode results; Perhaps there is data to decode and table pang the buffer unit that interweaves stores when table of interweaving accordingly when data pang buffer unit, the data to decode of data pang buffer unit being stored according to the table that interweaves of table pang the buffer unit storage that interweaves carries out iterative computation, obtains decode results.
The Turbo decoder for decoding method that the embodiment of the invention provides, adopt data ping-pong buffer unit and interweaved table ping-pong buffer unit, when data table tennis buffer unit free time and data pang buffer unit take, to data table tennis buffer unit input data, and show the table tennis buffer unit to interweaving and inform data length; Perhaps when data pang buffer unit free time and data table tennis buffer unit takies,, and inform data length to table pang the buffer unit that interweaves to data pang buffer unit input data; Therefore, can the ping-pong buffer data, and start the table ping-pong buffer unit that the interweaves table that becomes to interweave.The time has been saved in the input of this data and distribution, has improved degree of parallelism, thereby has improved efficient and throughput.
Further, in another embodiment of the present invention, as shown in Figure 9, among the above-mentioned steps S802 data to decode is carried out iterative computation, obtain decode results, use Gama computing module, memory module, Bata training module in the SISO unit, Alpha computing module, Beta computing module, data to decode is carried out iterative computation, obtain decode results and specifically can comprise the steps:
S901, Gama computing module obtain the input data from data ping-pong buffer unit, calculate result of calculation;
S902, described result of calculation is deposited in the memory module;
S903, Bata training module are from the Gama computing module or obtain the result of calculation of Gama computing module from the storage mould is determined, and calculate;
S904, Alpha computing module obtain the result of calculation of Gama computing module from memory module, calculate;
S905, Bata computing module obtain the result of calculation of Gama computing module from memory module, calculate.
Wherein, step S902 specifically comprises:
Three memory modules are set, comprise: first memory module, second memory module, the 3rd memory module;
The Gama computing module calculates the result of calculation when front window, deposits result of calculation in first memory module;
The Gama computing module calculates the result of calculation of next window, deposits result of calculation in second memory module;
The Gama computing module calculates the result of calculation of two windows down, deposits result of calculation in the 3rd memory module;
Same as the previously described embodiments, every calculating one window of Gama computing module just deposits data in a memory module, when three memory modules all deposit in after one time, and once more since first memory module, the circulation storage.
So, step S903, step S904 and step S905 are specially;
The Bata training module obtains result of calculation when front window from Gama computing module or first memory module, calculates;
The Alpha computing module obtains the result of calculation of the Gama computing module of next window from second memory module, calculate;
The Bata computing module obtains down the result of calculation of the Gama computing module of two windows from the 3rd memory module, calculate;
Because this three memory modules have been arranged, above-mentioned steps S903, step S904 and step S905 can parallel processings.
The Turbo decoder for decoding method that the embodiment of the invention provides, in the SISO internal configurations three memory modules, be used for storing respectively the result of calculation when front window, next window and following two windows of Gama computing module, therefore, Bata training module, Alpha computing module and Bata computing module can get access to the result of calculation of required Gama computing module from three memory modules, thereby can realize parallel processing, save and calculated the time, improve efficient and throughput.
One of ordinary skill in the art will appreciate that all or part of flow process that realizes in the foregoing description method, be to instruct relevant hardware to finish by computer program, described program can be stored in the computer read/write memory medium, this program can comprise the flow process as the embodiment of above-mentioned each side method when carrying out.Wherein, described storage medium can be magnetic disc, CD, read-only storage memory body (Read-Only Memory, ROM) or at random store memory body (Random Access Memory, RAM) etc.
The above; only be the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion by described protection range with claim.
Claims (10)
1, a kind of Turbo decoder is characterized in that, comprising:
Data ping-pong buffer unit is respectively applied for the buffer memory data to decode;
The table ping-pong buffer unit that interweaves is used for the buffer memory table that interweaves;
Input Control Element is used for when data table tennis buffer unit free time and data pang buffer unit take, and to data table tennis buffer unit input data to decode, and informs data to decode length to described interleave unit; Perhaps when data pang buffer unit free time and data table tennis buffer unit takies,, and inform data to decode length to described interleave unit to data pang buffer unit input data to decode;
Interleave unit is used to receive the data to decode length of the data table tennis buffer unit of informing from described Input Control Element, generates to interweave table and deposit the table table tennis buffer unit that interweaves in; Perhaps receive the data to decode length of data pang the buffer unit of informing from described Input Control Element, generating interweaves shows and deposits in table pang the buffer unit that interweaves;
Softly go into the soft SISO unit that goes out, be used for the data to decode of described data table tennis buffer unit storage being carried out iterative computation, obtain decode results according to the table that interweaves of the described table table tennis buffer unit storage that interweaves; Perhaps the data to decode of described data pang buffer unit being stored according to the described table that interweaves that interweaves the storage of table pang buffer unit carries out iterative computation, obtains decode results.
2, Turbo decoder according to claim 1 is characterized in that, described SISO unit comprises:
The Gama computing module is used for obtaining data from described data ping-pong buffer unit, calculates result of calculation, deposits described result of calculation in memory module, perhaps and to the Bata training module sends described result of calculation;
Memory module, the result of calculation that is used to store described Gama computing module;
The Bata training module is used for obtaining the result of calculation of described Gama computing module from described Gama computing module or from described memory module, calculates;
The Alpha computing module is used for obtaining from described memory module the result of calculation of described Gama computing module, calculates;
The Bata computing module is used for obtaining from described memory module the result of calculation of described Gama computing module, calculates.
3, Turbo decoder according to claim 2 is characterized in that, described memory module comprises:
First memory module is used to store the result of calculation when the described Gama computing module of front window;
Second memory module is used to store the result of calculation of the described Gama computing module of next window;
The 3rd memory module is used to store down the result of calculation of the described Gama computing module of two windows.
4, Turbo decoder according to claim 3 is characterized in that,
Described Bata training module is from described Gama computing module, perhaps obtains result of calculation when front window from described first memory module, calculates;
Described Alpha computing module obtains the result of calculation of the described Gama computing module of next window from described second memory module, calculate;
Described Bata computing module obtains down the result of calculation of the described Gama computing module of two windows from described the 3rd memory module, calculate.
5, Turbo decoder according to claim 4 is characterized in that, described Bata training module, Alpha computing module and the parallel processing of Bata computing module.
6, a kind of Trubo interpretation method is characterized in that, comprising: data ping-pong buffer unit is set and interweaves table ping-pong buffer unit;
When data table tennis buffer unit free time and data pang buffer unit take,,, generate and interweave table and deposit the table table tennis buffer unit that interweaves in according to data to decode length to data table tennis buffer unit input data to decode; Perhaps when data pang buffer unit free time and data table tennis buffer unit takies,,, generate and interweave table and deposit table pang the buffer unit that interweaves in according to data to decode length to data pang buffer unit input data to decode;
When there is data to decode in data table tennis buffer unit and the table table tennis buffer unit that interweaves stores when interweaving table accordingly, according to described the interweaving of table table tennis buffer unit storage that interweave showing the data to decode of described data table tennis buffer unit storage is carried out iterative computation, obtain decode results; Perhaps there is data to decode and table pang the buffer unit that interweaves stores when table of interweaving accordingly when data pang buffer unit, the data to decode of described data pang buffer unit being stored according to the described table that interweaves that interweaves the storage of table pang buffer unit carries out iterative computation, obtains decode results.
7, Turbo decoder for decoding method according to claim 6, it is characterized in that, described SISO unit comprises: Gama computing module, memory module, Bata training module, Alpha computing module, Beta computing module, described SISO unit are deciphered according to the described table iteration that interweaves that generates and are comprised:
The Gama computing module obtains described input data from described data ping-pong buffer unit, calculate result of calculation;
Described result of calculation is deposited in the memory module, perhaps and send to the Bata training module;
The Alpha computing module obtains the result of calculation of described Gama computing module from described memory module, calculate;
The Bata computing module obtains the result of calculation of described Gama computing module from described memory module, calculate.
8, Turbo decoder for decoding method according to claim 7 is characterized in that, described described result of calculation is deposited in the memory module comprises:
Three memory modules are set, comprise: first memory module, second memory module, the 3rd memory module;
The Gama computing module calculates the result of calculation when front window, deposits described result of calculation in described first memory module;
The Gama computing module calculates the result of calculation of next window, deposits described result of calculation in described second memory module;
The Gama computing module calculates the result of calculation of two windows down, deposits described result of calculation in described the 3rd memory module.
9, Turbo decoder for decoding method according to claim 8 is characterized in that, described Bata training module, Alpha computing module and Bata computing module obtain the result of calculation of described Gama computing module, calculates to comprise;
Described Bata training module is from described Gama computing module, perhaps gets result of calculation when front window from described first memory module, calculates;
Described Alpha computing module obtains the result of calculation of the described Gama computing module of next window from described second memory module, calculate;
Described Bata computing module obtains down the result of calculation of the described Gama computing module of two windows from described the 3rd memory module, calculate.
10, Turbo decoder for decoding method according to claim 9 is characterized in that, described Bata training module, Alpha computing module and the parallel processing of Bata computing module.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104767537A (en) * | 2015-03-19 | 2015-07-08 | 深圳市力合微电子股份有限公司 | Turbo decoding method for OFDM power line communication system |
| CN105634508A (en) * | 2015-12-21 | 2016-06-01 | 西安空间无线电技术研究所 | Realization method of low complexity performance limit approximate Turbo decoder |
| WO2017000682A1 (en) * | 2015-06-30 | 2017-01-05 | 深圳市中兴微电子技术有限公司 | Decoding method and apparatus and storage medium |
| CN113472478A (en) * | 2020-03-31 | 2021-10-01 | 广州海格通信集团股份有限公司 | Decoding front-end processing method, device, computer equipment and storage medium |
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2009
- 2009-03-26 CN CN2009101197730A patent/CN101515805B/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104767537A (en) * | 2015-03-19 | 2015-07-08 | 深圳市力合微电子股份有限公司 | Turbo decoding method for OFDM power line communication system |
| CN104767537B (en) * | 2015-03-19 | 2018-01-30 | 深圳市力合微电子股份有限公司 | A kind of Turbo interpretation methods for OFDM electric line communication systems |
| WO2017000682A1 (en) * | 2015-06-30 | 2017-01-05 | 深圳市中兴微电子技术有限公司 | Decoding method and apparatus and storage medium |
| CN106330206A (en) * | 2015-06-30 | 2017-01-11 | 深圳市中兴微电子技术有限公司 | Decoding method and device |
| CN105634508A (en) * | 2015-12-21 | 2016-06-01 | 西安空间无线电技术研究所 | Realization method of low complexity performance limit approximate Turbo decoder |
| CN105634508B (en) * | 2015-12-21 | 2019-03-26 | 西安空间无线电技术研究所 | A kind of implementation method of the Turbo decoder of the nearly performance limit of low complex degree |
| CN113472478A (en) * | 2020-03-31 | 2021-10-01 | 广州海格通信集团股份有限公司 | Decoding front-end processing method, device, computer equipment and storage medium |
| CN113472478B (en) * | 2020-03-31 | 2023-12-12 | 广州海格通信集团股份有限公司 | Decoding front-end processing method, decoding front-end processing device, computer equipment and storage medium |
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|---|---|
| CN101515805B (en) | 2011-07-06 |
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