CN108449090B - A Configurable Multi-Code Length and Multi-Rate LDPC Decoder - Google Patents

Abstract

A low-density parity check code LDPC decoder capable of configuring multiple code lengths and multiple code rates comprises a three-layer structure, wherein a top-layer module comprises an input soft information storage unit, an output soft information storage unit, a checksum storage unit, a decoding control unit, a macro definition unit and a core decoding unit; the core decoding layer module comprises an initialization unit, an iteration control unit, a variable information processing unit VPU, a check information processing unit CPU, an iteration information storage unit, a row logic connection unit, a column logic connection unit and a check unit; the check layer module comprises a check core unit and a check sum calculation unit. The decoder can realize flexible configuration of various code lengths and various code rates, can improve the throughput rate of the decoder, and is suitable for finishing the decoding work of the low-density parity check code LDPC with various code lengths and various code rates.

Description

A Configurable Multi-Code Length and Multi-Rate LDPC Decoder

technical field

The present invention relates to the field of communication technologies, and further relates to a low density parity check code LDPC (Low Density Parity Check Code) decoder capable of configuring multiple code lengths and multiple code rates in the field of wireless communication technologies. The present invention provides a low-density parity-check code LDPC decoder structure that can be configured with multiple code lengths and multiple code rates. The decoder under the structure is compatible with multiple code lengths and multiple code rates, and the code length codes The feature of flexible configuration of the rate is applicable to the decoding of low-density parity-check codes LDPC with various code lengths and various code rates.

Background technique

Low-density parity-check codes are a class of linear block codes with sparse check matrices proposed in the 1960s. Its bit error performance is very close to the Shannon limit, and it has the characteristics of flexible structure, relatively low decoding complexity and parallel operation, which is very suitable for hardware implementation. Therefore, it has been well developed in the field of channel coding and decoding in recent years. The code rate structure of low density parity check code LDPC is relatively flexible, and any code rate can be constructed. Therefore, it is particularly important for low density parity check code LDPC decoders compatible with different code lengths and different code rates to meet different service requirements.

The Institute of Microelectronics of the Chinese Academy of Sciences has disclosed a high-throughput low-density parity check in its patent document "An LDPC Decoder with High Throughput" (Patent Application No.: 200910081094.9, Application Publication No.: CN101854177A). code decoder. The decoder includes an input buffer, a check node operation unit, a variable node operation unit, an output buffer, a control logic unit and an interconnection network. Among them: the decoder adopts a partial parallel decoding structure, using x variable node operation units and y check node operation units, x and y are the number of columns and rows of the basic matrix of H, 1 input buffer, 1 output buffer. Each variable node operation unit is composed of a channel information accessor and an external information memory, and each check node operation unit is composed of an operation unit that calculates the input minimum value and the input second minimum value. The invention realizes simultaneous decoding input and output without increasing hardware consumption, thereby greatly improving the throughput rate of the decoder. The disadvantage of the decoder is that, first of all, the variable node calculation unit and the check node calculation unit used by the decoder only correspond to one check matrix structure, the code rate is single, and the requirements for different services , the decoder cannot meet the decoding requirements of multiple code lengths and multiple code rates. Secondly, the decoder does not encapsulate the extraction function of the check basis matrix parameters into a fixed module. When the code length changes, the code rate changes. Finally, the transplant of the decoder is difficult. Third, the partial parallel structure adopted by the decoder only solves the problem that the decoder of single code length and single code rate can improve its throughput while taking into account the lower consumption of hardware resources. , and is not suitable for multi-code length and multi-code rate decoders.

Huawei Technologies Co., Ltd. disclosed a patent document "Variable Code Length LDPC Code Encoding or Decoding Method and Device, and Encoder and Decoder" (application number CN200510012193.3, application publication number CN1017411396A) in its application. Variable code length low density parity check LDPC decoder. The decoder adopts a set of base index matrix storage units to store the base index matrix, and expands the base index matrix of each code length according to the expansion factor to obtain a check matrix, so as to achieve the purpose of variable code length. However, the decoder still has the disadvantage that although the decoder realizes the variable code length, it does not realize the variable code rate. Moreover, the decoder cannot use multiple code lengths and multiple code rates simultaneously in the same system.

SUMMARY OF THE INVENTION

The object of the present invention is to provide a configurable multi-code length, multi-code rate Low Density Parity Check Code LDPC (Low Density Parity Check Code) decoder structure for the shortcomings of the above-mentioned prior art. The decoder can realize the compatibility of multiple code lengths and multiple code rates, and can be flexibly configured with multiple code lengths and multiple code rates. Decoding of low-density parity-check codes (LDPC) with various code lengths and rates.

The decoder includes a three-layer structure of a top module, a core decoding layer module, and a check layer module; the top module includes a storage input soft information unit, a storage output soft information unit, a storage checksum unit, and a decoding control unit. , a macro definition unit, a core decoding unit; the core decoding layer module includes an initialization unit, an iteration control unit, a variable information processing unit VPU, a verification information processing unit CPU, an iteration information storage unit, a row logic connection unit, and a column logic unit. a connection unit, a verification unit; the verification layer module includes a verification core unit and a verification sum calculation unit;

The macro definition unit is used to store multiple check basis matrices and multiple standard expansion factors of the low density parity check code LDPC decoder corresponding to the code rate one-to-one, and all check basis matrices according to different standards The expansion factor is extended to obtain a check matrix corresponding to the code length; The standard expansion factor of the parity check code LDPC decoder to realize the configuration of the code length;

The core decoding unit adopts a partial parallel structure, and is used to complete the initialization, iterative decoding and verification work of the low-density parity-check code LDPC decoder;

The variable information processing unit VPU is used to update the variable information of the variable node. The variable information processing unit VPU has a total of 15 variable information processing unit VPU modules with the number of input ports, and the core decoding unit defines the check basis matrix input by the macro definition unit. The weight of each column is the benchmark, and the corresponding variable information processing unit VPU module is selected, and the core decoding unit is based on the maximum number of columns of the check basis matrix input by the macro definition unit, and the total number of the variable information processing unit VPU is selected;

The verification information processing unit CPU is used to update the verification information of the check node. The verification information processing unit CPU has a total of 15 types of verification information processing unit CPU modules with the number of input ports, and the core decoding unit inputs the macro definition unit. The weight of each row of the check base matrix is the benchmark, select the corresponding check information processing unit CPU module, the core decoding unit is based on the maximum number of rows of the check base matrix input by the macro definition unit, and select the check information processing unit CPU the total number of;

The iterative information storage unit includes an iterative information memory and an offset address generator, the offset address generator is used to generate read and write addresses of the iterative information memory, and the offset address generator utilizes the check basis matrix output by the macro definition unit The position information of the element is written in reverse order and read out sequentially to generate the read and write addresses of the iterative information memory.

Compared with the prior art, the present invention has the following advantages:

First, due to the macro definition unit of the present invention, it is possible to store multiple check basis matrices of the low density parity check code LDPC decoder corresponding to the code rate one-to-one, which overcomes the need for the decoder in the prior art. The variable node calculation unit and the check node calculation unit only correspond to one type of parity check matrix structure, and the problem of a single code rate enables the present invention to simultaneously decode low-density parity-check codes LDPC with multiple code rates.

Second, due to the macro definition unit of the present invention, a plurality of standard expansion factors of the low-density parity-check code LDPC decoder can be stored, and all check basis matrices are expanded according to different standard expansion factors to obtain a code equal to the length of the code. A corresponding parity check matrix overcomes the problem in the prior art that although the conversion of code lengths can be implemented, multiple code lengths cannot be used simultaneously in the same system, so that the present invention can decode low-density parity-check codes LDPC. Compatible with multiple code lengths.

Third, due to the macro definition unit of the present invention, multiple check basis matrices and multiple standard expansion factors of the low density parity check code LDPC decoder can be stored, and by replacing the input low density parity check code LDPC decoding The check basis matrix of the decoder can realize the configuration of different code rates. By changing the standard expansion factor of the input low-density parity-check code LDPC decoder, the configuration of different code lengths can be realized, which overcomes the problem of code length and code length in the prior art. The problem of difficulty in transplanting after rate change enables the multi-code length and multi-code rate of the low-density parity-check code LDPC decoder in the present invention to be flexibly configured.

Fourth, since the core decoding unit of the present invention adopts a partial parallel structure, the variable information processing unit VPU and the verification information processing unit CPU have modules with 15 types of input ports, and the variable information processing unit VPU with a large number of input ports. The module and the verification information processing unit CPU module are backward compatible with the variable information processing unit VPU module and the verification information processing unit CPU module with a small number of input ports, which overcomes the problems of multi-code length and multi-code rate in the prior art. The decoder improves its throughput while taking into account the problem of lower hardware resource consumption, so that the low density parity check code LDPC decoder in the present invention improves its throughput while taking into account lower hardware resource consumption.

Description of drawings

Fig. 1 is a three-layer structure diagram of the present invention.

Fig. 2 is a top-level module structure diagram of the present invention.

FIG. 3 is a structural diagram of a core decoding layer module of the present invention.

Detailed ways

The present invention will be further described below with reference to the accompanying drawings.

Referring to Fig. 1, the decoder structure of the present invention is further described, the decoder structure comprises a three-layer structure of a top module, a core decoding layer module, and a check layer module, and the overall structure of the decoder is divided by function , the top-level module is used to complete the timing and flow control of the decoder in the decoding process; the core decoding layer structure is used to complete the core iterative decoding work of the decoder; the check layer is used to complete the decoder verification Information calculation and storage work.

2, the top-level structure of the present invention is further described, the top-level module includes a storage input soft information unit, a storage output soft information unit, a storage checksum unit, a decoding control unit, a macro definition unit, and a core decoding unit. The decoding process of this decoder is: the decoding control unit sends the control instruction of starting decoding in the EMIF mapping signal to the storage input soft information unit, and the storage input soft information unit converts the serial initial soft information in the EMIF mapping signal Cache, and then provide it to the core decoding unit in parallel. The core decoding unit uses the various code length and code rate information provided by the macro definition unit to perform iterative decoding. After the iterative decoding is completed, the decoding control unit sends control commands respectively. For the storage output soft information unit and the storage checksum unit, the storage output soft information unit caches the parallel output soft information, and then outputs it serially; the storage checksum unit caches the checksum information, and outputs it after matching the timing sequence.

The macro definition unit is used to store multiple parity check basis matrices and multiple standard spreading factors of the low density parity check code LDPC decoder that correspond one-to-one with the code rate.

The check basis matrix and the standard expansion factor stored in the macro definition unit are further described in conjunction with the embodiment of the present invention. The macro definition unit of this embodiment realizes the compatibility of three code lengths, nine code rates, and three code rates. They are 1/2, 3/4, and 1/3 respectively; the check basis matrix corresponding to 1/2 code rate is mx0:

The check basis matrix corresponding to the 3/4 code rate is mx1:

The check basis matrix corresponding to 1/3 code rate is mx2:

Each of the above-mentioned three check base matrices is expanded according to 3 different standard expansion factors to obtain 9 check matrices corresponding to the code lengths one-to-one, realizing the compatibility of 9 code rates ,in:

The three different standard expansion factors corresponding to the first check basis matrix mx0 are z_faca:

z_faca = [26 40 90];

The three different standard expansion factors corresponding to the second check basis matrix mx1 are z_facb:

z_facb=[26 53 77];

The three different standard expansion factors corresponding to the third check basis matrix mx2 are z_facc:

z_facc = [22 24 90];

The 9 code rates obtained after expansion are the matrix mx:

By replacing the check basis matrix of the input low-density parity-check code LDPC decoder, the configuration of different code rates can be realized. configuration.

The macro definition unit first uses the input 3 check base matrices and 9 standard expansion factors to count various parameter information of the decoding core unit, specifically including: counting the number of rows, columns, maximum rows, The maximum number of columns, the number of non-1 elements, and the maximum number of non-1 elements information, wherein the number of rows of the three check basis matrices row=[8 15 16], the number of columns of the three check basis matrices col=[16 20 24], the maximum number of rows of the three check base matrices is 16, and the maximum number of columns is 24; the number of non-1 elements in the three check base matrices num=[50 59 83], three The number of non-1 elements in the check basis matrix is 83; then, the macro definition unit uses the input 3 check basis matrices and 9 standard expansion factors to construct 4 data tables, which are the column weight data table vpu_type , row weight data table cpu_type, column weight statistics table vpu_tn, row weight statistics table cpu_tn, the specific process is:

Count the column weight information of each column in the three check basis matrices separately, arrange the column weight information of each column in descending order, and take the maximum value of the column weight information of each column in the three check basis matrices and store it in the column weight data table. In vpu_type, vpu_type=[16 16 6 6 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2];

Calculate the row weight information of each row in the three check basis matrices separately, arrange the row weight information of each row in descending order, and store the maximum value of the row weight information of each row in the three check basis matrices in the column weight data table.

In vpu_type, cpu_type=[7 7 7 6 6 6 6 5 5 5 5 5 5 5 5 5];

Count the column weight information in the column weight data table vpu_type, store the column weight values that do not appear repeatedly in the first row of the column weight statistics data table vpu_tn, and store the number corresponding to each column weight value in the column weight statistics data. The second row of table vpu_tn, we can get

Count the row weight information in the row weight data table cpu_type, store the row weight values that do not appear repeatedly in the first row of the row weight statistics data table cpu_tn, and store the number corresponding to each row weight value in the row weight statistics data. The second row of the table cpu_tn, we can get

3, the core decoding layer structure of the present invention is further described, the core decoding layer module includes an initialization unit, an iteration control unit, a variable information processing unit VPU, a verification information processing unit CPU, and an iteration information storage unit, The row logic connection unit, the column logic connection unit, the check unit; the decoding process of the core decoding unit is: the initial soft information input in parallel from the top-level module is stored in the input soft information unit and stored in each initial information memory, respectively. The variable information processing unit VPU uses the respective initial soft information to attempt decoding, and inputs the decoding result to the verification unit for verification. If the checksum is 0, the decoding ends, otherwise the decoding soft information is connected by column logic. The unit is input into the iteration information storage unit, and the verification information processing unit CPU reads the variable information in the iteration information storage unit through the row logic connection unit to update the verification information. The verification information is input to the iterative information storage unit, and the iteration is repeated until the decoding is correct or the maximum number of iterations is reached, and finally the decoded soft information is output to the storage and output soft information unit of the top-level module in parallel, and the checksum information is output to the top-level module. The storage checksum unit.

The core decoding unit adopts a partial parallel structure, which is used to complete the initialization, iterative decoding and verification of the low density parity check code LDPC decoder;

The partial parallel structure adopted by the core decoding unit in the embodiment of the present invention means that the core decoding unit includes an initialization unit, a check unit, an iterative control unit, and 24 variable information processing units VPU working in parallel , 16 parallel work check information processing units CPU, 24 parallel work row logic connection units, 16 parallel work column logic connection units, 83 parallel work iterative information storage units, 24, 16, 83 are respectively The maximum number of columns, the maximum number of rows, and the maximum number of weights in the check basis matrix mx0, mx1, and mx2.

The variable information processing unit VPU is used to update the variable information of the variable node. The algorithm used by the variable information processing unit VPU to update the variable information of the variable node is not limited to a certain decoding algorithm based on belief propagation. The structure has good generality; the variable information processing unit VPU has a total of 15 variable information processing unit VPU modules with the number of input ports, each module has a unique number of input ports, the value of the number of input ports is set from [2, 16], the core The decoding unit selects the corresponding variable information processing unit VPU module based on the weight of each column of the check basis matrix input by the macro definition unit. In the embodiment of the present invention, the variable information can be selected according to the column weight statistical data table vpu_tn The type and quantity of the processing unit VPU, namely: select 2 variable information processing units VPU with 16 inputs, 2 variable information processing units VPU with 6 inputs, 1 variable information processing unit VPU with 5 inputs, and 4 variables with 3 inputs Information processing unit VPU, 15 variable information processing units VPU with 2 inputs; the variable information processing unit VPU module with a large input port number value is backward compatible with the variable information processing unit VPU module with a small input port number value, because the column weight statistics table vpu_tn stores the maximum value of the column weight in the three check basis matrices. Therefore, if the column weight value of the check basis matrix is less than the maximum column weight value, some input ports can be grounded to realize the variable information processing unit VPU module reuse. For example, the maximum column weight of the parity check matrix mx0 is 6. Therefore, when using a 1/2 code rate decoder, connect 10 pins of the 16-input variable information processing unit VPU module to ground, which can be used as 6-input The variable information processing unit VPU module.

The verification information processing unit CPU is used to update the verification information of the check nodes, and the algorithm used by the verification information processing unit CPU to update the verification information of the check nodes is not limited to a certain decoding algorithm based on belief propagation. ; The verification information processing unit CPU has a total of 15 verification information processing unit CPU modules with input port numbers, each module has a unique number of input ports, the number of input ports is set from [2, 16], and the core decoding unit is set to The weight of each row of the check basis matrix input by the macro definition unit is used as the benchmark, and the corresponding check information processing unit CPU module is selected. In the embodiment of the present invention, the check information processing unit CPU can be selected according to the row weight statistical data table cpu_tn Type and quantity, namely: select 3 7-input verification information processing unit CPU, 4 6-input verification information processing unit CPU, 9 5-input verification information processing unit CPU; input port number value is large The check information processing unit CPU module is backward compatible with the check information processing unit CPU module with a small number of input ports. Since the row weight statistics table cpu_tn stores the maximum value of the row weight in the three check basis matrices, if the If the row weight value of the test basis matrix is smaller than the maximum row weight value, some input ports can be grounded to realize the multiplexing of the CPU module of the verification information processing unit. For example, the maximum row weight of the check basis matrix mx1 is 4. Therefore, when using a 3/4 code rate decoder, grounding the 3 pins of the check information processing unit CPU module with 7 inputs can be used as 4 The input verification information is processed by the CPU module of the unit.

The iterative information storage unit includes an iterative information memory and an offset address generator, wherein the offset address generator is used to generate read and write addresses of the iterative information memory, and the offset address generator utilizes the elements in the check basis matrix output by the macro definition unit. The location information is written in reverse order and read sequentially to generate the read and write addresses of the iterative information memory. The advantage of building the offset address generator in the iterative information storage unit is that any variable information processing unit VPU, verification information processing unit When the unit CPU accesses the iterative information storage unit, there is no need to select an offset address, which can reduce logic resource consumption.

The row logic connection unit is used to select the corresponding total number of ports from the maximum number of rows of all check basis matrices input by the macro definition unit, and determine the logical connection mode between the check information processing unit CPU and the iteration information storage unit based on the total number of ports, The type and quantity used are corresponding to the type and quantity of the verification information processing unit CPU; in the embodiment of the present invention, three 7-port row logical connection units, four 6-port row logical connection units, and 9 row logical connection units are used. 5-port row logic connection unit.

The column logical connection unit selects the corresponding total number of ports from the maximum number of columns of all check basis matrices input by the macro definition unit, and determines the logical connection mode between the variable information processing unit VPU and the iterative information storage unit based on the total number of ports. The type and quantity of the VPU correspond to the type and quantity of the variable information processing unit VPU; in the embodiment of the present invention, two 16-port column logic connection units, two 6-port column logic connection units, and one 5-port column logic connection unit are used. Column logic connection unit, 4 3-port column logic connection units, 15 2-port column logic connection units.

The check layer module includes a check core unit and a checksum calculation unit.

The verification unit is used to complete the verification work of decoding, and performs decoding judgment on the soft information output by the variable information processing unit VPU each time. When the checksum is 0, the decoding is correct, and the iteration is stopped, otherwise the next iteration is continued. Decode until the maximum number of iterations is reached.

Claims (1)

1. a configurable multi-code length, multi-code rate low-density parity-check code LDPC decoder, is characterized in that, comprises the three-layer structure of top module, core decoding layer module, check layer module; Described The top-level module includes a storage input soft information unit, a storage output soft information unit, a storage checksum unit, a decoding control unit, a macro definition unit, and a core decoding unit; the core decoding layer module includes an initialization unit, an iteration control unit, a variable information processing unit VPU, a verification information processing unit CPU, an iteration information storage unit, a row logic connection unit, a column logic connection unit, and a verification unit; the verification layer module includes a verification core unit and a verification sum calculation unit; The macro definition unit is used to store multiple check basis matrices and multiple standard expansion factors of the low density parity check code LDPC decoder corresponding to the code rate one-to-one, and all check basis matrices according to different standards The expansion factor is extended to obtain a check matrix corresponding to the code length; The standard expansion factor of the parity check code LDPC decoder to realize the configuration of the code length; The core decoding unit adopts a partial parallel structure, and is used to complete the initialization, iterative decoding and verification work of the low-density parity check code LDPC decoder; the core decoding unit adopts a partial parallel structure means that the core The decoding unit includes 1 initialization unit, 1 check unit, 1 iteration control unit, m variable information processing units VPU working in parallel, n check information processing units CPU working in parallel, g rows working in parallel Logical connection unit, h column logical connection units working in parallel, k iteration information storage units working in parallel, m, n, k respectively represent the maximum number of columns, the maximum number of rows, and the maximum number of weights in all check basis matrices For the determined value, the values of g and m are equal, and the values of h and n are equal; The variable information processing unit VPU is used to update the variable information of the variable node. The variable information processing unit VPU has a total of 15 variable information processing unit VPU modules with the number of input ports, and the core decoding unit defines the check basis matrix input by the macro definition unit. The weight of each column is the benchmark, the corresponding variable information processing unit VPU module is selected, the core decoding unit is based on the maximum number of columns of the check basis matrix input by the macro definition unit, and the total number of variable information processing units VPU is selected; The information processing unit VPU has a total of 15 variables with the number of input ports. The information processing unit VPU module means that each module has a unique number of input ports. The number of input ports is set from [2, 16], and the variable with a large number of input ports The information processing unit VPU module is backward compatible with the variable information processing unit VPU module with a small number of input ports. Part of the input pins of the variable information processing unit VPU with a large number of input ports are grounded to replace the variable information with a small number of input ports. processing unit VPU; The verification information processing unit CPU is used to update the verification information of the check node. The verification information processing unit CPU has a total of 15 types of verification information processing unit CPU modules with the number of input ports, and the core decoding unit inputs the macro definition unit. The weight of each row of the check base matrix is the benchmark, select the corresponding check information processing unit CPU module, the core decoding unit is based on the maximum number of rows of the check base matrix input by the macro definition unit, and select the check information processing unit CPU The verification information processing unit CPU has a total of 15 verification information processing unit CPU modules with input port numbers, which means that each module has a unique number of input ports, and the number of input ports ranges from [2,16] Setting, the verification information processing unit CPU module with a large input port number value is backward compatible with the verification information processing unit CPU module with a small input port number value, and part of the input pins of the verification information processing unit CPU with a large input port number value Grounding to replace the verification information processing unit CPU with a small number of input ports; The iterative information storage unit includes an iterative information memory and an offset address generator, the offset address generator is used to generate read and write addresses of the iterative information memory, and the offset address generator utilizes the check basis matrix output by the macro definition unit The position information of the element is written in reverse order and read sequentially to generate the read and write addresses of the iterative information memory; The row logic connection unit is used to select the corresponding total number of ports from the maximum number of rows of all check basis matrices input by the macro definition unit, and determine the logic of the check information processing unit CPU and the iterative information storage unit based on the total number of ports. connection method; The column logical connection unit selects the corresponding total number of ports from the maximum number of columns of all check basis matrices input from the macro definition unit, and determines the logical connection mode between the variable information processing unit VPU and the iteration information storage unit based on the total number of ports ; The verification unit is used to complete the verification work of decoding, and performs decoding judgment on the soft information output by the variable information processing unit VPU each time. When the verification sum is 0, the decoding is correct, and the iteration is stopped, otherwise it continues. The next iteration is decoded until the maximum number of iterations is reached.

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