CN108449090B - LDPC decoder capable of configuring multiple code lengths and multiple code rates - Google Patents
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- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
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Abstract
A low-density parity check code LDPC decoder capable of configuring multiple code lengths and multiple code rates comprises a three-layer structure, wherein a top-layer module comprises an input soft information storage unit, an output soft information storage unit, a checksum storage unit, a decoding control unit, a macro definition unit and a core decoding unit; the core decoding layer module comprises an initialization unit, an iteration control unit, a variable information processing unit VPU, a check information processing unit CPU, an iteration information storage unit, a row logic connection unit, a column logic connection unit and a check unit; the check layer module comprises a check core unit and a check sum calculation unit. The decoder can realize flexible configuration of various code lengths and various code rates, can improve the throughput rate of the decoder, and is suitable for finishing the decoding work of the low-density parity check code LDPC with various code lengths and various code rates.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a low Density Parity Check code (LDPC) (Low Density Parity Check code) decoder capable of configuring multiple code lengths and multiple code rates in the technical field of wireless communication. The invention provides a low-density parity check code LDPC decoder structure capable of configuring multiple code lengths and multiple code rates, wherein a decoder under the structure has the characteristics of compatibility of multiple code lengths and multiple code rates, and flexible configuration of the code lengths and the code rates, and can be suitable for decoding low-density parity check codes LDPC with multiple code lengths and multiple code rates.
Background
Low density parity check codes are a class of linear block codes with sparse check matrices proposed in the 60's of the 20 th century. The error code performance of the method is very close to the Shannon limit, and the method has the characteristics of flexible structure, relatively low decoding complexity, parallel operation and the like, and is very suitable for hardware implementation. Therefore, the channel coding and decoding technology has been well developed in the field of channel coding and decoding in recent years. The code rate construction of the low density parity check code LDPC is flexible, and any code rate can be constructed, so that the low density parity check code LDPC decoder compatible with different code lengths and different code rates is particularly important for different service requirements.
The patent document "a high-throughput LDPC decoder" (patent application No. 200910081094.9, application publication No. CN101854177A) applied by the institute of microelectronics of Chinese academy of sciences discloses a high-throughput low-density parity-check code decoder. The decoder comprises an input cache, a check node operation unit, a variable node operation unit, an output cache, a control logic unit and an interconnection network. Wherein: the decoder adopts a partial parallel decoding structure, and uses x variable node operation units and y check node operation units, wherein x and y are the column number and the row number of a basic matrix of H, 1 input buffer and 1 output buffer respectively. Each variable node operation unit is composed of a channel information accessor and an external information memory, and each check node operation unit is composed of 1 operation unit for calculating an input minimum value and an input next minimum value. The invention realizes the simultaneous input and output of the decoding without increasing the hardware consumption, thereby greatly improving the throughput rate of the decoder. The decoder has the disadvantages that firstly, the variable node calculation unit and the check node calculation unit used by the decoder only correspond to a check matrix structure, the code rate is single, the decoder cannot meet the decoding requirements of the coexistence of multiple code lengths and multiple code rates for different services, secondly, the decoder does not package the extraction function of the check matrix parameters into a fixed module, when the code length and the code rate are changed, the decoder is difficult to transplant, and thirdly, the partial parallel structure adopted by the decoder only solves the problem of lower hardware resource consumption of the decoder with single code length and single code rate while improving the throughput rate of the decoder, and is not suitable for the decoder with multiple code lengths and multiple code rates.
The patent document "method and apparatus for encoding or decoding LDPC code with variable code length, and encoder and decoder" (application No. CN200510012193.3, application publication No. CN1017411396A) applied by huacheng technology limited discloses an LDPC decoder with variable code length for low density parity check codes. The decoder adopts a group of base index matrix storage units to store a base index matrix, and expands the base index matrix of each code length according to an expansion factor to obtain a check matrix, thereby achieving the purpose of variable code length. However, the decoder still has the disadvantage that the decoder realizes the variable code length and does not realize the variable code rate. Moreover, the decoder cannot use multiple code lengths and multiple code rates simultaneously in the same system.
Disclosure of Invention
The invention aims to provide a low-Density Parity Check code (LDPC) (Low Density Parity Check code) decoder structure capable of configuring multiple code lengths and multiple code rates, wherein the decoder under the structure can realize the compatibility of multiple code lengths and multiple code rates, the multiple code lengths and multiple code rates can be flexibly configured, the throughput rate of the decoder is improved, the lower hardware resource consumption is considered, and the decoder structure is suitable for completing the decoding work of the low-Density Parity Check code (LDPC) with multiple code lengths and multiple code rates.
The decoder comprises a top layer module, a core decoding layer module and a check layer module; the top module comprises a storage input soft information unit, a storage output soft information unit, a storage checksum unit, a decoding control unit, a macro definition unit and a core decoding unit; the core decoding layer module comprises an initialization unit, an iteration control unit, a variable information processing unit VPU, a check information processing unit CPU, an iteration information storage unit, a row logic connection unit, a column logic connection unit and a check unit; the checking layer module comprises a checking core unit and a checking sum calculating unit;
the macro definition unit is used for storing a plurality of check base matrices and a plurality of standard expansion factors of the low density parity check code LDPC decoder which are in one-to-one correspondence with the code rate, and expanding all the check base matrices according to different standard expansion factors to obtain check matrices in one-to-one correspondence with the code length; the configuration of different code rates is realized by replacing the check base matrix of the input low-density parity check code LDPC decoder, and the configuration of the code length is realized by replacing the standard expansion factor of the input low-density parity check code LDPC decoder;
the core decoding unit adopts a partial parallel structure and is used for finishing initialization, iterative decoding and check of the low-density parity check code LDPC decoder;
the variable information processing unit VPU is used for updating variable information of variable nodes, the variable information processing unit VPU has 15 variable information processing unit VPU modules with the number of input ports, the core decoding unit selects the corresponding variable information processing unit VPU module by taking each column weight of the check basis matrix input by the macro definition unit as a reference, and the core decoding unit selects the total number of the variable information processing unit VPUs by taking the maximum column number of the check basis matrix input by the macro definition unit as a reference;
the checking information processing unit CPU is used for updating checking information of the checking nodes, the checking information processing unit CPU has 15 kinds of checking information processing unit CPU modules with the number of input ports, the core decoding unit selects the corresponding checking information processing unit CPU module by taking the weight of each row of the checking base matrix input by the macro definition unit as a reference, and the core decoding unit selects the total number of the checking information processing unit CPU by taking the maximum row of the checking base matrix input by the macro definition unit as a reference;
the iteration information storage unit comprises an iteration information memory and an offset address generator, wherein the offset address generator is used for generating read-write addresses of the iteration information memory, and the offset address generator generates the read-write addresses of the iteration information memory by utilizing the position information of the check base matrix elements output by the macro definition unit in a mode of writing in a reverse order and reading out the sequence.
Compared with the prior art, the invention has the following advantages:
first, because the macro definition unit of the present invention can store a plurality of check basis matrices of the LDPC decoder, which are corresponding to the code rates one by one, the problem of a single code rate, which is caused by that the variable node calculation unit and the check node calculation unit used by the decoder in the prior art only correspond to one check matrix structure, is solved, so that the present invention can decode the LDPC codes of the low density parity check codes of a plurality of code rates at the same time.
Secondly, because the macro definition unit of the invention can store a plurality of standard expansion factors of the LDPC decoder, all the check base matrixes are expanded according to different standard expansion factors to obtain check matrixes corresponding to the code lengths one by one, the problem that although the code length can be changed in the prior art, a plurality of code lengths can not be used in the same system at the same time is solved, and the compatibility of the plurality of code lengths is realized when the LDPC decoder is used for decoding the low-density parity check code.
Thirdly, due to the macro definition unit, a plurality of check base matrixes and a plurality of standard expansion factors of the low density parity check code LDPC decoder can be stored, the configuration of different code rates is realized by replacing the check base matrix of the input low density parity check code LDPC decoder, the configuration of different code lengths is realized by replacing the standard expansion factor of the input low density parity check code LDPC decoder, and the problems of code length and difficult transplantation after code rate change in the prior art are solved, so that the multi-code length and multi-code rate of the low density parity check code LDPC decoder can be flexibly configured.
Fourthly, because the core decoding unit of the invention adopts a partial parallel structure, the variable information processing unit VPU and the check information processing unit CPU are respectively provided with 15 input port number modules, and the variable information processing unit VPU module with a large input port number value and the check information processing unit CPU module are downwards compatible with the variable information processing unit VPU module with a small input port number value and the check information processing unit CPU module, the problem that a decoder with multi-code length and multi-code rate in the prior art does not improve the throughput rate and simultaneously considers lower hardware resource consumption is solved, so that the LDPC decoder in the invention considers lower hardware resource consumption while improving the throughput rate.
Drawings
FIG. 1 is a three-layer structure of the present invention.
Fig. 2 is a top level module block diagram of the present invention.
FIG. 3 is a block diagram of the core decoding layer of the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
Referring to fig. 1, the decoder structure of the present invention is further described, where the decoder structure includes a three-layer structure of a top-layer module, a core decoding layer module, and a check layer module, the whole structure of the decoder is functionally divided, and the top-layer module is used to complete the timing sequence and flow control of the decoder in the decoding process; the core decoding layer structure is used for completing the core iterative decoding work of the decoder; the check layer is used for finishing the calculation and storage work of the decoder on the check information.
Referring to fig. 2, the top layer structure of the present invention is further described, where the top layer module includes a storage input soft information unit, a storage output soft information unit, a storage checksum unit, a decoding control unit, a macro definition unit, and a core decoding unit; the decoding process of the decoder is as follows: the decoding control unit sends a control instruction for starting decoding in the EMIF mapping signal to a storage input soft information unit, the storage input soft information unit caches serial initial soft information in the EMIF mapping signal and then provides the serial initial soft information to a core decoding unit in parallel, the core decoding unit carries out iterative decoding by using various code length and code rate information provided by a macro definition unit, after the iterative decoding is completed, the decoding control unit respectively sends the control instruction to a storage output soft information unit and a storage checksum unit, the storage output soft information unit caches parallel output soft information, and then the output soft information is output in series; and the storage checksum unit caches the checksum information and outputs the checksum information after matching the time sequence.
The macro definition unit is used for storing a plurality of check base matrixes and a plurality of standard expansion factors of the low-density parity check code LDPC decoder corresponding to the code rates one by one.
The check base matrix and the standard expansion factor stored in the macro definition unit are further described in combination with the embodiment of the invention, the macro definition unit of the embodiment realizes the compatibility of 3 code lengths and 9 code rates, and the three code rates are 1/2, 3/4 and 1/3 respectively; wherein the check basis matrix corresponding to the 1/2 code rate is mx 0:
3/4, the check matrix corresponding to the code rate is mx 1:
1/3, the check matrix corresponding to the code rate is mx 2:
expanding each check basis matrix in the 3 check basis matrices according to 3 different standard expansion factors respectively to obtain 9 check matrices corresponding to the code length one to one, and realizing compatibility of 9 code rates, wherein:
the 1 st check matrix mx0 has 3 different standard spreading factors z _ faca:
z_faca＝[26 40 90]；
the 2 nd check matrix mx1 has 3 different standard spreading factors z _ facb:
z_facb＝[26 53 77]；
the 3 rd check base matrix mx2 has 3 different standard spreading factors z _ facc:
z_facc＝[22 24 90]；
the 9 code rates obtained after the expansion are matrixes mx:
the configuration of different code rates is realized by replacing the check base matrix of the input low-density parity check code LDPC decoder, and the configuration of the code length is realized by replacing the standard expansion factor of the input low-density parity check code LDPC decoder.
The macro definition unit firstly uses the input 3 check basis matrices and 9 standard spreading factors to count various parameter information of the decoding core unit, and specifically includes: counting row number, column number, maximum row number, maximum column number, number of non-1 elements and maximum number information of non-1 elements of all the check base matrixes, wherein row number row of three check base matrixes is [ 81516 ], column number col of three check base matrixes is [ 162024 ], maximum row number of three check base matrixes is 16 and maximum column number is 24; the number num of non-1 elements in the three check matrix is [ 505983 ], and the number of non-1 elements in the three check matrix is 83; then, the macro definition unit constructs 4 data tables, namely a column weight data table vpu _ type, a row weight data table cpu _ type, a column weight statistical data table vpu _ tn and a row weight statistical data table cpu _ tn, by using the input 3 check matrixes and 9 standard spreading factors, and the specific process is as follows:
respectively counting the column weight information of each column in the 3 check base matrices, respectively arranging the column weight information of each column in a descending order, storing the maximum value of the column weight information of each column in the three check base matrices in a column weight data table vpu _ type, and obtaining vpu _ type ═ 1616663333222222222222222;
respectively counting the row weight information of each row in the 3 check base matrixes, respectively arranging the row weight information of each row in a descending order, and storing the maximum value of the row weight information of each row in the three check base matrixes in a column weight data table
In vpu _ type, cpu _ type ═ 7776666555555555;
counting the column weight information in the column weight data table vpu _ type, storing the column weight values which do not repeatedly appear in the first row of the column weight statistical data table vpu _ tn, storing the quantity corresponding to each column weight value in the second row of the column weight statistical data table vpu _ tn, and obtaining the column weight information
The line weight information in the statistic line weight data table cpu _ type stores the line weight values which do not repeatedly appear in the first line of the line weight statistic data table cpu _ tn, and stores the quantity corresponding to each line weight value in the second line of the line weight statistic data table cpu _ tn to obtain the line weight information
Referring to fig. 3, the core decoding layer structure of the present invention is further described, where the core decoding layer module includes an initialization unit, an iteration control unit, a variable information processing unit VPU, a check information processing unit CPU, an iteration information storage unit, a row logic connection unit, a column logic connection unit, and a check unit; the decoding process of the core decoding unit is as follows: initial soft information input in parallel from a soft information storage and input unit in a top module is respectively stored in each initial information memory, each variable information processing unit VPU performs trial decoding by using the respective initial soft information, a decoding result is input into a check unit for checking, if the check sum is 0, the decoding is finished, otherwise, the decoding soft information is input into an iteration information storage unit through a column logic connection unit, a check information processing unit CPU reads the variable information in the iteration information storage unit through a row logic connection unit for updating the check information, after the updating is finished, new check information is input into the iteration information storage unit through the row logic connection unit, the iteration is repeated in this way until the decoding is correct or the maximum iteration number is reached, and finally, the decoding soft information is output to a soft information storage and output unit of the top module in parallel, and outputting the checksum information to a storage checksum unit of the top module.
The core decoding unit adopts a partial parallel structure and is used for finishing initialization, iterative decoding and checking of the low-density parity check code LDPC decoder;
the partial parallel structure adopted by the core decoding unit in the embodiment of the invention means that the core decoding unit comprises 1 initialization unit, 1 check unit, 1 iteration control unit, 24 variable information processing units VPU working in parallel, 16 check information processing units CPU working in parallel, 24 row logic connection units working in parallel, 16 column logic connection units working in parallel and 83 iteration information storage units working in parallel, wherein 24, 16 and 83 are respectively the maximum column number, the maximum row number and the maximum weight number in check basis matrixes mx0, mx1 and mx 2.
The variable information processing unit VPU is used for updating variable information of the variable nodes, and an algorithm used when the variable information processing unit VPU updates the variable information of the variable nodes is not limited to a certain decoding algorithm based on belief propagation, so that the decoder structure has good universality; the variable information processing unit VPU has 15 kinds of variable information processing unit VPU modules with the number of input ports, each module has the unique number of input ports, the number value of the input ports is set from [2,16], the core decoding unit selects the corresponding variable information processing unit VPU module by taking each column weight of the check base matrix input by the macro definition unit as the reference, in the embodiment of the invention, the type and the number of the variable information processing unit VPU can be selected according to the column weight statistical data table VPU _ tn, namely: selecting 2 16-input variable information processing units VPU, 2 6-input variable information processing units VPU, 1 5-input variable information processing unit VPU, 4 3-input variable information processing units VPU and 15 2-input variable information processing units VPU; the variable information processing unit VPU module with the large input port quantity value is downward compatible with the variable information processing unit VPU module with the small input port quantity value, and the maximum value of the column weight in the three check base matrixes is stored in the column weight statistical data table VPU _ tn, so that some input ports can be grounded to realize multiplexing of the variable information processing unit VPU module if the column weight of the check base matrixes is smaller than the maximum column weight. For example, the maximum column weight of the check basis matrix mx0 is 6, and thus, when a decoder with a code rate of 1/2 is used, 10 pins of a variable information processing unit VPU module with 16 inputs are grounded, and the variable information processing unit VPU module with 6 inputs can be used.
The check information processing unit CPU is used for updating the check information of the check node, and the algorithm used when the check information processing unit CPU updates the check information of the check node is not limited to a certain decoding algorithm based on belief propagation; the check information processing unit CPU has 15 kinds of check information processing unit CPU modules with the number of input ports, each module has the unique number of input ports, the number value of the input ports is set from [2,16], the core decoding unit selects the corresponding check information processing unit CPU module by taking each row weight of the check base matrix input by the macro definition unit as the reference, in the embodiment of the invention, the type and the number of the check information processing unit CPU can be selected according to the row weight statistical data table CPU _ tn, namely: selecting 3 checking information processing units CPU with 7 inputs, 4 checking information processing units CPU with 6 inputs and 9 checking information processing units CPU with 5 inputs; the check information processing unit CPU module with the large input port quantity value is compatible with the check information processing unit CPU module with the small input port quantity value downwards, and the row weight statistical data table CPU _ tn stores the maximum value of the row weights in the three check base matrices, so that if the row weight value of the check base matrix is smaller than the maximum row weight value, some input ports can be grounded, and the multiplexing of the check information processing unit CPU module is realized. For example, the maximum row weight of the parity-check matrix mx1 is 4, and therefore, when a decoder with a code rate of 3/4 is used, 3 pins of the 7-input parity information processing unit CPU block are grounded and can be used as the 4-input parity information processing unit CPU block.
The iterative information storage unit comprises an iterative information memory and an offset address generator, wherein the offset address generator is used for generating read-write addresses of the iterative information memory, the offset address generator generates the read-write addresses of the iterative information memory by utilizing the position information of elements in the check base matrix output by the macro definition unit in a mode of writing in a reverse order and reading out the elements in the reverse order, and the offset address generator is built in the iterative information storage unit.
The row logic connection unit is used for selecting corresponding port total number from the maximum row number of all the check base matrixes input by the macro definition unit, determining a logic connection mode of the check information processing unit CPU and the iteration information storage unit by taking the port total number as a reference, and the used type and number of the logic connection mode correspond to the type and number of the check information processing unit CPU; in the embodiment of the present invention, 3 row logic connection units of 7 ports, 4 row logic connection units of 6 ports, and 9 row logic connection units of 5 ports are used.
The column logic connection unit selects corresponding port total number from the maximum column number of all check base matrixes input from the macro definition unit, determines a logic connection mode of the variable information processing unit VPU and the iteration information storage unit by taking the port total number as a reference, and the used type and number of the ports correspond to the type and number of the variable information processing unit VPU; in the embodiment of the present invention, 2 column logical connection units of 16 ports, 2 column logical connection units of 6 ports, 1 column logical connection unit of 5 ports, 4 column logical connection units of 3 ports, and 15 column logical connection units of 2 ports are used.
The check layer module comprises a check core unit and a check sum calculation unit.
The check unit is used for finishing check work of decoding, decoding judgment is carried out on the soft information output by the variable information processing unit VPU each time, when the check sum is 0, decoding is correct, iteration is stopped, otherwise, next iteration decoding is continued until the maximum iteration frequency is reached.
Claims (1)
1. A low-density parity check code LDPC decoder capable of configuring multiple code lengths and multiple code rates is characterized by comprising a three-layer structure of a top layer module, a core decoding layer module and a check layer module; the top module comprises a storage input soft information unit, a storage output soft information unit, a storage checksum unit, a decoding control unit, a macro definition unit and a core decoding unit; the core decoding layer module comprises an initialization unit, an iteration control unit, a variable information processing unit VPU, a check information processing unit CPU, an iteration information storage unit, a row logic connection unit, a column logic connection unit and a check unit; the checking layer module comprises a checking core unit and a checking sum calculating unit;
the macro definition unit is used for storing a plurality of check base matrices and a plurality of standard expansion factors of the low density parity check code LDPC decoder which are in one-to-one correspondence with the code rate, and expanding all the check base matrices according to different standard expansion factors to obtain check matrices in one-to-one correspondence with the code length; the configuration of different code rates is realized by replacing the check base matrix of the input low-density parity check code LDPC decoder, and the configuration of the code length is realized by replacing the standard expansion factor of the input low-density parity check code LDPC decoder;
the core decoding unit adopts a partial parallel structure and is used for finishing initialization, iterative decoding and check of the low-density parity check code LDPC decoder; the core decoding unit adopts a partial parallel structure, namely, the core decoding unit comprises 1 initialization unit, 1 check unit, 1 iteration control unit, m variable information processing units VPU working in parallel, n check information processing units CPU working in parallel, g row logic connection units working in parallel, h column logic connection units working in parallel and k iteration information storage units working in parallel, wherein m, n and k respectively represent numerical values determined by the maximum column number, the maximum row number and the maximum weight number in all check base matrixes, the values of g and m are equal, and the values of h and n are equal;
the variable information processing unit VPU is used for updating variable information of variable nodes, the variable information processing unit VPU has 15 variable information processing unit VPU modules with the number of input ports, the core decoding unit selects the corresponding variable information processing unit VPU module by taking each column weight of the check basis matrix input by the macro definition unit as a reference, and the core decoding unit selects the total number of the variable information processing unit VPUs by taking the maximum column number of the check basis matrix input by the macro definition unit as a reference; the variable information processing unit VPU module with 15 input port numbers in total means that each module has the unique input port number, the number value of the input port is set from [2,16], the variable information processing unit VPU module with the large input port number value is downward compatible with the variable information processing unit VPU module with the small input port number value, and part of input pins of the variable information processing unit VPU with the large input port number value are grounded to replace the variable information processing unit VPU with the small input port number value;
the checking information processing unit CPU is used for updating checking information of the checking nodes, the checking information processing unit CPU has 15 kinds of checking information processing unit CPU modules with the number of input ports, the core decoding unit selects the corresponding checking information processing unit CPU module by taking the weight of each row of the checking base matrix input by the macro definition unit as a reference, and the core decoding unit selects the total number of the checking information processing unit CPU by taking the maximum row of the checking base matrix input by the macro definition unit as a reference; the checking information processing unit CPU module with 15 input port numbers in total is characterized in that each module has the unique input port number, the number value of the input port is set from [2,16], the checking information processing unit CPU module with the large input port number value is downward compatible with the checking information processing unit CPU module with the small input port number value, and part of input pins of the checking information processing unit CPU with the large input port number value are grounded to replace the checking information processing unit CPU with the small input port number value;
the iteration information storage unit comprises an iteration information memory and an offset address generator, wherein the offset address generator is used for generating read-write addresses of the iteration information memory, and the offset address generator generates the read-write addresses of the iteration information memory by utilizing the position information of the check base matrix elements output by the macro definition unit in a mode of writing in a reverse order and reading out the sequence;
the row logic connection unit is used for selecting corresponding port total number from the maximum row number of all the check base matrixes input by the macro definition unit and determining a logic connection mode of the check information processing unit CPU and the iteration information storage unit by taking the port total number as a reference;
the column logic connection unit selects corresponding port total number from the maximum column number of all check base matrixes input from the macro definition unit, and determines a logic connection mode of the variable information processing unit VPU and the iteration information storage unit by taking the port total number as a reference;
and the check unit is used for finishing check work of decoding, performing decoding judgment on the soft information output by the variable information processing unit VPU each time, stopping iteration when the check sum is 0, and otherwise, continuing the next iteration decoding until the maximum iteration frequency is reached.
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