CN101047387B - Construction method of multi-code rate compatible LDPC code and its decoder - Google Patents
Construction method of multi-code rate compatible LDPC code and its decoder Download PDFInfo
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Abstract
A method for structuring multi-code rate compatible LDPC code includes carrying out sequencing from high to low as per code rate, distributing dimensionality in following to constraint conditions, using block-PEG algorithm to structure out H matrix of LDPC code with highest code rate, utilizing said matrix as reference to restructure H matrix with different code rate as per code rate order from high to low, making said restructuring obey on constraint conditions and setting zero element position in H matrix of high code rate LDPC code still to be zero element in H matrix of low code rate.
Description
Technical field
The present invention relates to a kind of channel coding technology, relate in particular to a kind of building method of multi-code rate compatible LDPC code, belong to areas of information technology.
Background technology
Channel coding technology is as the basic fundamental that guarantees the communication system reliable transmission, obtaining develop rapidly over past ten years, with Turbo code, LDPC sign indicating number (low density parity check code) is that the chnnel coding that large quantities of performances of representative can the approximation theory limit is found and obtains further investigation in succession, wherein the LDPC sign indicating number has especially obtained concern in recent years, in the formulation of every communication standard, it is extensively thought to replace Turbo code, becomes the main channel coding schemes of next generation communication system.Because actual communication systems often needs the chnnel coding of a plurality of speed to provide different error correcting capabilities for different channel conditions, in order to reduce the complexity of system, the receiver decoder of compatible a plurality of code checks must be considered.And as a kind of linear block codes, the flexibility of LDPC sign indicating number code rate adjustment is lower than turbo sign indicating number and convolution code.
The H matrix of LDPC sign indicating number must satisfy following three conditions:
1.H matrix is enough sparse, promptly the number of nonzero element is far smaller than the neutral element in the matrix;
2.H any two row of matrix have only one at the most at identical locational element ' 1 ';
3.H being listed in ' 1 ' on the same position, any two of matrix has only one at the most.
Wherein latter two condition is commonly called ranks constraints (RC-constraint).For a code length is n, and code check is the linear block codes of R, and the individual check digit of n (1-R) can be arranged, if its generator matrix is a full rank, and corresponding check digit of each check equations then.If limit each verification and must comprise k code element, each code element all must participate in j check equations, and k and j be constant, and then claiming such sign indicating number to collect is regular LDPC sign indicating number, is designated as (n, j, k) regular LDPC sign indicating number.
Except describing the LDPC sign indicating number, can also represent the formation of a LDPC sign indicating number with the mode of bipartite graph (Bipartite Graph) with the H matrix.As shown in Figure 1, be the bipartite graph of a LDPC sign indicating number, the node among the figure is divided into two types: following node is called variable node (Variable Node), and each variable node is corresponding with a code element of LDPC sign indicating number, so its number equals code length n; The node of top is called check-node (Check Node), and is corresponding with check equations, and its number is identical with the line number (=n (1-R)) of the check matrix H of sign indicating number.Variable node v
iWith check-node u
jBetween line represent and u
jContain and v in the corresponding j check equations
iI corresponding code element, promptly the capable i of j of H matrix classifies ' 1 ' as.
From the angle of graph theory, the node that connecting line arranged each other is adjoint point (Neighbor) each other, and the adjoint point quantity of a node is called the dimension (Degree) of this node.If from a node, through unduplicated limit, can get back to start node, then constitute a ring (cycle) through all limits on the path and node, the length of ring is defined as the limit number that comprises in the ring.The length of the shortest ring among the whole figure is called the girth (Girth) of figure.According to the ranks constraint of mentioning in the LDPC sign indicating number definition, 4 ring (cycle 4 free) length can not appear in the bipartite graph of LDPC sign indicating number is, and promptly the girth of the bipartite graph of LDPC sign indicating number is more than or equal to 6.
For regular LDPC sign indicating number, the dimension of the node of same type all is identical.But in the bipartite graph of irregular LDPC codes correspondence, the dimension of two types node is obeyed dimension distribution function separately respectively, and this distribution function retrains the dimension of each node on the whole.We can regard regular LDPC sign indicating number as is a kind of special circumstances of non-regular code.
The architectural characteristic of LDPC sign indicating number is the principal element of its performance of decision, and these architectural characteristics mainly comprise: the size of bipartite graph girth and the distribution of ring etc.Wherein the size of girth plays main effect, so it becomes a main measurement index in the LDPC sign indicating number construction process.
In bipartite graph, the decoding algorithm of LDPC sign indicating number---sum-product algorithm can be understood intuitively.As shown in Figure 2, at first, the soft information that each variable node obtains from channel with each bit starts iterative decoding algorithm as initial confidence level.Subsequently, the external information that each variable node comes according to the transmission of last iteration check-node is carried out and algorithm, and corresponding soft information is passed to the corresponding check node, if the first time iteration, then external information is set to 0; Each has the external information of the variable node of connection to check-node according to the soft information calculations that receives, and passes respectively.At last, variable node obtains discriminative information with all external informations and the addition of channel initial information, if court verdict meets the H MATRIX CHECK-UP, then stops decoding, otherwise carries out and algorithm, continues iteration, until reaching maximum iteration time.
Ldpc code decoder commonly used adopts and the similar structure of bipartite graph.Variable node and check-node are implemented as variable node unit (VNU) and check-node unit (CNU) in decoder, the sideline then is implemented as the connection data wire between VNU and the CNU.Finish in VNU with algorithm, integration method is finished in CNU, and external information is by the data wire transmission between VNU and the CNU.Along with the increase of interstitial content, numerous data wires will form the network of a complexity between VNU and the CNU, and the index increase along with the increase of interstitial content of its complexity.It has been generally acknowledged that code length surpasses after 1000 bits, utilizes existing technological means to realize that on hardware the bipartite graph structure of completely random is unable to do what one wishes.In order to simplify complexity, at the beginning of structure LDPC sign indicating number, just bipartite graph is configured to the form of accurate circulation (Quasi-Cyclic) usually.The most frequently used quasi-cyclic LDPC code is also referred to as displacement unit matrix LDPC sign indicating number, and its H matrix as shown in Figure 3.Whole H matrix is divided into the sub-piece of a plurality of identical sizes, and each sub-piece is filled with the unit matrix through cyclic shift, claims that usually filling process is a matrix permutation, and the unit matrix of cyclic shift then is called as permutation matrix.If the size of sub-piece is p * p, capable and n piece row of total m piece in the matrix, then the code length of this displacement unit matrix LDPC sign indicating number is np, code check is less than or equal to m/n.
If with symbol I representation unit matrix, the unit matrix that I (p) expression cyclic shift is p time, then replace the form of unit matrix LDPC sign indicating number shown in can being expressed as equivalently:
P wherein
X, yThe cyclic shift amount of representing the permutation matrix of the capable y row of x, therefore, the form shown in matrix shown in Figure 3 can be expressed as follows:
Displacement unit matrix LDPC sign indicating number also has following critical nature:
Character 1: any one length is that the ring of 2l can be expressed as in the displacement unit matrix LDPC sign indicating number
Illustrate: because all in the H matrix ' 1 ' all only are present in each permutation matrix, each bar limit of therefore encircling process all corresponds to a well-determined permutation matrix, so the path of loop process can identify with the permutation matrix of this loop process.
Character 2: the length that identifies in the character 1 is that the ring of 2l can be abbreviated as
Illustrate: each ring must be to be in delegation or same row through any two adjacent ' 1 ' in matrix, so the method for expressing of character 1 can be simplified.
Character 3: it is that the necessary and sufficient condition of 21 loop is that length appears in displacement unit matrix LDPC sign indicating number:
Wherein p represents the permutation matrix size.
At present, the method for transposition of structures unit matrix LDPC sign indicating number can be divided into two kinds of regular code and non-regular codes.For regular code, each height piece of H matrix is all replaced by the permutation matrix of non-zero, and the side-play amount of permutation matrix can obtain by the method for random search, also can determine by the method for algebraically, for example makes p
I, j=i * j; For non-regular code, the sub-piece of H matrix can also be filled by full null matrix except being filled by the displacement unit matrix, therefore before the side-play amount of determining each displacement unit matrix, needs at first to determine the position of each displacement unit matrix.So for non-rule displacement unit matrix LDPC sign indicating number, its constitution step is divided into two usually, at first determines the position of each non-zero permutation matrix, and then determines its side-play amount.Block-PEG algorithm for example, at first utilize the thinking of PEG algorithm, the maximization loop, determine the position of each non-zero permutation matrix, and then reject according to the condition of character 3 can not selecteed side-play amount, and in remaining side-play amount, carry out random choose, finish the construction process of whole displacement unit matrix LDPC sign indicating number.
In the system of reality, adopt systematic code usually, that is, the information bit and the check bit of each coding codeword clearly separated.The check matrix H of systematic code correspondingly also can be divided into syndrome matrix and information submatrix two parts, encodes for convenience, usually the verification submatrix is defined as next-door neighbour's double diagonal line form.
VNU and CNU number that displacement unit matrix ldpc code decoder needs greatly reduce, and the cost of paying then is the degree of parallelism that has reduced decoding algorithm, and some results of intermediate calculations need be stored among the RAM.A sub-piece of non-zero in the corresponding H matrix of each RAM among Fig. 5.The then corresponding one group of data wire that connects CNU and VNU of the sub-piece of each non-zero, each CNU is responsible for the long-pending computing of one group of check-node in the bipartite graph, each VNU is responsible for one group of variable node in the bipartite graph and computing.
At present, the method for the LDPC sign indicating number of realization multi code Rate of Chinese character compatibility mainly is divided into following three kinds.The firstth, the method for punching (puncture).The LDPC sign indicating number that this method at first constructs a low code check removes the part check bit by cutter then, obtains the LDPC sign indicating number of high code check.The advantage of this method is, the LDPC sign indicating number of the different code checks of receiving terminal can shared same decoder, and it is simple flexibly to operate, and shortcoming is the LDPC sign indicating number code length difference of different code checks, and for finite length, the multi code Rate of Chinese character LDPC code performance that obtains of punchinging is often unsatisfactory.Second method then is the LDPC sign indicating number of at first constructing a high code check, reaches the purpose of regulating code check by cutting the short message bit length then.The advantage of the multi-code rate compatible LDPC code that this method obtains with punching similarly, the LDPC sign indicating number of a plurality of code checks can use same decoder, shortcoming is the code length random length, and along with the shortening of code length, performance loss is serious.The third method is a kind of method of unifying to design, and this also is the most frequently used a kind of method.It is primarily aimed in the constant situation of different code check code lengths, claims also that therefore the multi-code rate compatible LDPC code that obtains is the CBMR-LDPC sign indicating number.This method is at first designed a special low code rate LDPC code H matrix, by merging specific row in the H matrix, reaches the purpose that obtains high code rate LDPC code then.As shown in Figure 6, at first construct the LDPC sign indicating number H matrix of one 1/2 code check, merge in twos by row then, obtain the LDPC sign indicating number H matrix of one 3/4 code check the H matrix.
Obviously, keep under the constant condition of code length, the LDPC sign indicating number of different code checks has different H matrixes, so LDPC sign indicating number of different code checks, its corresponding bipartite graph structure may be different fully, corresponding decoder architecture, and especially big variation also will take place in the structure of data wire network.If a decoder needs compatible multi code Rate of Chinese character LDPC sign indicating number, it just must have the ability of switching between the different pieces of information spider lines so, and this realizes having brought very big difficulty to hardware.
In order to simplify this difficulty, when structure CBMR-LDPC sign indicating number, below two criterions need be observed:
Criterion 1: the variable node dimension of the LDPC sign indicating number of different code checks distributes and keeps identical;
Criterion 2: each row of high code rate LDPC code H matrix comes from two row or the more stacks of multirow of lowest bit rate LDPC sign indicating number H matrix.
Adopt after the above-mentioned criterion, the contact between the LDPC sign indicating number bipartite graph of two code checks of height as shown in Figure 7.Decoder carries out different code checks when switching, and the CNU of high code check decoder only needs two CNU that will hang down the code check decoder to merge, and the data wire network need not to change.Simultaneously, because the dimension of variable node does not change, when carrying out the code check switching, all VNU need not to take place any variation.
The advantage of CBMR-LDPC sign indicating number is that the LDPC sign indicating number code length of different code checks remains unchanged, and the hardware that is suitable for ldpc code decoder is realized; Shortcoming is, when the row to the H matrix merges in twos, will cause a large amount of becates to occur, and will inevitably reduce the performance of high code rate LDPC code.The second, be 4 ring for fear of length after merging, occurring, when this method is hanged down code check H matrix at structure, also need be with respect to the structure of high code rate LDPC code H matrix.This makes the complexity of construction algorithm sharply increase along with increasing of code check number.The 3rd, method requires the H rectangular array distribution of weight of all code checks to remain unchanged, and this has increased difficulty to the structure of low code check H matrix equally, seeks all best column weight amount distribution of a multi code Rate of Chinese character and also causes algorithm complex to increase.
Summary of the invention
Present situation at present multi code Rate of Chinese character LDPC code constructing method, in order to realize reaching balance between difficulty and the complex structure degree, the present invention proposes the constraints of new structure non-regular permutation matrix fixed length multi code Rate of Chinese character LDPC sign indicating number and provided the method for constructing multi code Rate of Chinese character LDPC sign indicating number.This method comprises following three key steps:
1. the parameter of initialization multi-code rate compatible LDPC code: determine the dimension distribution function of code length N, the highest code check H matrix, the big or small p and the code check sequence R of each height piece of H matrix
1, R
2, R
3..., R
i..., R
tWherein t is the code check number that communication system is determined according to actual needs, and i represents the sequence number of H matrix, is the integer of 1～t, and sub-block size p must be able to be divided exactly positive integer sequence N, N (1-R
1), N (1-R
2) ..., N (1-R
i) ..., N (1-R
t);
2. adopt the Block-PEG algorithm construction to go out the highest code rate LDPC code H matrix, as female battle array of multi-code rate compatible LDPC code;
3. based on female battle array, according to code check order from high to low, determine the dimension distribution function of each code check H matrix, the LDPC sign indicating number H matrix of the different code checks of reconstruct, wherein, the dimension distribution function must satisfy constraints: the dimension of each variable node of low code rate LDPC code is not more than the dimension of high code rate LDPC code relevant variable node; Restructuring procedure must satisfy constraints: 0 element position still is 0 element in low code rate LDPC code H matrix in the high code rate LDPC code H matrix.
Wherein, in step 1, what at first need to determine is parameters such as code length, code check, and then the size of each height piece of definite H matrix, and what determine at last is the dimension distributed constant of the highest code check H matrix.Step 1 can be finished step by step by following three:
1-1, according to the needs of different communication systems, in conjunction with actual definite code length and code check parameter, the selection of code length and code check parameter does not have more constraints.For the convenience of follow-up explanation, the code length that makes multi-code rate compatible LDPC code is N, and compatible code check is followed successively by R from high to low
1, R
2..., R
i..., R
t, the H matrix that obtains each code check is respectively H
1, H
2..., H
i..., H
t, the line number that each matrix has is M
1, M
2..., M
i..., M
t, M is obviously arranged
1＜M
2＜...＜M
t1-2 is according to the sub-block size p of code length and the definite H matrix of code check distribution.For the sub-block size of each code check H matrix is consistent, must select positive integer N, N (1-R according to each code check H matrix size
1), N (1-R
2) ..., N (1-R
t) greatest common factor as the big or small p of sub-piece.If greatest common factor is 1, return step 1-1 so, adjust code length N, make that greatest common factor is a suitable size.If greatest common factor is excessive, so according to the needs of system, adjust p to less numerical value of sub-block size, p must can be divided exactly N.According to p, obtain N=np, M
1=m
1P, M
2=m
2P ..., M
i=m
iP ..., M
t=m
tP, each H matrix can be divided into m
i* n size is the sub-piece of p * p, and wherein i represents the sequence number of H matrix, is the integer of 1～t;
1-3, the dimension distribution function of the highest definite code check H matrix.
3-1, the sequence number with i represents current H matrix of constructing makes i=1;
3-2，i＝i+1；
3-3, statistical matrix H
I-1The weight of each piece row is noted the position of each row neutral element;
3-4, structural matrix H
iCorresponding bipartite graph, the capable corresponding check-node of each piece, the corresponding variable node of each piece row, the order of magnitude of the weight in every sideline equals the side-play amount size of the corresponding displacement unit matrix of H matrix, then weight is taken as negative value when the sideline originates in check-node, when originating in variable node, weight be taken as on the occasion of; Wherein, described weight is defined as: if the weight absolute value is u, then weight:
Because sideline itself does not have direction, therefore the starting point here refers to the starting point when a certain paths is through this edge line in the bipartite graph.For example, according to above-mentioned definition, can with the matrix notation of giving an example in the prior figures 3 bipartite graph form shown in Figure 5 just;
3-5, the initialization bipartite graph adds m
iThe individual check-node that does not have any connection, and according to the capable sequence number of the piece in the H matrix with its ordering for c
1, c
2..., c
Mi, each check-node representing matrix H wherein
iA piece capable, as shown in Figure 9;
3-6 is with m
iIndividual check-node is divided into three part: C
1, C
2And C
3, C wherein
1Comprise matrix H
I-1In, with current variable node have direct-connected check-node; C
2Comprised that then sequence number is m
I-1+ 1 to m
iCheck-node; C
3Then be to remove C
1And C
2Outside the residue check node.
Obviously, C
1The serial number range 1 to m of the check-node that comprises in the set
I-1, be a last code check R
I-1A part of check-node in the corresponding bipartite graph, and C
2What comprise then is because code check reduces matrix H
iCorresponding bipartite graph is with respect to H
I-1The check-node that increases newly in the bipartite graph.
3-7 adds variable node one by one in bipartite graph, each variable node is represented matrix H
iPiece row, and select C for each variable node
1With C
2In be connected with root node distance check-node farthest, described distance check-node farthest is meant when tree-shaped being deployed into of bipartite graph comprised C just
1With C
2During all check-node, the last in the figure C that occurs
1With C
2In check-node, if there are a plurality of check-nodes to meet the requirements, preferentially select C
1In node, if a plurality of C are arranged
1In node meet the requirements, then select one of them at random.Concrete steps are as follows:
A. be that root node is done tree-shaped expansion to bipartite graph with current variable node, as shown in figure 10; Need to prove that the dendrogram here is not proper tree, each node occurs and only appears at apart from the nearest position of root node, so the ring in the bipartite graph still exists in tree-shaped expanded view.
B. judge whether all m
iIndividual check-node is all in tree: if then enter step C; If check-node is arranged outside tree, then enters step D;
Wherein, if all m
iIndividual check-node all appears in the dendrogram, illustrates that then check-nodes all in the bipartite graph all is communicated with root node, and connect with any one check-node this moment, all will cause ring of new appearance in the bipartite graph.In order to make the girth maximum of this ring, will choose with root node distance check-node farthest and connect.And have check-node outside dendrogram, to refer to, and when dendrogram was deployed into the L layer, the variable node that all check-node of this layer are adjacent had all appeared in the dendrogram, and the check-node number that this moment, dendrogram comprised is less than m
iIndividual, then explanation has check-node and current root node to be in unconnected state.
C. seek C
1With C
2In with root node distance check-node farthest, form set C, preferentially select C
1In node, with connecting between select check-node and the root node, enter step e.
So-called distance is deployed into L-1 layer fashion and does not travel through C if refer to dendrogram farthest
1With C
2In all check-nodes, and C during to the L layer
1With C
2In all check-nodes all be comprised in dendrogram and suffered, the emerging check-node of L layer is exactly to need the distance check-node farthest sought so.
D. the outer check-node of order tree is formed set C ', if C ' and C
1Perhaps C
2Common factor all be empty set, enter step C so, otherwise minimum check-node and the root node of dimension of random choose connects from occur simultaneously.
E. travel through from root node to step C or check-node that D picks out the path, calculate the weight accumulated value s in the sideline of these path processes;
Wherein, if path is 2l, then weight accumulation
F. ask for weight absolute value candidate collection X={x| (s-x) modp ≠ 0,0≤x＜p}.If the check-node that above-mentioned steps C or D pick out has appeared in the dendrogram, after root node connects with it so, a loop to newly occur in the bipartite graph, the last item sideline starting point of this loop process is exactly the check-node that step C or D pick out.If establishing the weight absolute value in this sideline is x, the weight accumulation of loop just equals s-x so.Character according to displacement unit matrix LDPC sign indicating number, the necessary and sufficient condition that an equal length loop appears in bipartite graph is (s-x) mod p=0, just can avoid the ring that appearance equates with new loop-length in the bipartite graph in the H matrix as long as therefore can guarantee weight absolute value x eligible (s-x) modp ≠ 0.So the candidate collection of weight absolute value is defined as X={x| (s-x) modp ≠ 0,0≤x＜p}.
G. from the set of candidate's weight, pick out suitable weight absolute value and give newly-established sideline.The method of determining suitable weight absolute value has two kinds, and the one, random choose from candidate's weight absolute value set can guarantee the randomness of H matrix so to a certain extent, and enough simply; The 2nd, at first from candidate's weight absolute value set X, pick out absolute value set Y, satisfied (s-y) mod p of all the numerical value y among the Y and p are coprime, select the weight absolute value of a numerical value as the sideline again from Y at random.If set Y is empty, so just select a numerical value z from X, the common factor minimum of feasible (s-z) mod p and p, this a kind of method can be guaranteed each emerging loop girth maximum.
H. the current dimension of the check-node picked out of root node and step C or D adds 1;
3-8 judges whether to set up for current variable node and meets distribute all connections of needs of dimension, if not then return step 3-6, otherwise enters step 3-9;
3-9 checks whether to have added all n variable node, if not then return step 3-7, otherwise enters step 3-10;
Whether 3-10 judges r less than t, if then structure finishes, otherwise enters step 3-2.
Than the CBMR-LDPC sign indicating number, the complexity of building method provided by the invention is lower.From the constraints that dimension distributes, the present invention has provided a more loose dimension distribution constraints, and the dimension of greatly simplifying multi code Rate of Chinese character LDPC sign indicating number distributes and searches for difficulty.As long as determined that the LDPC sign indicating number variable node dimension of high code check distributes, just can this dimension be distributed as constraints, can search for the dimension distribution of each code check easily.Constraints from reconstruct, the criterion of observing with the CBMR-LDPC sign indicating number 2 is opposite, constraints of the present invention requires the LDPC sign indicating number H matrix of high code check of structure at first, and be initial matrix with this matrix, it is expanded to low code check H matrix size, and the position of wherein nonzero element is reconstructed, obtain the LDPC sign indicating number H matrix of low code check, make the H matrix of each code check not needed whole all matrix loops of considering, greatly reduced complexity by relatively independent structure.The main-process stream of the method for structure multi-code rate compatible LDPC code provided by the invention as shown in Figure 8.
Similarly, the method for the method of fixed length multi code Rate of Chinese character permutation matrix LDPC systematic code and above-mentioned fixed length multi code Rate of Chinese character permutation matrix LDPC nonsystematic code is similar.When a linear block codes was systematic code, its H matrix can be divided into check bit submatrix part and information bit submatrix part very significantly.Usually, we partly are specified to a specific forms with the check bit submatrix, and then the information bit submatrix is constructed.For above-mentioned building method, if transposition of structures matrix L DPC systematic code just need be defined as the initial condition of bipartite graph the initial configuration of check bit submatrix, and then according to original algorithm, the information bit submatrix be constructed.Be that building method mainly is divided into two stages, the phase I is according to the check bit submatrix initialization bipartite graph of precognition; Second stage tectonic information bit submatrix part.
In the phase I, the m that each check bit submatrix is comprised at first
iIndividual variable node and all check-nodes are arranged in " it " font formula, as Figure 11 (indicating the variable node of the corresponding check bit submatrix of variable node of p among the figure).Can either guarantee to have between the check bit verification relation like this, can guarantee in the bipartite graph acyclic again.Simultaneously, the weights in all sidelines all are changed to 0 in the bipartite graph, all filled by unit matrix with the sub-piece of all non-zeros that guarantees the syndrome matrix, and the leading diagonal all elements all are 1 that such structure can reduce the encoder complexity of systematic code.After the syndrome matrix is carried out above-mentioned arrangement, because only having with last check-node, last variable node of syndrome matrix is connected, therefore all check bits of a sub-piece correspondence in the syndrome matrix lower right corner have all only been participated in a check equations, as Figure 12, such structure is with the performance of severe exacerbation sign indicating number, so a non-null matrix is filled in the upper right corner at the check bit submatrix, this non-null matrix be unit matrix right side cyclic shift p-1 time of p * p by size, and the first capable nonzero element is adjusted into 0 obtains.For fear of length occurring is 4 ring, and makes bipartite graph loop maximum, and the submatrix side-play amount that this sub-piece is filled is chosen as greater than 0 arbitrary value less than p.In order to guarantee carrying out smoothly of systematic code coding, again this sub-piece first capable element 1 is replaced with 0, in fact not loop appearance in the syndrome matrix like this.The check bit submatrix that finally obtains partly has bipartite graph structure as shown in figure 13, there is and only have the element ' 1 ' of delegation to be replaced by ' 0 ' in this sub-piece of the meaning representation of dotted line among the figure, the line position that is replaced can be selected arbitrarily, wherein each variable node correspondence of bipartite graph all is piece row of H matrix, each check-node correspondence all be that a piece of H matrix is capable, the special submatrix that is filled at last is owing to be not a complete unit matrix, therefore its line is marked as dotted line, and the sub-piece form of its correspondence is as follows:
Check bit submatrix such as Figure 14 of finally obtaining.
Because the check bit submatrix of each code check has partly kept block characteristic, and constructed the maximized bipartite graph of loop in the phase I, therefore in second stage, the building method of their information bit submatrix parts separately can follow corresponding step in the method for constructing nonsystematic code fully.
Another object of the present invention is to provide the ldpc code decoder of the multi code Rate of Chinese character compatibility that adapts with said method.This decoder structurally only needs existing solid size rate decoder is done a little change, obtains fixed length multi code Rate of Chinese character LDPC sign indicating number in conjunction with the said method structure, just can realize the purpose of multi code Rate of Chinese character compatibility.Figure 15 is the structured flowchart of this decoder:
As shown in figure 15, be the structural representation of decoder.Decoder comprises: control module (Controller), variable node computing unit (VNU), check node calculation unit (CNU) and external information memory (Memory).Wherein, control module is used to control the sequential logic of whole decoder; The external information memory is used for storing the external information that iterative decoding process calculates, and its size depends on the size of each piecemeal in the H matrix and the number of piecemeal; The variable node computing unit be used to realize the ldpc decoder minimum-sum algorithm with the algorithm computing, and rule out each bit output, use for the check-node unit; The check node calculation unit is used for realizing the computing of asking for minimum value of ldpc decoder minimum-sum algorithm, and the check results of output verification equation.Be connected by one group of data wire respectively between control module and CNU and the VNU, and then be connected between the external information memory by one group of read-write control signal line.Connect by one group of line that reads and writes data between each CNU and the external information memory.Connect by one group of line that reads and writes data between each VNU and the external information memory.The characteristics of the decoder of compatibility of multi-rate of the present invention are the design of external information memory, the external information memory is that the RAM of p quantization width forms by a series of sizes, wherein a part of RAM has multiport and connects, be connected simultaneously on a plurality of CNU, read and write by different CNU when different code checks, wherein: p represents code length N, code check sequence R
1, R
2, R
3..., R
tThe size of each height piece of H matrix, p can be divided exactly positive integer sequence N, N (1-R
1), N (1-R
2) ..., N (1-R
t), t is the code check number that communication system is determined according to actual needs.
Technique effect of the present invention is that above-mentioned building method obtains multi code Rate of Chinese character LDPC sign indicating number and compares with the CBMR-LDPC sign indicating number, has the advantage that structure is simpler, the hardware implementation complexity is not high, code performance is more superior.This mainly be because the CBMR-LDPC sign indicating number at structure during high code rate LDPC code, the line number in the low code check H matrix of merging is too much, has formed a large amount of becates, has reduced the error performance of LDPC sign indicating number; This algorithm must be considered the constraint of each code check simultaneously when structure lowest bit rate LDPC sign indicating number simultaneously, and the code check number that can construct can not be too many, and algorithm complex is too high.Simultaneously, the multi-code rate compatible LDPC code of new method construct performance with single code rate LDPC code on performance is almost completely identical, and the floating-point simulation result as shown in figure 16.
Simultaneously, in construction process, it only is the position of permutation matrix has been subjected to the multi code Rate of Chinese character condition when selecting constraint, therefore the multi code Rate of Chinese character LDPC sign indicating number that obtains of neotectonics method, side-play amount selection course and single code rate LDPC code of each permutation matrix are identical, that is to say with once constructing the same permutation matrix choice of location result who obtains, can be applicable to the parameter of different permutation matrix sizes simultaneously, this makes this method can construct the multi code Rate of Chinese character LDPC sign indicating number that code length changes flexibly, these many code lengths multi code Rate of Chinese characters LDPC sign indicating number can be in the realization of the enterprising row decoder of same FPGA platform, compare with the CBMR-LDPC sign indicating number, complexity of the present invention is obviously lower, and performance is obviously better.
At last, design of encoder and implementation that the present invention proposes have following two main characteristics: realized in the first decoder that some have the RAM of particular interface, difference along with code check, control by different CNU, both saved storage resources, and can on solid size rate decoder basis, only realize the ldpc code decoder of multi code Rate of Chinese character compatibility again by little change.Second main feature of implementation is that the external information memory cell of the decoder RAM according to the maximum length code rate need be provided with, just fixed length multi-code rate compatible LDPC code decoder can be improved to a kind of multi-code rate compatible LDPC code decoder that different code length changes that adapts to, when between different code length, switching, only need to change the maximum read-write degree of depth of RAM.
Description of drawings
Fig. 1 is the schematic diagram that LDPC sign indicating number bipartite graph is represented;
Fig. 2 is a LDPC sign indicating number decoding schematic diagram;
Fig. 3 is a displacement unit matrix LDPC sign indicating number H matrix schematic diagram;
What Fig. 4 was based on piece has a weight bipartite graph;
Fig. 5 is the ldpc code decoder schematic diagram of using always;
Fig. 6 is a CBMR-LDPC sign indicating number H matrix construction schematic diagram;
Fig. 7 is that the CBMR-LDPC code decoder is realized schematic diagram;
Fig. 8 is the flow chart of non-regular permutation matrix LDPC code building method;
Fig. 9 is to be the initialized bipartite graph of unit with the piece;
Figure 10 represents that with current variable node be the schematic diagram that root node is done tree-shaped expansion;
Figure 11 is the initial bipartite graph of systematic code;
Figure 12 is a systematic code check bit submatrix general knowledge structural representation;
Figure 13 is the bipartite graph through the systematic code check bit submatrix of optimizing;
Figure 14 is the systematic code check bit submatrix schematic diagram through optimizing;
Figure 15 is the structural representation of decoder;
Figure 16 is a bit error rate floating-point simulation performance correlation curve;
Figure 17 is the initial bipartite graph of each code check systematic code of 8064 bits;
Figure 18 is a H matrix relationship schematic diagram between the different code checks
Figure 19 is multi-code rate compatible LDPC code RAM and computing unit connection diagram
Figure 20 is decoder control module hardware realization figure;
Figure 21 is variable node unit hardware realization figure;
Figure 22 is check-node unit hardware realization figure;
Figure 23 is decoder control module input-buffer submodule hardware realization figure;
Figure 24 is decoder control module sequencing control submodule hardware realization figure;
Figure 25 is decoder control module output buffers submodule hardware realization figure;
Embodiment
Below by embodiment, further specify the present invention in conjunction with the accompanying drawings, but the scope that does not limit the present invention in any way.Embodiment 1: the non-regular multi code Rate of Chinese character permutation matrix LDPC code of structure fixed length
The following specifically describes and utilize building method of the present invention, constructing a code length is 8064 bits, and code check is the process of 7/8,3/4,1/2 multi code Rate of Chinese character LDPC systematic code:
Step 3: utilize Block-PEG algorithm construction code check R
1The H matrix H of=7/8 correspondence
1
Step 4: statistics H
1The weight of each piece row in the matrix is as H
2The dimension of matrix information bit part distributes.
Step 5:, can obtain code check R according to the result of calculation of front
2=3/4 o'clock, piece row in the actual corresponding H matrix of each variable node in the bipartite graph, a piece in the actual corresponding H matrix of each check-node is capable.Whole H matrix always has 18 check-nodes, 72 variable nodes.The dimension distributed constant in sideline provides in step 2, because the size of each height piece is 112 * 112, therefore the weight span in every sideline is 0～111;
Step 7, in bipartite graph, add new variable node one by one:
A is divided into three groups with 18 check-nodes, and one group is than code check R
1, the check-node that increases newly, i.e. the 10th to the 18th check-node; Other one group is in matrix H
1In, current variable node has the check-node of connection, and undoubtedly, these check-nodes are the parts between nine of the 1st check-nodes to the; Remaining check-node is formed the 3rd group.
B is that root node is done tree-shaped expansion in bipartite graph with current variable node;
C, select a check-node and connect in bipartite graph: if all check-nodes all in bipartite graph, are so just selected apart from root node farthest, current dimension is minimum and belong to check-node in preceding two groups that steps A divides; If check-node is arranged not in tree, so just to select not in tree, current dimension is minimum and belong to check-node in preceding two groups that steps A divides.
D, all paths between the check-node that traversal is chosen in from the root node to the step c), and calculate its weight accumulated value respectively
E, calculated candidate weight set X={x| (s-x) modp ≠ 0,0≤x＜p}, p equals 112 here;
F, select a weight as newly-built stile line from the set of candidate's weight: a kind of mode is a random choose; Another mode is to select a weight from X, makes that the weight accumulation value in path and 112 greatest common factor are 1;
G, the current dimension of variable node adds 1;
Step 8 judges whether to reach the maximum dimension of the initialized variable node of step 3.If reach, then enter next step, otherwise return step 7;
Step 9 is judged whether 72 variable nodes have all added to finish, otherwise is returned step 7;
Step 10: statistics H
2The weight of each piece row in the matrix is as H
3The dimension of matrix information bit part distributes.
Step 11:, can obtain code check R according to the result of calculation of front
2=1/2 o'clock, piece row in the actual corresponding H matrix of each variable node in the bipartite graph, a piece in the actual corresponding H matrix of each check-node is capable.Whole H matrix always has 36 check-nodes, 72 variable nodes.The dimension distributed constant in sideline provides in step 2, because the size of each height piece is 112 * 112, therefore the weight span in every sideline is 0～111;
Step 12, the initialization bipartite graph, at first in bipartite graph, place 36 without any the check-node that connects, initialization check bit submatrix part then, 36 dimensions that check bit submatrix part is corresponding are that 2 variable node is placed as form shown in Figure 17 in bipartite graph, except that a sideline weight absolute value is 111, all the other sideline weights all are 0;
Step 13, in bipartite graph, add new variable node one by one:
H is divided into three groups with 36 check-nodes, and one group is than code check R
1, the check-node that increases newly, i.e. the 19th to the 36th check-node; Other one group is in matrix H
1In, current variable node has the check-node of connection, and undoubtedly, these check-nodes are the parts between 18 of the 1st check-nodes to the; Remaining check-node is formed the 3rd group.
I is that root node is done tree-shaped expansion in bipartite graph with current variable node;
J, select a check-node and connect in bipartite graph: if all check-nodes all in bipartite graph, are so just selected apart from root node farthest, current dimension is minimum and belong to check-node in preceding two groups that steps A divides; If check-node is arranged not in tree, so just to select not in tree, current dimension is minimum and belong to check-node in preceding two groups that steps A divides.
K, all paths between the check-node that traversal is chosen in from the root node to the step c), and calculate its weight accumulated value respectively
L, calculated candidate weight set X={x| (s-x) modp ≠ 0,0≤x＜p}, p equals 112 here;
M, select a weight as newly-built stile line from the set of candidate's weight: a kind of mode is a random choose; Another mode is to select a weight from X, makes that the weight accumulation value in path and 112 greatest common factor are 1;
N, the current dimension of variable node adds 1;
Step 14 judges whether to reach the maximum dimension of the initialized variable node of step 3.If reach, then enter next step, otherwise return step 13;
Step 15 is judged whether 72 variable nodes have all added to finish, otherwise is returned step 14;
Structure finishes.
Embodiment 2: decoder
The overall structure of decoder as shown in figure 15, it can be divided into Controller (control module), Memory (memory), VNU (variable node computing unit) and four parts of CNU (check node calculation unit).
Wherein the variable node computing unit needs 72 altogether, and the check node calculation unit needs 45 altogether, and decoding algorithm can adopt the shortcut calculation of sum-product algorithm---minimum-sum algorithm.Because code check is that the non-zero permutation matrix of 7/8 H matrix has 279 in the multi code Rate of Chinese character H matrix that obtains of structure, the H matrix of other code check splits by this matrix, therefore needing 279 sizes altogether when multi code Rate of Chinese character decoder decoding rate is 7/8 code word is the two-port RAM of 112 * 7bits (getting quantization width here is 7), multiplexing these 279 two-port RAMs of decoder when code check is worth for other, they provide intermediate data to be used for calculating to variable node computing unit and check node calculation unit when decoding as memory cell.Wherein there are 180 RAM when different code checks are worked, to provide read-write for different CNU, as shown in figure 18, these 180 RAM change along with the code check difference in the position of the corresponding non-zero submatrices of H matrix, but their change in location only is to change in same row, any variation does not take place in the annexation that is same VNU, and same RAM then needs to connect different CNU, when being operated in different code checks, they provide the reading and writing data function for different CNU, as shown in figure 19.
As shown in figure 20, control module mainly is divided into input-buffer (Receiver), sequencing control (DecoderCore) and three submodules of output buffers (Output) and realizes.Wherein input-buffer is as the input interface of decoder, be in the outermost end of decoder, receive stores information of channels, and provide channel information to help decoding in the decoding stage, to need 2 sizes altogether be the buffer storage of 8064 * 7bits to this module in the present embodiment, they are divided into two groups, alternately receive outside input information; Time-sequence control module then is the kernel control module of decoder, it is responsible for coordinating all variable nodes and check node calculation unit and begins to calculate in the correct moment, for all memories provide read/write address and guarantee that memory correctly reads and writes the intermediate computations data; Output buffers then after decoding is finished, for all information bit output provides buffer memory, and is preserved the temporary transient result after each iteration judgement in the decoding stage.
72 variable node computing unit Parallel Implementation ldpc decoder minimum-sum algorithms with the algorithm computing.When each iterative decoding, the at every turn multipotency of variable node computing unit receives 1 channel information and 7 decoding external informations, carry out with computing after normalization (3/4) amplitude limit output, output is added in the output information first place with this decoding hard decision result as the external information prefix simultaneously, gives one 1 bit wide port output decoding hard decision result in addition.Main computing branch two-stage is finished: the first order is respectively with 5,4 number additions summation; The summation sum of two of the first order and value is at first finished in the second level, is deducting 8 soft values of external information respectively, and carries out that amplitude limit is finished and computing, at last with the first place (decode results) of sum as the external information after 8 of prefix outputs and the computing.Concrete realization module as shown in figure 21.
The minimum-sum algorithm computing of 45 check node calculation unit Parallel Implementation ldpc decoder minimum-sum algorithms.When carrying out iterative decoding, the once multipotency in check node calculation unit receives 31 decoding external informations, carry out minimum and computing find minimum and time minimum value after correspondence export; Utilize the preceding last iteration decoding hard information prefix of soft information to carry out verification and check in this process simultaneously, with 1 bit wide port output check result.Main computing divides six grades to finish: the first order respectively with 2,2 numbers are asked minimum and, inferior minimum and computing; The second level finish the first order 16 values ask minimum and min, inferior minimum and hypomin computing; The third level finish the first order 8 values ask minimum and min, inferior minimum and hypomin computing; The fourth stage finish the first order 4 values ask minimum and min, inferior minimum and hypomin computing; Level V finish the first order 2 values ask minimum and min, inferior minimum and hypomin computing; The 6th grade respectively with the absolute value of 31 soft information and min relatively, if equate, selects hypomin, otherwise get min, obtains 31 values and add and go up symbol and export.Concrete realization module as shown in figure 22.
In the initial stage of operation of decoder, the directly actuated input-buffer of control module at first order receives a code word, the implementation phase of entering decoding after finishing receiving.The input buffer that input-buffer will receive offers the decoding time-sequence control module, reads when deciphering for it.Input-buffer starts the input information that the another one input buffer waits for that reception is new simultaneously, as shown in figure 23.
A code word that receives entered after the decoding stage, and decoding time-sequence control module (DecoderCore) is at first controlled first code word and entered and operation stages, and this moment, second code word began input.Subsequently first code word enter minimum value ask for computing and and operation stages, until reaching maximum iteration time or it has met the constraint of check equations.The whole decoder of this module controls is in the sequential in iterative decoding stage, the enable signal of output VNU unit, CNU unit and the two-port RAM of different side-play amounts read address signal.This module mainly comprises a state machine, an address generator and necessary combinational logic drive control signal, and hardware is realized block diagram as shown in figure 24.
Output buffer module mainly alternately offers the decoding time-sequence control module by two groups of output buffers RAM (each group size is 1 * 8064 bit) and uses, and exports when iterative decoding finishes.This Module Design thinking is similar to input buffer module.When iterative decoding carries out, output buffer module provide one group totally 1 size be 8064 bit RAM, be used for the decision bits that storage of variables node computing unit obtains, when iterative decoding finishes, the decision bits that this module just will be stored among the RAM is exported successively as decode results, simultaneously other one group of buffer memory RAM is transferred to decoding time-sequence control module control, be used for newly entering the decoding of 1 code word of decoder.The concrete structure of its hardware is with reference to Figure 25.
Claims (7)
1. the building method of a multi-code rate compatible LDPC code comprises the steps:
(1) initialization multi-code rate compatible LDPC code parameter: determine the dimension distribution function of code length N, the highest code check H matrix, the big or small p and the code check sequence R of each height piece of H matrix
1, R
2, R
3..., R
i..., R
t, wherein t is the code check number that communication system is determined according to actual needs, and i represents the sequence number of H matrix, is the integer of 1～t, and sub-block size p can be divided exactly positive integer sequence N, N (1-R
1), N (1-R
2) ..., N (1-R
i) ..., N (1-R
t);
(2) adopt the Block-PEG algorithm construction to go out the highest code rate LDPC code H matrix, as female battle array of multi-code rate compatible LDPC code;
(3) based on female battle array, according to code check order from high to low, determine the dimension distribution function of each code check H matrix, the LDPC sign indicating number H matrix of the different code checks of reconstruct, wherein, the dimension distribution function satisfies constraints 1: the dimension of each variable node of low code rate LDPC code is not more than the dimension of high code rate LDPC code relevant variable node, and restructuring procedure satisfies constraints 2: 0 element position still is 0 element in low code rate LDPC code H matrix in the high code rate LDPC code H matrix.
2. the building method of multi-code rate compatible LDPC code as claimed in claim 1 is characterized in that, described step (1) be divided into following three step by step:
1-1. determine code length N and code check, with the code check of compatibility from high to low successively ordering be R
1, R
2..., R
i..., R
t, the H matrix that obtains each code check is respectively H
1, H
2..., H
i..., H
t, the line number that each matrix has is M
1, M
2..., M
i..., M
t, M then
1＜M
2＜...＜M
t
1-2. select positive integer N, N (1-R
1), N (1-R
2) ..., N (1-R
t) greatest common factor as the sub-block size p of H matrix, according to p, obtain N=np, M
1=m
1P, M
2=m
2P ..., M
i=m
Ip..., M
t=m
tP, each H matrix is divided into m
i* n size is the sub-piece of p * p;
1-3. determine the dimension distribution function of the highest code check H matrix.
3. the building method of multi-code rate compatible LDPC code as claimed in claim 2 is characterized in that, determines the dimension distribution function of each code check H matrix in the described step (3) by density deduction or Gaussian approximation method.
4. the building method of multi-code rate compatible LDPC code as claimed in claim 2, it is characterized in that, described LDPC sign indicating number is a systematic code, its H matrix is divided into check bit submatrix part and information bit submatrix part, the m that when structure check bit submatrix part, at first each check bit submatrix is comprised
iIndividual variable node and all check-nodes are arranged in " it " font formula, fill a special non-null matrix in the upper right corner of check bit submatrix then, this non-null matrix be unit matrix right side cyclic shift p-1 time of p * p by size, and the first capable nonzero element is adjusted into 0 obtains.
5. as the building method of the described multi-code rate compatible LDPC code of each claim in the claim 1～4, it is characterized in that, described step (3) restructuring procedure is followed the maximum loop criterion, at first determine the position of the sub-piece of each H matrix non-zero, determine the cyclic shift amount of the sub-piece of each non-zero again.
6. the building method of multi-code rate compatible LDPC code as claimed in claim 5 is characterized in that, determines that the method for the position of the sub-piece of each H matrix non-zero comprises the following steps:
1) H of the current code check of structure
iThe bipartite graph of matrix correspondence, the capable corresponding check-node of each piece, the corresponding variable node of each piece row;
2) one by one in current bipartite graph, add variable node;
3) all check-nodes with current bipartite graph are divided into three part: C
1, C
2And C
3, C wherein
1Comprise matrix H
I-1In, have the check-node that is connected, C with current variable node
2Then comprised matrix H
iWith respect to H
I-1The check-node that increases newly, C
3Then be to remove C
1And C
2Outside the residue check node;
4) seek C
1With C
2In with root node distance check-node farthest, described distance check-node farthest is meant when tree-shaped being deployed into of bipartite graph comprised C just
1With C
2During all check-node, the last in the figure C that occurs
1With C
2In check-node, a plurality of if such check-node has, preferentially select C
1In node, if C
1In comprise a plurality of such nodes, then select one of them at random;
5) current variable node and the check-node that searches out are connected.
7. the ldpc code decoder of a multi code Rate of Chinese character compatibility comprises a control module, external information memory, a plurality of variable node computing unit and a plurality of check node calculation unit, and wherein control module is controlled the sequential logic of whole decoder; The external information that calculates in the external information memory stores iterative decoding process, its size depend on the size of each piecemeal in the H matrix and the number of piecemeal; The variable node computing unit realize the ldpc decoder minimum-sum algorithm with the algorithm computing, and rule out each bit output, use for the check-node unit; The computing of asking for minimum value in the ldpc decoder minimum-sum algorithm is realized in the check node calculation unit, and the check results of output verification equation; Be connected by one group of data wire respectively between control module and check node calculation unit and the variable node computing unit; Be connected by one group of read-write control signal line between control module and the external information memory; Connect by one group of line that reads and writes data between each check node calculation unit and the external information memory; Connect by one group of line that reads and writes data between each variable node computing unit and the external information memory; It is characterized in that: the external information memory is that the RAM of p quantization width forms by a series of sizes, wherein a part of RAM has multiport and connects, be connected simultaneously on a plurality of check node calculation unit, read and write by different check node calculation unit when different code checks, wherein: p represents code length N, code check sequence R
1, R
2, R
3..., R
tThe size of each height piece of H matrix, p can be divided exactly positive integer sequence N, N (1-R
1), N (1-R
2) ..., N (1-R
t), t is the code check number that communication system is determined according to actual needs.
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| CN105656491A (en) * | 2015-12-29 | 2016-06-08 | 东南大学—无锡集成电路技术研究所 | Multi-rate decoder for binary QC-LDPC codes and decoding method thereof |
| US10469104B2 (en) | 2016-06-14 | 2019-11-05 | Qualcomm Incorporated | Methods and apparatus for compactly describing lifted low-density parity-check (LDPC) codes |
| CN106877879A (en) * | 2016-12-30 | 2017-06-20 | 北京联想核芯科技有限公司 | The method and encoder of data processing |
| CN108347299B (en) * | 2017-01-25 | 2021-02-05 | 华为技术有限公司 | Data transmission method and device |
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| CN107947801B (en) * | 2017-11-24 | 2020-12-15 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Multi-code rate compatible LDPC code encoder |
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| CN108566263B (en) * | 2018-04-02 | 2021-12-14 | 南京邮电大学 | Multi-source multi-relay cooperation construction method based on QC-LDPC code |
| CN111224674B (en) * | 2018-11-27 | 2023-05-26 | 泰斗微电子科技有限公司 | Decoding method, device and decoder for multi-system LDPC code |
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