CN109379087B - Method for LDPC to modulate kernel coding and decoding rate according to error rate of flash memory component - Google Patents
Method for LDPC to modulate kernel coding and decoding rate according to error rate of flash memory component Download PDFInfo
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- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
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Abstract
The invention discloses a method for modulating a core coding and decoding rate by an LDPC according to an error rate of a flash memory component, which comprises the following steps: the method comprises the following steps: configuring a plurality of groups of different operation matrixes and operation sequences in a low-density parity check error correction controller inside a main control chip; step two: automatically managing and executing and checking code word decoding signals by using a system software program or hardware; step three: according to the actual operation condition, the operation of the data assembly controller is matched to select the corresponding matrix for operation, the matrix with low row weight is used under the requirement of low error bit number, and the matrix with high row weight is used under the requirement of high error bit number.
Description
Technical Field
The invention relates to the technical field of low-density parity-check error correcting codes (LDPC) for a data master control device, in particular to a method for modulating a core coding and decoding rate by the LDPC according to an error rate of a flash memory component.
Background
LDPC codes were first proposed in the 60's of the 20 th century by Gallager in his phd paper, but limited to the technical conditions at that time, lacking a feasible decoding algorithm, and were essentially ignored by people for the following 35 years, during which LDPC codes were generalized and their representation was given by Tanner in 1981, the latter named Tanner graph. The Turbo code was discovered by Berrou et al in 1993, and on the basis, MacKay and Neal et al studied the LDPC code again before and after 1995 and proposed a feasible decoding algorithm, thereby further discovering the good performance of the LDPC code and rapidly arousing strong reverberation and great attention. After research and development for over a decade, researchers have made breakthrough in all aspects, and the related technology of LDPC codes is becoming mature, and even commercialized application results have been started, and the technology has entered standards in related fields such as wireless communication.
LDPC codes, that is, Low Density Parity Check codes (LDPC), which are linear block codes with sparse Check matrices proposed by Robert g.gallager in 1963, have good performance approaching Shannon limit, Low decoding complexity and flexible structure, are research hotspots in the field of channel coding in recent years, and are currently widely applied to the fields of deep space communication, optical fiber communication, satellite digital video and audio broadcasting, and the like. LDPC codes have become a powerful competitor to fourth generation communication systems (4G), and LDPC code-based coding schemes have been adopted by the next generation satellite digital video broadcasting standard DVB-S2.
The LDPC code is a linear code defined by a check matrix, and in order to make decoding feasible, the check matrix is required to meet sparsity when the code length is longer, namely the density of 1 in the check matrix is lower, namely the number of 1 in the check matrix is required to be far less than the number of 0, and the density is required to be lower as the code length is longer.
The design of the check bit generation and check unit of the low density parity check error correction code (LDPC) of the current master control device adopts a single fixed check matrix, and is matched with the design of a pipeline of a fixed check bit generation core and a data check core, and also designed in a fixed speed mode. Therefore, the working efficiency of the master generation and checking cores cannot be effectively controlled under the condition of different data error rates, so that the master generation and checking cores can be maximized and most efficiently exerted.
Disclosure of Invention
The invention aims to provide a method for adjusting the core coding and decoding rate of an LDPC (low density parity check) according to the error rate of a flash memory component, which is characterized in that a plurality of groups of matrix storage spaces with different row weights are configured, a unit for effectively monitoring the error rate of read data is matched to detect the data error rate in real time, or different operation matrixes and operation sequences are called according to different interval settings and component configurations, so that the effect of effectively utilizing the working efficiency of generating and checking a core by a main control end is achieved, and the problems in the background art are solved.
In order to achieve the purpose, the invention provides the following technical scheme: a method for LDPC to modulate kernel coding rate according to error rate of flash memory device includes following steps:
the method comprises the following steps: configuring a plurality of groups of different operation matrixes and operation sequences in a low-density parity check error correction controller inside a main control chip;
step two: automatically managing and executing and checking code word decoding signals by using a system software program or hardware;
step three: according to the actual operation condition, the corresponding matrix is selected to operate in cooperation with the operation of the data component controller, the matrix with low row weight is used under the requirement of low error bit number, and the matrix with high row weight is used under the requirement of high error bit number.
Preferably, the main control chip in the first step is internally provided with a low density parity check error correction controller and a data component controller.
Preferably, a check bit generation unit and a check error correction unit are arranged in the low density parity check error correction controller, the check bit generation unit is configured with a plurality of generator matrices, and the check error correction unit is configured with a plurality of check matrices.
Preferably, the data component controller is internally provided with a plurality of data components.
Preferably, the matrices in step three are all configured with weight values.
Compared with the prior art, the invention has the beneficial effects that:
the matrix storage spaces with different row weights are configured, a unit for effectively monitoring the error rate of read data is matched to timely detect the data error rate, or different operation matrixes and operation sequences are called according to different interval settings and component configurations, so that the effect of effectively utilizing the working efficiency of generating and checking the kernel by the main control end is achieved.
Drawings
Fig. 1 is a schematic diagram of a low density parity check control unit in a main control chip configured with a plurality of different operation matrices and operation sequences.
Fig. 2 is a schematic diagram of the low density parity check control unit operating status, configuration of multiple sets of matrices, and dynamic matrix calling mechanism in the main control chip.
FIG. 3 is a diagram of a low density parity check control unit inside a main control chip.
FIG. 4 is a diagram illustrating the operation of the LDPC control unit in the main control chip without configuring multiple sets of matrices and a dynamic matrix calling mechanism.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, the present invention provides a technical solution: a method for LDPC to modulate kernel coding rate according to error rate of flash memory device includes following steps:
the method comprises the following steps: configuring a plurality of groups of different operation matrixes and operation sequences in a low-density parity check error correction controller inside a main control chip;
step two: automatically managing and executing and checking code word decoding signals by using a system software program or hardware;
step three: according to the actual operation condition, the corresponding matrix is selected to operate in cooperation with the operation of the data component controller, the matrix with low row weight is used under the requirement of low error bit number, and the matrix with high row weight is used under the requirement of high error bit number.
The main control chip is internally provided with a low-density parity check error correction controller and a data component controller, the low-density parity check error correction controller is internally provided with a check bit generation unit and a check error correction unit, the check bit generation unit is provided with a plurality of generation matrixes, the check error correction unit is provided with a plurality of check matrixes, namely a plurality of groups of different operation matrixes and operation sequences are configured, and the data component controller is internally provided with a plurality of data components.
The principle of the invention is as follows: the invention discloses a check bit generation and data check unit design of a low-density parity check error correcting code (LDPC), which is configured with a plurality of groups of matrix storage spaces with different row weights (column-weight), is matched with a unit for effectively monitoring the error rate of read data so as to detect the data error rate in time, or calls different operation matrixes and operation sequences according to different interval settings and component configurations, thereby achieving the effect of effectively utilizing the working efficiency of a master control end for generating and checking a core.
The check matrix configured with different row weights represents different instruction cycles, but relatively represents different checking capabilities. For example, a matrix with high row weights (e.g., row weight of 6, and code length and code rate are omitted in the following description) has a code word decoding cycle lower than that of a matrix with low row weights (e.g., row weight of 3), but has a higher check capability than that of a matrix with low row weights. The current ldpc error correction code core operation method generally adopts a sequential or programmed operation method of the effective values in the matrix, so that the ratio of the total effective value number in the matrix is approximately a row weight ratio (e.g., 6: 3), the code word encoding/decoding instruction cycle is approximately a row weight ratio (e.g., 6: 3), the data throughput of the operation is an inverse ratio of the row weight (e.g., 3: 6), but the parity error correction capability is better if the row weight is higher (e.g., probability of error correctable bits is 10: 7, which is approximately positively correlated with the row weight ratio), and the actual number of error correctable bits is different according to the matrix arrangement.
In addition, the checking and error correcting unit can also output the characteristic value of each code word decoding to be supplied to system software or firmware for reference, and observe the error bit condition of data according to the data obtained by dynamic monitoring so as to dynamically adjust and call different matrixes by programming, or the hardware automatically and dynamically calls different matrixes according to the requirements of different components or different partitions in the single component.
In the first embodiment, a plurality of sets of matrices and dynamic matrix invoking mechanisms are configured, as shown in fig. 2, a validation bit generating unit generates a matrix 1 and a matrix 2, the matrix 1 and the matrix 2 are operated by a data component controller, and finally the matrix 1 and the matrix 2 are respectively checked by an error checking unit, assuming that a codeword decoding period of the matrix 1 is a codeword decoding period a and a codeword decoding period of the matrix 2 is a codeword decoding period B, a low-density parity-check error correction controller will perform sorting according to row weight values of the codeword decoding period a and the codeword decoding period B, and dynamically invoke different matrices by programming according to error bit conditions of data observation data obtained by dynamic monitoring, or hardware automatically invokes different matrices according to different component requirements or different partitions inside a single component.
In the second embodiment, a conventional calling mechanism for multiple groups of matrixes and dynamic matrixes is not configured, as shown in fig. 3-4, a check bit generation unit generates a matrix, a data component controller operates the matrix, and finally an error correction unit checks the matrix, so that only one matrix can be provided in the whole generation, operation and check processes, that is, only one code word decoding period is provided in the same time period, the code word decoding periods of the matrix are sequentially performed, and the pipeline type and the speed are fixed, and different matrixes cannot be dynamically called by themselves.
According to the first and second embodiments, the configuration of the plurality of different operation matrixes and operation sequences in the low density parity check error correction controller inside the main control chip can achieve the effect of effectively utilizing the work performance of the generation and check of the kernel at the main control terminal compared with the configuration without the configuration of the plurality of different operation matrixes and operation sequences.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (1)
1. A method for LDPC to modulate kernel coding and decoding rate according to error rate of flash memory component is characterized in that: the method comprises the following steps:
the method comprises the following steps: configuring a plurality of groups of different operation matrixes and operation sequences in a low-density parity check controller inside a main control chip;
step two: automatically managing and executing and checking code word decoding signals by using a system software program or hardware;
step three: according to the actual operation condition, the corresponding matrix is selected to carry out operation by matching with the operation of the data component controller, the matrix with low row weight is used under the requirement of low error bit number, and the matrix with high row weight is used under the requirement of high error bit number;
a low-density parity check controller and a data component controller are arranged in the main control chip in the first step;
a check bit generating unit and a check error correcting unit are arranged in the low-density parity check controller, the check bit generating unit is provided with a plurality of generating matrixes, and the check error correcting unit is provided with a plurality of check matrixes;
the data component controller is internally provided with a plurality of data components.
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| CN201811247400.7A CN109379087B (en) | 2018-10-24 | 2018-10-24 | Method for LDPC to modulate kernel coding and decoding rate according to error rate of flash memory component |
| PCT/CN2018/115508 WO2020082447A1 (en) | 2018-10-24 | 2018-11-14 | Method for adjusting ldpc encoding and decoding rate of kernel according to flash memory component error rate |
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| US7222289B2 (en) * | 2002-09-30 | 2007-05-22 | Certance Llc | Channel processor using reduced complexity LDPC decoder |
| CN1976238A (en) * | 2006-12-21 | 2007-06-06 | 复旦大学 | Method for constituting quasi-circulating low-density parity check code based on block fill algorithm |
| JP5485069B2 (en) * | 2010-08-06 | 2014-05-07 | パナソニック株式会社 | Error correction decoding apparatus and error correction decoding method |
| TWI530959B (en) * | 2014-06-17 | 2016-04-21 | 慧榮科技股份有限公司 | Method for controlling a memory apparatus, and associated memory apparatus thereof and associated controller thereof |
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| CN1781254A (en) * | 2003-02-26 | 2006-05-31 | 弗拉里奥恩技术公司 | Method and apparatus for performing low-density parity-check (LDPC) code operations using a multi-level permutation |
| CN101471672A (en) * | 2007-12-27 | 2009-07-01 | 华为技术有限公司 | Method for generating check matrix and corresponding encoding method and encoder |
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Application publication date: 20190222 Assignee: Zhongguancun Technology Leasing Co.,Ltd. Assignor: JIANGSU HUACUN ELECTRONIC TECHNOLOGY Co.,Ltd. Contract record no.: X2022980017352 Denomination of invention: A Method for LDPC to Adjust the Core Encoding and Decoding Rate Based on the Error Rate of Flash Memory Components Granted publication date: 20220329 License type: Exclusive License Record date: 20220930 |
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Denomination of invention: A Method for LDPC to Adjust the Core Encoding and Decoding Rate Based on the Error Rate of Flash Memory Components Effective date of registration: 20221008 Granted publication date: 20220329 Pledgee: Zhongguancun Technology Leasing Co.,Ltd. Pledgor: JIANGSU HUACUN ELECTRONIC TECHNOLOGY Co.,Ltd. Registration number: Y2022980017514 |