WO2020082447A1 - Method for adjusting ldpc encoding and decoding rate of kernel according to flash memory component error rate - Google Patents

Method for adjusting ldpc encoding and decoding rate of kernel according to flash memory component error rate Download PDF

Info

Publication number
WO2020082447A1
WO2020082447A1 PCT/CN2018/115508 CN2018115508W WO2020082447A1 WO 2020082447 A1 WO2020082447 A1 WO 2020082447A1 CN 2018115508 W CN2018115508 W CN 2018115508W WO 2020082447 A1 WO2020082447 A1 WO 2020082447A1
Authority
WO
WIPO (PCT)
Prior art keywords
matrix
matrices
error rate
flash memory
check
Prior art date
Application number
PCT/CN2018/115508
Other languages
French (fr)
Chinese (zh)
Inventor
陈育鸣
李庭育
洪振洲
魏智汎
Original Assignee
江苏华存电子科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 江苏华存电子科技有限公司 filed Critical 江苏华存电子科技有限公司
Publication of WO2020082447A1 publication Critical patent/WO2020082447A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding

Definitions

  • the invention relates to the technical field of low-density parity check error correction code (LDPC) used for a data master device, in particular to a method for LDPC to adjust the core coding rate according to the error rate of flash memory components.
  • LDPC low-density parity check error correction code
  • the LDPC code was first proposed by Gallager in his doctoral thesis in the 1960s, but was limited to the technical conditions at that time and lacked a feasible decoding algorithm. It was basically ignored by people for the next 35 years, during which it was promoted by Tanner in 1981
  • the LDPC code also gives a graphical representation of the LDPC code, which is later called the Tanner graph.
  • Berrou et al. Discovered the Turbo code.
  • MacKay and Neal et al. Re-examined the LDPC code, and proposed a feasible decoding algorithm, thereby further discovering the good performance of the LDPC code. , Quickly aroused strong response and great concern.
  • LDPC code related technology has also become increasingly mature, and even has begun to have commercial application results, and entered the wireless communication and other related fields Standard.
  • LDPC codes are a type of linear codes defined by a check matrix.
  • the check matrix needs to meet the "sparseness" when the code length is long, that is, the density of 1 in the check matrix is relatively low, which is the requirement
  • the number of 1s in the check matrix is much smaller than the number of 0s, and the longer the code length, the lower the density.
  • the design of the low-density parity check error correction code (LDPC) check digit generation and check unit of the current main control device adopts a single fixed check matrix, cooperates with the fixed check digit generation core and the data check and verification core pipeline The design is also done at a fixed rate. In this way, it is impossible to effectively control the working efficiency of the generation and verification core of the main control terminal under different data error rates, so that it can be maximized and maximized. Therefore, an improved technology is urgently needed to Solve this problem in the prior art.
  • LDPC low-density parity check error correction code
  • the purpose of the present invention is to provide a method for LDPC to adjust the core coding and decoding rate according to the error rate of the flash memory component, configure multiple sets of matrix storage spaces with different row weights, and equip with a unit that effectively monitors the read data error rate to detect data errors in a timely manner Rate, or according to different interval settings and component configurations, call different operation matrices and operation sequences to achieve the effective use of the working efficiency of the main control terminal to generate and verify the core, to solve the problems raised in the background art.
  • An LDPC method for modulating the core coding and decoding rate according to the error rate of the flash memory component includes the following steps:
  • Step 1 Configure multiple sets of different operation matrices and operation sequences in the low density parity check controller inside the main control chip;
  • Step 2 Use system software programs or hardware to automatically manage execution and check codeword decoding signals
  • Step 3 According to the actual operating conditions, cooperate with the data component controller to select the corresponding matrix for operation, use the matrix with low row weights when the number of error bits is low, and use the matrix with high row weights when the demand is high .
  • the main control chip is provided with a low-density parity controller and a data component controller.
  • the low-density parity check controller is internally provided with a check bit generation unit and a check error correction unit, the check bit generation unit is configured with a plurality of generation matrices, and the check error correction unit is configured with a number of checks matrix.
  • the data component controller is internally configured with several data components.
  • the main control end generates and verifies the working efficiency of the core.
  • Fig. 1 is a schematic diagram of a low-density parity control unit inside a main control chip configured with multiple sets of different operation matrices and operation sequences.
  • Figure 2 is a schematic diagram of the operation status of the low-density parity control unit inside the main control chip, which is configured with multiple sets of matrix and dynamic matrix calling mechanism.
  • Figure 3 is a schematic diagram of a low-density parity control unit inside the main control chip.
  • Figure 4 shows the operation status of the low-density parity control unit inside the main control chip, without multiple sets of matrix and dynamic matrix calling mechanism.
  • the present invention provides a technical solution: a method for LDPC to adjust the core coding and decoding rate according to the error rate of the flash memory component, including the following steps:
  • Step 1 Configure multiple sets of different operation matrices and operation sequences in the low density parity check controller inside the main control chip;
  • Step 2 Use system software programs or hardware to automatically manage execution and check codeword decoding signals
  • Step 3 According to the actual operating conditions, cooperate with the data component controller to select the corresponding matrix for operation, use the matrix with low row weights when the number of error bits is low, and use the matrix with high row weights when the demand is high .
  • the main control chip is provided with a low-density parity controller and a data component controller.
  • the low-density parity controller is provided with a check bit generation unit and an error correction and correction unit.
  • the check bit generation unit is provided with a number of generation matrices , Check that the error correction unit is configured with several check matrices, that is, multiple sets of different operation matrices and operation sequences, and the data component controller is equipped with several data components.
  • the present invention discloses a low-density parity check error correction code (LDPC) check bit generation and data check unit design, configured with multiple sets of matrix storage space with different row weights (column-weight), equipped with The unit that effectively monitors the error rate of the read data can detect the data error rate in a timely manner, or call different operation matrices and operation sequences according to different interval settings and component configurations, so as to effectively use the work efficiency of the main control terminal to generate and verify the core utility.
  • LDPC low-density parity check error correction code
  • the check matrix configured with different row weights represents different instruction cycles, but relatively also represents different check capabilities.
  • a matrix with a high row weight for example, a row weight of 6, the following example omits the codeword length and code rate is omitted
  • the matrix with a low row weight for example: row weight is 3
  • the check ability is higher than the matrix with low row weight.
  • the current low-density parity check error correction code core operation method generally uses the effective value sequence or programming operation method in the matrix, so the ratio of the total effective value number in the matrix is approximately the line weight ratio (for example: 6: 3), codeword
  • the cycle time of the compiled code is approximately the ratio of line weights (example: 6: 3)
  • the data throughput of its operation is inversely proportional to the value of line weights (example: 3: 6)
  • the ability to check and correct errors is based on line weight Excellent (for example: the probability of error correcting digits is 10: 7, which is roughly related to the line weight ratio)
  • the actual number of error correcting bits varies according to the arrangement of the matrix.
  • check error correction unit can also output the characteristic value of each codeword decoding to the system software or firmware for reference, observe the error bit status of the data according to the data obtained by dynamic monitoring, and dynamically adjust and call different matrices by programming, or
  • the hardware can dynamically call different matrices according to the needs of different components or different partitions within a single component.
  • the verification bit generation unit generates matrix 1 and matrix 2 and performs operations on matrix 1 and matrix 2 through the data component controller, and finally passes inspection
  • the error correction unit checks matrix 1 and matrix 2, respectively, assuming that the codeword decoding cycle of matrix 1 is codeword decoding cycle A, the codeword decoding cycle of matrix 2 is codeword decoding cycle B, and low density parity check
  • the controller will sort according to the line weight values of codeword decoding cycle A and codeword decoding cycle B, observe the error bit status of the data according to the data obtained from dynamic monitoring, dynamically adjust and call different matrices by programming, or the hardware will Different components require, or different partitions within a single component, dynamically call different matrices on their own.
  • the conventional unconfigured multiple sets of matrix and dynamic matrix calling mechanism are shown in Figure 3-4.
  • the verification bit generation unit generates the matrix, performs operations on the matrix through the data component controller, and finally calibrates separately by checking the error correction unit. Check the matrix, the codeword decoding cycle of the matrix is carried out in sequence, pipelined, and the rate is fixed, and it is not possible to dynamically call different matrices on its own.

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

A method for adjusting an LDPC encoding and decoding rate of a kernel according to a flash memory component error rate, the method comprising the following steps: step I, configuring multiple sets of different computation matrices and computation sequences in a low density parity check controller located in a main control chip; step II, performing, by means of a system software program or hardware, automatic management with respect to the execution and checking of a codeword decoding signal; and step III, selecting, according to an actual operation condition, a corresponding matrix for computation by taking operations of a data component controller into consideration, using a matrix having a low column weight for a low error bit requirement, and using a matrix having a high column weight for a high error bit requirement. The method configures a storage space for multiple sets of matrices having different column weights, incorporates a unit effectively monitoring a data reading error rate to achieve timely data error rate detection, and invokes, according to different interval settings and component configurations, different computation matrices and computation sequences, thereby effectively utilizing a main control terminal to provide operation performance of a checking kernel.

Description

LDPC根据闪存组件错误率调变核编译码速率的方法Method for LDPC to adjust kernel coding and decoding rate according to error rate of flash memory component 技术领域Technical field
本发明涉及用于数据主控装置之低密度奇偶校验纠错码(LDPC)技术领域，具体为一种LDPC根据闪存组件错误率调变核编译码速率的方法。The invention relates to the technical field of low-density parity check error correction code (LDPC) used for a data master device, in particular to a method for LDPC to adjust the core coding rate according to the error rate of flash memory components.
背景技术Background technique
LDPC码最早在20世纪60年代由Gallager在他的博士论文中提出，但限于当时的技术条件，缺乏可行的译码算法，此后的35年间基本上被人们忽略，其间由Tanner在1981年推广了LDPC码并给出了LDPC码的图表示，即后来所称的Tanner图。1993年Berrou等人发现了Turbo码，在此基础上，1995年前后MacKay和Neal等人对LDPC码重新进行了研究，提出了可行的译码算法，从而进一步发现了LDPC码所具有的良好性能，迅速引起强烈反响和极大关注。经过十几年来的研究和发展，研究人员在各方面都取得了突破性的进展，LDPC码的相关技术也日趋成熟，甚至已经开始有了商业化的应用成果，并进入了无线通信等相关领域的标准。The LDPC code was first proposed by Gallager in his doctoral thesis in the 1960s, but was limited to the technical conditions at that time and lacked a feasible decoding algorithm. It was basically ignored by people for the next 35 years, during which it was promoted by Tanner in 1981 The LDPC code also gives a graphical representation of the LDPC code, which is later called the Tanner graph. In 1993, Berrou et al. Discovered the Turbo code. On this basis, around 1995, MacKay and Neal et al. Re-examined the LDPC code, and proposed a feasible decoding algorithm, thereby further discovering the good performance of the LDPC code. , Quickly aroused strong response and great concern. After more than ten years of research and development, researchers have made breakthrough progress in all aspects, LDPC code related technology has also become increasingly mature, and even has begun to have commercial application results, and entered the wireless communication and other related fields Standard.
LDPC码是通过校验矩阵定义的一类线性码，为使译码可行，在码长较长时需要校验矩阵满足“稀疏性”，即校验矩阵中1的密度比较低，也就是要求校验矩阵中1的个数远小于0的个数，并且码长越长，密度就要越低。LDPC codes are a type of linear codes defined by a check matrix. In order to make decoding feasible, the check matrix needs to meet the "sparseness" when the code length is long, that is, the density of 1 in the check matrix is relatively low, which is the requirement The number of 1s in the check matrix is much smaller than the number of 0s, and the longer the code length, the lower the density.
现行主控装置之低密度奇偶校验纠错码(LDPC)的校验位产生与校验单元设计，皆采用单一固定校验矩阵，配合固定的校验位产生 核与数据检查校验核流水线的设计，也以固定的速率的方式做设计。如此一来便无法在不同数据错误率的情况下，有效控制主控端产生与校验核的工作效率，使其可以做最大化与最有效率的发挥，因此，亟待一种改进的技术来解决现有技术中所存在的这一问题。The design of the low-density parity check error correction code (LDPC) check digit generation and check unit of the current main control device adopts a single fixed check matrix, cooperates with the fixed check digit generation core and the data check and verification core pipeline The design is also done at a fixed rate. In this way, it is impossible to effectively control the working efficiency of the generation and verification core of the main control terminal under different data error rates, so that it can be maximized and maximized. Therefore, an improved technology is urgently needed to Solve this problem in the prior art.
发明内容Summary of the invention
本发明的目的在于提供一种LDPC根据闪存组件错误率调变核编译码速率的方法，配置多组不同行权重的矩阵储存空间，配上有效监测读取数据错误率的单元以适时检测数据错误率，或者根据不同区间设定与组件配置，调用不同运算矩阵与运算序列，达到有效利用主控端产生与校验核的工作效能之效用，以解决上述背景技术中提出的问题。The purpose of the present invention is to provide a method for LDPC to adjust the core coding and decoding rate according to the error rate of the flash memory component, configure multiple sets of matrix storage spaces with different row weights, and equip with a unit that effectively monitors the read data error rate to detect data errors in a timely manner Rate, or according to different interval settings and component configurations, call different operation matrices and operation sequences to achieve the effective use of the working efficiency of the main control terminal to generate and verify the core, to solve the problems raised in the background art.
为实现上述目的，本发明提供如下技术方案：一种LDPC根据闪存组件错误率调变核编译码速率的方法，包括以下步骤：In order to achieve the above object, the present invention provides the following technical solution: An LDPC method for modulating the core coding and decoding rate according to the error rate of the flash memory component includes the following steps:
步骤一：在主控芯片内部的低密度奇偶校验控制器内配置多组不同运算矩阵与运算序列；Step 1: Configure multiple sets of different operation matrices and operation sequences in the low density parity check controller inside the main control chip;
步骤二：利用系统软件程序或硬件自动管理执行和检查码字译码信号；Step 2: Use system software programs or hardware to automatically manage execution and check codeword decoding signals;
步骤三：依照实际运作状况，配合数据组件控制器运作挑选对应的矩阵来做运算，在错误位数低的需求下使用行权重低的矩阵，在错误位高的需求下使用行权重高的矩阵。Step 3: According to the actual operating conditions, cooperate with the data component controller to select the corresponding matrix for operation, use the matrix with low row weights when the number of error bits is low, and use the matrix with high row weights when the demand is high .
优选的，所述步骤一中主控芯片内部设置有低密度奇偶校验控制器及数据组件控制器。Preferably, in the first step, the main control chip is provided with a low-density parity controller and a data component controller.
优选的，所述低密度奇偶校验控制器内部设置有校验位产生单元及检查纠错单元，所述校验位产生单元配置有若干生成矩阵，所述检查纠错单元配置有若干校验矩阵。Preferably, the low-density parity check controller is internally provided with a check bit generation unit and a check error correction unit, the check bit generation unit is configured with a plurality of generation matrices, and the check error correction unit is configured with a number of checks matrix.
优选的，所述数据组件控制器内部配置有若干数据组件。Preferably, the data component controller is internally configured with several data components.
与现有技术相比，本发明的有益效果是：Compared with the prior art, the beneficial effects of the present invention are:
配置多组不同行权重的矩阵储存空间，配上有效监测读取数据错误率的单元以适时检测数据错误率，或者根据不同区间设定与组件配置，调用不同运算矩阵与运算序列，达到有效利用主控端产生与校验核的工作效能之效用。Configure multiple sets of matrix storage space with different row weights, equipped with a unit that effectively monitors the read data error rate to detect the data error rate in a timely manner, or call different operation matrices and operation sequences according to different interval settings and component configurations to achieve effective use The main control end generates and verifies the working efficiency of the core.
附图说明BRIEF DESCRIPTION
图1为主控芯片内部的低密度奇偶校验控制单元，配置多组不同运算矩阵与运算序列示意图。Fig. 1 is a schematic diagram of a low-density parity control unit inside a main control chip configured with multiple sets of different operation matrices and operation sequences.
图2为主控芯片内部的低密度奇偶校验控制单元运作状况,配置多组矩阵与动态矩阵调用机制示意图。Figure 2 is a schematic diagram of the operation status of the low-density parity control unit inside the main control chip, which is configured with multiple sets of matrix and dynamic matrix calling mechanism.
图3为主控芯片内部的低密度奇偶校验控制单元示意图。Figure 3 is a schematic diagram of a low-density parity control unit inside the main control chip.
图4为主控芯片内部的低密度奇偶校验控制单元运作状况,未配置多组矩阵与动态矩阵调用机制示意图。Figure 4 shows the operation status of the low-density parity control unit inside the main control chip, without multiple sets of matrix and dynamic matrix calling mechanism.
具体实施方式detailed description
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他 实施例，都属于本发明保护的范围。The technical solutions in the embodiments of the present invention will be described clearly and completely in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present invention.
请参阅图1，本发明提供一种技术方案：一种LDPC根据闪存组件错误率调变核编译码速率的方法，包括以下步骤：Referring to FIG. 1, the present invention provides a technical solution: a method for LDPC to adjust the core coding and decoding rate according to the error rate of the flash memory component, including the following steps:
步骤一：在主控芯片内部的低密度奇偶校验控制器内配置多组不同运算矩阵与运算序列；Step 1: Configure multiple sets of different operation matrices and operation sequences in the low density parity check controller inside the main control chip;
步骤二：利用系统软件程序或硬件自动管理执行和检查码字译码信号；Step 2: Use system software programs or hardware to automatically manage execution and check codeword decoding signals;
步骤三：依照实际运作状况，配合数据组件控制器运作挑选对应的矩阵来做运算，在错误位数低的需求下使用行权重低的矩阵，在错误位高的需求下使用行权重高的矩阵。Step 3: According to the actual operating conditions, cooperate with the data component controller to select the corresponding matrix for operation, use the matrix with low row weights when the number of error bits is low, and use the matrix with high row weights when the demand is high .
主控芯片内部设置有低密度奇偶校验控制器及数据组件控制器，低密度奇偶校验控制器内部设置有校验位产生单元及检查纠错单元，校验位产生单元配置有若干生成矩阵，检查纠错单元配置有若干校验矩阵，即配置多组不同运算矩阵与运算序列，数据组件控制器内部配置有若干数据组件。The main control chip is provided with a low-density parity controller and a data component controller. The low-density parity controller is provided with a check bit generation unit and an error correction and correction unit. The check bit generation unit is provided with a number of generation matrices , Check that the error correction unit is configured with several check matrices, that is, multiple sets of different operation matrices and operation sequences, and the data component controller is equipped with several data components.
本发明原理：本发明公开了一种低密度奇偶校验纠错码(LDPC)的校验位产生与资料校验单元设计，配置多组不同行权重(column-weight)的矩阵储存空间，配上有效监测读取数据错误率的单元以适时检测数据错误率，或者根据不同区间设定与组件配置，调用不同运算矩阵与运算序列，达到有效利用主控端产生与校验核的工作效能之效用。Principle of the present invention: The present invention discloses a low-density parity check error correction code (LDPC) check bit generation and data check unit design, configured with multiple sets of matrix storage space with different row weights (column-weight), equipped with The unit that effectively monitors the error rate of the read data can detect the data error rate in a timely manner, or call different operation matrices and operation sequences according to different interval settings and component configurations, so as to effectively use the work efficiency of the main control terminal to generate and verify the core utility.
其中，配置不同行权重的校验矩阵代表着不同的指令周期，但 相对也代表着不同的校验能力。举例说明，行权重高的矩阵(例：行权重为6，以下举例说明省略不计码字长度与码率)其码字编解碼周期低于行权重低的矩阵(例：行权重为3)，但校验能力高于行权重低的矩阵。现行低密度奇偶校验纠错码核运作方式，大致上皆采用矩阵内有效值循序或编程运算方式，所以矩阵内总有效值数量比值约略为行权重比(例：6：3)，码字编译码指令周期约略为行权重比值(例：6：3)，其运算之数据吞吐率为行权重值之反比(例：3：6)，但校验纠错能力则以行权重高着为优(例：可纠错位数概率10：7，大略与行权重比正相关)，实际可纠错位元数依照矩阵排列不同而有所不同。Among them, the check matrix configured with different row weights represents different instruction cycles, but relatively also represents different check capabilities. For example, a matrix with a high row weight (for example, a row weight of 6, the following example omits the codeword length and code rate is omitted) whose codeword coding and decoding period is lower than the matrix with a low row weight (for example: row weight is 3), But the check ability is higher than the matrix with low row weight. The current low-density parity check error correction code core operation method generally uses the effective value sequence or programming operation method in the matrix, so the ratio of the total effective value number in the matrix is approximately the line weight ratio (for example: 6: 3), codeword The cycle time of the compiled code is approximately the ratio of line weights (example: 6: 3), the data throughput of its operation is inversely proportional to the value of line weights (example: 3: 6), but the ability to check and correct errors is based on line weight Excellent (for example: the probability of error correcting digits is 10: 7, which is roughly related to the line weight ratio), the actual number of error correcting bits varies according to the arrangement of the matrix.
此外，检查纠错单元还可以将每个码字译码的特征值输出供给系统软件或韧体参考，根据动态监测得到的数据观察数据的错误位状况，以编程动态调整调用不同的矩阵，或者硬件自行根据不同组件需要，或者单一组件内部的不同分区，自行动态调用不同的矩阵。In addition, the check error correction unit can also output the characteristic value of each codeword decoding to the system software or firmware for reference, observe the error bit status of the data according to the data obtained by dynamic monitoring, and dynamically adjust and call different matrices by programming, or The hardware can dynamically call different matrices according to the needs of different components or different partitions within a single component.
实施例的，配置多组矩阵与动态矩阵调用机制，如图2所示，效验位产生单元生成矩阵1、生成矩阵2，通过数据组件控制器对矩阵1和矩阵2来做运算，最后通过检查纠错单元分别校验矩阵1和矩阵2,假设矩阵1的码字译码周期为码字译码周期A，矩阵2的码字译码周期为码字译码周期B，低密度奇偶校验控制器会根据码字译码周期A和码字译码周期B的行权重值进行排序，根据动态监测得到的数据观察数据的错误位状况，以编程动态调整调用不同的矩 阵，或者硬件自行根据不同组件需要，或者单一组件内部的不同分区，自行动态调用不同的矩阵。In the embodiment, multiple sets of matrix and dynamic matrix calling mechanisms are configured. As shown in FIG. 2, the verification bit generation unit generates matrix 1 and matrix 2 and performs operations on matrix 1 and matrix 2 through the data component controller, and finally passes inspection The error correction unit checks matrix 1 and matrix 2, respectively, assuming that the codeword decoding cycle of matrix 1 is codeword decoding cycle A, the codeword decoding cycle of matrix 2 is codeword decoding cycle B, and low density parity check The controller will sort according to the line weight values of codeword decoding cycle A and codeword decoding cycle B, observe the error bit status of the data according to the data obtained from dynamic monitoring, dynamically adjust and call different matrices by programming, or the hardware will Different components require, or different partitions within a single component, dynamically call different matrices on their own.
实施例的，常规未配置多组矩阵与动态矩阵调用机制，如图3-4所示，效验位产生单元生成矩阵，通过数据组件控制器对矩阵来做运算，最后通过检查纠错单元分别校验矩阵，矩阵的码字译码周期按顺序进行，流水线式、速率固定，无法自行动态调用不同的矩阵。In the embodiment, the conventional unconfigured multiple sets of matrix and dynamic matrix calling mechanism are shown in Figure 3-4. The verification bit generation unit generates the matrix, performs operations on the matrix through the data component controller, and finally calibrates separately by checking the error correction unit. Check the matrix, the codeword decoding cycle of the matrix is carried out in sequence, pipelined, and the rate is fixed, and it is not possible to dynamically call different matrices on its own.
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行多种变化、修改、替换和变型，本发明的范围由所附权利要求及其等同物限定。Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, and substitutions can be made to these embodiments without departing from the principle and spirit of the present invention And variations, the scope of the invention is defined by the appended claims and their equivalents.

Claims (3)

  1. 一种LDPC根据闪存组件错误率调变核编译码速率的方法，其特征在于：包括以下步骤：A method for LDPC to adjust the core coding and decoding rate according to the error rate of the flash memory component is characterized by the following steps:
    步骤一：在主控芯片内部的低密度奇偶校验控制器内配置多组不同运算矩阵与运算序列；Step 1: Configure multiple sets of different operation matrices and operation sequences in the low density parity check controller inside the main control chip;
    步骤二：利用系统软件程序或硬件自动管理执行和检查码字译码信号；Step 2: Use system software programs or hardware to automatically manage execution and check codeword decoding signals;
    步骤三：依照实际运作状况，配合数据组件控制器运作挑选对应的矩阵来做运算，在错误位数低的需求下使用行权重低的矩阵，在错误位高的需求下使用行权重高的矩阵。Step 3: According to the actual operating conditions, cooperate with the data component controller to select the corresponding matrix for operation, use the matrix with low row weights when the number of error bits is low, and use the matrix with high row weights when the demand is high .
  2. 根据权利要求1所述的一种LDPC根据闪存组件错误率调变核编译码速率的方法，其特征在于：所述步骤一中主控芯片内部设置有低密度奇偶校验控制器及数据组件控制器。The method of LDPC according to claim 1 to adjust the core coding and decoding rate according to the error rate of the flash memory component, characterized in that: in step one, a low density parity check controller and data component control are provided inside the main control chip Device.
  3. 根据权利要求2所述的一种LDPC根据闪存组件错误率调变核编译码速率的方法，其特征在于：所述低密度奇偶校验控制器内部设置有校验位产生单元及检查纠错单元，所述校验位产生单元配置有若干生成矩阵，所述检查纠错单元配置有若干校验矩阵。The method of LDPC according to claim 2 to adjust the core coding and decoding rate according to the error rate of the flash memory component, characterized in that: the low density parity check controller is provided with a check bit generating unit and an error checking and correction unit , The check bit generating unit is configured with several generating matrices, and the error checking and correction unit is configured with several check matrices.
    根据权利要求2所述的一种LDPC根据闪存组件错误率调变核编译码速率的方法，其特征在于：所述数据组件控制器内部配置有若干数据组件。The method of LDPC according to claim 2 to adjust the core coding and decoding rate according to the error rate of the flash memory component, wherein the data component controller is internally configured with a number of data components.
PCT/CN2018/115508 2018-10-24 2018-11-14 Method for adjusting ldpc encoding and decoding rate of kernel according to flash memory component error rate WO2020082447A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811247400.7 2018-10-24
CN201811247400.7A CN109379087B (en) 2018-10-24 2018-10-24 Method for LDPC to modulate kernel coding and decoding rate according to error rate of flash memory component

Publications (1)

Publication Number Publication Date
WO2020082447A1 true WO2020082447A1 (en) 2020-04-30

Family

ID=65401983

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/115508 WO2020082447A1 (en) 2018-10-24 2018-11-14 Method for adjusting ldpc encoding and decoding rate of kernel according to flash memory component error rate

Country Status (2)

Country Link
CN (1) CN109379087B (en)
WO (1) WO2020082447A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111611195A (en) * 2019-02-26 2020-09-01 北京知存科技有限公司 Software-definable storage and calculation integrated chip and software definition method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1976238A (en) * 2006-12-21 2007-06-06 复旦大学 Method for constituting quasi-circulating low-density parity check code based on block fill algorithm
US20130139038A1 (en) * 2010-08-06 2013-05-30 Panasonic Corporation Error correcting decoding device and error correcting decoding method
CN107424199A (en) * 2017-08-07 2017-12-01 联通系统集成有限公司河南省分公司 It is a kind of to figure encryption correcting data error and detection method
CN108449090A (en) * 2018-01-25 2018-08-24 西安电子科技大学 A kind of configurable multi-code is long, multi code Rate of Chinese character ldpc decoder

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7222289B2 (en) * 2002-09-30 2007-05-22 Certance Llc Channel processor using reduced complexity LDPC decoder
KR101058324B1 (en) * 2003-02-26 2011-08-22 콸콤 인코포레이티드 Method and apparatus for performing low density parity check (LDPC) code operations using multi-level permutation
CN101471672B (en) * 2007-12-27 2011-04-13 华为技术有限公司 Method for generating check matrix and corresponding encoding method and encoder
JP5535220B2 (en) * 2008-09-30 2014-07-02 エルエスアイ コーポレーション Method and apparatus for soft data generation for memory devices using decoder performance feedback
US8312346B2 (en) * 2009-05-01 2012-11-13 Mirics Semiconductor Limited Systems and methods for communications
TWI530959B (en) * 2014-06-17 2016-04-21 慧榮科技股份有限公司 Method for controlling a memory apparatus, and associated memory apparatus thereof and associated controller thereof
US20160164537A1 (en) * 2014-12-08 2016-06-09 Samsung Electronics Co., Ltd. Method and apparatus for parallel concatenated ldpc convolutional codes enabling power-efficient decoders

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1976238A (en) * 2006-12-21 2007-06-06 复旦大学 Method for constituting quasi-circulating low-density parity check code based on block fill algorithm
US20130139038A1 (en) * 2010-08-06 2013-05-30 Panasonic Corporation Error correcting decoding device and error correcting decoding method
CN107424199A (en) * 2017-08-07 2017-12-01 联通系统集成有限公司河南省分公司 It is a kind of to figure encryption correcting data error and detection method
CN108449090A (en) * 2018-01-25 2018-08-24 西安电子科技大学 A kind of configurable multi-code is long, multi code Rate of Chinese character ldpc decoder

Also Published As

Publication number Publication date
CN109379087A (en) 2019-02-22
CN109379087B (en) 2022-03-29

Similar Documents

Publication Publication Date Title
US10191804B2 (en) Updating reliability data
KR102308935B1 (en) Error correction code (ecc) selection in nand flash controllers with multiple error correction codes
TWI626830B (en) Low-density parity check decoder and associated power saving method
US9319073B2 (en) Mitigation of write errors in multi-level cell flash memory through adaptive error correction code decoding
CN102624403B (en) Method and system for the efficient decoding to cascading error correcting code
US8245111B2 (en) Performing multi-bit error correction on a cache line
US9214963B1 (en) Method and system for monitoring data channel to enable use of dynamically adjustable LDPC coding parameters in a data storage system
US11086716B2 (en) Memory controller and method for decoding memory devices with early hard-decode exit
WO2012042444A1 (en) Decoding in solid state memory devices
US11275646B1 (en) Solid-state drive error recovery based on machine learning
US10009045B2 (en) Decoding method, memory controlling circuit unit and memory storage device
KR20180031572A (en) Method of operating memory device, memory device using the same and memory system including the device
US20180166142A1 (en) Flash command that reports a count of cell program failures
WO2020082447A1 (en) Method for adjusting ldpc encoding and decoding rate of kernel according to flash memory component error rate
US20150149856A1 (en) Decoding with log likelihood ratios stored in a controller
US10289348B2 (en) Tapered variable node memory
WO2020124980A1 (en) Adaptive polar code error correction code system and method used for flash memory controller
KR102004928B1 (en) Data storage device and processing method for error correction code thereof
US20180351577A1 (en) Iteration-adaptive decoding for non-binary ldpc codes
CN103354101B (en) A kind of LDPC code decoding device for flash memory error correction
US20190324849A1 (en) Error correction circuit and memory system including the same
WO2020082448A1 (en) Flash memory component error rate modulation core coding/decoding rate power saving method
CN109347490A (en) One kind decoding core master control set for correcting data error ECC
CN112256473A (en) Self-adaptive error correction method for distributed storage system
TWI836558B (en) Memory controller and method for controlling data in decoding pipeline

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18937652

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18937652

Country of ref document: EP

Kind code of ref document: A1