WO2012151725A1 - 一种半导体存储器结构及其控制方法 - Google Patents

一种半导体存储器结构及其控制方法 Download PDF

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Publication number
WO2012151725A1
WO2012151725A1 PCT/CN2011/001353 CN2011001353W WO2012151725A1 WO 2012151725 A1 WO2012151725 A1 WO 2012151725A1 CN 2011001353 W CN2011001353 W CN 2011001353W WO 2012151725 A1 WO2012151725 A1 WO 2012151725A1
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Prior art keywords
semiconductor memory
voltage
memory structure
effect transistor
field effect
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PCT/CN2011/001353
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English (en)
French (fr)
Inventor
王鹏飞
孙清清
张卫
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Fudan University
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Fudan University
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Priority to US13/501,833 priority Critical patent/US20140003122A1/en
Publication of WO2012151725A1 publication Critical patent/WO2012151725A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H10B63/34—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors of the vertical channel field-effect transistor type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8836—Complex metal oxides, e.g. perovskites, spinels

Definitions

  • the present invention relates to the field of semiconductor non-volatile memory technologies, and in particular, to a semiconductor memory structure and a control method thereof, and more particularly to a semiconductor memory structure using a self-aligned process and a control method thereof.
  • BACKGROUND OF THE INVENTION With the continuous development of microelectronic technology, the development of integrated circuit chips basically follows Moore's Law, that is, the integration degree of semiconductor chips increases at a rate that doubles every 18 months, which makes the design of integrated circuits toward the system on chip.
  • the direction of integration (SOC) is developing, and a key technology for implementing SOC is the integration of low-power, high-density, fast-access on-chip memory.
  • phase change memory stores data by utilizing the large difference in conductivity of the sulfur compound in the crystalline and amorphous states.
  • the phase change chalcogenide exhibits a reversible phase transition when it is turned from the amorphous phase to the crystalline phase. In the amorphous phase, the material is highly disordered and there is no lattice structure of the crystal.
  • phase change memory utilizes the impedance difference between the two phases.
  • the intense heat generated by current injection can initiate a phase change in the material.
  • the material properties after phase change are determined by the current, voltage and operating time of the injection.
  • 1 is a cross-sectional view of a typical phase change memory cell. As shown in FIG. 1, a layer of chalcogenide compound 100 is sandwiched between a top electrode 105 and a bottom electrode 101, and a heating resistor 102 extending from the bottom electrode 101 is shown. The chalcogenide layer 100 is contacted.
  • phase change memory cell 106 includes a transistor 107 and a phase change element 108, and a source/drain of the transistor 107 (S/D). Grounding, and another S/D of transistor 107 is coupled to one end of phase change element 108.
  • phase change element 108 The gate of the transistor 107 is connected to the gate voltage V G .
  • the other end of phase change element 108 is coupled to bit line voltage V Bl _.
  • bit line voltage V Bl _ Access to the storage in phase change element 108
  • voltage V G is applied to transistor 107 and transistor 107 is turned on, and bit line voltage V BL is applied to phase change element 108 such that a read current passes through phase change element 108 and transistor 107.
  • the data stored in the phase change element 120 is read.
  • Phase change memories offer faster write and erase speeds and better scaling than traditional Flash floating gate memories.
  • the reading and writing of information of the resistive memory is realized by reading or changing the resistance of the resistive material.
  • FIG. 3 is a schematic diagram of the basic structure of a resistive memory.
  • a resistance change memory layer 110 is provided between the upper electrode 109 and the lower electrode 111.
  • the upper electrode 109 and the lower electrode 111 generally use a metal material having a relatively stable chemical property such as Pt and Ti, and the resistance change memory layer 110 is usually a binary or ternary metal oxide such as Ti0 2 , ZrO, Cu 2 0 and SrTiO 3 .
  • the resistance value of the resistance change memory layer 110 can have two unused states under the applied voltage, that is, a high resistance state and a low resistance state, which can be respectively used to characterize "0" and "two states.
  • the resistance value of the resistive memory can be reversibly converted between the high resistance state and the low resistance state, thereby realizing the function of information storage.
  • the high resistance state storage is generally defined. Bit binary information 0, low resistance state stores one bit binary information 1. Since the initial resistance state of the resistive material is high resistance state, the operation of writing 1 to the information bit (corresponding to the resistance material changing from high resistance state to low) The resistance state is defined as the write operation, and the operation of writing 0 to the information bit (corresponding to the resistance material changing from low resistance state to high resistance state) is defined as the erase operation.
  • the device write operation is generally required at the top electrode and A short voltage pulse of approximately 1-5V is applied between the bottom electrodes, and an appropriate maximum current limit is set to avoid the device being abruptly increased by several orders of magnitude due to a sudden increase in current during the transition from high impedance to low resistance.
  • Lost The erase operation of the device generally requires the application of a short voltage pulse of approximately 0.5-1 V in the same or opposite direction as the write voltage.
  • the voltage pulse width for writing and erasing ranges from tens of nanoseconds to hundreds of microseconds. The unequal, depending on the characteristics of the specific resistive material.
  • the erase voltage width is generally larger than the write pulse width.
  • the reading of the device memory information can be achieved by applying a small voltage of about 0.2V and detecting the corresponding current.
  • the resistivity is independent of the size of the material, so theoretically the memory performance of the resistive memory does not degrade as the device size shrinks. This determines the potential integration capability of the resistive memory is much higher than the current mainstream Flash float.
  • the resistive memory device has a simple structure and can be easily integrated with existing CMOS production processes. However, both phase change memory and resistive memory require a large erasing current, so special The array access device erases the same.
  • the disclosure of the invention aims to provide a semiconductor memory structure, the semiconductor memory The memory structure may employ a special array access device for performing operations on reading, writing, etc. of the semiconductor memory.
  • the present invention provides a semiconductor memory structure
  • the semiconductor memory structure includes a variable resistance memory cell and a tunneling field effect transistor structure for operating the semiconductor memory; wherein the tunneling field effect transistor includes a source, a drain, and a low doping a channel region and a gate; the gate of the tunneling field effect transistor is connected to any one of the plurality of word lines, and the source thereof is connected to any one of the plurality of source lines, and the variable resistor thereof Both ends are connected to the bit line and the drain of the tunneling field effect transistor, respectively.
  • the method of controlling such a semiconductor memory structure includes three steps of resetting, setting, and reading.
  • the step of resetting the semiconductor memory structure is: applying a first voltage to a source line connected to the semiconductor memory; applying a second voltage to a word line connected to the semiconductor memory structure; A third voltage is applied to the bit lines connected to the memory structure; thereby causing the pn junction diode of the tunneling field effect transistor in the semiconductor memory structure to be forward biased, the semiconductor memory structure being reset, and the resistance thereof becoming large.
  • the first voltage ranges from 0.1 V to 4 V; the second voltage ranges from -1 V to 1 V; and the third voltage ranges from 0 V to 3 V.
  • the step of setting the semiconductor memory structure is: applying a fourth voltage to a source line connected to the semiconductor memory structure; applying a fifth voltage to a word line connected to the semiconductor memory structure; The bit line connected to the semiconductor memory structure applies a sixth voltage; thereby causing the semiconductor memory structure to be set, and the resistance thereof becomes small.
  • the fourth voltage ranges from 0 V to -3 V; the fifth voltage ranges from 0 V to 10 V; and the sixth voltage ranges from 0.1 V to 3 V.
  • the step of reading the semiconductor memory structure is: applying a seventh voltage to a source line connected to the semiconductor memory structure; applying an eighth voltage to a word line connected to the semiconductor memory structure; The bit line connected to the semiconductor memory structure applies a ninth voltage; thus, based on the magnitude of the output current, data stored in the semiconductor memory structure is selected for reading. Further, the seventh voltage ranges from 0 V to -3 V; the eighth voltage ranges from 0 V to 10 V; and the ninth voltage ranges from 0.1 V to 2 V.
  • the drain of the tunneling field effect transistor in the semiconductor memory structure proposed by the present invention is on the top of a platform structure perpendicular to the horizontal surface, the platform structure is a semiconductor substrate material, and the source is in the In the substrate extending outward from the bottom of the platform structure, the low doped channel region is between the drain and the source, and the gate covers the portion below the low doped region of the platform structure.
  • the semiconductor substrate is monocrystalline silicon, polycrystalline silicon or silicon on insulator (SOI).
  • the gate is a stacked structure comprising at least one conductive layer and an insulating layer separating the conductive layer from the semiconductor substrate; the conductive layer is polysilicon, amorphous silicon, tungsten metal, Titanium nitride, tantalum nitride or metal silicide, the insulating layer being Si0 2 , Hf0 2 , HfSiO, HfSiON, SiON or Al 2 0 3 , or a mixture of several of them.
  • the gate conductive layer surrounds the vertical low doped channel region to form a sidewall structure, and the variable resistance memory cell is composed of a phase change material or a resistive material.
  • the device structure proposed by the present invention can also constitute an array of semiconductor memory structures.
  • Such a method of controlling an array of semiconductor memory structures may first reset a plurality of memories in a semiconductor memory array and then set individual memories therein.
  • the control method of the semiconductor memory structure of the present invention uses a tunneling field effect transistor to perform erasing, reading and the like on the semiconductor memory structure, and the vertical gate-controlled diode structure in the tunneling field effect transistor can satisfy not only the resistive memory and
  • the phase change memory requires a large current for writing, and can increase the density of the memory device array, and is very suitable for the manufacture of a semiconductor memory chip, and the control method and the control circuit thereof are also relatively simple.
  • BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view of a typical phase change memory cell.
  • FIG. 2 is a schematic equivalent circuit diagram of a phase change memory cell.
  • Figure 3 is a cross-sectional view of a typical resistive memory cell.
  • 4 is a top plan view of an embodiment of a semiconductor memory structure provided by the present invention.
  • FIG. 5 is a cross-sectional view showing an embodiment of a semiconductor memory structure according to the present invention.
  • FIG. 6 is an equivalent circuit diagram of an embodiment of a semiconductor memory structure according to the present invention.
  • FIG. 7 is an equivalent circuit diagram of resetting an embodiment of a semiconductor memory structure array control method according to the present invention.
  • FIG. 8 is an equivalent circuit diagram of a method for controlling a semiconductor memory array according to an embodiment of the present invention.
  • FIG. 9 is an equivalent circuit diagram of reading a semiconductor memory array control method according to an embodiment of the present invention.
  • the curves obtained by etching are generally characterized by being curved or rounded, but in the embodiments of the present invention, they are all represented by rectangles, and the representations in the figures are schematic, but this should not be construed as limiting the scope of the invention.
  • the terms wafer and substrate are used to be understood to include semiconductor wafers being processed, possibly including other thin film layers prepared thereon.
  • 4 is a top view of a control method of a semiconductor memory structure according to the present invention
  • FIG. 5 is a cross-sectional view showing a structure of a semiconductor memory provided by the present invention.
  • a semiconductor substrate 200 is provided as shown; n-type doped region 201 shown ions; 202 shown Si0 2 gate dielectric; high-k material 203 is illustrated gate dielectric; 204 shown in FIG.
  • the gate conductive layer such as TiN or TaN, the gate conductive layer 204 forms a sidewall structure around the vertical channel; 205 is polysilicon; and 202, 203, 204, and 205 are shown to form a tunneling field effect transistor.
  • a gate and the gate covers a channel of the device and the channel is perpendicular to a surface of the substrate on which the tunneling field effect transistor is located;
  • 206 is a p-type ion doped region;
  • 208 is shown by Si0 2 , Si 3 N 4 or an insulating layer composed of an insulating material mixed therebetween;
  • 208 is a memory cell composed of a phase change material or a resistive material for storing electric charge;
  • 209 is a memory cell 208
  • the connected metal electrodes may be TiN, Ti, Ta, or TaN.
  • the gate of the tunneling field effect transistor can control the current through the memory cell 208 to effect read and write operations on the memory cell 208.
  • FIG. 6 is an equivalent circuit diagram of a semiconductor memory structure control method according to the present invention.
  • the bit line BL is connected to the metal electrode 209
  • the word line WL is connected to the gate of the tunneling field effect transistor
  • the source line SL and the source or drain of the tunneling field effect transistor are connected.
  • a semiconductor memory array can be constructed from a plurality of semiconductor memories as shown in FIG. 5, and FIG. 7, FIG. 8, and FIG. 9 are equivalent circuit diagrams for resetting, setting, and reading a semiconductor memory array, respectively. Specifically, the step of resetting the semiconductor memory array is as shown in FIG.
  • the step of setting the semiconductor memory array is as shown in FIG. 8: a voltage of 0 V is applied to all of the source lines SL1 and SL2; a voltage of 0 V is applied to all of the word lines WL1, WL3, and WL4, and a voltage is applied to the word line WL2.
  • the step of reading the semiconductor memory array is as shown in FIG. 9: a voltage of 0 V is applied to all of the source lines SL1 and SL2; a voltage of 0 V is applied to all of the word lines WL1, WL3, and WL4, and a voltage of 3 V is applied to the word line WL2;
  • the bit line BL2 is applied with a voltage of 0.5V. Based on the magnitude of the current, the data stored in the memory cells shown in 302 of Fig. 9 can be read. To prevent the set operation, the voltage applied to the bit line WL in the reading step should be lower than the voltage applied to the bit line WL in the set step.
  • a vertical gate-controlled diode structure in a tunneling field effect transistor can not only satisfy a large current requirement for writing to a resistive memory and a phase change memory, but also can increase the density of a memory device array, and is highly suitable for use in The manufacture of a semiconductor memory chip, and the control method and control circuit thereof are also relatively simple.
  • many different embodiments can be constructed without departing from the spirit and scope of the invention. It is to be understood that the invention is not limited to the specific examples described in the specification, unless the scope of the claims.

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Description

一种半导体存储器结构及其控制方法
技术领域 本发明属于半导体非挥发性存储器技术领域， 具体涉及一种半导体存储 器结构及其控制方法， 特别涉及一种采用自对准工艺的半导体存储器结构及 其控制方法。 背景技术 随着微电子技术的不断发展， 集成电路芯片的发展基本上遵循摩尔定 律， 即半导体芯片的集成度以每 18个月翻一番的速度增长， 这使得集成电 路的设计朝着片上系统集成（SOC ) 的方向发展， 而实现 SOC的一个关键 技术就是低功耗、 高密度、 存取速度快的片上存储器的集成。 如今的集成电 路器件技术已经处于 30纳米左右， 但是传统浮栅（ Flash )存储器由于耦合 比和电压较高等问题， 艮难缩小到 30纳米以下， 因此新型的非挥发性存储 器的开发成为了当前研究的热点。 相变存储器和阻变存储器都可以作为新型 的存储器。 相变存储器（ phase change memory )是利用硫 <族化合物在晶态和非晶 态时的巨大导电性差异来存储数据的。 相变硫族化合物在由无定形相转向结 晶相时会表现出可逆的相变现象， 在无定形相时， 材料是高度无序的状态， 不存在结晶体的网格结构。 在此种状态下， 材料具有高阻抗和高反射率。 相 反地， 在结晶相， 材料具有规律的晶体结构， 具有低阻抗和低反射率。 相变 存储器利用的就是两相间的阻抗差。 由电流注入产生的剧烈的热量可以引发 材料的相变。 相变后的材料性质由注入的电流、 电压及操作时间决定。 图 1 为一个典型的相变存储器单元的剖面图，如图 1所示，一层硫族化合物层 100 夹在顶端电极 105与底端电极 101之间， 底端电极 101延伸出的加热电阻 102接触硫族化合物层 100。 电流注入加热电阻 102与硫族化合物层 100的 连接点后产生的焦耳热引起相变， 在晶体结构硫族化合物层 100中产生了无 定形相的区域 103， 区域 104为结晶向的区域， 由于反射率的差异， 无定形 相区域 103呈现如蘑菇菌盖的形状。 图 2为一个相变存储器单元的概要等效 电路图，如图 2所示，相变存储器单元 106包含 1个晶体管 107和一个相变 元件 108， 晶体管 107的一个源极 /漏极（S/D )接地， 且晶体管 107的另一 S/D与相变元件 108的一端连接。 晶体管 107的栅极与栅极电压 VG连接。 相变元件 108的另一端与位线电压 VBl_连接。要存取相变元件 108中的储存 的数据时， 电压 VG施加于晶体管 107, 且开启晶体管 107， 且位线电压 VBL 施加于相变元件 108, 使得一读取电流经过相变元件 108及晶体管 107。 基 于输出电流的大小，储存在相变元件 120的数据得以被读取。与传统的 Flash 浮栅存储器相比，相变存储器具有更快的写入和擦除速度和更好的缩放比例。 阻变存储器的信息读写是依靠读取或者改变阻变材料的电阻来实现的。 图 3为一个阻变存储器的基本结构示意图。 如图 3所示， 在上电极 109和下 电极 111之间， 设置有电阻转变存储层 110。 上电极 109和下电极 111通常 使用 Pt和 Ti等化学性质较稳定的金属材料， 电阻转变存储层 110通常为 Ti02、 ZrO、 Cu20和 SrTi03等二元或三元金属氧化物。 电阻转变存储层 110 的电阻值在外加电压作用下可以具有两种不用的状态， 即高阻态和低阻态， 其可以分别用来表征 "0" 和 " 两种状态。 在不同外加电压的作用下， 阻变存储器的电阻值在高阻态和低阻态之间可以实现可逆转换， 以此来实现 信息存储的功能。 在阻变存储器的读写操作中， 一般定义高阻态存储一位二 进制信息 0, 低阻态存储一位二进制信息 1。 由于阻变材料的初始阻态为高 阻态， 因此将向信息位写入 1的操作 （对应阻变材料由高阻态转为低阻态） 定义为写入操作， 而向信息位写入 0的操作（对应阻变材料由低阻态转为高 阻态）定义为擦除操作。 器件写入操作， 一般需要在顶电极和底电极之间施 加大约 1-5V的短电压脉冲， 并设置适当的最大电流限制， 以避免阻变材料 由高阻态转向低阻态的过程中由于电流突然增大数个量级而导致器件失效。 器件的擦除操作，一般需要施加与写入电压同向或反向的大约 0.5-1V的短电 压脉冲。 用于写入和擦除的电压脉冲宽度从数十纳秒到上百微秒不等， 视具 体的阻变材料特性而定。 擦除电压宽度一般大于写入脉冲宽度。 器件存储信 息的读取可以通过施加 0.2V左右的小电压并检测相应的电流大小实现。 由 于材料本身的电阻率与材料的尺度无关， 因此理论上阻变存储器的存储性能 并不会随着器件尺寸的缩小而退化。 这就决定了阻变存储器潜在的集成能力 远远高于当前主流的 Flash浮栅存储器。 另一方面， 阻变存储器的器件结构 简单， 可以非常容易地实现与现有的 CMOS生产工艺的集成。 但是相变存储器和阻变存储器都需要较大的擦写电流，因此需要特殊的 阵列存取器件对其进行擦写。 发明的公开 本发明的目的在于提出一种半导体存储器结构， 该半导体存储器结构可 以采用特殊的阵列存取器件来进行对半导体存储器读、 写等的操作。 为达到本发明的上述目的， 本发明提出了一种半导体存储器结构， 所述 半导体存储器结构包括一个电阻可变的存储单元和一个用于对半导体存储 器进行操作的隧穿场效应晶体管结构； 其中， 所述的隧穿场效应晶体管包括 一个源极、 一个漏极、 一个低掺杂沟道区和一个栅极； 所述隧穿场效应晶体 管的栅极与多条字线中的任意一条相连接， 其源极与多条源线中的任意一条 相连接， 其可变电阻的两端分别连至位线和所述隧穿场效应晶体管的漏极。 对这种半导体存储器结构的进行控制的方法包括复位、 置位、 读取三个 步骤。 对所述的半导体存储器结构的复位步骤为： 对与所述半导体存储器相连 的源线施加第一个电压； 对与所述半导体存储器结构相连的字线施加第二个 电压； 对与所述半导体存储器结构相连的位线施加第三个电压； 由此使所述 半导体存储器结构中隧穿场效应晶体管的 p-n结二极管被正向偏置， 该半导 体存储器结构被重置， 其阻值变大。 进一步地， 所述第一个电压的范围为 0.1 V到 4 V; 所述第二个电压的 范围为 -1 V到 1 V; 所述第三个电压的范围为 0 V到 3 V。 对所述的半导体存储器结构的置位步骤为： 对与所述半导体存储器结构 相连的源线施加第四个电压； 对与所述半导体存储器结构相连的字线施加第 五个电压； 对与所述半导体存储器结构相连的位线施加第六个电压； 由此使 所述半导体存储器结构被置位， 其阻值变小。
进一步地， 所述第四个电压的范围为 0 V到 -3 V； 所述第五个电压的 范围为 0 V到 10 V； 所述第六个电压的范围为 0.1 V到 3 V。 对所述的半导体存储器结构的读取步骤为： 对与所述半导体存储器结构 相连的源线施加第七个电压； 对与所述半导体存储器结构相连的字线施加第 八个电压； 对与所述半导体存储器结构相连的位线施加第九个电压； 由此， 基于输出电流的大小， 存储在半导体存储器结构中的数据被选中读取。 进一步地， 所述第七个电压的范围为 0 V到 -3 V； 所述第八个电压的 范围为 0 V到 10 V； 所述第九个电压的范围为 0.1 V到 2 V。 进一步地， 本发明提出的半导体存储器结构中的隧穿场效应晶体管的漏 极处于一个垂直于水平表面的平台结构的顶部， 该平台结构采用的是半导体 村底材料， 所述的源极处于所述平台结构底部向外延伸的衬底内， 所述的低 掺杂沟道区处于所述漏极与源极之间， 所述的栅极将该平台结构的低掺杂区 以下的部位覆盖以控制通过沟道区域的源极与漏极之间的电流大小。 所述的 半导体衬底为单晶硅、 多晶硅或者绝缘体上的硅 (SOI)。所述的栅极是一个叠 层结构， 其包括至少一个导电层和一个将所述导电层与所述半导体衬底隔离 的绝缘层； 所述的导电层为多晶硅、 无定形硅、 钨金属、 氮化钛、 氮化钽或 者金属硅化物， 所述的绝缘层为 Si02、 Hf02、 HfSiO、 HfSiON、 SiON 或 Al203， 或者它们之中几种的混合物。 所述的栅极导电层环绕在垂直的低掺杂沟道区周围形成边墙结构， 而电 阻可变的存储器单元由相变材料构成或者阻变材料构成。 由本发明所提出的器件结构 ,还可以组成一种半导体存储器结构的阵列。 这种半导体存储器结构的阵列的控制方法， 可以先对半导体存储器阵列中的 多个存储器进行复位， 再对其中的个别存储器进行置位。 本发明所述的半导体存储器结构的控制方法采用隧穿场效应晶体管进行 对半导体存储器结构的擦写、 读等操作， 隧穿场效应晶体管中垂直的栅控二 极管结构不仅可以满足对阻变存储器和相变存储器进行写入的大电流要求， 而且可以提高存储器件阵列的密度， 非常适用于半导体存储器芯片的制造， 而且， 其控制方法及控制电路也较为简单。 附图的简要说明 图 1为一个典型的相变存储器单元的剖面图。 图 2为一个相变存储器单元的概要等效电路图。 图 3为一个典型的阻变存储器单元的剖面图。 图 4为本发明提供的一种半导体存储器结构实施例的俯视图。 图 5为本发明提供的一种半导体存储器结构实施例的截面图。 图 6为本发明提供的一种半导体存储器结构实施例的等效电路图。 图 7为本发明提供的一个半导体存储器结构阵列控制方法实施例进行复 位的等效电路图。 图 8为本发明提供的一个半导体存储器阵列控制方法实施例进行置位的 等效电路图。 图 9为本发明提供的一个半导体存储器阵列控制方法实施例进行读取的 等效电路图。 实现本发明的最佳方式 下面将参照附图对本发明的一个示例性实施方式作详细说明。 在图中， 为了方便说明， 放大了或缩小了层和区域的厚度， 所示大小并不代表实际尺 寸。 参考图是本发明的理想化实施例的示意图， 本发明所示的实施例不应该 被认为仅限于图中所示区域的特定形状， 而是包括所得到的形状， 比如制造 引起的偏差。 例如刻蚀得到的曲线通常具有弯曲或圆润的特点， 但在本发明 实施例中， 均以矩形表示， 图中的表示是示意性的， 但这不应该被认为是限 制本发明的范围。 同时在下面的描述中， 所使用的术语晶片和衬底可以理解 为包括正在工艺加工中的半导体晶片，可能包括在其上所制备的其它薄膜层。 如图 4为本发明所提供的一种半导体存储器结构的控制方法的俯视图， 图 5为本发明所提供的一种半导体存储器结构的截面图。 如图 4和图 5, 所 示 200为提供的半导体衬底； 所示 201为 n型离子掺杂区域； 所示 202为 Si02栅介质； 所示 203为高 k材料栅介质； 所示 204为栅极导电层比如为 TiN或者 TaN， 栅极导电层 204环绕在垂直的沟道周围形成边墙结构； 所示 205为多晶硅； 所示 202、 203、 204和 205构成隧穿场效应晶体管的栅极， 而且， 该栅极覆盖器件的沟道且所述沟道与该隧穿场效应晶体管所处的衬底 表面垂直； 所示 206为 p型离子掺杂区域； 所示 208为由 Si02、 Si3N4或者 它们之间相混合的绝缘材料构成的绝缘层； 所示 208为由相变材料或者阻变 材料构成的用于存储电荷的存储单元；所示 209为与存储单元 208相连的金 属电极， 可以为 TiN、 Ti、 Ta、 或者 TaN。 隧穿场效应晶体管的栅极可以控 制通过存储器单元 208的电流， 而实现对存储器单元 208的读写操作。 图 6为本发明提供的一种半导体存储器结构控制方法的等效电路图。如 图 6所示， 位线 BL与金属电极 209相连接， 字线 WL与所述隧穿场效应晶 体管的栅极相连接， 源线 SL与所述隧穿场效应晶体管的源极或者漏极相连 接。 由多个如图 5所示的半导体存储器可以构成一个半导体存储器阵列，如 图 7、 图 8和图 9分别为对一个半导体存储器阵列进行复位、 置位和读取的 等效电路图。 具体的说， 对半导体存储器阵列进行复位的步骤如图 7: 对源线 SL1和 SL2全部施加电压 2V; 对字线 WL1、 WL2、 WL3和 WL4全部施加电压 0V; 对位线 BL1施加电压 0V， 对位线 BL2施加电压 2V。 由于 SL2= BL2=2V, 因此与 BL2相连的存储器中没有电流经过， 而 BL1=0V< SL1 =0V，因此与 BL1相连的隧穿场效应晶体管的 p-n被正向偏置， 有电流经过， 与 BL1相连的存储器被选中复位， 其电阻变大。 对半导体存储器阵列进行置位的步骤如图 8: 对源线 SL1和 SL2全部施加电压 0V; 对字线 WL1、 WL3和 WL4全部施加电压 0V, 对字线 WL2施加电压
3V; 对位线 BL1施加电压 1V, 对位线 BL2施加电压 0V。 由于 WL2=3V> SL1=0V,图 8中 301中所示的隧穿场效应晶体管的 p-n 被反向偏置， 301 中所示的存储器被选中置位， 其阻值变小。
对半导体存储器阵列进行读取的步骤如图 9: 对源线 SL1和 SL2全部施加电压 0V; 对字线 WL1、 WL3和 WL4全部施加电压 0V, 对字线 WL2施加电压 3V; 对位线 BL1和位线 BL2施加电压 0.5V。 基于电流的大小， 图 9中 302中所示的存储单元中储存的数据得以被 读取。 为防止置位操作， 读取步骤中施加在位线 WL的电压应比置位步骤中 施加在位线 WL的电压低。 工业应用性 根据本发明， 隧穿场效应晶体管中垂直的栅控二极管结构不仅可以满足 对阻变存储器和相变存储器进行写入的大电流要求 , 而且可以提高存储器件 阵列的密度， 非常适用于半导体存储器芯片的制造， 而且， 其控制方法及控 制电路也较为简单。 如上所述， 在不偏离本发明精神和范围的情况下， 还可以构成许多有很 大差别的实施例。 应当理解， 除了如所附的权利要求所限定的， 本发明不限 于在说明书中所述的具体实例。

Claims

权 利 要求
1、 一种半导体存储器结构， 其特征在于： 包括一个电阻可变的存储单 元和一个用于对半导体存储器进行操作的隧穿场效应晶体管结构； 其中， 所述的隧穿场效应晶体管包括一个源极、 一个漏极、 一个低掺杂 沟道区和一个栅极； 所述隧穿场效应晶体管的栅极与多条字线中的任意一条相连接， 其源极 与多条源线中的任意一条相连接， 其可变电阻的两端分别连至位线和所述隧 穿场效应晶体管的漏极。
2、 根据权利要求 1所述的半导体存储器结构， 其特征在于:所述的隧穿 场效应晶体管的漏极处于一个垂直于水平表面的平台结构的顶部， 该平台结 构采用的是半导体衬底材料， 所述的源极处于所述平台结构底部向外延伸的 衬底内， 所述的低掺杂沟道区处于所述漏极与源极之间， 所述的栅极将该平 台结构的低掺杂区以下的部位覆盖以控制通过沟道区域的源极与漏极之间的 电¾1大小。
3、 根据权利要求 1或 2所述的半导体存储器结构， 其特征在于:所述的 半导体衬底为单晶硅、 多晶硅或者绝缘体上的硅； 所述的栅极是一个叠层结 构， 其包括至少一个导电层和一个将所述导电层与所述半导体衬底隔离的绝 缘层； 所述的导电层为多晶硅、 无定形硅、 钨金属、 氮化钛、 氮化钽或者金 属硅化物， 所述的绝缘层为 Si02、 Hf02、 HfSiO、 HfSiON、 SiON或 Al203， 或者它们之中几种的混合物。
4、 根据权利要求 1或 2所述的半导体存储器结构， 其特征在于:所述的 栅极导电层环绕在垂直的低掺杂沟道区周围形成边墙结构； 所述的电阻可变 的存储器单元由相变材料构成或者阻变材料构成。
5、 如权利要求 1 至 4之一所述的半导体存储器结构的控制方法， 包括 复位、 置位、 读取操作； 其特征在于： 对所述的复位操作步骤如下： 对与所述半导体存储器结构相连的源线施加第一个电压； 对与所述半导体存储器结构相连的字线施加第二个电压； 对与所述半导体存储器结构相连的位线施加第三个电压； 由此使所述半导体存储器结构中隧穿场效应晶体管的 p-n结二极管被正 向偏置， 该半导体存储器结构被重置， 其阻值变大；
对所述的置位操作步骤如下： 对与所述半导体存储器结构相连的源线施加第四个电压； 对与所述半导体存储器结构相连的字线施加第五个电压； 对与所述半导体存储器结构相连的位线施加第六个电压； 由此使所述半导体存储器结构被置位， 其阻值变小； 对所述的读取操作步骤如下： 对与所述半导体存储器结构相连的源线施加第七个电压； 对与所述半导体存储器结构相连的字线施加第八个电压； 对与所述半导体存储器结构相连的位线施加第九个电压； 由此，基于输出电流的大小，存储在所述半导体存储器中的数据被读取。
6、 根据权利要求 5所述的控制方法， 其特征在于， 所述第一个电压的 范围为 0.1 V到 4 V； 所述第二个电压的范围为 -1 V到 1 V; 所述第三个电 压的范围为 0 V到 -3 V;
7、 根据权利要求 5所述的控制方法， 其特征在于， 所述第四个电压的 范围为 0 V到 -3 V； 所述第五个电压的范围为 0 V到 10 V； 所述第六个电 压的范围为 0.1 V到 3 V。
8、 根据权利要求 5所述的控制方法， 其特征在于， 所述第七个电压的 范围为 0 V到 -3 V; 所述第八个电压的范围为 0 V到 10 V; 所述第九个电 压的范围为 0.1 V到 2 V。
9、 一种半导体存储器结构的阵列， 其特征在于由权利要求 1 至 4之一 所述的半导体存储器结构组成。
10、 如权利要求 9所述的半导体存储器结构的阵列的控制方法， 其特征 在于， 先对半导体存储器阵列中的多个存储器进行复位， 再对其中的个别存 储器进行置位。
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