WO2012136000A1 - Glue filling method and device in the semiconductor package - Google Patents

Glue filling method and device in the semiconductor package Download PDF

Info

Publication number
WO2012136000A1
WO2012136000A1 PCT/CN2011/072462 CN2011072462W WO2012136000A1 WO 2012136000 A1 WO2012136000 A1 WO 2012136000A1 CN 2011072462 W CN2011072462 W CN 2011072462W WO 2012136000 A1 WO2012136000 A1 WO 2012136000A1
Authority
WO
WIPO (PCT)
Prior art keywords
primer
substrate
oven
flow
filling
Prior art date
Application number
PCT/CN2011/072462
Other languages
French (fr)
Chinese (zh)
Inventor
金鹏
卢基存
Original Assignee
北京大学深圳研究生院
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 北京大学深圳研究生院 filed Critical 北京大学深圳研究生院
Priority to PCT/CN2011/072462 priority Critical patent/WO2012136000A1/en
Priority to CN201180004482.2A priority patent/CN103109361B/en
Publication of WO2012136000A1 publication Critical patent/WO2012136000A1/en

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81053Bonding environment
    • H01L2224/8109Vacuum
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/8185Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/81855Hardening the adhesive by curing, i.e. thermosetting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83104Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus by applying pressure, e.g. by injection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83194Lateral distribution of the layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83986Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Definitions

  • the invention relates to a method and a device for filling a primer in a semiconductor package.
  • Surface mount is one of the most popular packaging methods for assembling electronic devices on substrates or printed circuit board PCBs.
  • the surface mount device is interconnected with a substrate using a plurality of metal solder joints (such as lead-tin alloy) with a gap between the mount device and the substrate.
  • metal solder joints such as lead-tin alloy
  • CTE coefficients of thermal expansion
  • stress and strain will occur in the solder joint when the temperature changes.
  • the stress and strain generated by the temperature change of the device during use will cause the solder joint to break and fail.
  • the common practice in the electronics industry is to fill the underfill material between the device and the substrate, thereby reducing the deformation and strain of the solder joint and improving the reliability life of the solder joint.
  • the packaging process of the underfill is often called Underfill.
  • Examples of electronics that require underfill include flip chip, chip scale package (CSP) and ball grid array (BGA) packages. Air gaps in other forms of packaging, such as voids between electronic device stacks, may also require padding.
  • flip chip package the active side of the semiconductor chip is "flip" and is mounted directly on the printed circuit board by ball joints.
  • the chip material is silicon, gallium arsenide, etc.
  • CTE is 2-4ppm/ °C
  • the substrate material is organic (such as FR-4, polyimide and BT, CTE is 20ppm/ °C ) or inorganic materials (such as alumina and low temperature co-fired ceramics, CTE 3-10 ppm / °C
  • CTE 3-10 ppm / °C
  • CSP chip scale package
  • BGA ball grid array
  • the semiconductor chip is mounted on a substrate made of a material such as BT, and the substrate is then connected to the printed circuit board PCB through solder joints.
  • the thermal expansion coefficient of the substrate and the printed circuit board is different, The gap between them also requires a primer fill, while the underfill fill can greatly increase the ability of the solder joint to withstand external mechanical stresses, such as the stress experienced by the mobile device when it falls to the ground.
  • Primer filling is a very time consuming process, and despite the many underfill processes such as no-flow and wafer-level processes, the traditional capillary flow underfill process still dominates today's industry.
  • a liquid primer material is applied to a printed circuit board PCB or a mounting device on a substrate with a pinhole or nozzle to heat the substrate to a temperature at which the primer can flow (eg, 70). -90 degrees Celsius) to reduce the viscosity of the underfill.
  • the primer flows and fills the gap between the device and the substrate.
  • the above process is performed on a heating table on the dispensing device.
  • the primer flows and fills the gap (such as 0.05).
  • the gap such as 0.05.
  • - 0.15mm flip chip and for 0.3 - 0.8 mm CSP takes longer.
  • the underfill flow takes longer than 15 seconds, and it takes longer for the larger device and the smaller gap to fill.
  • is the viscosity coefficient of the primer
  • L is the flow distance
  • h is the flow gap height
  • is the contact angle of the primer to the substrate.
  • Another major problem with the capillary flow underfill process is the presence of voids in the primer material, especially for large devices, smaller device and substrate gaps, and more solder joint devices.
  • the liquid primer material flows unevenly in the gap between the device and the substrate.
  • the flow velocity changes in the area with solder joints, and the flow near the edge of the device tends to be faster than the middle.
  • the surface environment of the device and the substrate changes.
  • the presence of flux and residue can change the flow rate of the primer. Air bubbles appear between the fast and slow flow areas of the primer, and the bubbles become voids after the primer cures.
  • the existence of the void not only changes the size of the primer, but also forms a pressure concentration point inside the primer, and moisture is easily accumulated in the cavity, which adversely affects the reliability of the device.
  • US Patent 5,998,242 "Vacuum assisted Underfill process and apparatus for semiconductor package Fabrication is about placing a vacuum chamber on a single device substrate.
  • the primer is applied around the device through a needle through the vacuum chamber and fills the gap between the device and the substrate.
  • the vacuum environment is beneficial to reduce air bubbles in the primer, but the vacuum chamber for the device and the special primer coating equipment are the difficulties of this method.
  • US Patent 6,653,172 Methods For providing void-free layers for semiconductor assemblies, a method for removing bubbles from a primer is described. Special pressurization equipment is also required.
  • the prior invention has mainly reduced the glue flow time of a single electronic device to improve the efficiency of the process.
  • a small cavity is pressed against the substrate of the device, and a vacuum or high pressure within the cavity accelerates the flow of the primer around the device and reduces air bubbles in the primer.
  • They have some major process and equipment difficulties, and the cavity needs to be customized for the size of the device. After the device is changed, the design of the cavity needs to change.
  • Another disadvantage is that although the primer flow time is reduced, However, it takes time to place a cavity on the device substrate and to evacuate or pressurize. The most important thing is that the underfill filling is still completed by one device and one device, and the overall process efficiency is not high. Therefore, there is an urgent need for a simple and versatile process and equipment, and at the same time, a high efficiency and void-free primer filling method can be achieved.
  • the main technical problem to be solved by the present invention is to provide a method and a device for filling a primer in a semiconductor device package, which can shorten the time consuming process of the underfill filling process.
  • the present technology takes a semiconductor device as an example, but can also be applied to other devices such as optoelectronics that require a primer filling process or even a top potting.
  • the present invention adopts the following technical solutions:
  • a primer filling method in a semiconductor package for filling a gap between a substrate and a semiconductor device packaged on the substrate comprising:
  • Primer coating applying a primer to the edge of the semiconductor device on the substrate by using a primer coating machine
  • Primer flow transferring the substrate coated with the primer into an oven, heating at a primer flow temperature until a primer is filled into a gap between the substrate and the semiconductor device;
  • Primer curing heating at the primer curing temperature until the primer cures.
  • the oven is maintained in a vacuum environment as the primer flows.
  • the advantage is that there is no void in the primer, and the vacuum furnace evacuates the air between the device and the substrate before the primer fills the gap. Even if the primer is filled before entering the vacuum furnace, the vacuum furnace will drive out the bubbles in the primer as long as the primer is not cured. Therefore, the process window of the present invention for bubble-free underfill filling is large.
  • the primer is applied along the periphery of the semiconductor device in a symmetrical manner as the primer is applied.
  • the substrate is tilted in the oven while the primer is flowing, and a surface is covered on the surface of the semiconductor device before the primer flows.
  • Adhesive layer Adhesive layer.
  • the primer comprises a liquid primer, a solid primer or a paste primer.
  • the liquid primer is applied to the substrate by a dropping process;
  • a solid primer it is applied to the substrate by means of heated needle coating and solid block placement; when the paste is applied, it is applied to the substrate by a printing process or a needle tube.
  • a batch process is used to simultaneously perform primer flow and solidification on a plurality of substrates.
  • the present invention also provides a primer filling device for a semiconductor package for filling a gap between a substrate and a semiconductor device packaged on the substrate, comprising:
  • a primer coating machine for applying a primer to an edge of a semiconductor device on the substrate
  • the oven is used to heat the primer on the substrate coated with the primer placed therein at a primer flow temperature until the primer is filled into the gap between the substrate and the semiconductor device;
  • the gum curing temperature heats the primer until the primer cures.
  • the oven for performing the flow of the primer is a vacuum oven or a vacuum reflow oven.
  • the oven for curing the primer is a hot plate, a conventional oven or a reflow oven.
  • the invention can effectively shorten the time required for the primer to flow, thereby reducing the time consumption of the primer filling process as a whole.
  • Figure 1 is a schematic diagram of a capillary flow underfill filling process commonly used in the industry today; wherein, Figure 1A It is a liquid primer coating process diagram on the dispenser; Figure 1B is a gap diagram of the substrate and the substrate gap flow on the dispenser; the substrate temperature is maintained at the temperature required for the primer to flow (eg 70-90 ° C); 1C is a cure diagram of the primer; the curing temperature is usually at a higher temperature (eg 125-165 ° C);
  • FIG. 2 is a process diagram of a capillary flow primer filling process in an embodiment of the present invention
  • FIG. 2A is a liquid primer coating process diagram on a dispenser
  • FIG. 2B is in an oven (vacuum oven or vacuum reflow oven, temperature 70) -90 ° C) the bottom glue flow fill chip and substrate gap diagram
  • Figure 2C is in the oven (vacuum oven or vacuum reflow oven) primer cure diagram
  • Figure 3 is a schematic view of the symmetrical coating process along the periphery of the device; wherein, Figure 3A is a top view of the primer uniformly coated around the device; Figure 3B It is a cross-sectional view of the primer evenly coated around the device.
  • the present invention relates to a method and apparatus for filling a primer in a device such as a semiconductor package.
  • the encapsulation herein refers to the interconnection of one or more semiconductor package devices to a printed circuit board substrate or a device using a bonding material such as solder.
  • the conventional underfill is applied to the edge of the package component on a machine, and the primer flows through the capillary in an air environment and fills the gap between the substrate and the device. Finally, The primer is cured in a conventional air heating furnace.
  • the main disadvantage of the conventional method is that the adhesive flow of a single component is long or the production efficiency is low, and voids are likely to occur due to the flow of the primer material in the air.
  • the present invention provides a high efficiency void-free primer filling method and apparatus, as follows:
  • a primer filling method in a semiconductor package for filling a gap between a substrate and a semiconductor device packaged on the substrate comprising:
  • Primer coating applying a primer to the edge of the semiconductor device on the substrate by using a primer coating machine
  • Primer flow transferring the substrate coated with the primer into an oven, heating at a primer flow temperature until a primer is filled into a gap between the substrate and the semiconductor device;
  • Primer curing heating at the primer curing temperature until the primer cures.
  • the primer used in the prior art is generally a liquid primer which is coated with a glue needle or a jet pump and controls the gantry along both sides of the device.
  • Asymtek's C-720 is an example of a liquid primer coater.
  • the primer may comprise a liquid primer, a solid primer or a paste primer, i.e., in addition to conventional liquid primers, the invention may also be filled with a paste and a solid primer material.
  • the liquid underfill material is applied to the substrate along the edge of the device by a machine dropping method, and the solid and paste underfill materials are directly placed and printed or coated on the substrate, respectively, and the primer can be like a conventional The process is placed on one or both sides of the device, and three or four sides of the device can be placed.
  • the heating plate of the dispenser may be heated or slightly heated in order to adhere the primer to the edge of the device. Since the viscosity of the primer is still large because it is not heated, the purpose of the present invention on the dispenser is that the gap between the device and the substrate does not flow or the flow distance is small.
  • Another possible state for the underfill used for filling is solid at room temperature (eg epoxy).
  • epoxy resin is that once cured, the viscosity will be very low and have a high proportion of inorganic fillers (such as 80% SiO2 particles). A higher proportion of filler has a lower coefficient of thermal expansion and higher reliability.
  • Solid primers are applied in two ways: (1) heated needle or nozzle coating (2) solid coating.
  • needle coating the primer is heated in a syringe to a medium temperature to melt into a liquid state. During coating, heating near the needle of the needle causes the primer to drip along the edge of the device. It can also be coated with a heated nozzle.
  • the primer falls on a substrate at room temperature or low temperature, it cools and solidifies into a solid.
  • the primer solid is first shaped into strips of the size of the base device, and the strip-shaped primer is placed along the device by a robot.
  • the substrate is usually heated or coated with a layer of bonding material to ensure adhesion of the primer to the substrate.
  • a paste primer is used, a template with a hole such as a steel plate may be printed on the substrate. It can also be applied by nozzle or nozzle.
  • the primer coating process of the present invention has the following three differences from the prior art primer coating process:
  • the printed circuit board substrate of the present invention may or may not be heated.
  • the substrate may not be heated or heated only to a temperature lower than that required for the flow of the primer (less than 70-90). °C). Therefore, the primer applied on the substrate has a low temperature and a high viscosity, which weakens the fluidity of the primer in the primer coating process.
  • the existing process generally adopts a liquid primer, and in addition to the liquid primer, the solid and paste primer can also be applied.
  • the primer can be applied along the four sides of the device, however in the prior art, the primer is applied only along one or both sides of the device to reduce bubble generation. Therefore, process engineers do not need to perform a large number of experiments to minimize bubbles, which are adjusted by the coating scheme and substrate temperature.
  • the needle cross section can be a small square shape.
  • An important parameter during coating is the size of the primer, which is equal to the volume of the gap between the device and the substrate plus the amount of primer required for the edge of the device.
  • the device is placed obliquely in the oven so that the primer on the surface flows to the side walls of the device and the gap between the device and the substrate is filled.
  • the upper surface of the device is first covered with a non-adhesive layer such as, for example, Teflon.
  • the primer flow is performed.
  • the flow and cure of the primer in the present invention is carried out in an oven in an air or vacuum environment.
  • the oven can for example be a separate reflow oven or an oven with three to seven heating zones and a moving belt.
  • the temperature profile of the primer flowing in the oven and curing is divided into two stages.
  • the primer flow temperature of the first stage (for example, 70 to 90) °C ) is to reduce the viscosity of the primer to promote the flow of the primer.
  • the primer is filled with a gap and heated to the second stage of the primer cure temperature (eg, 140-165 ° C)
  • the length of cure depends on the cure rate of the primer. As long as the primer can fill the gap before curing, a temperature profile of more than 2 stages of the oven can be used.
  • a simple conventional oven and reflow oven can be used for small device packages that are less prone to bubble formation.
  • a simple conventional oven and reflow oven can be used for small device packages that are less prone to bubble formation.
  • a vacuum oven, a vacuum reflow oven or a vacuum chamber for the flow and curing of the primer.
  • the device and PCB board will be transferred from the coating machine to the vacuum oven.
  • the starting temperature of the oven is a temperature between the room temperature and the gel flow temperature (for example, 70-90 ° C) or the primer flow temperature.
  • the oven is raised to the primer flow temperature and held for a period of time until the primer fills the gap between the device and the substrate and forms a fillet around the device.
  • the package is then baked or cured by UV curing at the base curing temperature (eg, 125-165 ° C) from the same vacuum oven or another conventional oven.
  • a vacuum furnace may or may not be used during the curing process.
  • the main purpose of the primer flow in a vacuum oven is to remove the air between the chip and the substrate before the primer fills the gap; and even if the primer has been coated and filled with gaps, two temperature gradients are used in the vacuum oven. The heating of the curve also drives the air away.
  • a vacuum reflow furnace can also be used in the present invention, and the device primer can be covered with a vacuum chamber in a certain area of the reflow furnace when flowing.
  • the primer-coated package is placed in a movable vacuum chamber, a batch of the package is placed, the vacuum chamber is evacuated, and then the temperature in the vacuum chamber is raised to the flow temperature of the glue, or the temperature in the vacuum chamber is initially Maintaining the flow temperature of the primer, it takes time for the substrate to heat up.
  • the primer is warmed up.
  • the oven is in a vacuum environment, and the flow of the primer is in a vacuum, thereby avoiding the air flow process.
  • the curing of the primer can be in any environment, and the baking machine can be a hot plate, a conventional oven or a reflow oven.
  • the primer For small devices (5mm or less), the primer should be applied along one or both sides of the device and the package placed in a conventional oven or reflow oven. Since small devices are less prone to bubble generation, vacuuming is generally not required.
  • the baking temperature is also a medium flow temperature and a higher curing temperature. Transfer the primer flow process from the dispenser to the oven, the primer flow time is reduced, and the process efficiency is improved.
  • the benefit of transferring the primer flow process from the dispenser to the oven is that it can significantly increase productivity and reduce equipment investment.
  • a plurality of substrates can be subjected to a primer flow and a filling gap in a batch process in an oven.
  • the flow of the primer can only be carried out one by one. For example, it takes 20 seconds to fill the gap of 100 flip chips, and the total time required on the dispenser will be 2000 seconds.
  • the primer cure can also be carried out in batch mode in an oven.
  • the present invention also achieves uniformity of the bottom glue volume around the device.
  • the edge of the device is filled with excess primer around the device. Its cross section is rounded, and the consistency of the fillet helps to improve reliability.
  • the cross section of the fillet is generally concave and convex if the primer is applied in excess.
  • the problem with conventional primers is that the primer is not uniform around the device because the primer is applied on one or both sides of the device, the primer flows from the coated edge to the uncoated edge, and the bottom is often coated with more primer. On uncoated edges. In the worst case, there is no coating edge without primer.
  • the current practice in the industry is to apply a layer of primer around the device after the primer is filled.
  • the present invention can apply a primer along the periphery of the device in a symmetrical manner during the application of the primer to ensure uniformity of the fillet at the edge of the device.
  • the present invention employs different machines to separately treat the primer coating and flow. This brings many advantages:
  • the primer material can be used in a wider form, and the substrate can be heated or slightly heated.
  • the substrate must be heated compared with the prior art to simplify the process or save energy.
  • the application of the primer along the periphery of the device in a symmetrical manner during the coating of the primer can ensure the consistency of the underfill at the end of the primer coating process, that is, at the end of the primer filling process.
  • the prior art requires an additional process to ensure this consistency.
  • the bottom glue flow in the oven can save the flow process time and save equipment investment, especially through the batch processing method to simultaneously process the bottom glue flow of multiple devices, can greatly reduce the overall underfill filling of a batch of devices time.
  • the oven into a vacuum environment to complete the flow of the primer in a vacuum, the possibility of voids in the filling of the primer can be greatly reduced.

Abstract

Glue (4) filling method and device in the semiconductor package is provided. The glue (4) is coated to one edge or four edges of semiconductor or chips on the substrate, the glue (4) is flowing between the chip and the substrate until the space is full filled. Several edges of device are coated glue (4) and the device is moved to the vacuum box, the glue (4) is batch flowing in the several devices so that the time of filling glue (4) is decreased and the production efficiency is increased. The glue (4) is solidified in the vacuum box and the air bubbles cancel during formed glue (4) time and the cavities cancel due to the gas volatilize during glue (4) solidified. The quality and the reliability of device glue (4) filling is increased.

Description

一种半导体封装中的底胶填充方法及设备  Primer filling method and device in semiconductor package 技术领域Technical field
本发明涉及一种半导体封装中的底胶填充方法及设备。 The invention relates to a method and a device for filling a primer in a semiconductor package.
背景技术Background technique
表面贴装是目前将电子器件组装在基板或印刷电路板PCB的最流行的封装方法之一。在这种封装中,表面贴装器件与基板采用多元化金属焊点(如铅锡合金)互连,在贴装器件与基板之间存在间隙。如果贴装器件与基板热膨胀系数(CTE)不同,在温度变化时焊点中会产生应力和应变,使用过程中器件温度变化产生的应力和应变将导致焊点疲劳断裂而失效。要解决这种可靠性问题,电子行业的共同做法是在器件与基板间隙填充底胶材料,从而减少焊点的变形和应变,提高焊点的可靠性寿命,底胶的封装过程通常被称为底部填充。Surface mount is one of the most popular packaging methods for assembling electronic devices on substrates or printed circuit board PCBs. In this package, the surface mount device is interconnected with a substrate using a plurality of metal solder joints (such as lead-tin alloy) with a gap between the mount device and the substrate. If the placement device and the substrate have different coefficients of thermal expansion (CTE), stress and strain will occur in the solder joint when the temperature changes. The stress and strain generated by the temperature change of the device during use will cause the solder joint to break and fail. To solve this reliability problem, the common practice in the electronics industry is to fill the underfill material between the device and the substrate, thereby reducing the deformation and strain of the solder joint and improving the reliability life of the solder joint. The packaging process of the underfill is often called Underfill.
需要底部填充的电子器件例子包括倒装芯片,芯片级封装(CSP)和球格阵列(BGA)封装等。其它形式的封装中的空气间隙(如电子器件叠加间的空隙)也可能需要填充底胶。在倒装芯片封装中,半导体芯片的有源面是“翻转”,通过球形焊点直接安装在印刷电路基板上。该芯片材料是硅、砷化镓等,其 CTE为2-4ppm/ ℃ ,基板材料是有机物(如FR-4、聚酰亚胺和BT, CTE为20ppm/ ℃ )或者无机材料(如氧化铝及低温共烧陶瓷,CTE为3-10 ppm/ ℃ ),由于芯片和基板之间热膨胀系数不匹配,工作中的温度变化会导致焊点上产生疲劳应力和应变,其结果是焊点断裂和焊点开路的发生。通常的做法是在芯片与基板的间隙处填充聚合物底胶。底胶填充有助于分散应力,减少焊接接头应变,从而提高焊点可靠性。在芯片级封装(CSP)和球格阵列(BGA)封装中,半导体芯片安装在由BT等材料制成的基板,基板再通过焊点与印刷电路板PCB连接。基板与印刷电路板的热膨胀系数不同, 它们之间的间隙也需要底胶填充,同时底胶填充可以大大提高焊点抵抗外部机械应力(如手机器件摔掉到地上时所受的应力)的能力。 Examples of electronics that require underfill include flip chip, chip scale package (CSP) and ball grid array (BGA) packages. Air gaps in other forms of packaging, such as voids between electronic device stacks, may also require padding. In a flip chip package, the active side of the semiconductor chip is "flip" and is mounted directly on the printed circuit board by ball joints. The chip material is silicon, gallium arsenide, etc. CTE is 2-4ppm/ °C, the substrate material is organic (such as FR-4, polyimide and BT, CTE is 20ppm/ °C ) or inorganic materials (such as alumina and low temperature co-fired ceramics, CTE 3-10 ppm / °C Because the thermal expansion coefficient between the chip and the substrate does not match, the temperature change during operation causes fatigue stress and strain on the solder joint, and the result is breakage of the solder joint and open circuit of the solder joint. It is common practice to fill the polymer primer at the gap between the chip and the substrate. The underfill fill helps to distribute stress and reduce weld joint strain, thereby improving solder joint reliability. In chip scale package (CSP) and ball grid array (BGA) packages, the semiconductor chip is mounted on a substrate made of a material such as BT, and the substrate is then connected to the printed circuit board PCB through solder joints. The thermal expansion coefficient of the substrate and the printed circuit board is different, The gap between them also requires a primer fill, while the underfill fill can greatly increase the ability of the solder joint to withstand external mechanical stresses, such as the stress experienced by the mobile device when it falls to the ground.
底胶填充是一个非常耗时的过程,尽管已出现多种底胶填充工艺如无流动与晶圆级工艺,但传统的毛细管流动底胶填充工艺在今天的工业界仍占主导地位。在传统的毛细管流动底胶填充工艺中,用针孔或喷嘴将液态的底胶材料涂在印刷电路板PCB或基板上的贴装器件四周,加热基板至一个底胶可以流动的温度(如70-90摄氏度)以降低底部填充胶的粘度。在毛细管力驱动下,底胶流动并填充器件与基板的间隙,以上工艺过程都是在点胶设备上的加热台上完成的。尽管底胶点滴的时间只需要一秒或更短,但是底胶流动及填充间隙(如0.05 - 0.15毫米的倒装芯片和为0.3 - 0.8毫米CSP)需要的时间较长。例如要填充一个10毫米的器件/基板间隙,底部填充流动的时间超过15秒,更大器件和更小间隙的底胶填充需要的时间更长。假设液态的底胶为牛顿液态,流动过程为二维层流,根据Navier-Stokos 方程,底胶的流动时间t为t= (3µL^2)/hrcosθ。其中µ是底胶的粘滞系数,L是流动距离,h是流动间隙高度,θ是底胶与基板的接触角度。底胶填充需要较长时间的原因除了单个器件中底胶的毛细血管流动速度慢以外,另一个主要原因是点胶机加热台的空间有限,器件又得在加热台上底胶流动结束后才能被移出点胶机,因而无法同时批处理大量器件,生产效率(以每小时底胶填充的器件UPH计)很低。底胶材料充满间隙之后,整个封装器件再移出点胶机, 到一个空气压力的烤箱和回流炉中以较高的底胶固化温度(如125-165 ℃ )进行加热固化,固化时间和温度取决于底部填充材料的性质。Primer filling is a very time consuming process, and despite the many underfill processes such as no-flow and wafer-level processes, the traditional capillary flow underfill process still dominates today's industry. In a conventional capillary flow underfill process, a liquid primer material is applied to a printed circuit board PCB or a mounting device on a substrate with a pinhole or nozzle to heat the substrate to a temperature at which the primer can flow (eg, 70). -90 degrees Celsius) to reduce the viscosity of the underfill. Driven by capillary force, the primer flows and fills the gap between the device and the substrate. The above process is performed on a heating table on the dispensing device. Although the time of the primer is only one second or less, the primer flows and fills the gap (such as 0.05). - 0.15mm flip chip and for 0.3 - 0.8 mm CSP) takes longer. For example, to fill a 10 mm device/substrate gap, the underfill flow takes longer than 15 seconds, and it takes longer for the larger device and the smaller gap to fill. Assume that the liquid primer is Newtonian and the flow is a two-dimensional laminar flow, according to Navier-Stokos Equation, the flow time t of the primer is t= (3 μL^2)/hrcosθ. Where μ is the viscosity coefficient of the primer, L is the flow distance, h is the flow gap height, and θ is the contact angle of the primer to the substrate. The reason why the primer filling takes a long time is not only the slow flow rate of the capillaries in the single device, but also the other reason is that the space of the dispenser heating table is limited, and the device has to be finished after the bottoming of the heating platform. Being removed from the dispenser, it is not possible to batch process a large number of devices at the same time, and the production efficiency (in terms of the UPH meter filled with glue per hour) is very low. After the primer material is filled with the gap, the entire packaged device is removed from the dispenser. Heat curing in an air pressure oven and reflow oven at a higher primer cure temperature (eg, 125-165 °C) depending on the nature of the underfill material.
阻碍毛细管流动底胶填充工艺广泛运用的因素除了上述的工艺耗时长, 特别是底胶流动并填满器件与基板间隙所需要的时间过长之外,且底胶流动填充过程是一个一个器件单独完成,空洞发生从而影响底胶填充的质量和可靠性也是因素之一。下面对此进行说明。Factors that hinder the widespread use of the capillary flow underfill process are in addition to the lengthy process described above. In particular, the time required for the primer to flow and fill the gap between the device and the substrate is too long, and the underfill flow filling process is one of the components separately, and the occurrence of voids affects the quality and reliability of the underfill filling. . This will be explained below.
毛细管流动底胶填充工艺的另一个主要问题是底胶材料中存在空洞,特别是对大的器件,较小的器件与基板间隙、以及较多焊点器件而言,空洞问题更为严重。液态的底胶材料在器件与基板的间隙中流动是不均匀的,在有焊点的区域流动速度变化,同时在靠近器件边缘的流动往往比中间快,另外器件和基板的表面环境变化如助焊剂和残留物的存在都可以改变底胶的流动速度。在底胶流动快与流动慢的区域之间就会出现气泡,气泡在底胶固化后就成为空洞。空洞的存在不仅改变了底胶体积,而且形成了底胶内部的压力集中点,同时湿气易在空洞中聚集,对器件的可靠性产生不良的影响。Another major problem with the capillary flow underfill process is the presence of voids in the primer material, especially for large devices, smaller device and substrate gaps, and more solder joint devices. The liquid primer material flows unevenly in the gap between the device and the substrate. The flow velocity changes in the area with solder joints, and the flow near the edge of the device tends to be faster than the middle. In addition, the surface environment of the device and the substrate changes. The presence of flux and residue can change the flow rate of the primer. Air bubbles appear between the fast and slow flow areas of the primer, and the bubbles become voids after the primer cures. The existence of the void not only changes the size of the primer, but also forms a pressure concentration point inside the primer, and moisture is easily accumulated in the cavity, which adversely affects the reliability of the device.
以往的专利已经有一些提高底胶填充工艺效率和空洞的方法和设备。工艺效率的提高主要是利用真空吸附或空气压力提高单个器件中底胶的流动速度,减少底胶填充的时间。Previous patents have had some methods and equipment to improve the efficiency and voids of the underfill process. The improvement of process efficiency is mainly to increase the flow speed of the primer in a single device by vacuum adsorption or air pressure, and reduce the filling time of the primer.
美国专利6,048,656《Void-free underfill of surface mounted chips》阐述了一种底胶的真空吸附工艺和设备,基板上贴装的半导体器件边缘用阻挡材料密封起来,留下一个底胶入口以及一个出口。在出口处抽真空,加速底胶的流动,并去除器件与基板间的空气,减少最后底胶中的空洞。阻挡层和真空的吸附工具需要根据器件的大小而改变。类似的真空吸附工艺是在美国专利7,791,209B2《Method of underfill air vent for flipchip BGA》中,不同的是底胶是通过在基板的中央钻出的一个小孔流出。底胶在器件边缘涂布,通过真空快速从基板的小孔中吸附出来。主要的工艺困难在于需要在基板钻孔以及需要额外设备收集真空吸附出来的底胶。 US Patent 6,048,656 "Void-free underfill of surface mounted Chips describes a vacuum adsorption process and equipment for the primer. The edge of the semiconductor device mounted on the substrate is sealed with a barrier material, leaving a primer inlet and an outlet. Vacuuming at the outlet accelerates the flow of the primer and removes air between the device and the substrate, reducing voids in the final primer. The barrier and vacuum adsorption tools need to be varied depending on the size of the device. A similar vacuum adsorption process is in US Patent 7,791,209B2 Method Of underfill air vent for flipchip In BGA, the difference is that the primer is discharged through a small hole drilled in the center of the substrate. The primer is applied to the edge of the device and quickly adsorbed from the small holes of the substrate by vacuum. The main process difficulty is the need to drill holes in the substrate and the need for additional equipment to collect the vacuum-adsorbed primer.
另外一个提高底胶流动速度和减少气泡的方法是提高器件外部的空气压力。美国专利5,203,076《Vacuum infiltration of underfill material for flip-chip devices》阐述了在倒装芯片基板上加一个空腔盖子,芯片周围涂布底胶后,先对空腔抽真空然后加压,驱动底胶的流动,该方法的一个缺点是同时需要真空和加压设备。另一个利用底胶流动两侧空气压力不同驱动底胶流动的专利是美国专利6,895,666 B2《Underfill system for semiconductor package》,在器件的底胶出口处通过空气流动造成一个低压,整个工艺设备也较复杂。Another way to increase the flow rate of the primer and reduce air bubbles is to increase the air pressure outside the device. US Patent 5,203,076 "Vacuum Infiltration of underfill material for flip-chip Devices describes the addition of a cavity cover on the flip-chip substrate. After applying the primer around the chip, the cavity is vacuumed and then pressurized to drive the flow of the primer. One disadvantage of this method is that vacuum is required at the same time. Pressurized equipment. Another patent that uses different air pressures on both sides of the primer to drive the flow of the primer is US Patent 6,895,666. B2 "Underfill system for semiconductor Package, a low pressure caused by air flow at the bottom rubber outlet of the device, and the entire process equipment is also complicated.
一些以往的发明专利仅仅减少底胶中的空洞。美国专利5,998,242《Vacuum assisted underfill process and apparatus for semiconductor package fabrication》是关于在单个器件基板上放一个真空腔,底胶通过一个穿透真空腔的针管涂布在器件的周围,再填满器件与基板的间隙。真空环境有利于减少底胶中的气泡,但针对器件定制的真空腔以及特别的底胶涂布设备是该方法的难点。美国专利6,653,172《Methods for providing void-free layers for semiconductor assemblies》说明了加压去除底胶气泡的方法, 同样需要特别的加压设备。 Some previous invention patents only reduce voids in the primer. US Patent 5,998,242 "Vacuum assisted Underfill process and apparatus for semiconductor package Fabrication is about placing a vacuum chamber on a single device substrate. The primer is applied around the device through a needle through the vacuum chamber and fills the gap between the device and the substrate. The vacuum environment is beneficial to reduce air bubbles in the primer, but the vacuum chamber for the device and the special primer coating equipment are the difficulties of this method. US Patent 6,653,172, Methods For providing void-free layers for semiconductor assemblies, a method for removing bubbles from a primer is described. Special pressurization equipment is also required.
综上所述,以往的发明主要是减少单个电子器件的底胶流动时间来提高工艺的效率。一个小空腔压在器件的基板上,空腔内的真空或高压加速器件周围底胶的流动和减少底胶中的气泡。它们有一些主要的工艺和设备的难点,需要针对器件的大小等特性定制空腔,器件改变以后,空腔的设计需要随之改变。另一个缺点是虽然底胶流动时间减少了, 但需要时间在器件基板上放空腔以及抽真空或加压。最主要的是底胶填充仍是一个器件接一个器件完成,总体工艺效率不高。因此迫切需要工艺和设备简单通用,并同时能达到高效率和无空洞的底胶填充方法。In summary, the prior invention has mainly reduced the glue flow time of a single electronic device to improve the efficiency of the process. A small cavity is pressed against the substrate of the device, and a vacuum or high pressure within the cavity accelerates the flow of the primer around the device and reduces air bubbles in the primer. They have some major process and equipment difficulties, and the cavity needs to be customized for the size of the device. After the device is changed, the design of the cavity needs to change. Another disadvantage is that although the primer flow time is reduced, However, it takes time to place a cavity on the device substrate and to evacuate or pressurize. The most important thing is that the underfill filling is still completed by one device and one device, and the overall process efficiency is not high. Therefore, there is an urgent need for a simple and versatile process and equipment, and at the same time, a high efficiency and void-free primer filling method can be achieved.
技术问题technical problem
本发明要解决的主要技术问题是,提供一种半导体器件封装中的底胶填充方法及设备,能够缩短底胶填充工艺的耗时。本技术以半导体器件为例,但同样也可以用于其它如光电子等需要底胶填充工艺甚至顶部灌胶的器件。 The main technical problem to be solved by the present invention is to provide a method and a device for filling a primer in a semiconductor device package, which can shorten the time consuming process of the underfill filling process. The present technology takes a semiconductor device as an example, but can also be applied to other devices such as optoelectronics that require a primer filling process or even a top potting.
技术解决方案Technical solution
为解决上述技术问题,本发明采用了如下技术方案: In order to solve the above technical problems, the present invention adopts the following technical solutions:
一种半导体封装中的底胶填充方法,用于在基板与封装在所述基板上的半导体器件之间的间隙填充底胶,包括: A primer filling method in a semiconductor package for filling a gap between a substrate and a semiconductor device packaged on the substrate, comprising:
底胶涂布:利用底胶涂布机器在所述基板上的半导体器件边缘涂布底胶; Primer coating: applying a primer to the edge of the semiconductor device on the substrate by using a primer coating machine;
底胶流动:将涂布好底胶的所述基板转移到烤箱中,以底胶流动温度进行加热,直至底胶填充到所述基板与所述半导体器件之间的间隙; Primer flow: transferring the substrate coated with the primer into an oven, heating at a primer flow temperature until a primer is filled into a gap between the substrate and the semiconductor device;
底胶固化:以底胶固化温度进行加热直至所述底胶固化。 Primer curing: heating at the primer curing temperature until the primer cures.
在本发明的一种实施例中,在所述底胶流动时,维持所述烤箱内为真空环境。 其优点是底胶中无空洞,真空炉在底胶填充间隙之前就将器件与基板间的空气排空。即使是在进入真空炉前底胶就已经填充了间隙,只要底胶未固化则真空炉也会将底胶中的气泡驱除。因此,本发明对无气泡底胶填充的工艺窗口是很大的。 In one embodiment of the invention, the oven is maintained in a vacuum environment as the primer flows. The advantage is that there is no void in the primer, and the vacuum furnace evacuates the air between the device and the substrate before the primer fills the gap. Even if the primer is filled before entering the vacuum furnace, the vacuum furnace will drive out the bubbles in the primer as long as the primer is not cured. Therefore, the process window of the present invention for bubble-free underfill filling is large.
在本发明的一种实施例中,底胶涂布时,以对称方式沿所述半导体器件四周涂布所述底胶。 In one embodiment of the invention, the primer is applied along the periphery of the semiconductor device in a symmetrical manner as the primer is applied.
在本发明的一种实施例中,在所述底胶流动时,所述基板被倾斜放在所述烤箱内,以及在所述底胶流动之前,在所述半导体器件表面先覆盖一层非粘性层。 In an embodiment of the invention, the substrate is tilted in the oven while the primer is flowing, and a surface is covered on the surface of the semiconductor device before the primer flows. Adhesive layer.
在本发明的一种实施例中,所述底胶包括液态底胶、固态底胶或者糊态底胶。 In one embodiment of the invention, the primer comprises a liquid primer, a solid primer or a paste primer.
在本发明的一种实施例中,液态底胶时,采用点滴工艺涂布到所述基板上; 固态底胶时,采用加热针管涂布和固体块放置的方法涂布到所述基板上;糊态底胶时,采用印刷工艺或针管涂布到所述基板上 。 In an embodiment of the present invention, the liquid primer is applied to the substrate by a dropping process; In the case of a solid primer, it is applied to the substrate by means of heated needle coating and solid block placement; when the paste is applied, it is applied to the substrate by a printing process or a needle tube.
在本发明的一种实施例中,在所述底胶流动和底胶固化中,采用批处理方式同时对多块基板进行底胶流动和固化。 In one embodiment of the present invention, in the primer flow and the primer curing, a batch process is used to simultaneously perform primer flow and solidification on a plurality of substrates.
本发明也提供了一种半导体封装中的底胶填充设备,用于在基板与封装在所述基板上的半导体器件之间的间隙填充底胶,包括: The present invention also provides a primer filling device for a semiconductor package for filling a gap between a substrate and a semiconductor device packaged on the substrate, comprising:
底胶涂布机,在所述基板上的半导体器件边缘涂布底胶; a primer coating machine for applying a primer to an edge of a semiconductor device on the substrate;
烤箱用于以底胶流动温度对置入其中的涂布好底胶的所述基板上的底胶进行加热,直至底胶填充到所述基板与所述半导体器件之间的间隙;以及以底胶固化温度对所述底胶进行加热直至所述底胶固化。 The oven is used to heat the primer on the substrate coated with the primer placed therein at a primer flow temperature until the primer is filled into the gap between the substrate and the semiconductor device; The gum curing temperature heats the primer until the primer cures.
在本发明的一种实施例中,所述 用于进行底胶流动的 烤箱为真空烤箱或真空回流炉。 In one embodiment of the invention, the oven for performing the flow of the primer is a vacuum oven or a vacuum reflow oven.
在本发明的一种实施例中,所述 用于底胶固化的 烤箱为热板、传统烤箱或回流炉。 In one embodiment of the invention, the oven for curing the primer is a hot plate, a conventional oven or a reflow oven.
本发明可以有效缩短底胶流动所需时间,从而从整体上减少底胶填充工艺的耗时。 The invention can effectively shorten the time required for the primer to flow, thereby reducing the time consumption of the primer filling process as a whole.
附图说明DRAWINGS
图 1是当前工业界普遍采用的毛细管流动底胶填充工艺图;其中,图1A 是在点胶机上液态底胶涂布工艺图;图1B是在点胶机上底胶流动填充芯片与基板间隙图;基板温度保持在底胶流动所需要的温度(如70-90℃);图1C是底胶固化图;固化温度通常在一个更高的温度(如125-165℃);Figure 1 is a schematic diagram of a capillary flow underfill filling process commonly used in the industry today; wherein, Figure 1A It is a liquid primer coating process diagram on the dispenser; Figure 1B is a gap diagram of the substrate and the substrate gap flow on the dispenser; the substrate temperature is maintained at the temperature required for the primer to flow (eg 70-90 ° C); 1C is a cure diagram of the primer; the curing temperature is usually at a higher temperature (eg 125-165 ° C);
图2是本发明实施例中的毛细管流动底胶填充工艺图;其中,图2A是在点胶机上液体底胶涂布工艺图;图2B是在烤箱中(真空烤箱或真空回流炉,温度70-90℃)底胶流动填充芯片与基板的间隙图;图2C是在烤箱中(真空烤箱或真空回流炉)底胶固化图;2 is a process diagram of a capillary flow primer filling process in an embodiment of the present invention; wherein, FIG. 2A is a liquid primer coating process diagram on a dispenser; FIG. 2B is in an oven (vacuum oven or vacuum reflow oven, temperature 70) -90 ° C) the bottom glue flow fill chip and substrate gap diagram; Figure 2C is in the oven (vacuum oven or vacuum reflow oven) primer cure diagram;
图 3是沿器件四周底胶对称涂布工艺图;其中,图3A是底胶沿器件四周均匀涂布的俯视图;图3B 是底胶沿器件四周均匀涂布的截面图。Figure 3 is a schematic view of the symmetrical coating process along the periphery of the device; wherein, Figure 3A is a top view of the primer uniformly coated around the device; Figure 3B It is a cross-sectional view of the primer evenly coated around the device.
本发明的实施方式Embodiments of the invention
下面通过具体实施方式结合附图对本发明作进一步详细说明。The present invention will be further described in detail below with reference to the accompanying drawings.
本发明涉及半导体封装等器件中底胶填充的方法与设备。本文中的封装是指利用焊料等连接粘结材料将一个或多个半导体封装器件与印刷电路板基板互连或器件之间的互连。参见图1,传统的底胶填充是在一台机器上将底胶涂在封装元器件边缘,底胶再在空气环境下通过毛细血管作用流动并填充到衬底与器件之间的间隙,最后底胶在传统的空气加热炉中固化。传统方法主要缺点是单个元器件的底胶流动工艺时间长或生产效率低,以及因在空气中流动底胶材料而容易出现空洞。为此,参见图2,本发明给出了一种高效率无空洞的底胶填充方法及设备,具体如下:The present invention relates to a method and apparatus for filling a primer in a device such as a semiconductor package. The encapsulation herein refers to the interconnection of one or more semiconductor package devices to a printed circuit board substrate or a device using a bonding material such as solder. Referring to Figure 1, the conventional underfill is applied to the edge of the package component on a machine, and the primer flows through the capillary in an air environment and fills the gap between the substrate and the device. Finally, The primer is cured in a conventional air heating furnace. The main disadvantage of the conventional method is that the adhesive flow of a single component is long or the production efficiency is low, and voids are likely to occur due to the flow of the primer material in the air. To this end, referring to FIG. 2, the present invention provides a high efficiency void-free primer filling method and apparatus, as follows:
一种半导体封装中的底胶填充方法,用于在基板与封装在所述基板上的半导体器件之间的间隙填充底胶,包括:A primer filling method in a semiconductor package for filling a gap between a substrate and a semiconductor device packaged on the substrate, comprising:
底胶涂布:利用底胶涂布机器在所述基板上的半导体器件边缘涂布底胶;Primer coating: applying a primer to the edge of the semiconductor device on the substrate by using a primer coating machine;
底胶流动:将涂布好底胶的所述基板转移到烤箱中,以底胶流动温度进行加热,直至底胶填充到所述基板与所述半导体器件之间的间隙;Primer flow: transferring the substrate coated with the primer into an oven, heating at a primer flow temperature until a primer is filled into a gap between the substrate and the semiconductor device;
底胶固化:以底胶固化温度进行加热直至所述底胶固化。Primer curing: heating at the primer curing temperature until the primer cures.
可以看到,在底胶填充工艺流程中,包括底胶涂布过程、底胶流动过程、底胶固化过程,下面分别予以说明。It can be seen that in the underfill filling process, including the primer coating process, the primer flow process, and the primer curing process, the following are respectively described.
1、底胶涂布 1, primer coating
现有技术中所用的底胶一般为液态底胶,是用胶针或喷泵和控制龙门沿器件上两侧进行涂布。Asymtek公司的C-720就是液体底胶涂布机的一个例子。The primer used in the prior art is generally a liquid primer which is coated with a glue needle or a jet pump and controls the gantry along both sides of the device. Asymtek's C-720 is an example of a liquid primer coater.
在本发明的一种实施例中,底胶可以包括液态底胶、固态底胶或者糊态底胶,即除了传统的液态底胶外,本发明还能运用糊态及固态底胶材料填充。一般的,液体底部填充材料是由机器点滴方法沿器件的边缘涂布到基板上,固体和糊状底部填充材料分别用直接放置和印刷或涂布到基板上器件的周围,底胶可以像传统的工艺一样放在器件的一边或两边,也可以放器件的三边或四边。并底胶涂布时,点胶机的加热板可以不加热或稍稍加热,目的是使底胶粘在器件的边缘。 因未被加热,底胶粘滞系数仍大,点胶机上本发明的目的是底胶在器件与基板之间的间隙不流动或流动距离较小。 In one embodiment of the invention, the primer may comprise a liquid primer, a solid primer or a paste primer, i.e., in addition to conventional liquid primers, the invention may also be filled with a paste and a solid primer material. Generally, the liquid underfill material is applied to the substrate along the edge of the device by a machine dropping method, and the solid and paste underfill materials are directly placed and printed or coated on the substrate, respectively, and the primer can be like a conventional The process is placed on one or both sides of the device, and three or four sides of the device can be placed. When the primer is applied, the heating plate of the dispenser may be heated or slightly heated in order to adhere the primer to the edge of the device. Since the viscosity of the primer is still large because it is not heated, the purpose of the present invention on the dispenser is that the gap between the device and the substrate does not flow or the flow distance is small.
用于填充的底胶另一种可能的状态时室温下为固体(例如环氧树脂)。环氧树脂的优点在于一旦被固化,粘度会非常低并具有高比例无机填充物(如80%的SiO2颗粒), 更高比例的填充物具有更低的热膨胀系数和更高的可靠性。Another possible state for the underfill used for filling is solid at room temperature (eg epoxy). The advantage of epoxy resin is that once cured, the viscosity will be very low and have a high proportion of inorganic fillers (such as 80% SiO2 particles). A higher proportion of filler has a lower coefficient of thermal expansion and higher reliability.
固体底胶涂布有两种方式:(1)加热的针管或喷嘴涂布(2)固态涂布。对于针管涂布,底胶在注射器中加热到一个中等温度熔化成液态。在涂布时,在针管针头附近加热使底胶沿着器件边缘点滴下来, 也可使用加热的喷嘴涂布。底胶落到室温或低温的基板上时便冷却凝固成固体。对于固态涂布方式,先将底胶固体定型成基底器件大小的条状,用机械手将条状底胶沿着器件放置。通常采用加热基板或在基板上涂一层粘结材料以确保底胶与基板的粘结。在采用糊状底胶时,可采用带孔的模板如钢板印刷到基板上, 也可用或喷嘴涂布。Solid primers are applied in two ways: (1) heated needle or nozzle coating (2) solid coating. For needle coating, the primer is heated in a syringe to a medium temperature to melt into a liquid state. During coating, heating near the needle of the needle causes the primer to drip along the edge of the device. It can also be coated with a heated nozzle. When the primer falls on a substrate at room temperature or low temperature, it cools and solidifies into a solid. For the solid-state coating method, the primer solid is first shaped into strips of the size of the base device, and the strip-shaped primer is placed along the device by a robot. The substrate is usually heated or coated with a layer of bonding material to ensure adhesion of the primer to the substrate. When a paste primer is used, a template with a hole such as a steel plate may be printed on the substrate. It can also be applied by nozzle or nozzle.
综上所述,本发明中的底胶涂布工艺与现有技术的底胶涂布工艺有以下3个不同点:In summary, the primer coating process of the present invention has the following three differences from the prior art primer coating process:
1、 本发明中的印刷电路板基材可以加热或不加热。在现有技术的工艺中,需要加热基板降低底胶黏度,促进底胶流动。在本发明中,可以不对基板加热或仅加热到低于底胶流动需要的温度(低于70-90 ℃ )。因此,基板上涂布的底胶温度低、粘度高,这减弱了底胶涂布工艺中底胶的流动性。1, The printed circuit board substrate of the present invention may or may not be heated. In the prior art process, it is necessary to heat the substrate to reduce the viscosity of the primer and promote the flow of the primer. In the present invention, the substrate may not be heated or heated only to a temperature lower than that required for the flow of the primer (less than 70-90). °C). Therefore, the primer applied on the substrate has a low temperature and a high viscosity, which weakens the fluidity of the primer in the primer coating process.
2、 现有工艺一般采用液态底胶,而本发明除液态底胶外,固态和糊状底胶也可以得到应用。2. The existing process generally adopts a liquid primer, and in addition to the liquid primer, the solid and paste primer can also be applied.
3、 本发明中,底胶可以沿器件的四边进行涂布,然而在现有工艺中,底胶只沿器件的一边或两边涂布以减少气泡产生。因此,工艺工程师并不需要为尽量减小气泡而进行大量的实验,通过涂布方案和衬底温度来进行调节。涂布时,胶针截面可以为小方形,涂布时的一个重要参数是底胶体积,它等于器件与基板间隙的体积加上器件边缘需要的底胶体积。 3, In the present invention, the primer can be applied along the four sides of the device, however in the prior art, the primer is applied only along one or both sides of the device to reduce bubble generation. Therefore, process engineers do not need to perform a large number of experiments to minimize bubbles, which are adjusted by the coating scheme and substrate temperature. When coating, the needle cross section can be a small square shape. An important parameter during coating is the size of the primer, which is equal to the volume of the gap between the device and the substrate plus the amount of primer required for the edge of the device.
在本发明中,有可能会使器件表面上也被涂布底胶。因此,将器件倾斜地放在烤箱中使表面上的底胶流动到器件的侧墙并将器件与基板间的间隙填充完。为防止底胶粘附到器件的表面,器件上表面需先覆盖一层非粘性层,例如如聚四氟乙烯。In the present invention, it is possible to apply a primer to the surface of the device as well. Therefore, the device is placed obliquely in the oven so that the primer on the surface flows to the side walls of the device and the gap between the device and the substrate is filled. To prevent the primer from adhering to the surface of the device, the upper surface of the device is first covered with a non-adhesive layer such as, for example, Teflon.
底胶涂布到PCB基板后,则要进行底胶流动。与在点胶机上加热台上底胶流动工艺不同,本发明中底胶的流动和固化都是在空气或真空环境的烤箱中进行。该烤箱例如可以是一个独立的回流炉或具有三到七个加热区和一个移动带的烤箱。底胶在烤箱中流动与固化的温度曲线分两个阶段。第一阶段的底胶流动温度(例如70~90 ℃ )是降低底胶粘度促进底胶流动。一旦底胶填充好间隙,被加热到第二阶段的底胶固化温度(如140-165℃),固化时间长短取决与底胶的固化速率。只要底胶在固化前能填充间隙,可以采用超过2阶段烤箱温度曲线。After the primer is applied to the PCB substrate, the primer flow is performed. Unlike the underfill flow process on a dispenser on a dispenser, the flow and cure of the primer in the present invention is carried out in an oven in an air or vacuum environment. The oven can for example be a separate reflow oven or an oven with three to seven heating zones and a moving belt. The temperature profile of the primer flowing in the oven and curing is divided into two stages. The primer flow temperature of the first stage (for example, 70 to 90) °C ) is to reduce the viscosity of the primer to promote the flow of the primer. Once the primer is filled with a gap and heated to the second stage of the primer cure temperature (eg, 140-165 ° C), the length of cure depends on the cure rate of the primer. As long as the primer can fill the gap before curing, a temperature profile of more than 2 stages of the oven can be used.
在底胶流动时,对于不易引发气泡的小器件封装,采用简单的传统烤箱和回流炉即可。而对于容易引发气泡的大器件封装,为了防止底胶流动中会产生气泡,可以采用将烤箱内维持为真空环境的方式,例如采用真空烤箱、真空回流炉或真空室进行底胶流动和固化。When the primer flows, a simple conventional oven and reflow oven can be used for small device packages that are less prone to bubble formation. For large device packages that are prone to bubble formation, in order to prevent bubbles from occurring in the flow of the primer, it is possible to maintain the vacuum in the oven, for example, using a vacuum oven, a vacuum reflow oven or a vacuum chamber for the flow and curing of the primer.
例如,底胶涂布完过后,器件和PCB板将从涂布机器上转移到真空烤箱中。烤箱的起始温度为室温到底胶流动温度(例如70-90℃)之间的某个温度或底胶流动温度。随后,将烤箱升至底胶流动温度并保持一段时间直到底胶填充完器件与基板的间隙并在器件周围形成圆角。最后,该封装体再由同一个个真空烤箱或另外的传统烤箱在底胶固化温度(例如125-165℃)进行烘烤或者经过紫外线固化。在固化过程中,可以使用也可以不使用真空炉。For example, after the primer is applied, the device and PCB board will be transferred from the coating machine to the vacuum oven. The starting temperature of the oven is a temperature between the room temperature and the gel flow temperature (for example, 70-90 ° C) or the primer flow temperature. Subsequently, the oven is raised to the primer flow temperature and held for a period of time until the primer fills the gap between the device and the substrate and forms a fillet around the device. Finally, the package is then baked or cured by UV curing at the base curing temperature (eg, 125-165 ° C) from the same vacuum oven or another conventional oven. A vacuum furnace may or may not be used during the curing process.
在真空烤箱中进行底胶流动的主要目的是在底胶填充间隙前将芯片与基板间的空气抽走;且即使已经将底胶涂布并填充了间隙,在真空烤箱中采用两个温度梯度曲线的加热方式也可以将空气赶走。真空回流炉同样可以应用于本发明中,器件底胶流动时可以在回流炉的某个区中用一个真空腔盖住。或者,将涂布好底胶的封装体放入可移动真空室,将一批封装体放置好,真空室开始抽空,然后将真空室内温度升到底胶流动温度,也可以真空室内温度一开始就维持在底胶流动温度,因基板升温需要时间,关键是底胶升温,在开始流动或流动很小距离时,烤箱处于真空环境中,底胶的流动过程处于真空中,从而避免了空气流动过程中的底胶气泡和固化后的空洞。最后底胶的固化可以在任何环境中,烘烤机器可以为热板,传统烤箱或回流炉。The main purpose of the primer flow in a vacuum oven is to remove the air between the chip and the substrate before the primer fills the gap; and even if the primer has been coated and filled with gaps, two temperature gradients are used in the vacuum oven. The heating of the curve also drives the air away. A vacuum reflow furnace can also be used in the present invention, and the device primer can be covered with a vacuum chamber in a certain area of the reflow furnace when flowing. Alternatively, the primer-coated package is placed in a movable vacuum chamber, a batch of the package is placed, the vacuum chamber is evacuated, and then the temperature in the vacuum chamber is raised to the flow temperature of the glue, or the temperature in the vacuum chamber is initially Maintaining the flow temperature of the primer, it takes time for the substrate to heat up. The key is that the primer is warmed up. When the flow or flow is small, the oven is in a vacuum environment, and the flow of the primer is in a vacuum, thereby avoiding the air flow process. The underlying bubble and the void after curing. Finally, the curing of the primer can be in any environment, and the baking machine can be a hot plate, a conventional oven or a reflow oven.
对于小器件(5mm或更少),底胶只要沿器件一边或两边涂布即可,然后将封装体放入传统烤箱或回流炉。由于小器件不易产生气泡,一般无需进行抽真空处理。烘烤温度也同样是一个中等的流动温度和一个较高的固化温度。将底胶流动工艺从点胶机上转移到烤箱中,底胶流动时间降低,工艺效率得到提升。For small devices (5mm or less), the primer should be applied along one or both sides of the device and the package placed in a conventional oven or reflow oven. Since small devices are less prone to bubble generation, vacuuming is generally not required. The baking temperature is also a medium flow temperature and a higher curing temperature. Transfer the primer flow process from the dispenser to the oven, the primer flow time is reduced, and the process efficiency is improved.
将底胶流动工艺从点胶机转移到烤箱中的好处是可以明显地提高生产效率并降低设备投资。此外,在底胶流动中,可以在烤箱中采用批处理方式对多块基板进行底胶流动和填充间隙。而在点胶机,底胶流动只能逐个进行。例如,对100个倒装芯片进行底胶填充间隙需要20秒钟,而在点胶机上所需的总时间将是2000秒。同样的,底胶固化也可以在烤箱中采用批处理方式进行。The benefit of transferring the primer flow process from the dispenser to the oven is that it can significantly increase productivity and reduce equipment investment. In addition, in the flow of the primer, a plurality of substrates can be subjected to a primer flow and a filling gap in a batch process in an oven. In the dispenser, the flow of the primer can only be carried out one by one. For example, it takes 20 seconds to fill the gap of 100 flip chips, and the total time required on the dispenser will be 2000 seconds. Similarly, the primer cure can also be carried out in batch mode in an oven.
除了高效率和无气泡的优点,本发明还能实现器件四周边缘底胶体积的一致性。器件边缘底胶圆角是多余的底胶围绕器件四周形成的,它的横截面是圆弧形,底胶圆角的一致性有助于提高可靠性。该圆角的横截面通常为凹形,如果底胶涂布过量则为凸形。传统底胶的问题是底胶在器件周围不均匀,因为底胶在器件的一边或最多两边涂布,底胶从涂布的边缘流向没有涂布的边缘,最后往往涂布边缘的底胶多于未有涂布的边缘。 最坏的情况下没有涂布边缘没有底胶。为了达到一致性,目前行业中的做法是在底胶填充后再在器件四周涂布一层底胶,然而这增加了工艺步骤,降低了效率。参见图3,本发明则可以在底胶涂布时以对称方式沿器件的四周涂布底胶而保证底胶在器件边缘圆角的一致性。In addition to the advantages of high efficiency and no bubble, the present invention also achieves uniformity of the bottom glue volume around the device. The edge of the device is filled with excess primer around the device. Its cross section is rounded, and the consistency of the fillet helps to improve reliability. The cross section of the fillet is generally concave and convex if the primer is applied in excess. The problem with conventional primers is that the primer is not uniform around the device because the primer is applied on one or both sides of the device, the primer flows from the coated edge to the uncoated edge, and the bottom is often coated with more primer. On uncoated edges. In the worst case, there is no coating edge without primer. In order to achieve consistency, the current practice in the industry is to apply a layer of primer around the device after the primer is filled. However, this increases the process steps and reduces the efficiency. Referring to Figure 3, the present invention can apply a primer along the periphery of the device in a symmetrical manner during the application of the primer to ensure uniformity of the fillet at the edge of the device.
不同于现有技术以点胶机一种设备完成整个底胶涂布和底胶流动工艺,本发明采用不同机器来分别处理底胶涂布和流动。这带来了诸多优势:Unlike the prior art which accomplishes the entire primer coating and primer flow process with a dispenser machine, the present invention employs different machines to separately treat the primer coating and flow. This brings many advantages:
1、底胶涂布时,可采用的底胶材料形式更广,并且可以对基板不进行加热或稍稍加热,相比于现有技术必须给基板加热可以简化工艺或节省耗能。此外,在底胶涂布时采用以对称方式沿器件的四周涂布底胶的方式可以在底胶涂布阶段即保证底胶填充工艺结束时的底胶圆角一致性。而现有技术需要增加工艺来保证该一致性。1. When the primer is coated, the primer material can be used in a wider form, and the substrate can be heated or slightly heated. The substrate must be heated compared with the prior art to simplify the process or save energy. In addition, the application of the primer along the periphery of the device in a symmetrical manner during the coating of the primer can ensure the consistency of the underfill at the end of the primer coating process, that is, at the end of the primer filling process. The prior art requires an additional process to ensure this consistency.
2、底胶流动在烤箱中进行,可以节省流动工艺耗时以及节约设备投资,尤其通过批处理方式同时处理多个器件的底胶流动工艺,更可大大减少一批次器件的总体底胶填充时间。此外,通过将烤箱内置为真空环境以在真空中完成底胶流动,可大大减少底胶填充中出现空洞的可能性。2, the bottom glue flow in the oven, can save the flow process time and save equipment investment, especially through the batch processing method to simultaneously process the bottom glue flow of multiple devices, can greatly reduce the overall underfill filling of a batch of devices time. In addition, by incorporating the oven into a vacuum environment to complete the flow of the primer in a vacuum, the possibility of voids in the filling of the primer can be greatly reduced.
以上内容是结合具体的实施方式对本发明所作的进一步详细说明,不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说,在不脱离本发明构思的前提下,还可以做出若干简单推演或替换,都应当视为属于本发明的保护范围。The above is a further detailed description of the present invention in connection with the specific embodiments, and the specific embodiments of the present invention are not limited to the description. It will be apparent to those skilled in the art that the present invention may be made without departing from the spirit and scope of the invention.

Claims (10)

  1. 一种半导体封装中的底胶填充方法,用于在基板与封装在所述基板上的半导体器件之间的间隙填充底胶,其特征在于,包括: A method for filling a primer in a semiconductor package for filling a gap between a substrate and a semiconductor device packaged on the substrate, characterized in that it comprises:
    底胶涂布:利用底胶涂布机器在所述基板上的半导体器件边缘涂布底胶;Primer coating: applying a primer to the edge of the semiconductor device on the substrate by using a primer coating machine;
    底胶流动:将涂布好底胶的所述基板转移到烤箱中,以底胶流动温度进行加热,直至底胶填充到所述基板与所述半导体器件之间的间隙;Primer flow: transferring the substrate coated with the primer into an oven, heating at a primer flow temperature until a primer is filled into a gap between the substrate and the semiconductor device;
    底胶固化:以底胶固化温度进行加热直至所述底胶固化。Primer curing: heating at the primer curing temperature until the primer cures.
  2. 如权利要求1所述的方法,其特征在于,在所述底胶流动时,维持所述烤箱内为真空环境。 The method of claim 1 wherein said oven is maintained in a vacuum environment as said primer flows.
  3. 如权利要求1所述的方法,其特征在于,底胶涂布时,以对称方式沿所述半导体器件四周涂布所述底胶。 The method of claim 1 wherein said primer is applied around said semiconductor device in a symmetrical manner during application of the primer.
  4. 如权利要求1所述的方法,其特征在于,在所述底胶流动时,所述基板被倾斜放在所述烤箱内,以及在所述底胶流动之前,在所述半导体器件表面先覆盖一层非粘性层。 The method of claim 1 wherein said substrate is tilted within said oven while said primer flows, and said semiconductor device surface is first covered prior to said primer flow A layer of non-adhesive layer.
  5. 如权利要求1所述的方法,其特征在于,所述底胶包括液态底胶、固态底胶或者糊态底胶。 The method of claim 1 wherein said primer comprises a liquid primer, a solid primer or a paste primer.
  6. 如权利要求5所述的方法,其特征在于,液态底胶时,采用点滴工艺涂布到所述基板上;固态底胶时,采用加热针管涂布和固体块放置的方法涂布到所述基板上;糊态底胶时,采用印刷工艺或针管涂布到所述基板上。 The method according to claim 5, wherein the liquid primer is applied to the substrate by a droplet process; and the solid primer is applied to the film by a method of heating needle coating and solid block placement. On the substrate; when the paste is applied, the substrate is coated by a printing process or a needle tube.
  7. 如权利要求1-6任一所述的方法,其特征在于,在所述底胶流动和底胶固化中,采用批处理方式同时对多块基板进行底胶流动和固化。 The method according to any one of claims 1 to 6, wherein in the primer flow and the primer curing, the substrate is simultaneously flowed and solidified by a batch process.
  8. 一种半导体封装中的底胶填充设备,用于在基板与封装在所述基板上的半导体器件之间的间隙填充底胶,其特征在于,包括: A primer filling device for a semiconductor package, wherein a gap between a substrate and a semiconductor device packaged on the substrate is filled with a primer, comprising:
    底胶涂布机,在所述基板上的半导体器件边缘涂布底胶; a primer coating machine for applying a primer to an edge of a semiconductor device on the substrate;
    烤箱,用于以底胶流动温度对置入其中的涂布好底胶的所述基板上的底胶进行加热,直至底胶填充到所述基板与所述半导体器件之间的间隙;以及以底胶固化温度对所述底胶进行加热直至所述底胶固化。 An oven for heating a primer on the substrate coated with the primer disposed therein at a primer flow temperature until a primer is filled into a gap between the substrate and the semiconductor device; The primer cures the primer until the primer cures.
  9. 如权利要求8所述的底胶填充设备,其特征在于,所述用于进行底胶流动的烤箱为真空烤箱或真空回流炉。 The primer filling apparatus according to claim 8, wherein the oven for performing the flow of the primer is a vacuum oven or a vacuum reflow furnace.
  10. 如权利要求8所述的底胶填充设备,其特征在于,所述用于底胶固化的烤箱为热板、传统烤箱或回流炉。 The primer filling apparatus according to claim 8, wherein the oven for curing the primer is a hot plate, a conventional oven or a reflow oven.
PCT/CN2011/072462 2011-04-06 2011-04-06 Glue filling method and device in the semiconductor package WO2012136000A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2011/072462 WO2012136000A1 (en) 2011-04-06 2011-04-06 Glue filling method and device in the semiconductor package
CN201180004482.2A CN103109361B (en) 2011-04-06 2011-04-06 Primer fill method in a kind of semiconductor packages and equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2011/072462 WO2012136000A1 (en) 2011-04-06 2011-04-06 Glue filling method and device in the semiconductor package

Publications (1)

Publication Number Publication Date
WO2012136000A1 true WO2012136000A1 (en) 2012-10-11

Family

ID=46968532

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2011/072462 WO2012136000A1 (en) 2011-04-06 2011-04-06 Glue filling method and device in the semiconductor package

Country Status (2)

Country Link
CN (1) CN103109361B (en)
WO (1) WO2012136000A1 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106449685A (en) * 2016-10-24 2017-02-22 江苏钜芯集成电路技术股份有限公司 Glue spraying technology for photosensitive chip packaging
CN106548951A (en) * 2016-11-25 2017-03-29 维沃移动通信有限公司 A kind of method for packing of fingerprint recognition module chip
CN107293498A (en) * 2017-07-03 2017-10-24 华进半导体封装先导技术研发中心有限公司 A kind of flip-chip preparation method
CN108260292A (en) * 2017-12-08 2018-07-06 江西合力泰科技有限公司 Increase the method for underfill coverage rate after a kind of SMT
CN110072347A (en) * 2019-04-09 2019-07-30 南昌嘉研科技有限公司 A kind of safeguard structure and its processing method of chip bga
CN113113325A (en) * 2021-04-08 2021-07-13 中国电子科技集团公司第二十四研究所 Bottom filling and encapsulating method for multi-chip flip-chip welding three-layer encapsulation structure
CN114554769A (en) * 2020-11-18 2022-05-27 英业达科技有限公司 Sealing method of server

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104569109B (en) * 2014-12-31 2018-01-02 武汉邮电科学研究院 A kind of chip structure and its integrated encapsulation method towards ISFET sensors
CN108108681A (en) * 2017-12-14 2018-06-01 江西合力泰科技有限公司 With high bio-identification module for resisting external force ability and preparation method thereof
CN108906527A (en) * 2018-06-04 2018-11-30 昆山丘钛微电子科技有限公司 A kind of glue fill method and glue curing method
US20230178445A1 (en) * 2021-12-06 2023-06-08 International Business Machines Corporation Underfill vacuum process
CN116705656B (en) * 2023-05-29 2024-03-22 武汉光启源科技有限公司 Method and device for directionally removing bubbles of glue at bottom

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6391683B1 (en) * 2000-06-21 2002-05-21 Siliconware Precision Industries Co., Ltd. Flip-chip semiconductor package structure and process for fabricating the same
CN1574255A (en) * 2003-05-22 2005-02-02 台湾积体电路制造股份有限公司 Flip chip assembly process and substrate used therewith and printed half-tone screen free from being stained with solder

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6703299B2 (en) * 2001-12-21 2004-03-09 Intel Corporation Underfill process for flip-chip device
JP2007141935A (en) * 2005-11-15 2007-06-07 Toray Eng Co Ltd Dispensing device and mounting system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6391683B1 (en) * 2000-06-21 2002-05-21 Siliconware Precision Industries Co., Ltd. Flip-chip semiconductor package structure and process for fabricating the same
CN1574255A (en) * 2003-05-22 2005-02-02 台湾积体电路制造股份有限公司 Flip chip assembly process and substrate used therewith and printed half-tone screen free from being stained with solder

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106449685A (en) * 2016-10-24 2017-02-22 江苏钜芯集成电路技术股份有限公司 Glue spraying technology for photosensitive chip packaging
CN106548951A (en) * 2016-11-25 2017-03-29 维沃移动通信有限公司 A kind of method for packing of fingerprint recognition module chip
CN107293498A (en) * 2017-07-03 2017-10-24 华进半导体封装先导技术研发中心有限公司 A kind of flip-chip preparation method
CN108260292A (en) * 2017-12-08 2018-07-06 江西合力泰科技有限公司 Increase the method for underfill coverage rate after a kind of SMT
CN110072347A (en) * 2019-04-09 2019-07-30 南昌嘉研科技有限公司 A kind of safeguard structure and its processing method of chip bga
CN114554769A (en) * 2020-11-18 2022-05-27 英业达科技有限公司 Sealing method of server
CN114554769B (en) * 2020-11-18 2024-03-22 英业达科技有限公司 Sealing method of server
CN113113325A (en) * 2021-04-08 2021-07-13 中国电子科技集团公司第二十四研究所 Bottom filling and encapsulating method for multi-chip flip-chip welding three-layer encapsulation structure

Also Published As

Publication number Publication date
CN103109361B (en) 2016-04-13
CN103109361A (en) 2013-05-15

Similar Documents

Publication Publication Date Title
WO2012136000A1 (en) Glue filling method and device in the semiconductor package
CN108133670B (en) Integrated packaging LED display module packaging method and LED display module
TWI413195B (en) Method and apparatus of compression molding for reducing viods in molding compound
CN108231607A (en) Chip packaging method and encapsulating structure
WO2012068762A1 (en) Ic chip package of sip system integration level and manufacturing method thereof
TW201707162A (en) Resin sealing apparatus and resin sealing method
JP2004296555A (en) Semiconductor device and method for manufacturing the same
CN105762084B (en) Packaging method and packaging device of flip chip
JP2005079577A (en) Manufacturing method for wafer level chip-size package, and molding equipment used for the same
US10504841B2 (en) Semiconductor package and method of forming the same
JP2011514686A (en) Method for bonding a chip on a wafer
JP4319759B2 (en) Resin sealing device and resin sealing method
TW201818482A (en) Resin-sealing device and resin-sealing method
JP2002110721A (en) Method for manufacturing semiconductor device
JP2004128286A (en) Chip-like electronic component and manufacturing method thereof, pseudo wafer used for the manufacturing and manufacturing method thereof, and mounting structure
JP2004282042A (en) Assembling method for semiconductor device
JP3561209B2 (en) Flip chip mounting binder and method of manufacturing semiconductor device using the same
CN111370337A (en) Method for reducing package warpage
JP2010092983A (en) Semiconductor device and method of manufacturing the same, and semiconductor manufacturing apparatus
JP2607877B2 (en) Method for manufacturing resin-reinforced LSI mounting structure
JP2001015534A (en) Manufacturing apparatus for semiconductor device and method of manufacturing the same
CN114566436A (en) Deep pad wafer-level preparation method for reducing wafer-level adhesive bonding bubbles
JP2006295186A (en) Integrated circuit packaging process through non-tape die attaching method
JP2004063524A (en) Apparatus and method for mounting or printed circuit board
CN110277323B (en) Negative pressure packaging process, structure and equipment for fan-out module

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 201180004482.2

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11863033

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11863033

Country of ref document: EP

Kind code of ref document: A1