WO2012129816A1 - 一种半导体存储器阵列及其编程方法 - Google Patents

一种半导体存储器阵列及其编程方法 Download PDF

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WO2012129816A1
WO2012129816A1 PCT/CN2011/072400 CN2011072400W WO2012129816A1 WO 2012129816 A1 WO2012129816 A1 WO 2012129816A1 CN 2011072400 W CN2011072400 W CN 2011072400W WO 2012129816 A1 WO2012129816 A1 WO 2012129816A1
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memory cells
programming
memory
array
adjacent
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French (fr)
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蔡一茂
黄如
唐粕人
秦石强
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Peking University
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Peking University
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Priority to US13/146,005 priority patent/US8593848B2/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts

Definitions

  • Nonvolatile memories represented by flash memories are widely used in various products such as mobile phones, notebooks, palmtop computers, and solid state hard disks because of their data retention capability in the event of power failure and the ability to erase data multiple times. Storage and communication equipment.
  • flash memory has occupied most of the market share of non-volatile semiconductor memory.
  • NOR flash memory is widely used in code memory chips of mobile terminals such as mobile phones because of its fast random reading speed.
  • the conventional NOR flash memory adopts the channel hot electron injection method.
  • the literature [1][2][3] uses a split-gate programming method to reduce power consumption.
  • This technique utilizes different voltages across the gate, ie, a lower voltage is applied to the gate near the source, and a high voltage is applied to the gate near the drain, thereby improving programming efficiency and thereby reducing power consumption.
  • the existing split-gate technology is designed for one unit, which brings about the complexity of the process, especially the programming voltage difference between the source and the drain of the memory cell, which limits the flash memory cell. The channel is reduced.
  • the literature [4][5] uses two adjacent cells on the same word line to participate in programming.
  • the bit line voltage thus programmed is shared by two adjacent cells, so that the source-drain pass-through problem of a single device can be effectively avoided.
  • this technique is based on a conventional NOR type array (shown in FIG. 1) or an NROM array.
  • the word lines and bit lines in the array are perpendicular to each other, so that two adjacent cells participating in programming share a word line. This word line controls the voltage of the control gate, so these arrays cannot be programmed with split gates, so there is a problem with programming power consumption limitations.
  • An array structure of a flash memory comprising: a plurality of memory cells, a word line connecting the control gates of the memory cells, a bit line connecting the drain terminals of the memory cells, the bit lines and the word lines are intersected at an angle, and the intersecting angle ranges from 0 Within ⁇ 180°, but not including 90, that is, the bit line and the word line are not perpendicular to each other.
  • Each of the two memory cells adjacent in the channel direction shares the source terminal, and the row-oriented word lines connect the control gates of all the memory cells in the same row in the array, and the bit lines connect the drain terminals of all the memory cells in the same column.
  • the control gates of two memory cells adjacent to each other between the two bit lines in the channel direction are respectively controlled by two adjacent word lines, and the drain terminals are respectively controlled by two bit lines, and the source terminals are shared.
  • the above array has no special requirements for the flash memory unit, and may be a floating gate type flash memory unit or a trap type flash memory.
  • the word line and bit line material may be a metal or a metal compound or a semiconductor material wire.
  • a method of programming a flash memory that utilizes a hot electron injection mechanism.
  • a selected cell when a selected cell is programmed, it participates in programming in association with an adjacent memory cell that is co-sourced along the channel direction, and the two memory cells are in a series relationship.
  • the bit line of the selected memory cell is connected to a bias voltage (3 ⁇ 5V)
  • the word line is connected to a bias voltage (7 ⁇ 10V)
  • the bit line of the memory cell adjacent to the channel direction is grounded, and the word line is biased.
  • Set voltage (3 ⁇ 7V) shared by two serial storage units
  • the source is suspended to achieve low power programming.
  • electrons are accelerated in the channel of adjacent cells and then attracted into the charge storage layer by a longitudinal electric field generated by the word line voltage bias in the channel of the selected memory cell.
  • the bit lines connecting the drain terminals of the memory cells and the word lines connecting the memory cell control gates are not perpendicular to each other, but intersect at an angle.
  • the control gates of two memory cells adjacent in the channel direction between each two bit lines are respectively controlled by two word lines, and the drain terminals are respectively controlled by two bit lines, and the source terminals are shared.
  • the present invention provides a programming method for the array structure of the flash memory, which can reduce programming power consumption.
  • the adjacent memory cells co-sourced along the channel direction participate in programming, wherein the bit line of the selected memory cell is connected to the bias voltage (3 ⁇ 5V),
  • the word line is connected to the bias voltage (7 ⁇ 10V), and the memory cell bit line connected in series is grounded, the word line is connected to the bias voltage (3 ⁇ 7V), and the source terminals shared by the two serially connected memory cells are suspended to achieve low power consumption. program.
  • the flash memory array structure and the programming method thereof provided by the invention have the following advantages: the memory cells adjacent to each other in the channel direction between two adjacent bit lines are respectively connected by two word lines to the control gate. . Therefore, the array can adopt the programming method provided by the present invention, two adjacent memory cells are connected in series to participate in programming, and the high bit line voltage required for programming is allocated in two memory cells, which can effectively avoid the punch-through effect, and thus the size of the memory cell The reduction in capacity is improved, thereby increasing the storage density.
  • the memory cells adjacent in the channel direction can be controlled by two word lines respectively, and different voltages are applied to the two word lines, so that the split gate programming can be realized in the array, thereby effectively reducing Programming power consumption.
  • FIG. 1 is a schematic diagram of a prior art flash memory array, wherein:
  • FIG. 2 is a schematic diagram of a flash memory array of the present invention, wherein:
  • FIG. 3 is a schematic diagram of two memory cells adjacent to each other in the channel direction between strip lines in the array of the present invention, wherein: 001 - bit line N, 002 - bit line N + l, 003 - word line N, 004 - word line N+l, 005 - common source, 006 - cell charge storage layer, 007 - memory cell N, 008 - memory cell N+1 BEST MODE FOR CARRYING OUT THE INVENTION
  • the present invention will be further described below in conjunction with three embodiments, but the use of the present invention is not limited to the specific embodiments below.
  • the flash memory array provided by the present invention is as shown in FIG. 2, and includes: 01—bit line, 02—word line, 03—drain end contact hole, 04—two memories adjacent to each other along the channel direction between the two bit lines unit.
  • the memory cell between the two bit lines is as shown in FIG. 3, including: 001 - bit line N, 002 - bit line N + l, 003 - word line N, 004 - word line N + l, 005 - common source , 006 - cell charge storage layer, 007 - memory cell N, 008 - memory cell N + l.
  • the array is characterized in that the word lines in the row direction connect the control gates of all memory cells in the same row in the array.
  • bit lines and word lines in the column direction are angled intersections that connect the drains of all the memory cells in the same column.
  • the control gates of two memory cells adjacent to each other between the two bit lines in the channel direction are respectively controlled by two adjacent word lines, and the drain terminals are respectively controlled by two bit lines, and the source terminals are shared.
  • a new programming method which includes: a memory cell adjacent in the channel direction between two adjacent bit lines is connected in series to participate in programming, wherein one bit line is grounded, and another bit line is connected to a high bit line.
  • the voltage, common source floating, so the high bit line voltage required for programming is distributed in two memory cells, which can effectively avoid the punch-through effect.
  • the control gates of the two cells are respectively connected by two word lines.
  • bit line N (001 ) of the adjacent memory cell (007) is grounded, and the word line N (003) is connected to the voltage of 3 ⁇ 7V;
  • bit line of the selected memory cell (008) is connected to the voltage of N+1 (3 ⁇ 5V), and the word line N+1 (004) is connected to the voltage of 7-10V.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)

Abstract

提供了一种属于超大规模集成电路制造技术中的非易失性存储器技术领域的闪存存储器的阵列结构及其编程方法。该闪存存储器阵列包括：多个存储单元，连接存储单元的字线和位线，其中连接存储单元漏端的位线和连接存储单元控制栅的字线不是互相垂直，而是成角度交叉，每两条位线之间两个沿沟道方向相邻的存储单元的控制栅分别由两条字线控制，漏端分别由两条位线控制，这两个存储单元共享源端。还提供了该闪存存储器阵列结构的编程方法，可实现低功耗编程。

Description

一种半导体存储器阵列及其编程方法 技术领域 本发明属于超大规模集成电路制造技术中的非易失存储器技术领域， 具体涉及一种非易 失存储器阵列及其编程方法。 背景技术 以闪存为代表的非易失存储器因为其断电情况下的数据保持能力以及可多次擦写数据等 优点被广泛应用于各种产品中， 比如手机、 笔记本、 掌上电脑和固态硬盘等存储及通讯设备。 如今闪存已经占据了非易失半导体存储器的大部分市场份额，其中 NOR闪存因为其随机读取 速度快而被广泛应用在手机等移动终端的代码存储芯片中。然而普通的 NOR型闪存采用的沟 道热电子注入方式， 这种编程方式存在两个重要的限制： 一是沟道热电子编程的效率很低， 因此功耗很大； 二是这种编程方式需要较高的位线电压 （通常在 4~5V)， 因此为了防止在这 个高位线电压的穿通现象发生， 普通 NOR闪存阵列中的存储单元的沟道长度不能急剧缩小， 限制了存储单元尺寸的减小和 NOR闪存的存储密度的提高。 这两个限制使得 NOR型闪存难 于满足人们对大容量、 低成本、 低功耗非易失存储技术的需求。
针对 NOR闪存沟道热电子编程功耗大的缺点， 文献 [1][2][3]采用了分裂栅 （split-gate) 的编程方法来减小功耗。该技术利用在栅上采用不同的电压， 即靠近源端的栅接较低的电压， 而靠近漏端的栅接高电压， 因此可以提高编程效率， 从而降低功耗。 但是现有的分裂栅技术 都是针对一个单元进行设计， 带来了工艺的复杂程度， 特别是这种基于存储单元的需要较大 的源漏两端的编程电压差， 从而限制了闪存存储单元的沟道缩小。
针对 NOR闪存沟道热电子编程所需位线电压高导致的单元沟道缩小受到限制这个挑战， 文献 [4][5]采用同一字线上的两个相邻的单元共同参与编程的方法， 这样编程的位线电压被两 个相邻的单元共同承担， 因此可以有效避免单个器件的源漏穿通问题。 但是这种技术都是基 于传统的 NOR型阵列 （如图 1所示） 或者 NROM阵列， 阵列中的字线和位线互相垂直， 因 此共同参与编程的两个相邻单元共用一根字线， 该字线控制控制栅的电压， 所以这些阵列无 法采用分裂栅的编程方式， 故存在编程功耗限制的问题。
总而言之，如何能够提高闪存的尺寸缩小及降低功耗的能力是闪存技术亟待解决的难题。 【参考文献】： [1] S. Kianian, A. Levi, D. Lee, and Y.-W. Hu, "A novel 3 volts-only, small sector erase, high density Flash EEPROM," in Symp. VLSI Tech. Dig., 199 , pp. 71-72.；
[2] B. Yeh, "Single transistor non-volatile electrically alterable semiconductor memory device," U.S. Patent 5 029 130, Jul. 1991.；
[3] Ma, Y.; Pang, C.S.; Pathak, J.; Tsao, S.C.; Chang, C.F.; Yamauchi, Y; Yoshimi, M.; "A novel high density contactless flash memory array using split-gate sources-side-injection cell for 5 V-only applications " Symposium on VLSI Technology, 1994. Page(s): 49 - 50. ；
[4]Wen-Jer Tsai, Ou T.F., Huang J.S., Cheng C.H., Chun- Yuan Lu, Wang T.， Chen K.F., Han T.T., Lu T.C.,Chen K.C., Chih-Yuan Lu, "A highly punch through-immune operation method for an ultra-short-channel hot-carrier-injection type non-volatile memory cell" Electron Devices Meeting, IEEE International 2008. Page(s): 1 - 4;
[5]Tahui Wang, Chun- Jung Tang, Li, C.-W., Chih Hsiung Lee, Ou, T.-F., Yao-Wen Chang, Wen-Jer Tsai, Tao-Cheng Lu, Chen, K.-C., Chih-Yuan Lu, "A Novel Hot-Electron Programming Method in a Buried Diffusion Bit-Line SONOS Memory by Utilizing Nonequilibrium Charge Transport" Electron Device Letters, IEEE Volume: 30 , Issue: 2 2009 , Page(s): 165 - 167。 发明内容 本发明提供一种闪存存储器的阵列结构及其编程方法， 可以同时提高闪存的尺寸缩小能 力及降低其功耗。
一种闪存存储器的阵列结构， 包括： 多个存储单元， 连接存储单元控制栅的字线， 连接 存储单元的漏端的位线， 位线和字线是成角度交叉， 其相交的角度范围在 0~180°之内， 但不 包括 90， 即位线和字线相互不垂直。 其中沿沟道方向相邻的每两个存储单元共享源端， 行方 向的字线连接阵列中同一行中的所有存储单元的控制栅， 位线连接同一列中的所有存储单元 的漏端。 在这个阵列中， 每两条位线之间沿沟道方向相邻的两个存储单元的控制栅分别由两 条相邻字线控制， 漏端分别由两条位线控制， 源端共享。
上述阵列对闪存存储单元无特殊要求， 可以是浮栅类闪存单元， 也可以是陷阱类闪存。 对字线和位线材料也无特殊要求， 可以是金属也可以是金属化合物或者半导体材料导线。
一种闪存存储器的编程方法， 该编程方法利用热电子注入机制。 在上述阵列中， 对选定 的单元编程的时候， 与它沿沟道方向共源的相邻存储单元共同参与编程， 两个存储单元成串 联的关系。 其中选定的存储单元的位线接偏置电压 （3~5V ) ，字线接偏置电压 （7~10V)， 和 它沿沟道方向相邻的存储单元位线接地， 字线接偏置电压（3〜7V)，两个串联的存储单元共享 的源端悬浮， 实现低功耗编程。 在此编程方法中， 电子在相邻的单元的沟道内被加速， 然后 在被选定的存储单元的沟道内被字线电压偏置产生的纵向电场吸引， 注入到电荷存储层中。
本发明阵列结构中， 连接存储单元漏端的位线和连接存储单元控制栅的字线不是互相垂 直， 而是成角度交叉。 每两条位线之间两个沿沟道方向相邻的存储单元的控制栅分别由两条 字线控制， 漏端分别由两条位线控制， 源端共享。 本发明提供该闪存存储器的阵列结构的编 程方法， 可以降低编程功耗。 该编程方法中， 对选定的单元编程的时候， 与它沿沟道方向共 源的相邻存储单元共同参与编程， 其中选定的存储单元的位线接偏置电压（3〜5V)，字线接偏 置电压 （7~10V)， 和它串联的存储单元位线接地， 字线接偏置电压 （3~7V) ，两个串联的存 储单元共享的源端悬浮， 实现低功耗编程。
与现有技术相比， 本发明提出的闪存存储器阵列结构及其编程方法有如下优势： 两个相 邻位线之间的沿沟道方向相邻的存储单元分别由两条字线连接控制栅。 因此该阵列可以采用 本发明所提供的编程方法， 两个相邻存储单元串联共同参与编程， 编程所需的高位线电压分 配在两个存储单元中， 可以有效避免穿通效应， 因此存储单元的尺寸缩小能力得到提升， 从 而提高存储密度。 同时， 由于本发明提供的阵列， 能够使得沿沟道方向相邻的存储单元分别 由两条字线控制， 对两个字线施加不同的电压， 因此可以在阵列中实现分裂栅编程， 有效降 低编程功耗。
因此， 上述存储器阵列及其编程方法可有效提高闪存存储器的尺寸缩小能力及降低其功 耗。 附图说明 图 1 为现有技术的闪存存储器阵列示意图， 其中：
1_位线， 2—字线
图 2 为本发明的闪存存储器阵列示意图， 其中：
01_位线， 02_字线， 03_漏端接触孔, 04_两条位线之间沿沟道方向相邻的两个存储 单元
图 3为本发明中阵列中条位线之间沿沟道方向相邻的两个存储单元的示意图， 其中： 001—位线 N， 002—位线 N+l， 003—字线 N， 004—字线 N+l， 005—共源端， 006—单 元电荷存储层， 007—存储单元 N， 008—存储单元 N+1 具体实施方式 下面结合三个实施例来进一步说明本发明， 但本发明的用途并不仅限于下面的具体实施 例子。
本发明提供的闪存存储器阵列如图 2所示， 包括： 01—位线， 02—字线， 03—漏端接 触孔, 04—两条位线之间沿沟道方向相邻的两个存储单元。两条位线之间的存储单元如图 3所 示，包括： 001—位线 N， 002—位线 N+l， 003—字线 N， 004—字线 N+l， 005—共源端， 006— 单元电荷存储层， 007—存储单元 N， 008—存储单元 N+l。 该阵列的特征在于： 行方向的字 线连接阵列中同一行中的所有存储单元的控制栅。 列方向的位线和字线是成角度交叉， 连接 同一列中的所有存储单元的漏端。 在这个阵列中， 每两条位线之间沿沟道方向相邻的两个存 储单元的控制栅分别由两条相邻字线控制， 漏端分别由两条位线控制， 源端共享。
基于上述闪存阵列， 提出新的编程方法， 包括： 两个相邻位线之间的沿沟道方向相邻的 存储单元串联共同参与编程， 其中一条位线接地， 另外一条位线接高位线编程电压， 共源端 悬浮， 因此编程所需的高位线电压分配在两个存储单元中， 可以有效避免穿通效应。 与此同 时两个单元的控制栅分别由两条字线连接， 编程时对两个字线施加不同的电压， 因此可以在 阵列中实现分裂栅编程， 有效降低编程功耗。
下面结合图 3详细说明本发明提供的编程方法的优选实施例。 假定要对图 3中的第 N+1 存储单元 （008) 进行编程：
( 1 ) 和它相邻的存储单元 （007) 的位线 N (001 ) 接地， 字线 N (003 ) 接 3~7V电压；
(2)被选择编程的存储单元（008) 的位线 N+1接（3~5V) 的电压， 字线 N+1 (004)接 7-10V的电压；
(3 ) 相邻两单元 N和 N+1的共源端 （005 ) 悬浮。 最后需要注意的是， 公布实施例的目的在于帮助进一步理解本发明， 但是本领域的技术 人员可以理解： 在不脱离本发明及所附的权利要求的精神和范围内， 各种替换和修改都是可 能的。 因此， 本发明不应局限于实施例所公开的内容， 本发明要求保护的范围以权利要求书 界定的范围为准。

Claims

权 利 要 求 书
、 一种闪存存储器的阵列结构， 包括多个存储单元组成阵列， 其特征在于， 位线和字线 相交， 但相互不垂直， 字线连接阵列中同一行中的所有存储单元的控制栅， 位线连 接同一列中的所有存储单元的漏端， 沿沟道方向相邻的每两个存储单元共享源端。 、 如权利要求 1所述的闪存存储器阵列的存储单元， 其特征在于： 两条位线之间沿沟道 方向相邻的两个存储单元的控制栅分别由两条相邻字线控制， 漏端分别由两条位线 控制， 源端共享。
、 如权利要求 1所述的闪存存储器阵列的存储单元， 其特征在于： 所述存储单元是浮栅 类闪存存储单元或陷阱类闪存存储单元。
、 一种如权利要求 1 所述闪存存储器阵列的编程方法， 其特征在于， 两个相邻位线之 间的沿沟道方向相邻的存储单元串联共同参与编程， 其中一条位线接地， 另外一条 位线接高位线编程电压， 共源端悬浮， 与此同时上述两个存储单元的控制栅分别由 两条字线连接， 编程时对两个字线施加不同的电压。
、 如权利要求 4所述的编程方法， 其特征在于： 被选择编程的存储单元的位线接 3〜5V 的电压， 字线接 7~10V的电压， 源端悬浮。
、 如权利要求 5 所述的编程方法， 其特征在于： 和被选择编程的存储单元串联相邻的 存储单元的位线接地， 字线接 3~7V电压。
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