WO2012124690A1 - Active matrix substrate and method for manufacturing active matrix substrate - Google Patents

Active matrix substrate and method for manufacturing active matrix substrate Download PDF

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Publication number
WO2012124690A1
WO2012124690A1 PCT/JP2012/056411 JP2012056411W WO2012124690A1 WO 2012124690 A1 WO2012124690 A1 WO 2012124690A1 JP 2012056411 W JP2012056411 W JP 2012056411W WO 2012124690 A1 WO2012124690 A1 WO 2012124690A1
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Prior art keywords
insulating layer
electrode
auxiliary capacitance
interlayer insulating
active matrix
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PCT/JP2012/056411
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French (fr)
Japanese (ja)
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雅貴 山中
堀田　和重
牧田　直樹
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シャープ株式会社
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Priority to JP2013504739A priority Critical patent/JPWO2012124690A1/en
Publication of WO2012124690A1 publication Critical patent/WO2012124690A1/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L29/78627—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile

Definitions

  • the present invention relates to an active matrix substrate used for a display device or the like.
  • a display device such as a liquid crystal display device, an organic EL (Electro Luminescence) display device, a flexible display device, or an electronic book has a thin film transistor (hereinafter also referred to as “TFT”) as a switching element of each pixel.
  • TFT thin film transistor
  • an active matrix substrate also referred to as “TFT substrate”.
  • the active matrix substrate includes a plurality of data lines, a plurality of gate lines, a plurality of TFTs arranged at intersections thereof, a pixel electrode for applying a voltage to a light modulation layer such as a liquid crystal layer, and an applied voltage.
  • a pixel electrode for applying a voltage to a light modulation layer such as a liquid crystal layer, and an applied voltage.
  • Auxiliary capacitance wiring, auxiliary capacitance electrodes, and the like are formed to hold the voltage for a longer time.
  • FIG. 14A shows a cross-sectional configuration of the TFT region in the active matrix substrate of Patent Document 1
  • FIG. 14B shows a cross-sectional configuration of the auxiliary capacitance (additional capacitance) region.
  • channel regions 12a and 12b formed on an insulating substrate 11, source electrodes 23, and a TFT region of the active matrix substrate The drain electrode 24a, the channel layers 12a and 12b, the source electrode 23, the gate insulating film 13 formed so as to cover the drain electrode 24a, the gate electrodes 3a and 3b formed on the gate insulating film 13, and the second A first interlayer insulating film 14 and a second interlayer insulating film 17 formed on the first interlayer insulating film 14 are disposed.
  • the source bus wiring 2 and the metal layer 10 are disposed between the first interlayer insulating film 14 and the second interlayer insulating film 17, and the pixel electrode 4 is disposed on the second interlayer insulating film 17.
  • the source bus wiring 2 and the metal layer 10 are connected to the source electrode 23 and the drain electrode 24a through contact holes formed in the first interlayer insulating film 14 and the gate insulating film 13, respectively.
  • the pixel electrode 4 is connected to the metal layer 10 through a contact hole formed in the second interlayer insulating film 17.
  • the additional capacitor electrode 6 and the first interlayer insulating film 14 formed on the gate insulating film 13 and the second interlayer insulating film 17 formed on the first interlayer insulating film 14 are disposed.
  • the metal layer 10 is disposed between the first interlayer insulating film 14 and the second interlayer insulating film 17, and the pixel electrode 4 is disposed on the second interlayer insulating film 17.
  • the metal layer 10 is connected to the capacitor lower electrode 5 via a contact hole formed in the first interlayer insulating film 14 and the gate insulating film 13, and the pixel electrode 4 is connected via a contact hole in the second interlayer insulating film 17. Are connected to the metal layer 10.
  • Patent Document 1 an additional capacitor is formed between the capacitor lower electrode 5 and the additional capacitor electrode 6 and an additional capacitor is also formed between the metal layer 10 and the additional capacitor electrode 6 due to the above configuration. Therefore, it is said that a necessary capacity can be obtained with a small area and an aperture ratio of a display area can be improved.
  • FIG. 15 shows a cross-sectional configuration of an example of an active matrix substrate used in a liquid crystal display device.
  • the active matrix substrate 200 includes a semiconductor layer 214, a gate insulating layer 216, a first interlayer insulating layer 218, a second interlayer insulating layer 219, and a pixel electrode 220 that are sequentially stacked on the substrate 201. I have.
  • the semiconductor layer 214 is made of, for example, crystalline silicon
  • the gate insulating layer 216 and the first interlayer insulating layer 218 are made of, for example, silicon nitride
  • the second interlayer insulating layer 219 is made of, for example, an organic insulating material
  • the pixel electrode 220 is For example, it is made of ITO (Indium Tin Oxide).
  • the semiconductor layer 214 in the TFT portion 203 of the active matrix substrate 200 includes the channel portion 230, the Si (n ⁇ ) portions 231 and 232 that are in contact with both ends of the channel portion 230, and the respective channel portions 230 of the Si (n ⁇ ) portions 231 and 232.
  • Si (n +) portions 233 and 234 are in contact with the opposite side.
  • a scanning line extends over the gate insulating layer 216 above the channel portion 230, and a part of the scanning line becomes the gate electrode 240.
  • Contact holes are formed in the first interlayer insulating layer 218 on each of the Si (n +) portions 233 and 234, and a source electrode 243 and a drain electrode 244 are formed so as to fill the contact holes. Lower portions of the source electrode 243 and the drain electrode 244 are in contact with the Si (n +) portions 233 and 234, respectively. Si (n +) portions 233 and 234 function as contact portions for the source electrode 243 and the drain electrode 244, respectively.
  • the upper part of the source electrode 243 is connected to a signal line 246 extending on the first interlayer insulating layer 218.
  • a contact hole is formed in the second interlayer insulating layer 219 above the drain electrode 244, and the pixel electrode 220 is in contact with the drain electrode 244 through the contact hole.
  • the semiconductor layer 214 is composed of an Si (n ⁇ ) portion 237, and an auxiliary capacitance electrode (upper layer electrode) 245 is formed on the gate insulating layer 216.
  • the Si (n ⁇ ) portion 237 below the auxiliary capacitance electrode 245 functions as the auxiliary capacitance lower electrode (lower layer electrode) 239, and is constituted by the auxiliary capacitance electrode 245, the auxiliary capacitance lower electrode 239, and the gate insulating layer 216 between the two electrodes.
  • a storage capacitor is formed.
  • the gate insulating layer 216 can be formed very thin with a dielectric. Therefore, even if the area occupied by the auxiliary capacitance electrode 245 and the auxiliary capacitance lower electrode 239 (area occupied in the substrate surface) is reduced, a relatively large auxiliary capacitance can be obtained, the pixel density is increased, and the aperture ratio is improved. Can be achieved.
  • capacitance is formed between the capacitor lower electrode 5 and the additional capacitor electrode 6 and between the metal layer 10 and the additional capacitor electrode 6.
  • a signal line is disposed on the interlayer insulating layer
  • a scanning line is disposed below the interlayer insulating layer.
  • the interlayer insulating layer functions as an insulation between the two lines. Is responsible. Therefore, the thickness of the interlayer insulating layer is several times to 10 times that of the gate insulating layer.
  • the present invention has been made in view of the above, and provides a high-definition and high-luminance display device while ensuring a sufficient auxiliary capacity, or an active device that can be suitably used for such a display device.
  • An object is to provide a matrix substrate.
  • An active matrix substrate includes a semiconductor layer, an insulating layer formed on the semiconductor layer, an auxiliary capacitance electrode formed on the insulating layer, and a first electrode formed on the auxiliary capacitance electrode.
  • a first interlayer insulating layer; a recess formed in the first interlayer insulating layer above the storage capacitor electrode; a storage capacitor upper electrode formed on a bottom surface of the recess; and the storage capacitor upper electrode A second interlayer insulating layer formed; and a pixel electrode formed on the second interlayer insulating layer.
  • a layer made of silicon oxide is disposed between the upper surface of the auxiliary capacitance electrode and the auxiliary capacitance upper electrode, and the distance from the upper surface of the auxiliary capacitance electrode to the lower surface of the auxiliary capacitance upper electrode is 10 nm. It is 100 nm or less.
  • a layer made of silicon nitride is disposed between the upper surface of the auxiliary capacitance electrode and the auxiliary capacitance upper electrode, and the distance from the upper surface of the auxiliary capacitance electrode to the lower surface of the auxiliary capacitance upper electrode is 10 nm. It is 200 nm or less.
  • the auxiliary capacitor upper electrode and the semiconductor layer are electrically connected via a contact hole formed in the insulating layer and the first interlayer insulating layer, and the auxiliary capacitor upper electrode The pixel electrode is electrically connected through a contact hole formed in the second interlayer insulating layer.
  • the semiconductor layer includes a storage capacitor lower electrode made of a semiconductor doped with an impurity and formed under the storage capacitor electrode.
  • an additional insulating layer is formed on the auxiliary capacitance electrode, the upper surface of the auxiliary capacitance electrode is in contact with the lower surface of the additional insulating layer, and the lower surface of the auxiliary capacitance upper electrode is the additional insulating layer. It is in contact with the top surface.
  • the additional insulating layer is made of silicon nitride, and the first interlayer insulating layer is made of silicon oxide.
  • the manufacturing method of the active matrix substrate according to the present invention includes a step of forming a semiconductor layer, a step of forming an insulating layer on the semiconductor layer, a step of forming an auxiliary capacitance electrode on the insulating layer, and the auxiliary Forming a first interlayer insulating layer on the capacitor electrode; forming a recess in the first interlayer insulating layer above the auxiliary capacitor electrode; and forming an auxiliary capacitor upper electrode on the bottom surface of the recess A step of forming a second interlayer insulating layer on the storage capacitor upper electrode, and a step of forming a pixel electrode on the second interlayer insulating layer.
  • a layer made of silicon oxide is formed between the upper surface of the auxiliary capacitance electrode and the auxiliary capacitance upper electrode, and the distance from the upper surface of the auxiliary capacitance electrode to the bottom surface of the recess is 10 nm or more and 100 nm or less.
  • the recess is formed in the first interlayer insulating layer.
  • a layer made of silicon nitride is formed between the upper surface of the auxiliary capacitor electrode and the upper electrode of the auxiliary capacitor, and the distance from the upper surface of the auxiliary capacitor electrode to the bottom surface of the recess is 10 nm or more and 200 nm or less.
  • the recess is formed in the first interlayer insulating layer.
  • the step of forming the recess includes a step of forming a resist on the first interlayer insulating layer, a step of forming an opening of the resist above the auxiliary capacitance electrode, and the step of forming the resist. Selectively etching the first interlayer insulating layer under the opening.
  • the step of forming the recess includes a step of forming a resist on the first interlayer insulating layer, a first window, and a plurality of second windows having a higher light transmittance than the first window. And a step of irradiating the resist with light through the first window and the plurality of second windows, and removing the resist irradiated with light. Forming a recess and a plurality of openings in the resist; and selectively etching the first interlayer insulating layer through the resist to form the first interlayer insulating layer on the auxiliary capacitance electrode. Forming a recess, and forming a contact hole leading to the semiconductor layer under the opening of the resist.
  • the manufacturing method includes a step of doping impurities into the semiconductor layer, and in the step of forming the auxiliary capacitance electrode, the auxiliary capacitance electrode is formed on the semiconductor layer doped with the impurity. Is done.
  • the manufacturing method includes a step of forming an additional insulating layer on the auxiliary capacitance electrode, and the additional insulating layer is used as an etching stopper in the step of forming the recess in the first interlayer insulating layer. Then, the first interlayer insulating layer is etched so that the additional insulating layer is exposed at the bottom surface of the recess.
  • the additional insulating layer is formed from silicon nitride, and the first interlayer insulating layer is formed from silicon oxide.
  • a large auxiliary capacitance can be formed between the auxiliary capacitance electrode and the auxiliary capacitance upper electrode, a display device with high display quality can be provided.
  • a large auxiliary capacitance can be obtained with an electrode having a small occupied area, so that a high-definition display device can be provided.
  • an auxiliary capacitance can be formed between the auxiliary capacitance electrode and the semiconductor layer, so that a display device with higher display quality or higher A fine display device can be provided.
  • FIG. 1 is a cross-sectional view schematically showing a configuration of an active matrix substrate 100 according to Embodiment 1 of the present invention. It is the perspective view which represented typically the structure of the liquid crystal display device 1000 by Embodiment 1 of this invention.
  • FIG. 2 is a plan view schematically showing a configuration of a pixel region in an active matrix substrate 100 according to Embodiment 1.
  • 2 is a circuit diagram illustrating a configuration of a pixel of an active matrix substrate 100 according to Embodiment 1.
  • FIGS. 4A to 4G are cross-sectional views illustrating a method for manufacturing the active matrix substrate 100 according to the first embodiment. It is sectional drawing which represented typically the structure of the active matrix substrate 100 by Embodiment 2 of this invention.
  • FIGS. 4A to 4D are cross-sectional views illustrating a method for manufacturing the active matrix substrate 100 according to the second embodiment.
  • FIGS. 5A to 5F are cross-sectional views illustrating a method for manufacturing the active matrix substrate 100 according to the third embodiment. It is sectional drawing which represented typically the structure of the active matrix substrate 100 by Embodiment 4 of this invention.
  • 6 is a circuit diagram illustrating a configuration of a pixel of an active matrix substrate 100 according to Embodiment 4.
  • FIGS. 8A to 8F are cross-sectional views illustrating a method for manufacturing the active matrix substrate 100 according to the fourth embodiment.
  • FIGS. 9A to 9D are cross-sectional views illustrating a method for manufacturing the active matrix substrate 100 according to the fifth embodiment.
  • 5E to 5G are cross-sectional views illustrating a method for manufacturing the active matrix substrate 100 according to the fifth embodiment.
  • (A) And (b) is sectional drawing showing the structure of the active-matrix board
  • FIG. It is sectional drawing which represented typically the structure of the active matrix substrate 200 of a reference example.
  • the active matrix substrate of the present invention can be used as an active matrix substrate for various display devices such as liquid crystal display devices and organic EL display devices.
  • display devices such as liquid crystal display devices and organic EL display devices.
  • known components can basically be used for components other than the active matrix substrate described below, such as the counter substrate and peripheral wiring.
  • FIG. 1 is a cross-sectional view schematically showing the configuration of the active matrix substrate 100 according to the first embodiment.
  • an active matrix substrate 100 includes a semiconductor layer 114, a gate insulating layer (also simply referred to as an insulating layer) 116, a first interlayer insulating layer 118, and a second interlayer insulating layer that are sequentially stacked on the substrate 101. 119 and a pixel electrode 120.
  • the semiconductor layer 114 is made of, for example, crystalline silicon or polysilicon
  • the gate insulating layer 116 and the first interlayer insulating layer 118 are made of, for example, silicon nitride
  • the second interlayer insulating layer 119 is made of, for example, an organic insulating material.
  • the electrode 120 is made of, for example, ITO.
  • a plurality of pixels are formed on the active matrix substrate 100, and each pixel has a TFT portion 103 in which a TFT 125 is formed and a Cs portion 105 in which an auxiliary capacitor 150 is formed.
  • the semiconductor layer 114 of the TFT 125 in the TFT unit 103 includes a channel unit 130, Si (n ⁇ ) units 131 and 132 in contact with both ends of the channel unit 130, and the Si (n ⁇ ) units 131 and 132 on the opposite side to the channel unit 130.
  • Si (n +) portions 133 and 134 are in contact with the end portions.
  • a scanning line extends on the gate insulating layer 116 above the channel portion 130, and a part of the scanning line becomes a gate electrode 140.
  • Contact holes are formed in the first interlayer insulating layer 118 on each of the Si (n +) portions 133 and 134, and a source electrode 143 and a drain electrode 144 are formed so as to fill the contact holes. Lower portions of the source electrode 143 and the drain electrode 144 are in contact with Si (n +) portions 133 and 134, respectively. Si (n +) portions 133 and 134 function as contact portions for the source electrode 143 and the drain electrode 144, respectively.
  • the upper part of the source electrode 143 is connected to a signal line 146 extending over the first interlayer insulating layer 118.
  • a contact hole is formed in the second interlayer insulating layer 119 above the drain electrode 144, and the pixel electrode 120 is in contact with the drain electrode 144 through the contact hole.
  • the semiconductor layer 114 is composed of an Si (n ⁇ ) portion 137, and an auxiliary capacitance electrode 145 is formed on the gate insulating layer 116.
  • the Si (n ⁇ ) parts 131, 132, and 137 are semiconductor layers whose resistance is reduced by doping impurities.
  • the Si (n ⁇ ) portion 137 below the auxiliary capacitance electrode 145 functions as the auxiliary capacitance lower electrode 139.
  • the auxiliary capacitance lower electrode 139 may be formed of a Si (n +) semiconductor.
  • a recess 160 is formed in the first interlayer insulating layer 118 above the auxiliary capacitance electrode 145.
  • a storage capacitor upper electrode 149 is formed on the bottom surface of the recess 160.
  • the distance d from the upper surface of the auxiliary capacitance electrode 145 to the lower surface of the auxiliary capacitance upper electrode 149 (or the bottom surface of the recess 160) is 10 nm or more and 100 nm or less when the first interlayer insulating layer 118 is made of silicon oxide. In this case, it is 10 nm or more and 200 nm or less.
  • the auxiliary capacitance upper electrode 149 is a part of the metal layer 147 formed on the upper surface of the first interlayer insulating layer 118.
  • the metal layer 147 is connected to the drain electrode 144 on the first interlayer insulating layer 118 and is connected to the pixel electrode 120 through a contact hole formed in the second interlayer insulating layer 119.
  • the auxiliary capacitance upper electrode 149 and the auxiliary capacitance lower electrode 139 are electrically connected through the metal layer 147, the drain electrode 144 filling the contact hole formed in the gate insulating layer 116 and the first interlayer insulating layer 118, and the semiconductor layer 114. It is connected.
  • the auxiliary capacitor upper electrode 149 and the pixel electrode 120 are electrically connected through a contact hole formed in the metal layer 147 and the second interlayer insulating layer 119.
  • a capacitance is formed by the auxiliary capacitance electrode 145, the auxiliary capacitance lower electrode 139, and the gate insulating layer 116 between both electrodes, and the first interlayer insulation between the auxiliary capacitance electrode 145, the auxiliary capacitance upper electrode 149, and both electrodes.
  • a capacitor is also formed by the layer 118, and the sum of these two capacitors becomes the auxiliary capacitor 150 of each pixel. Since the gate insulating layer 116 is very thin and has a thickness of 10 nm to 100 nm, a large capacitance can be formed between the auxiliary capacitance electrode 145 and the auxiliary capacitance lower electrode 139.
  • the recess 160 is formed in the first interlayer insulating layer 118, the distance between the auxiliary capacitance electrode 145 and the auxiliary capacitance upper electrode 149 can be reduced, so that a large capacitance is also present between these two electrodes. Can be formed.
  • auxiliary capacitor 150 having a large capacity in each pixel as compared with the conventional active matrix substrate.
  • the first interlayer insulating layer 118 other than the recess 160 is formed to a sufficient thickness, a large capacity can be obtained. Therefore, an active matrix substrate that can realize both display quality and reliability at a high level is provided. It becomes possible to provide. Furthermore, even if the area occupied by the auxiliary capacitance electrode 145, the auxiliary capacitance lower electrode 139, and the auxiliary capacitance upper electrode 149 is reduced, a relatively large auxiliary capacitance can be obtained, so that the pixel density is increased and the aperture ratio is improved. Can be achieved.
  • FIG. 2 is a perspective view schematically showing the configuration of the liquid crystal display device 1000 according to the present invention.
  • the liquid crystal display device 1000 includes an active matrix substrate 100 according to an embodiment of the present invention as its TFT substrate.
  • FIG. 3 is a plan view schematically showing an arrangement configuration of pixels in the active matrix substrate 100, and
  • FIG. 4 is a circuit diagram showing a circuit configuration of each pixel.
  • the liquid crystal display device 1000 includes an active matrix substrate 100 and a counter substrate 500 facing each other with a liquid crystal layer interposed therebetween, and polarizing plates attached to the outer surfaces of the active matrix substrate 100 and the counter substrate 500. 510 and 520 and a backlight unit 530 for emitting display light.
  • the counter substrate 500 includes a color filter and a common electrode.
  • the color filter includes an R (red) filter, a G (green) filter, and a B (blue) filter, each of which is arranged corresponding to a pixel.
  • the counter substrate 500 may correspond to a display method of four primary colors or more.
  • the common electrode is formed so as to cover the plurality of pixel electrodes 120 with the liquid crystal layer interposed therebetween. In accordance with the potential difference applied between the common electrode and each pixel electrode 120, the liquid crystal between both electrodes is aligned for each pixel, and display is performed.
  • a plurality of scanning lines (gate bus lines) 141 and a plurality of signal lines (data bus lines) 146 are arranged on the active matrix substrate 100 so as to be orthogonal to each other.
  • a TFT 125 is formed for each pixel 110 near the intersection of the scanning line 141 and the signal line 146.
  • the pixel 110 is defined as a region delimited by a center line between two adjacent scanning lines 141 and two adjacent signal lines 146.
  • Each pixel 110 is provided with a pixel electrode 120 that is electrically connected to the drain electrode 144 of the TFT 125.
  • a storage capacitor line 142 extends in parallel with the scanning line 141 between two adjacent scanning lines 141.
  • the scanning line 141 and the signal line 146 are respectively connected to the scanning line driving circuit 540 and the signal line driving circuit 550 shown in FIG.
  • a scanning signal for switching on / off of the TFT 125 is supplied from the scanning line driving circuit 540 to the scanning line 141 according to control by the control circuit 560, and signal line driving is performed to the signal line 146 according to control by the control circuit 560.
  • a display signal (voltage applied to the pixel electrode 120) is supplied from the circuit 550.
  • a display capacitor is formed between the pixel electrode 120 and the counter electrode 170 of the counter substrate 500 facing each other with the liquid crystal layer 180 interposed therebetween.
  • the pixel electrode 120, the auxiliary capacitor lower electrode 139, and the auxiliary capacitor upper electrode 149 have the same potential as the drain electrode of the TFT 125, and the same reference potential as that of the counter electrode 170 is applied to the auxiliary capacitor electrode 145 through the auxiliary capacitor line 142. It is done.
  • the capacitance formed between the auxiliary capacitance electrode 145 and the auxiliary capacitance lower electrode 139 and between the auxiliary capacitance electrode 145 and the auxiliary capacitance upper electrode 149 functions as an auxiliary capacitance for maintaining the display capacitance. .
  • the capacity Cs of the auxiliary capacity 150 is expressed by the following formula.
  • Cs1 is a capacitance formed between the auxiliary capacitance electrode 145 and the auxiliary capacitance upper electrode 149
  • Cs2 is a capacitance formed between the auxiliary capacitance electrode 145 and the auxiliary capacitance lower electrode 139.
  • A represents the occupied area in the substrate surface of the auxiliary capacitance electrode 145
  • ⁇ 1 is the dielectric constant of the first interlayer insulating layer 118
  • d 1 is the distance d between the auxiliary capacitance electrode 145 and the auxiliary capacitance upper electrode 149
  • ⁇ 2 represents the dielectric constant of the gate insulating layer 116
  • d 2 represents the distance between the auxiliary capacitance electrode 145 and the auxiliary capacitance lower electrode 139 (the thickness of the gate insulating layer 116).
  • the first interlayer insulating layer 118 is formed of the same material as the gate insulating layer 116 and the distance d between the auxiliary capacitance electrode 145 and the auxiliary capacitance upper electrode 149 is the same as the thickness of the gate insulating layer 116, From the equation, it is possible to obtain twice the capacitance Cs compared to the case where the auxiliary capacitance upper electrode 149 is not formed. Alternatively, the area A occupied by the auxiliary capacitance electrode 145 can be halved in order to obtain the same capacitance Cs.
  • the relative dielectric constants ⁇ r1 and ⁇ r2 of both materials are about 7.0 and about 3.9, respectively, so ⁇ 1 and ⁇ 2 are about 7.0 * ⁇ 0 and about 3.9 * ⁇ 0 , respectively ( ⁇ 0 : dielectric constant of vacuum). Therefore, when the thickness d 1 of the first interlayer insulating layer 118 under the recess 160 is substantially equal to the thickness d 2 of the gate insulating layer 116, the capacitance is about three times that when the auxiliary capacitance upper electrode 149 is not formed. Cs can be obtained. Alternatively, in order to obtain the same capacitance Cs, the area occupied by the auxiliary capacitance electrode 145 can be reduced to about 3.
  • the thickness of the gate insulating layer 116 made of silicon oxide is 10 to 100 nm in order to obtain a larger capacity (for example, twice that of the case where only the gate insulating film is used) while functioning as an insulating layer. It is more preferable that the thickness is 30 to 80 nm. The optimum thickness of the gate insulating layer 116 is about 50 nm.
  • the thickness d of the first interlayer insulating layer 118 under the recess 160 is set to For example, the thickness is preferably 10 to 100 nm, more preferably 30 to 80 nm. The optimum value of thickness d is about 50 nm.
  • the thickness d of the first interlayer insulating layer 118 under the recess 160 is preferably 10 to 200 nm, for example, and preferably 30 to 160 nm. Practically more preferable.
  • the optimum thickness d is about 100 nm.
  • FIGS. 5A to 5G are cross-sectional views schematically showing a method for manufacturing the active matrix substrate 100. 5A to 5G also show the manufacturing process of the driver TFT portion 107 included in the active matrix substrate 100.
  • the driver TFT portion 107 is a driver TFT formation region arranged in a peripheral region outside the display region composed of a plurality of pixels 110.
  • the driver TFT includes TFTs formed in the peripheral region such as the TFT of the scanning line driver circuit 540 and the TFT of the signal line driver circuit 550 shown in FIG.
  • a base film (not shown) is formed on a substrate 101 such as a glass substrate, and a semiconductor layer 114 made of crystalline silicon or polysilicon is laminated thereon.
  • the base film is, for example, a multilayer film of a silicon nitride film and a silicon oxide film.
  • the semiconductor layer 114 can be obtained by depositing amorphous silicon and then crystallizing or polysiliconizing the amorphous silicon by a known technique such as irradiation with an excimer laser or the like.
  • the semiconductor layer 114 is patterned by photolithography to selectively leave the semiconductor layer 114 in the TFT portion 103, the Cs portion 105, and the driver TFT portion 107. Thereafter, a gate insulating layer 116 is formed so as to cover the semiconductor layer 114, and the structure shown in FIG. After the gate insulating layer 116 is formed, a low-concentration p-type impurity 190 is ion-implanted into the remaining semiconductor layer 114 through the gate insulating layer 116 from above.
  • the region of the TFT portion 103 and the region of the driver TFT portion 107 that becomes the channel portion 330 of the driver TFT are covered with a resist 185, and an n-type impurity 191 such as phosphorus is applied from above. Dope. Thereby, the semiconductor layer 114 in a region not covered with the resist 185 becomes a Si (n ⁇ ) semiconductor portion.
  • a metal layer is formed on the gate insulating layer 116 by sputtering or CVD.
  • the material of the metal layer it is desirable to use any of refractory metals W, Ta, Ti, Mo or alloy materials thereof.
  • the metal layer is patterned by photolithography to obtain the auxiliary capacitance electrode 145 of the Cs portion 105, the gate electrode 140 of the TFT portion 103, and the gate electrode 340 of the driver TFT portion 107 as shown in FIG. .
  • the scanning line 141 and the auxiliary capacitance line 142 not shown here are also formed at the same time.
  • the semiconductor layer 114 is doped with an n-type impurity 191 such as phosphorus using the auxiliary capacitance electrode 145, the gate electrode 140, and the gate electrode 340 as a mask. As a result, a TFT channel portion 130 in the TFT portion 103 is obtained.
  • the n-type impurity is further selectively doped to obtain the semiconductor layer 114 of the TFT portion 103 and the driver TFT portion 107 as shown in FIG. That is, in the TFT portion 103, the channel portion 130 under the gate electrode 140, the Si (n ⁇ ) portions 131 and 132 in contact with both ends of the channel portion 130, and the outer ends of the Si (n ⁇ ) portions 131 and 132, respectively. Si (n +) portions 133 and 134 are formed. In the driver TFT portion 107, the channel portion 330 below the gate electrode 340, the Si (n ⁇ ) portions 331 and 332 in contact with both ends of the channel portion 330, and the outer ends of the Si (n ⁇ ) portions 331 and 332, respectively.
  • Si (n +) portions 333 and 334 in contact are formed. Further, the semiconductor layer 114 of the Cs portion 105 becomes the Si (n ⁇ ) portion 137, and a portion below the auxiliary capacitance electrode 145 among them becomes the auxiliary capacitance lower electrode 139.
  • a step of selectively doping the semiconductor layer 114 with a p-type impurity is added, so that one of the TFTs of the TFT portion 103 and the driver TFT portion 107 is a P-type TFT and the other is an N-type TFT. It is also possible to change the threshold voltage of both TFTs by changing the concentration of doped impurities.
  • Both TFTs of the TFT portion 103 and the driver TFT portion 107 may be P-type TFTs.
  • both the N-type TFT and the P-type TFT may be included in the plurality of TFTs formed in the driver TFT portion 107. All of the plurality of TFTs in the driver TFT unit 107 may be N-type TFTs, and all of them may be P-type TFTs.
  • silicon nitride is laminated on the gate insulating layer 116 so as to cover the auxiliary capacitance electrode 145, the gate electrode 140, and the gate electrode 340, thereby obtaining the first interlayer insulating layer 118.
  • a resist 185 is applied on the first interlayer insulating layer 118, and the resist 185 on the auxiliary capacitance electrode 145 is removed to form an opening, thereby obtaining a stacked structure shown in FIG.
  • the first interlayer insulating layer 118 under the opening of the resist 185 is selectively etched to form a recess 160 above the auxiliary capacitance electrode 145. Thereafter, the resist 185 is removed to obtain a stacked structure shown in FIG. Thereafter, although not shown, the first interlayer insulating layer 118 and the gate insulating layer 116 are selectively removed by photolithography, and the Si (n +) portions 133, 134, 333, and 334 are respectively removed. A contact hole is formed on top.
  • a metal layer is stacked on the first interlayer insulating layer 118.
  • the metal layer has, for example, a three-layer structure of Ti / Al / Ti.
  • the metal layer may have a two-layer structure such as Al / Ti, Cu / Ti, Cu / Mo (molybdenum), or a single-layer structure using one of these metals.
  • the metal layer is patterned by photolithography to obtain the auxiliary capacitor upper electrode 149, the metal layer 147, the source electrodes 143 and 343, and the drain electrodes 144 and 344, as shown in FIG. At this time, a signal line 146 not shown here is also formed at the same time.
  • a second interlayer insulating layer 119 functioning as a planarizing film is stacked on the first interlayer insulating layer 118, and a contact hole is formed in the second interlayer insulating layer 119 above the drain electrode 144.
  • ITO is stacked on the second interlayer insulating layer 119 and patterned by photolithography to form the pixel electrode 120, whereby the active matrix substrate 100 shown in FIG. 5G is completed.
  • the active matrix substrate 100 formed in this way in addition to the capacitance between the auxiliary capacitance electrode 145 and the auxiliary capacitance lower electrode 139, a capacitance is also formed between the auxiliary capacitance electrode 145 and the auxiliary capacitance upper electrode 149. Therefore, the auxiliary capacitor 150 having a larger capacity can be formed for each pixel.
  • the auxiliary capacitor upper electrode 149 is formed on the bottom surface of the recess 160, a large capacity can be obtained even if the first interlayer insulating layer 118 other than the recess 160 is formed to a sufficient thickness. Therefore, an active matrix substrate excellent in both display quality and reliability can be provided.
  • auxiliary capacitance electrode 145 since a relatively large auxiliary capacitance can be obtained even if the area occupied by the auxiliary capacitance electrode 145 is reduced, it is possible to increase the density of the pixels and improve the aperture ratio. Furthermore, since the auxiliary capacitor upper electrode 149 is formed in the same manufacturing process as the source electrode 143, the drain electrode 144, etc., a large auxiliary capacity can be obtained without complicating the manufacturing process. Further, according to the active matrix substrate 100, since the first interlayer insulating layer 118 having a sufficient thickness is formed at a portion where the signal line and the scanning line intersect, a sufficient insulating function between the two lines is ensured, A large auxiliary capacity can be ensured without degrading the signal quality of both lines.
  • FIG. 6 is a cross-sectional view schematically showing the configuration of the active matrix substrate 100 according to the second embodiment.
  • the active matrix substrate 100 according to the second embodiment includes a semiconductor layer 114, a gate insulating layer 116, an additional insulating layer 117, a first interlayer insulating layer 118, and a second interlayer sequentially stacked on the substrate 101.
  • An insulating layer 119 and a pixel electrode 120 are provided.
  • the additional insulating layer 117 is formed on the gate insulating layer 116 so as to cover the auxiliary capacitance electrode 145 and the gate electrode 140.
  • a recess 160 is formed in the first interlayer insulating layer 118 above the auxiliary capacitance electrode 145.
  • the space between the auxiliary capacitance electrode 145 and the auxiliary capacitance upper electrode 149 is filled with the additional insulating layer 117. That is, the upper surface of the auxiliary capacitance electrode 145 is in contact with the lower surface of the additional insulating layer 117, and the lower surface of the auxiliary capacitance upper electrode 149 is in contact with the upper surface of the additional insulating layer 117.
  • a distance d between the upper surface of the auxiliary capacitance electrode 145 and the lower surface of the auxiliary capacitance upper electrode 149 (the bottom surface of the recess 160) corresponds to the thickness of the additional insulating layer 117 between the two electrodes.
  • the additional insulating layer 117 is made of, for example, silicon nitride, and the first interlayer insulating layer 118 is made of, for example, silicon oxide.
  • the additional insulating layer 117 serves as an etching stopper.
  • the distance d (or the thickness of the additional insulating layer 117) from the upper surface of the auxiliary capacitance electrode 145 to the lower surface of the auxiliary capacitance upper electrode 149 is 10 nm or more and 200 nm or less.
  • the distance d is more preferably 60 to 160 nm, and the optimum value is about 100 nm.
  • 7A to 7D are cross-sectional views schematically showing a method for manufacturing the active matrix substrate 100 according to the second embodiment. 7A to 7D also show a manufacturing process of the driver TFT portion 107 included in the active matrix substrate 100. FIG.
  • the laminated structure shown in FIG. 7A is obtained through steps similar to the manufacturing steps of the first embodiment shown in FIGS. 5A to 5C. Thereafter, the semiconductor layer 114 is doped with an n-type impurity to obtain the semiconductor layer 114 having the structure shown in FIG. 7B including the Si (n +) portions 133, 134, 333, and 334.
  • silicon nitride is stacked on the gate insulating layer 116 so as to cover the auxiliary capacitance electrode 145, the gate electrode 140, and the gate electrode 340 to form an additional insulating layer 117, and silicon oxide is stacked thereon.
  • a first interlayer insulating layer 118 is obtained.
  • a resist 185 is applied on the first interlayer insulating layer 118, and the resist 185 on the auxiliary capacitance electrode 145 is removed to form an opening, thereby obtaining a stacked structure shown in FIG. 7B.
  • the first interlayer insulating layer 118 under the opening of the resist 185 is etched to form a recess 160 above the auxiliary capacitance electrode 145.
  • silicon nitride can function as an etching stopper by using an etchant that exhibits an etching rate lower than that of silicon oxide.
  • the resist 185 is removed to obtain a laminated structure shown in FIG.
  • the first interlayer insulating layer 118, the additional insulating layer 117, and the gate insulating layer 116 are selectively removed by photolithography, and Si (n +) portions 133, 134, 333 are removed. , And 334 are formed on each of the contact holes.
  • a metal layer is stacked on the first interlayer insulating layer 118 and patterned by photolithography, and as shown in FIG. 7D, the auxiliary capacitor upper electrode 149, the metal layer 147, the source electrode 143, and 343 and drain electrodes 144 and 344 are obtained. At this time, a signal line 146 not shown here is also formed at the same time.
  • a second interlayer insulating layer 119 is stacked on the first interlayer insulating layer 118, and a contact hole is formed in the second interlayer insulating layer 119 on the drain electrode 144.
  • ITO is laminated on the second interlayer insulating layer 119 and patterned by photolithography to form the pixel electrode 120, thereby completing the active matrix substrate 100 shown in FIG. 7D.
  • the additional insulating layer 117 serves as an etching stopper when forming the recess 160, the recess 160 having a uniform depth for a plurality of pixels without strictly controlling the etching time. Can be formed. Thereby, it is possible to provide a high-quality display in which variation in luminance among a plurality of pixels is suppressed.
  • FIG. 3 is cross-sectional views schematically showing a method for manufacturing the active matrix substrate 100 according to the third embodiment. Since the cross-sectional configuration of the active matrix substrate 100 according to the third embodiment is basically the same as that of the second embodiment, the illustration is omitted here, and only the manufacturing method will be described.
  • the laminated structure shown in FIG. 8A is obtained through the same process as the manufacturing process of the first embodiment shown in FIGS. 5A to 5C. Thereafter, the semiconductor layer 114 is doped with n-type impurities to obtain the semiconductor layer 114 including Si (n +) portions 133, 134, 333, and 334.
  • silicon nitride is stacked on the gate insulating layer 116 so as to cover the auxiliary capacitance electrode 145, the gate electrode 140, and the gate electrode 340 to form an additional insulating layer 117, and silicon oxide is stacked thereon.
  • a first interlayer insulating layer 118 is obtained.
  • a resist 185 is applied on the first interlayer insulating layer 118.
  • a mask 187 is disposed above the resist 185.
  • the mask 187 is a gray-tone mask, and in order to perform halftone exposure, a first window (semi-transmissive portion) 188 that exhibits a low light transmittance and a second window (a light transmittance that is higher than the first window 188). Total transmission part) 189. Portions other than the first window 188 and the second window 189 of the mask 187 are light shielding portions that do not substantially transmit light.
  • the first window 188 is disposed above the auxiliary capacitance electrode 145, and the second window 189 is disposed above each of the Si (n +) portions 133, 134, 333, and 334.
  • the first interlayer insulating layer 118 is selectively etched through the resist 185 to form a recess in the first interlayer insulating layer 118 under the opening 186 as shown in FIG. At this time, the first interlayer insulating layer 118 other than under the opening 186 is left without being etched.
  • the entire resist 185 is thinned by ashing the resist 185 with oxygen plasma or the like, and the first interlayer insulating layer 118 is exposed at the bottom of the recess 184. At this time, a portion of the resist 185 other than the recess 184 and the opening 186 is left, and the first interlayer insulating layer 118 therebelow is not exposed. Thereafter, etching is performed again, and as shown in FIG. 8E, a recess 160 of the first interlayer insulating layer 118 is formed above the auxiliary capacitance electrode 145, and Si (n +) portions 133, 134, 333, And a contact hole leading to 334 is formed.
  • the additional insulating layer 117 is used as an etching stopper, the additional insulating layer 117 is exposed at the bottom of the recess 160.
  • the contact hole is formed through the first interlayer insulating layer 118, the additional insulating layer 117, and the gate insulating layer 116. Thereafter, the resist 185 is removed.
  • a metal layer is stacked on the first interlayer insulating layer 118 and patterned by a photolithography method to form an auxiliary capacitor upper electrode 149, a metal layer 147, source electrodes 143 and 343, and a drain. Electrodes 144 and 344 are obtained. Thereafter, a second interlayer insulating layer 119 is stacked on the first interlayer insulating layer 118, and a contact hole is formed in the second interlayer insulating layer 119 on the drain electrode 144. Next, ITO is laminated on the second interlayer insulating layer 119 and patterned by photolithography to form the pixel electrode 120, whereby the active matrix substrate 100 shown in FIG. 8F is completed.
  • the additional insulating layer 117 serves as an etching stopper when forming the recess 160, the recess 160 having a uniform depth for a plurality of pixels without strictly controlling the etching time. Can be formed. Thereby, it is possible to provide a high-quality display in which variation in luminance among a plurality of pixels is suppressed. Further, by using halftone exposure, the recess 160 and the contact hole can be formed in the first interlayer insulating layer 118 with one resist, so that the manufacturing efficiency can be improved and the manufacturing cost can be reduced.
  • the halftone exposure used here can be applied to the manufacturing method of the first embodiment.
  • FIG. 9 is a cross-sectional view schematically showing the configuration of the active matrix substrate 100 according to Embodiment 4
  • FIG. 10 is a circuit diagram showing the configuration of the pixels in the active matrix substrate 100.
  • the active matrix substrate 100 includes a semiconductor layer 114, a gate insulating layer 116, an additional insulating layer 117, a first interlayer insulating layer 118, a second interlayer insulating layer 119, and a pixel electrode, which are sequentially stacked on the substrate 101. 120.
  • the additional insulating layer 117 is formed on the gate insulating layer 116 so as to cover the auxiliary capacitance electrode 145 and the gate electrode 140. Similar to the second embodiment, the concave portion 160 of the first interlayer insulating layer 118 is formed above the auxiliary capacitance electrode 145, and the additional insulating layer 117 is exposed at the bottom of the concave portion 160. In the fourth embodiment, the Cs portion 105 does not include the semiconductor layer 114, and no auxiliary capacitance lower electrode is formed. Therefore, the auxiliary capacitor 150 includes the auxiliary capacitor electrode 145, the auxiliary capacitor upper electrode 149, and the additional insulating layer 117 between the two electrodes. Other configurations are basically the same as those of the second embodiment.
  • auxiliary capacitor 150 Even in such a configuration of the auxiliary capacitor 150, by forming the recess 160, the distance between the auxiliary capacitor electrode 145 and the auxiliary capacitor upper electrode 149 can be shortened, so that a relatively large auxiliary capacitor can be obtained. Can do. Further, by using a member having a high dielectric constant for the additional insulating layer 117, a larger auxiliary capacitance can be obtained.
  • a configuration in which the concave portion 160 is formed without forming the additional insulating layer 117 as in the first embodiment is also included in the fourth embodiment.
  • FIGS. 11A to 11F are cross-sectional views schematically showing a method for manufacturing the active matrix substrate 100 according to the fourth embodiment.
  • a base film (not shown) is formed on the substrate 101, and a semiconductor layer 114 made of crystalline silicon or polysilicon is stacked thereon.
  • the semiconductor layer 114 is patterned by photolithography, and the semiconductor layer 114 is selectively left in the TFT portion 103 and the driver TFT portion 107. At this time, the semiconductor layer 114 is not left in the Cs portion 105.
  • a gate insulating layer 116 is formed so as to cover the semiconductor layer 114, and p-type impurities 190 are ion-implanted into the remaining semiconductor layer 114 as shown in FIG.
  • a resist 185 is formed above the region of the TFT portion 103 and the region of the driver TFT portion 107 that becomes the channel portion 330 of the driver TFT, and the n-type impurity 191 is applied from above. Dope. Thereby, the semiconductor layer 114 in the region not covered with the resist 185 in the driver TFT portion 107 becomes the Si (n ⁇ ) semiconductor portion.
  • a metal layer is formed on the gate insulating layer 116, and is patterned by photolithography.
  • the auxiliary capacitance electrode 145 of 105, the gate electrode 140 of the TFT portion 103, and the gate electrode 340 of the driver TFT portion 107 are obtained.
  • the semiconductor layer 114 is doped with an n-type impurity using the auxiliary capacitance electrode 145, the gate electrode 140, and the gate electrode 340 as a mask. As a result, a TFT channel portion 130 in the TFT portion 103 is obtained.
  • an additional insulating layer 117 is stacked so as to cover the auxiliary capacitance electrode 145, the gate electrode 140, and the gate electrode 340, and the first interlayer insulating layer 118 is stacked thereon.
  • a resist 185 is applied on the first interlayer insulating layer 118, and the resist 185 on the auxiliary capacitance electrode 145 is removed to form an opening, thereby obtaining a stacked structure shown in FIG.
  • the first interlayer insulating layer 118 under the opening of the resist 185 is etched to form a recess 160 above the auxiliary capacitance electrode 145 as shown in FIG.
  • the additional insulating layer 117 functions as an etching stopper.
  • the storage capacitor upper electrode 149, the metal layer 147, the source electrodes 143 and 343, and the drain electrodes 144 and 344 are formed as in the second embodiment, and the second interlayer insulation is formed thereon.
  • the layer 119 and the pixel electrode 120 are sequentially formed to complete the active matrix substrate 100 shown in FIG.
  • FIGS. 13 (e) to (g) are cross-sectional views schematically showing a method for manufacturing the active matrix substrate 100 according to the fifth embodiment. Since the cross-sectional configuration of the active matrix substrate 100 according to the fifth embodiment is basically the same as that of the fourth embodiment, the illustration is omitted here, and only the manufacturing method will be described.
  • the semiconductor layer 114 is stacked on the substrate 101 by the same method as in the fourth embodiment, and is patterned by photolithography to leave the semiconductor layer 114 of the TFT portion 103 and the driver TFT portion 107. At this time, the semiconductor layer 114 is not left in the Cs portion 105.
  • a gate insulating layer 116 so as to cover the semiconductor layer 114, a low-concentration p-type impurity 190 is ion-implanted into the remaining semiconductor layer 114 as shown in FIG.
  • a metal layer is formed on the gate insulating layer 116 and patterned by photolithography, and as shown in FIG. 12B, the auxiliary capacitance electrode 145 of the Cs portion 105 and the gate electrode of the TFT portion 103 are formed. 140 and the gate electrode 340 of the driver TFT portion 107 are obtained. However, at this time, the auxiliary capacitor electrode 145, the gate electrode 140, and the gate electrode 340 are formed so that the width thereof is wider than the final width. Thereafter, the semiconductor layer 114 is doped with an n-type impurity 191 such as phosphorus from above without removing the resist 185 left on the storage capacitor electrode 145, the gate electrode 140, and the gate electrode 340. Thereby, the semiconductor layer 114 in a region not covered with the resist 185 becomes a Si (n +) semiconductor portion.
  • the auxiliary capacitor electrode 145, the gate electrode 140, and the gate electrode 340 are side-etched by, for example, wet etching to reduce the width of these electrodes. Since the resist 185 is left, these electrodes are not etched from the top by side etching, but only from the side surface, and the width is reduced as shown in FIG.
  • the resist 185 is removed, and the semiconductor layer 114 is doped with an n-type impurity 191 using the auxiliary capacitance electrode 145, the gate electrode 140, and the gate electrode 340 as a mask. Accordingly, the channel portion 130, Si (n ⁇ ) portions 131 and 132, Si (n +) portions 133 and 134 in the TFT portion 103, and the channel portion 330, Si (n ⁇ ) portions 331 and 332 in the driver TFT portion 107, Si (n +) portions 333 and 334 are completed.
  • a recess 184 is formed in the resist 185 above 145, and an opening 186 is formed in the resist 185 above the Si (n +) portions 133, 134, 333, and 334.
  • a depression is formed in the first interlayer insulating layer below the opening 186, the first interlayer insulating layer 118 under the recess 184 is left without being etched.
  • etching is performed again, and as shown in FIG. A recess 160 is formed in one interlayer insulating layer 118, and contact holes that lead to Si (n +) portions 133, 134, 333, and 334 are formed.
  • the additional insulating layer 117 is used as an etching stopper.
  • a metal layer is stacked on the first interlayer insulating layer 118 and patterned by photolithography to obtain the auxiliary capacitor upper electrode 149, the metal layer 147, the source electrodes 143 and 343, and the drain electrodes 144 and 344.
  • a second interlayer insulating layer 119 is stacked on the first interlayer insulating layer 118, and a contact hole is formed in the second interlayer insulating layer 119 on the drain electrode 144.
  • ITO is laminated on the second interlayer insulating layer 119 and patterned by photolithography to form the pixel electrode 120, whereby the active matrix substrate 100 shown in FIG. 13G is completed.
  • the additional insulating layer 117 serves as an etching stopper when forming the recess 160, a uniform depth is provided to a plurality of pixels without strictly controlling the etching time.
  • the concave portion 160 can be formed. Thereby, it is possible to provide a high-quality display in which variation in luminance among a plurality of pixels is suppressed. Further, by using halftone exposure, the recess 160 and the contact hole can be formed in the first interlayer insulating layer 118 with one resist, so that the manufacturing efficiency can be improved and the manufacturing cost can be reduced.
  • N-type TFTs are formed in both the TFT portion 103 and the driver TFT portion 107.
  • a P-type TFT is formed in the driver TFT portion 107, an additional photolithography step and a p-type impurity doping step for the semiconductor layer 114 are required. According to the above manufacturing method, such a step is performed. There is no need to add, and manufacturing efficiency is improved.
  • the auxiliary process is performed while the resist 185 is left between the two doping steps of the n-type impurity 191.
  • Wet etching is performed on the capacitor electrode 145, the gate electrode 140, and the gate electrode 340.
  • a photolithography step is only required once.
  • the (n +) parts 333 and 334 can be completed with few steps and with high production efficiency.
  • the present invention can be suitably used for various display devices such as liquid crystal display devices, organic EL display devices, and flexible displays.

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Abstract

This active matrix substrate is provided with: a semiconductor layer (114); an insulating layer (116) that is formed on the semiconductor layer (114); an auxiliary capacitor electrode (145) that is formed on the insulating layer (116); a first interlayer insulating layer (118) that is formed on the auxiliary capacitor electrode (145); a recessed portion (160) that is formed in the first interlayer insulating layer (118) above the auxiliary capacitor electrode (145); an auxiliary capacitor upper electrode (149) that is formed on the bottom surface of the recessed portion (160); a second interlayer insulating layer (119) that is formed on the auxiliary capacitor upper electrode (149); and a pixel electrode (120) that is formed on the second interlayer insulating layer (119). Consequently, an auxiliary capacitor can have a larger capacity and a smaller size, so that a high-quality and high-precision display can be provided.

Description

アクティブマトリクス基板およびアクティブマトリクス基板の製造方法Active matrix substrate and method of manufacturing active matrix substrate
　本発明は、表示装置等に用いられるアクティブマトリクス基板に関する。 The present invention relates to an active matrix substrate used for a display device or the like.
　液晶表示装置、有機ＥＬ（Ｅｌｅｃｔｒｏ　Ｌｕｍｉｎｅｓｃｅｎｃｅ）表示装置、フレキシブル表示装置、電子ブック等の表示装置は、一般に、各画素のスイッチング素子として薄膜トランジスタ（Ｔｈｉｎ　Ｆｉｌｍ　Ｔｒａｎｓｉｓｔｏｒ；以下、「ＴＦＴ」とも呼ぶ）が形成されたアクティブマトリクス基板（「ＴＦＴ基板」とも呼ぶ）を備えている。 Generally, a display device such as a liquid crystal display device, an organic EL (Electro Luminescence) display device, a flexible display device, or an electronic book has a thin film transistor (hereinafter also referred to as “TFT”) as a switching element of each pixel. And an active matrix substrate (also referred to as “TFT substrate”).
　アクティブマトリクス基板には、複数のデータライン、複数のゲートライン、これらの交差部にそれぞれ配置された複数のＴＦＴ、液晶層などの光変調層に電圧を印加するための画素電極、印加された電圧をより長時間保持するための補助容量配線および補助容量電極などが形成されている。 The active matrix substrate includes a plurality of data lines, a plurality of gate lines, a plurality of TFTs arranged at intersections thereof, a pixel electrode for applying a voltage to a light modulation layer such as a liquid crystal layer, and an applied voltage. Auxiliary capacitance wiring, auxiliary capacitance electrodes, and the like are formed to hold the voltage for a longer time.
　アクティブマトリクス基板の一例が特許文献１に記載されている。図１４（ａ）は、特許文献１のアクティブマトリクス基板におけるＴＦＴ領域の断面構成を表しており、図１４（ｂ）は補助容量（付加容量）領域の断面構成を表している。 An example of an active matrix substrate is described in Patent Document 1. FIG. 14A shows a cross-sectional configuration of the TFT region in the active matrix substrate of Patent Document 1, and FIG. 14B shows a cross-sectional configuration of the auxiliary capacitance (additional capacitance) region.
　特許文献１の記載によれば、図１４（ａ）に示すように、このアクティブマトリクス基板のＴＦＴ領域には、絶縁性基板１１の上に形成されたチャネル層１２ａ、１２ｂ、ソース電極２３、およびドレイン電極２４ａと、チャネル層１２ａ、１２ｂ、ソース電極２３、およびドレイン電極２４ａを覆うように形成されたゲート絶縁膜１３と、ゲート絶縁膜１３の上に形成されたゲート電極３ａ、３ｂ、および第１層間絶縁膜１４と、第１層間絶縁膜１４の上に形成された第２層間絶縁膜１７が配置されている。第１層間絶縁膜１４と第２層間絶縁膜１７との間にはソースバス配線２および金属層１０が配置され、第２層間絶縁膜１７の上には画素電極４が配置されている。ソースバス配線２および金属層１０は、第１層間絶縁膜１４およびゲート絶縁膜１３に形成されたコンタクトホールを介して、それぞれソース電極２３およびドレイン電極２４ａに接続されている。画素電極４は第２層間絶縁膜１７に形成されたコンタクトホールを介して金属層１０に接続されている。 According to the description in Patent Document 1, as shown in FIG. 14A, channel regions 12a and 12b formed on an insulating substrate 11, source electrodes 23, and a TFT region of the active matrix substrate, The drain electrode 24a, the channel layers 12a and 12b, the source electrode 23, the gate insulating film 13 formed so as to cover the drain electrode 24a, the gate electrodes 3a and 3b formed on the gate insulating film 13, and the second A first interlayer insulating film 14 and a second interlayer insulating film 17 formed on the first interlayer insulating film 14 are disposed. The source bus wiring 2 and the metal layer 10 are disposed between the first interlayer insulating film 14 and the second interlayer insulating film 17, and the pixel electrode 4 is disposed on the second interlayer insulating film 17. The source bus wiring 2 and the metal layer 10 are connected to the source electrode 23 and the drain electrode 24a through contact holes formed in the first interlayer insulating film 14 and the gate insulating film 13, respectively. The pixel electrode 4 is connected to the metal layer 10 through a contact hole formed in the second interlayer insulating film 17.
　図１４（ｂ）に示すように、補助容量領域には、絶縁性基板１１の上に形成された容量用下部電極５と、容量用下部電極５を覆うように形成されたゲート絶縁膜１３と、ゲート絶縁膜１３の上に形成された付加容量電極６および第１層間絶縁膜１４と、第１層間絶縁膜１４の上に形成された第２層間絶縁膜１７が配置されている。第１層間絶縁膜１４と第２層間絶縁膜１７との間には金属層１０が配置され、第２層間絶縁膜１７の上には画素電極４が配置されている。金属層１０は第１層間絶縁膜１４およびゲート絶縁膜１３に形成されたコンタクトホールを介して容量用下部電極５に接続されており、画素電極４は第２層間絶縁膜１７のコンタクトホールを介して金属層１０に接続されている。 As shown in FIG. 14B, in the auxiliary capacitance region, a capacitor lower electrode 5 formed on the insulating substrate 11 and a gate insulating film 13 formed so as to cover the capacitor lower electrode 5 The additional capacitor electrode 6 and the first interlayer insulating film 14 formed on the gate insulating film 13 and the second interlayer insulating film 17 formed on the first interlayer insulating film 14 are disposed. The metal layer 10 is disposed between the first interlayer insulating film 14 and the second interlayer insulating film 17, and the pixel electrode 4 is disposed on the second interlayer insulating film 17. The metal layer 10 is connected to the capacitor lower electrode 5 via a contact hole formed in the first interlayer insulating film 14 and the gate insulating film 13, and the pixel electrode 4 is connected via a contact hole in the second interlayer insulating film 17. Are connected to the metal layer 10.
　特許文献１では、上記の構成により、容量用下部電極５と付加容量電極６との間に付加容量が形成されると共に、金属層１０と付加容量電極６との間にも付加容量が形成されるため、小さな面積で必要な容量を得ることができ、表示面積の開口率を向上させることができるとされている。 In Patent Document 1, an additional capacitor is formed between the capacitor lower electrode 5 and the additional capacitor electrode 6 and an additional capacitor is also formed between the metal layer 10 and the additional capacitor electrode 6 due to the above configuration. Therefore, it is said that a necessary capacity can be obtained with a small area and an aperture ratio of a display area can be improved.
特開平４－２９１２４０号公報JP-A-4-291240
　近年、例えば液晶表示装置について考えた場合、スマートフォンなどの急速な普及に伴って、液晶パネルの更なる高精細化が望まれている。高精細化を進める際に問題となるのが、画素サイズの縮小に伴う画素開口率の低下である。高い開口率を維持するためには、遮光部材の配置面積を小さくする必要があり、画素内に形成される補助容量（Ｃｓ）のサイズ(補助容量の形成に寄与する電極面積)も小さくする必要がある。しかし、補助容量のサイズが小さくなると、補助容量の容量も小さくなりＴＦＴから液晶に印加された電圧の保持能力が低下する。 In recent years, for example, when considering a liquid crystal display device, with the rapid spread of smartphones and the like, higher definition of liquid crystal panels is desired. A problem in promoting high definition is a decrease in the pixel aperture ratio accompanying the reduction in pixel size. In order to maintain a high aperture ratio, it is necessary to reduce the arrangement area of the light shielding member, and it is also necessary to reduce the size of the auxiliary capacitance (Cs) formed in the pixel (electrode area contributing to the formation of the auxiliary capacitance). There is. However, when the size of the auxiliary capacitor is reduced, the capacity of the auxiliary capacitor is also reduced, and the holding ability of the voltage applied from the TFT to the liquid crystal is lowered.
　図１５に、液晶表示装置に用いられるアクティブマトリクス基板の一例の断面構成を示す。図１５に示すように、アクティブマトリクス基板２００は、基板２０１の上に順次積層された半導体層２１４、ゲート絶縁層２１６、第１層間絶縁層２１８、第２層間絶縁層２１９、および画素電極２２０を備えている。半導体層２１４は、例えば結晶質シリコンからなり、ゲート絶縁層２１６および第１層間絶縁層２１８は、例えば窒化シリコンからなり、第２層間絶縁層２１９は、例えば有機絶縁材料からなり、画素電極２２０は例えばＩＴＯ（Ｉｎｄｉｕｍ　Ｔｉｎ　Ｏｘｉｄｅ）からなる。 FIG. 15 shows a cross-sectional configuration of an example of an active matrix substrate used in a liquid crystal display device. As shown in FIG. 15, the active matrix substrate 200 includes a semiconductor layer 214, a gate insulating layer 216, a first interlayer insulating layer 218, a second interlayer insulating layer 219, and a pixel electrode 220 that are sequentially stacked on the substrate 201. I have. The semiconductor layer 214 is made of, for example, crystalline silicon, the gate insulating layer 216 and the first interlayer insulating layer 218 are made of, for example, silicon nitride, the second interlayer insulating layer 219 is made of, for example, an organic insulating material, and the pixel electrode 220 is For example, it is made of ITO (Indium Tin Oxide).
　アクティブマトリクス基板２００のＴＦＴ部２０３における半導体層２１４は、チャネル部２３０、チャネル部２３０両端に接するＳｉ（ｎ－）部２３１および２３２、Ｓｉ（ｎ－）部２３１および２３２それぞれのチャネル部２３０とは反対側に接するＳｉ（ｎ＋）部２３３および２３４を有している。チャネル部２３０上方のゲート絶縁層２１６の上には、走査線が延びており、走査線の一部がゲート電極２４０となる。 The semiconductor layer 214 in the TFT portion 203 of the active matrix substrate 200 includes the channel portion 230, the Si (n−) portions 231 and 232 that are in contact with both ends of the channel portion 230, and the respective channel portions 230 of the Si (n−) portions 231 and 232. Si (n +) portions 233 and 234 are in contact with the opposite side. A scanning line extends over the gate insulating layer 216 above the channel portion 230, and a part of the scanning line becomes the gate electrode 240.
　Ｓｉ（ｎ＋）部２３３および２３４それぞれの上の第１層間絶縁層２１８にはコンタクトホールが形成されており、それらのコンタクトホールを埋めるように、ソース電極２４３およびドレイン電極２４４が形成されている。ソース電極２４３およびドレイン電極２４４の下部は、それぞれＳｉ（ｎ＋）部２３３および２３４に接している。Ｓｉ（ｎ＋）部２３３および２３４は、それぞれソース電極２４３およびドレイン電極２４４に対するコンタクト部として機能する。 Contact holes are formed in the first interlayer insulating layer 218 on each of the Si (n +) portions 233 and 234, and a source electrode 243 and a drain electrode 244 are formed so as to fill the contact holes. Lower portions of the source electrode 243 and the drain electrode 244 are in contact with the Si (n +) portions 233 and 234, respectively. Si (n +) portions 233 and 234 function as contact portions for the source electrode 243 and the drain electrode 244, respectively.
　ソース電極２４３の上部は、第１層間絶縁層２１８の上を延びる信号線２４６に接続されている。ドレイン電極２４４の上の第２層間絶縁層２１９にはコンタクトホールが形成されており、このコンタクトホールを介して画素電極２２０がドレイン電極２４４に接している。 The upper part of the source electrode 243 is connected to a signal line 246 extending on the first interlayer insulating layer 218. A contact hole is formed in the second interlayer insulating layer 219 above the drain electrode 244, and the pixel electrode 220 is in contact with the drain electrode 244 through the contact hole.
　アクティブマトリクス基板２００のＣｓ部２０５においては、半導体層２１４はＳｉ（ｎ－）部２３７で構成され、ゲート絶縁層２１６の上には補助容量電極（上層電極）２４５が形成されている。補助容量電極２４５の下のＳｉ（ｎ－）部２３７は補助容量下部電極（下層電極）２３９として機能し、補助容量電極２４５、補助容量下部電極２３９、および両電極の間のゲート絶縁層２１６によって補助容量が形成される。 In the Cs portion 205 of the active matrix substrate 200, the semiconductor layer 214 is composed of an Si (n−) portion 237, and an auxiliary capacitance electrode (upper layer electrode) 245 is formed on the gate insulating layer 216. The Si (n−) portion 237 below the auxiliary capacitance electrode 245 functions as the auxiliary capacitance lower electrode (lower layer electrode) 239, and is constituted by the auxiliary capacitance electrode 245, the auxiliary capacitance lower electrode 239, and the gate insulating layer 216 between the two electrodes. A storage capacitor is formed.
　ゲート絶縁層２１６は、誘電体によって非常に薄く形成することが可能である。したがって、補助容量電極２４５および補助容量下部電極２３９の占有面積（基板面内において占める面積）を小さくしても、比較的大きな補助容量を得ることができ、画素の高密度化、開口率の向上を図ることができる。 The gate insulating layer 216 can be formed very thin with a dielectric. Therefore, even if the area occupied by the auxiliary capacitance electrode 245 and the auxiliary capacitance lower electrode 239 (area occupied in the substrate surface) is reduced, a relatively large auxiliary capacitance can be obtained, the pixel density is increased, and the aperture ratio is improved. Can be achieved.
　しかし、近年、表示装置に対する小型化、高精細化、高輝度化の要求はますます強くなってきている。小型化、高精細化を高輝度化と両立させるためには、補助容量の占有面積を更に小さくして、画素を更に小型化、高開口率化する必要があるが、同時に十分な補助容量を確保する必要もあるため、占有面積の縮小には限界がある。 However, in recent years, there has been an increasing demand for smaller, higher definition, and higher brightness display devices. In order to achieve both downsizing and high definition with high brightness, it is necessary to further reduce the area occupied by the auxiliary capacitor, further downsize the pixel and increase the aperture ratio. Since it is also necessary to ensure, there is a limit to the reduction of the occupied area.
　特許文献１のアクティブマトリクス基板では、容量用下部電極５と付加容量電極６との間、および金属層１０と付加容量電極６との間に容量が形成されるとされている。しかし、層間絶縁層の上には信号線が配置され、層間絶縁層の下には走査線が配置されており、信号線と走査線が交わる部位において、層間絶縁層は両線間の絶縁機能を担っている。そのため、層間絶縁層の厚さはゲート絶縁層に比べて数倍～１０倍程度の厚さを有している。また、信号線および走査線の信号品質を向上させるためには、層間絶縁層を厚くして両線間の寄生容量を低減させる必要がある。したがって、特許文献１のアクティブマトリクス基板においては、金属層１０と付加容量電極６との間の距離を大きくする必要があり、金属層１０と付加容量電極６との間に十分な補助容量を形成することができない。 In the active matrix substrate of Patent Document 1, capacitance is formed between the capacitor lower electrode 5 and the additional capacitor electrode 6 and between the metal layer 10 and the additional capacitor electrode 6. However, a signal line is disposed on the interlayer insulating layer, and a scanning line is disposed below the interlayer insulating layer. At the portion where the signal line and the scanning line intersect, the interlayer insulating layer functions as an insulation between the two lines. Is responsible. Therefore, the thickness of the interlayer insulating layer is several times to 10 times that of the gate insulating layer. In addition, in order to improve the signal quality of the signal line and the scanning line, it is necessary to increase the thickness of the interlayer insulating layer to reduce the parasitic capacitance between the two lines. Therefore, in the active matrix substrate of Patent Document 1, it is necessary to increase the distance between the metal layer 10 and the additional capacitance electrode 6, and a sufficient auxiliary capacitance is formed between the metal layer 10 and the additional capacitance electrode 6. Can not do it.
　本発明は、上記に鑑みてなされたものであり、十分な補助容量を確保するとともに、高精彩かつ高輝度な表示装置を提供すること、または、そのような表示装置に好適に用いられ得るアクティブマトリクス基板を提供することを目的とする。 The present invention has been made in view of the above, and provides a high-definition and high-luminance display device while ensuring a sufficient auxiliary capacity, or an active device that can be suitably used for such a display device. An object is to provide a matrix substrate.
　本発明によるアクティブマトリクス基板は、半導体層と、前記半導体層の上に形成された絶縁層と、前記絶縁層の上に形成された補助容量電極と、前記補助容量電極の上に形成された第１層間絶縁層と、前記補助容量電極の上方の前記第１層間絶縁層に形成された凹部と、前記凹部の底面の上に形成された補助容量上部電極と、前記補助容量上部電極の上に形成された第２層間絶縁層と、前記第２層間絶縁層の上に形成された画素電極と、を備えている。 An active matrix substrate according to the present invention includes a semiconductor layer, an insulating layer formed on the semiconductor layer, an auxiliary capacitance electrode formed on the insulating layer, and a first electrode formed on the auxiliary capacitance electrode. A first interlayer insulating layer; a recess formed in the first interlayer insulating layer above the storage capacitor electrode; a storage capacitor upper electrode formed on a bottom surface of the recess; and the storage capacitor upper electrode A second interlayer insulating layer formed; and a pixel electrode formed on the second interlayer insulating layer.
　ある実施形態では、前記補助容量電極の上面と前記補助容量上部電極との間に酸化シリコンからなる層が配置され、前記補助容量電極の上面から前記補助容量上部電極の下面までの距離が、１０ｎｍ以上１００ｎｍ以下である。 In one embodiment, a layer made of silicon oxide is disposed between the upper surface of the auxiliary capacitance electrode and the auxiliary capacitance upper electrode, and the distance from the upper surface of the auxiliary capacitance electrode to the lower surface of the auxiliary capacitance upper electrode is 10 nm. It is 100 nm or less.
　ある実施形態では、前記補助容量電極の上面と前記補助容量上部電極との間に窒化シリコンからなる層が配置され、前記補助容量電極の上面から前記補助容量上部電極の下面までの距離が、１０ｎｍ以上２００ｎｍ以下である。 In one embodiment, a layer made of silicon nitride is disposed between the upper surface of the auxiliary capacitance electrode and the auxiliary capacitance upper electrode, and the distance from the upper surface of the auxiliary capacitance electrode to the lower surface of the auxiliary capacitance upper electrode is 10 nm. It is 200 nm or less.
　ある実施形態では、前記補助容量上部電極と前記半導体層とが、前記絶縁層および前記第１層間絶縁層に形成されたコンタクトホールを介して電気的に接続されており、前記補助容量上部電極と前記画素電極とが、前記第２層間絶縁層に形成されたコンタクトホールを介して電気的に接続されている。 In one embodiment, the auxiliary capacitor upper electrode and the semiconductor layer are electrically connected via a contact hole formed in the insulating layer and the first interlayer insulating layer, and the auxiliary capacitor upper electrode The pixel electrode is electrically connected through a contact hole formed in the second interlayer insulating layer.
　ある実施形態では、前記半導体層が、前記補助容量電極の下部に形成され、不純物をドープした半導体からなる補助容量下部電極を含む。 In one embodiment, the semiconductor layer includes a storage capacitor lower electrode made of a semiconductor doped with an impurity and formed under the storage capacitor electrode.
　ある実施形態では、前記補助容量電極の上に追加絶縁層が形成されており、前記補助容量電極の上面が前記追加絶縁層の下面と接し、前記補助容量上部電極の下面が前記追加絶縁層の上面と接している。 In one embodiment, an additional insulating layer is formed on the auxiliary capacitance electrode, the upper surface of the auxiliary capacitance electrode is in contact with the lower surface of the additional insulating layer, and the lower surface of the auxiliary capacitance upper electrode is the additional insulating layer. It is in contact with the top surface.
　ある実施形態では、前記追加絶縁層が窒化シリコンからなり、前記第１層間絶縁層が酸化シリコンからなる。 In one embodiment, the additional insulating layer is made of silicon nitride, and the first interlayer insulating layer is made of silicon oxide.
　本発明によるアクティブマトリクス基板の製造方法は、半導体層を形成する工程と、前記半導体層の上に絶縁層を形成する工程と、前記絶縁層の上に補助容量電極を形成する工程と、前記補助容量電極の上に第１層間絶縁層を形成する工程と、前記補助容量電極の上方の前記第１層間絶縁層に凹部を形成する工程と、前記凹部の底面の上に補助容量上部電極を形成する工程と、前記補助容量上部電極の上に第２層間絶縁層を形成する工程と、前記第２層間絶縁層の上に画素電極を形成する工程と、を含んでいる。 The manufacturing method of the active matrix substrate according to the present invention includes a step of forming a semiconductor layer, a step of forming an insulating layer on the semiconductor layer, a step of forming an auxiliary capacitance electrode on the insulating layer, and the auxiliary Forming a first interlayer insulating layer on the capacitor electrode; forming a recess in the first interlayer insulating layer above the auxiliary capacitor electrode; and forming an auxiliary capacitor upper electrode on the bottom surface of the recess A step of forming a second interlayer insulating layer on the storage capacitor upper electrode, and a step of forming a pixel electrode on the second interlayer insulating layer.
　ある実施形態では、前記補助容量電極の上面と前記補助容量上部電極との間に酸化シリコンからなる層が形成され、前記補助容量電極の上面から前記凹部の底面までの距離が、１０ｎｍ以上１００ｎｍ以下となるように、前記第１層間絶縁層に前記凹部が形成される。 In one embodiment, a layer made of silicon oxide is formed between the upper surface of the auxiliary capacitance electrode and the auxiliary capacitance upper electrode, and the distance from the upper surface of the auxiliary capacitance electrode to the bottom surface of the recess is 10 nm or more and 100 nm or less. Thus, the recess is formed in the first interlayer insulating layer.
　ある実施形態では、前記補助容量電極の上面と前記補助容量上部電極との間に窒化シリコンからなる層が形成され、前記補助容量電極の上面から前記凹部の底面までの距離が、１０ｎｍ以上２００ｎｍ以下となるように、前記第１層間絶縁層に前記凹部が形成される。 In one embodiment, a layer made of silicon nitride is formed between the upper surface of the auxiliary capacitor electrode and the upper electrode of the auxiliary capacitor, and the distance from the upper surface of the auxiliary capacitor electrode to the bottom surface of the recess is 10 nm or more and 200 nm or less. Thus, the recess is formed in the first interlayer insulating layer.
　ある実施形態では、前記凹部を形成する工程は、前記第１層間絶縁層の上にレジストを形成する工程と、前記補助容量電極の上方に前記レジストの開口を形成する工程と、前記レジストの前記開口の下の前記第１層間絶縁層を選択的にエッチングする工程と、を含む。 In one embodiment, the step of forming the recess includes a step of forming a resist on the first interlayer insulating layer, a step of forming an opening of the resist above the auxiliary capacitance electrode, and the step of forming the resist. Selectively etching the first interlayer insulating layer under the opening.
　ある実施形態では、前記凹部を形成する工程は、前記第１層間絶縁層の上にレジストを形成する工程と、第１窓と、前記第１窓よりも光透過率の高い複数の第２窓とを有するマスクを前記レジストの上方に配置する工程と、前記第１窓および前記複数の第２窓を介して前記レジストに光を照射する工程と、光を照射された前記レジストを除去して、前記レジストに窪みと複数の開口とを形成する工程と、前記レジストを介して前記第１層間絶縁層を選択的にエッチングして、前記補助容量電極の上に前記第１層間絶縁層の前記凹部を形成するとともに、前記レジストの前記開口の下に前記半導体層に通じるコンタクトホールを形成する工程と、を含む。 In one embodiment, the step of forming the recess includes a step of forming a resist on the first interlayer insulating layer, a first window, and a plurality of second windows having a higher light transmittance than the first window. And a step of irradiating the resist with light through the first window and the plurality of second windows, and removing the resist irradiated with light. Forming a recess and a plurality of openings in the resist; and selectively etching the first interlayer insulating layer through the resist to form the first interlayer insulating layer on the auxiliary capacitance electrode. Forming a recess, and forming a contact hole leading to the semiconductor layer under the opening of the resist.
　ある実施形態では、上記製造方法は前記半導体層に不純物をドープする工程を含み、前記補助容量電極を形成する工程において、前記補助容量電極が、前記不純物をドープされた前記半導体層の上に形成される。 In one embodiment, the manufacturing method includes a step of doping impurities into the semiconductor layer, and in the step of forming the auxiliary capacitance electrode, the auxiliary capacitance electrode is formed on the semiconductor layer doped with the impurity. Is done.
　ある実施形態では、上記製造方法は前記補助容量電極の上に追加絶縁層を形成する工程を含み、前記第１層間絶縁層に前記凹部を形成する工程において、前記追加絶縁層をエッチングストッパとして用いて、前記凹部の底面に前記追加絶縁層が露出するように前記第１層間絶縁層がエッチングされる。 In one embodiment, the manufacturing method includes a step of forming an additional insulating layer on the auxiliary capacitance electrode, and the additional insulating layer is used as an etching stopper in the step of forming the recess in the first interlayer insulating layer. Then, the first interlayer insulating layer is etched so that the additional insulating layer is exposed at the bottom surface of the recess.
　ある実施形態では、前記追加絶縁層が窒化シリコンから形成され、前記第１層間絶縁層が酸化シリコンから形成される。 In one embodiment, the additional insulating layer is formed from silicon nitride, and the first interlayer insulating layer is formed from silicon oxide.
　本発明によれば、補助容量電極と補助容量上部電極との間に大きな補助容量を形成することができるので、表示品質の高い表示装置を提供することができる。また、本発明によれば、大きな補助容量を占有領域の小さな電極で得ることができるので、高精細な表示装置を提供することができる。また、補助容量電極と補助容量上部電極から得られる補助容量に加えて、補助容量電極と半導体層との間にも補助容量を形成することができるので、より表示品質の高い表示装置またはより高精細な表示装置を提供することができる。 According to the present invention, since a large auxiliary capacitance can be formed between the auxiliary capacitance electrode and the auxiliary capacitance upper electrode, a display device with high display quality can be provided. In addition, according to the present invention, a large auxiliary capacitance can be obtained with an electrode having a small occupied area, so that a high-definition display device can be provided. In addition to the auxiliary capacitance obtained from the auxiliary capacitance electrode and the auxiliary capacitance upper electrode, an auxiliary capacitance can be formed between the auxiliary capacitance electrode and the semiconductor layer, so that a display device with higher display quality or higher A fine display device can be provided.
本発明の実施形態１によるアクティブマトリクス基板１００の構成を模式的に表した断面図である。1 is a cross-sectional view schematically showing a configuration of an active matrix substrate 100 according to Embodiment 1 of the present invention. 本発明の実施形態１による液晶表示装置１０００の構成を模式的に表した斜視図である。It is the perspective view which represented typically the structure of the liquid crystal display device 1000 by Embodiment 1 of this invention. 実施形態１によるアクティブマトリクス基板１００における画素領域の構成を模式的に表した平面図である。FIG. 2 is a plan view schematically showing a configuration of a pixel region in an active matrix substrate 100 according to Embodiment 1. 実施形態１によるアクティブマトリクス基板１００の画素の構成を表した回路図である。2 is a circuit diagram illustrating a configuration of a pixel of an active matrix substrate 100 according to Embodiment 1. FIG. （ａ）～（ｇ）は、実施形態１によるアクティブマトリクス基板１００の製造方法を表した断面図である。FIGS. 4A to 4G are cross-sectional views illustrating a method for manufacturing the active matrix substrate 100 according to the first embodiment. 本発明の実施形態２によるアクティブマトリクス基板１００の構成を模式的に表した断面図である。It is sectional drawing which represented typically the structure of the active matrix substrate 100 by Embodiment 2 of this invention. （ａ）～（ｄ）は、実施形態２によるアクティブマトリクス基板１００の製造方法を表した断面図である。FIGS. 4A to 4D are cross-sectional views illustrating a method for manufacturing the active matrix substrate 100 according to the second embodiment. （ａ）～（ｆ）は、実施形態３によるアクティブマトリクス基板１００の製造方法を表した断面図である。FIGS. 5A to 5F are cross-sectional views illustrating a method for manufacturing the active matrix substrate 100 according to the third embodiment. 本発明の実施形態４によるアクティブマトリクス基板１００の構成を模式的に表した断面図である。It is sectional drawing which represented typically the structure of the active matrix substrate 100 by Embodiment 4 of this invention. 実施形態４によるアクティブマトリクス基板１００の画素の構成を表した回路図である。6 is a circuit diagram illustrating a configuration of a pixel of an active matrix substrate 100 according to Embodiment 4. FIG. （ａ）～（ｆ）は、実施形態４によるアクティブマトリクス基板１００の製造方法を表した断面図である。FIGS. 8A to 8F are cross-sectional views illustrating a method for manufacturing the active matrix substrate 100 according to the fourth embodiment. （ａ）～（ｄ）は、実施形態５によるアクティブマトリクス基板１００の製造方法を表した断面図である。FIGS. 9A to 9D are cross-sectional views illustrating a method for manufacturing the active matrix substrate 100 according to the fifth embodiment. （ｅ）～（ｇ）は、実施形態５によるアクティブマトリクス基板１００の製造方法を表した断面図である。FIGS. 5E to 5G are cross-sectional views illustrating a method for manufacturing the active matrix substrate 100 according to the fifth embodiment. （ａ）および（ｂ）は、特許文献１に記載されたアクティブマトリクス基板の構成を表した断面図である。(A) And (b) is sectional drawing showing the structure of the active-matrix board | substrate described in patent document 1. FIG. 参考例のアクティブマトリクス基板２００の構成を模式的に表した断面図である。It is sectional drawing which represented typically the structure of the active matrix substrate 200 of a reference example.
　以下、図面を参照しながら、本発明の実施形態によるアクティブマトリクス基板を説明する。ただし、本発明の範囲は以下の実施形態に限られるものではない。本発明のアクティブマトリクス基板は、液晶表示装置、有機ＥＬ表示装置など、各種の表示装置のアクティブマトリクス基板として用いられ得る。本発明によるアクティブマトリクス基板を表示装置に用いる場合、その対向基板、周辺配線など、以下に説明するアクティブマトリクス基板以外の構成要素には、基本的に公知の構成要素が用いられ得る。 Hereinafter, an active matrix substrate according to an embodiment of the present invention will be described with reference to the drawings. However, the scope of the present invention is not limited to the following embodiments. The active matrix substrate of the present invention can be used as an active matrix substrate for various display devices such as liquid crystal display devices and organic EL display devices. When the active matrix substrate according to the present invention is used in a display device, known components can basically be used for components other than the active matrix substrate described below, such as the counter substrate and peripheral wiring.
　（実施形態１）
　図１は、実施形態１によるアクティブマトリクス基板１００の構成を模式的に表した断面図である。図１に示すように、アクティブマトリクス基板１００は、基板１０１の上に順次積層された半導体層１１４、ゲート絶縁層（単に絶縁層とも呼ぶ）１１６、第１層間絶縁層１１８、第２層間絶縁層１１９、および画素電極１２０を備えている。半導体層１１４は、例えば結晶質シリコンまたはポリシリコンからなり、ゲート絶縁層１１６および第１層間絶縁層１１８は、例えば窒化シリコンからなり、第２層間絶縁層１１９は、例えば有機絶縁材料からなり、画素電極１２０は例えばＩＴＯからなる。 (Embodiment 1)
FIG. 1 is a cross-sectional view schematically showing the configuration of the active matrix substrate 100 according to the first embodiment. As shown in FIG. 1, an active matrix substrate 100 includes a semiconductor layer 114, a gate insulating layer (also simply referred to as an insulating layer) 116, a first interlayer insulating layer 118, and a second interlayer insulating layer that are sequentially stacked on the substrate 101. 119 and a pixel electrode 120. The semiconductor layer 114 is made of, for example, crystalline silicon or polysilicon, the gate insulating layer 116 and the first interlayer insulating layer 118 are made of, for example, silicon nitride, and the second interlayer insulating layer 119 is made of, for example, an organic insulating material. The electrode 120 is made of, for example, ITO.
　アクティブマトリクス基板１００には複数の画素が形成されており、各画素は、ＴＦＴ１２５が形成されたＴＦＴ部１０３と、補助容量１５０が形成されたＣｓ部１０５とを有している。 A plurality of pixels are formed on the active matrix substrate 100, and each pixel has a TFT portion 103 in which a TFT 125 is formed and a Cs portion 105 in which an auxiliary capacitor 150 is formed.
　ＴＦＴ部１０３におけるＴＦＴ１２５の半導体層１１４は、チャネル部１３０、チャネル部１３０両端に接するＳｉ（ｎ－）部１３１および１３２、Ｓｉ（ｎ－）部１３１および１３２それぞれのチャネル部１３０とは反対側の端部に接するＳｉ（ｎ＋）部１３３および１３４を有している。チャネル部１３０の上方のゲート絶縁層１１６の上には、走査線が延びており、走査線の一部がゲート電極１４０となっている。 The semiconductor layer 114 of the TFT 125 in the TFT unit 103 includes a channel unit 130, Si (n−) units 131 and 132 in contact with both ends of the channel unit 130, and the Si (n−) units 131 and 132 on the opposite side to the channel unit 130. Si (n +) portions 133 and 134 are in contact with the end portions. A scanning line extends on the gate insulating layer 116 above the channel portion 130, and a part of the scanning line becomes a gate electrode 140.
　Ｓｉ（ｎ＋）部１３３および１３４それぞれの上の第１層間絶縁層１１８にはコンタクトホールが形成されており、それらのコンタクトホールを埋めるように、ソース電極１４３およびドレイン電極１４４が形成されている。ソース電極１４３およびドレイン電極１４４の下部は、それぞれＳｉ（ｎ＋）部１３３および１３４に接している。Ｓｉ（ｎ＋）部１３３および１３４は、それぞれソース電極１４３およびドレイン電極１４４に対するコンタクト部として機能する。 Contact holes are formed in the first interlayer insulating layer 118 on each of the Si (n +) portions 133 and 134, and a source electrode 143 and a drain electrode 144 are formed so as to fill the contact holes. Lower portions of the source electrode 143 and the drain electrode 144 are in contact with Si (n +) portions 133 and 134, respectively. Si (n +) portions 133 and 134 function as contact portions for the source electrode 143 and the drain electrode 144, respectively.
　ソース電極１４３の上部は、第１層間絶縁層１１８の上を延びる信号線１４６に接続されている。ドレイン電極１４４の上の第２層間絶縁層１１９にはコンタクトホールが形成されており、このコンタクトホールを介して画素電極１２０がドレイン電極１４４に接している。 The upper part of the source electrode 143 is connected to a signal line 146 extending over the first interlayer insulating layer 118. A contact hole is formed in the second interlayer insulating layer 119 above the drain electrode 144, and the pixel electrode 120 is in contact with the drain electrode 144 through the contact hole.
　Ｃｓ部１０５においては、半導体層１１４はＳｉ（ｎ－）部１３７で構成され、ゲート絶縁層１１６の上には補助容量電極１４５が形成されている。Ｓｉ（ｎ－）部１３１、１３２、１３７は、不純物をドープすることにより低抵抗化された半導体層である。補助容量電極１４５の下のＳｉ（ｎ－）部１３７は補助容量下部電極１３９として機能する。補助容量下部電極１３９をＳｉ（ｎ＋）半導体にて形成することもあり得る。 In the Cs portion 105, the semiconductor layer 114 is composed of an Si (n−) portion 137, and an auxiliary capacitance electrode 145 is formed on the gate insulating layer 116. The Si (n−) parts 131, 132, and 137 are semiconductor layers whose resistance is reduced by doping impurities. The Si (n−) portion 137 below the auxiliary capacitance electrode 145 functions as the auxiliary capacitance lower electrode 139. The auxiliary capacitance lower electrode 139 may be formed of a Si (n +) semiconductor.
　補助容量電極１４５の上方の第１層間絶縁層１１８には凹部１６０が形成されている。凹部１６０の底面には補助容量上部電極１４９が形成されている。補助容量電極１４５の上面から補助容量上部電極１４９の下面（あるいは凹部１６０の底面）までの距離ｄは、第１層間絶縁層１１８が酸化シリコンからなる場合、１０ｎｍ以上１００ｎｍ以下であり、窒化シリコンからなる場合、１０ｎｍ以上２００ｎｍ以下である。 A recess 160 is formed in the first interlayer insulating layer 118 above the auxiliary capacitance electrode 145. A storage capacitor upper electrode 149 is formed on the bottom surface of the recess 160. The distance d from the upper surface of the auxiliary capacitance electrode 145 to the lower surface of the auxiliary capacitance upper electrode 149 (or the bottom surface of the recess 160) is 10 nm or more and 100 nm or less when the first interlayer insulating layer 118 is made of silicon oxide. In this case, it is 10 nm or more and 200 nm or less.
　補助容量上部電極１４９は第１層間絶縁層１１８の上面に形成された金属層１４７の一部である。金属層１４７は第１層間絶縁層１１８の上でドレイン電極１４４に接続されており、第２層間絶縁層１１９に形成されたコンタクトホールを介して画素電極１２０に接続されている。補助容量上部電極１４９と補助容量下部電極１３９は、金属層１４７、ゲート絶縁層１１６および第１層間絶縁層１１８に形成されたコンタクトホールを埋めるドレイン電極１４４、および半導体層１１４を介して電気的に接続されている。また、補助容量上部電極１４９と画素電極１２０は、金属層１４７および第２層間絶縁層１１９に形成されたコンタクトホールを介して電気的に接続されている。 The auxiliary capacitance upper electrode 149 is a part of the metal layer 147 formed on the upper surface of the first interlayer insulating layer 118. The metal layer 147 is connected to the drain electrode 144 on the first interlayer insulating layer 118 and is connected to the pixel electrode 120 through a contact hole formed in the second interlayer insulating layer 119. The auxiliary capacitance upper electrode 149 and the auxiliary capacitance lower electrode 139 are electrically connected through the metal layer 147, the drain electrode 144 filling the contact hole formed in the gate insulating layer 116 and the first interlayer insulating layer 118, and the semiconductor layer 114. It is connected. The auxiliary capacitor upper electrode 149 and the pixel electrode 120 are electrically connected through a contact hole formed in the metal layer 147 and the second interlayer insulating layer 119.
　補助容量電極１４５、補助容量下部電極１３９、および両電極の間のゲート絶縁層１１６によって容量が形成されるとともに、補助容量電極１４５、補助容量上部電極１４９、および両電極の間の第１層間絶縁層１１８によっても容量が形成され、これら２つの容量を合わせたものが各画素の補助容量１５０となる。ゲート絶縁層１１６は非常に薄く、その厚さは１０ｎｍ以上１００ｎｍ以下であるため、補助容量電極１４５と補助容量下部電極１３９との間に大きな容量を形成することができる。また、第１層間絶縁層１１８に凹部１６０が形成されることから、補助容量電極１４５と補助容量上部電極１４９との間の距離も小さくすることができるので、これら両電極の間にも大きな容量を形成することができる。 A capacitance is formed by the auxiliary capacitance electrode 145, the auxiliary capacitance lower electrode 139, and the gate insulating layer 116 between both electrodes, and the first interlayer insulation between the auxiliary capacitance electrode 145, the auxiliary capacitance upper electrode 149, and both electrodes. A capacitor is also formed by the layer 118, and the sum of these two capacitors becomes the auxiliary capacitor 150 of each pixel. Since the gate insulating layer 116 is very thin and has a thickness of 10 nm to 100 nm, a large capacitance can be formed between the auxiliary capacitance electrode 145 and the auxiliary capacitance lower electrode 139. In addition, since the recess 160 is formed in the first interlayer insulating layer 118, the distance between the auxiliary capacitance electrode 145 and the auxiliary capacitance upper electrode 149 can be reduced, so that a large capacitance is also present between these two electrodes. Can be formed.
　したがって、従来のアクティブマトリクス基板に比べて、大きな容量の補助容量１５０を各画素に形成することが可能となる。また、凹部１６０以外の第１層間絶縁層１１８を十分な厚さに形成したとしても、大きな容量を得ることができるので、表示品質および信頼性の両方を高いレベルで実現し得るアクティブマトリクス基板を提供することが可能となる。さらに、補助容量電極１４５、補助容量下部電極１３９、および補助容量上部電極１４９の占有面積を小さくしても、比較的大きな補助容量を得ることができるので、画素の高密度化、開口率の向上を図ることができる。 Therefore, it is possible to form the auxiliary capacitor 150 having a large capacity in each pixel as compared with the conventional active matrix substrate. In addition, even if the first interlayer insulating layer 118 other than the recess 160 is formed to a sufficient thickness, a large capacity can be obtained. Therefore, an active matrix substrate that can realize both display quality and reliability at a high level is provided. It becomes possible to provide. Furthermore, even if the area occupied by the auxiliary capacitance electrode 145, the auxiliary capacitance lower electrode 139, and the auxiliary capacitance upper electrode 149 is reduced, a relatively large auxiliary capacitance can be obtained, so that the pixel density is increased and the aperture ratio is improved. Can be achieved.
　図２は、本発明による液晶表示装置１０００の構成を模式的に表した斜視図である。液晶表示装置１０００は、そのＴＦＴ基板として本発明の実施形態によるアクティブマトリクス基板１００を備えている。図３は、アクティブマトリクス基板１００における画素の配置構成を模式的に表した平面図であり、図４は、各画素の回路構成を表した回路図である。 FIG. 2 is a perspective view schematically showing the configuration of the liquid crystal display device 1000 according to the present invention. The liquid crystal display device 1000 includes an active matrix substrate 100 according to an embodiment of the present invention as its TFT substrate. FIG. 3 is a plan view schematically showing an arrangement configuration of pixels in the active matrix substrate 100, and FIG. 4 is a circuit diagram showing a circuit configuration of each pixel.
　図２に示すように、液晶表示装置１０００は、液晶層を挟んで互いに対向するアクティブマトリクス基板１００および対向基板５００と、アクティブマトリクス基板１００および対向基板５００のそれぞれの外面に貼り付けられた偏光板５１０および５２０と、表示用の光を出射するバックライトユニット５３０とを備えている。 As shown in FIG. 2, the liquid crystal display device 1000 includes an active matrix substrate 100 and a counter substrate 500 facing each other with a liquid crystal layer interposed therebetween, and polarizing plates attached to the outer surfaces of the active matrix substrate 100 and the counter substrate 500. 510 and 520 and a backlight unit 530 for emitting display light.
　対向基板５００は、カラーフィルタおよび共通電極を備えている。カラーフィルタは、３原色表示の場合、それぞれが画素に対応して配置されたＲ（赤）フィルタ、Ｇ（緑）フィルタ、およびＢ（青）フィルタを含む。対向基板５００を４原色以上の表示方式に対応させてもよい。共通電極は、液晶層を挟んで複数の画素電極１２０を覆うように形成されている。共通電極と各画素電極１２０との間に与えられる電位差に応じて両電極の間の液晶が画素毎に配向し、表示がなされる。 The counter substrate 500 includes a color filter and a common electrode. In the case of displaying three primary colors, the color filter includes an R (red) filter, a G (green) filter, and a B (blue) filter, each of which is arranged corresponding to a pixel. The counter substrate 500 may correspond to a display method of four primary colors or more. The common electrode is formed so as to cover the plurality of pixel electrodes 120 with the liquid crystal layer interposed therebetween. In accordance with the potential difference applied between the common electrode and each pixel electrode 120, the liquid crystal between both electrodes is aligned for each pixel, and display is performed.
　図３および図４に示すように、アクティブマトリクス基板１００には、複数の走査線（ゲートバスライン）１４１と複数の信号線（データバスライン）１４６とが、互いに直交するように配置されており、走査線１４１と信号線１４６との交点付近にはＴＦＴ１２５が画素１１０毎に形成されている。ここでは、画素１１０を、隣り合う２つの走査線１４１と隣り合う２つの信号線１４６との中心線によって区切られた領域として定義する。各画素１１０には、ＴＦＴ１２５のドレイン電極１４４に電気的に接続された画素電極１２０が配置されている。隣り合う２つの走査線１４１の間には補助容量線１４２が走査線１４１と平行に延びている。 As shown in FIGS. 3 and 4, a plurality of scanning lines (gate bus lines) 141 and a plurality of signal lines (data bus lines) 146 are arranged on the active matrix substrate 100 so as to be orthogonal to each other. A TFT 125 is formed for each pixel 110 near the intersection of the scanning line 141 and the signal line 146. Here, the pixel 110 is defined as a region delimited by a center line between two adjacent scanning lines 141 and two adjacent signal lines 146. Each pixel 110 is provided with a pixel electrode 120 that is electrically connected to the drain electrode 144 of the TFT 125. A storage capacitor line 142 extends in parallel with the scanning line 141 between two adjacent scanning lines 141.
　走査線１４１及び信号線１４６は、それぞれ、図２に示す走査線駆動回路５４０および信号線駆動回路５５０に接続されている。走査線１４１には、制御回路５６０による制御に応じて走査線駆動回路５４０からＴＦＴ１２５のオン－オフを切り替える走査信号が供給され、信号線１４６には、制御回路５６０による制御に応じて信号線駆動回路５５０から表示信号（画素電極１２０への印加電圧）が供給される。 The scanning line 141 and the signal line 146 are respectively connected to the scanning line driving circuit 540 and the signal line driving circuit 550 shown in FIG. A scanning signal for switching on / off of the TFT 125 is supplied from the scanning line driving circuit 540 to the scanning line 141 according to control by the control circuit 560, and signal line driving is performed to the signal line 146 according to control by the control circuit 560. A display signal (voltage applied to the pixel electrode 120) is supplied from the circuit 550.
　図４に示すように、液晶層１８０を挟んで対向する画素電極１２０と対向基板５００の対向電極１７０との間には表示容量が形成される。画素電極１２０、補助容量下部電極１３９、および補助容量上部電極１４９は、ＴＦＴ１２５のドレイン電極と同電位であり、補助容量電極１４５には補助容量線１４２を介して対向電極１７０と同じ基準電位が与えられる。この構成により、補助容量電極１４５と補助容量下部電極１３９との間、および補助容量電極１４５と補助容量上部電極１４９との間に形成される容量は、表示容量を保つための補助容量として機能する。 As shown in FIG. 4, a display capacitor is formed between the pixel electrode 120 and the counter electrode 170 of the counter substrate 500 facing each other with the liquid crystal layer 180 interposed therebetween. The pixel electrode 120, the auxiliary capacitor lower electrode 139, and the auxiliary capacitor upper electrode 149 have the same potential as the drain electrode of the TFT 125, and the same reference potential as that of the counter electrode 170 is applied to the auxiliary capacitor electrode 145 through the auxiliary capacitor line 142. It is done. With this configuration, the capacitance formed between the auxiliary capacitance electrode 145 and the auxiliary capacitance lower electrode 139 and between the auxiliary capacitance electrode 145 and the auxiliary capacitance upper electrode 149 functions as an auxiliary capacitance for maintaining the display capacitance. .
　補助容量１５０の容量Ｃｓは次の式で表される。
　Ｃｓ＝Ｃｓ１＋Ｃｓ２＝ε1＊Ａ／ｄ1＋ε2＊Ａ／ｄ2 The capacity Cs of the auxiliary capacity 150 is expressed by the following formula.
Cs = Cs1 + Cs2 = ε 1 * A / d 1 + ε 2 * A / d 2
　ここで、Ｃｓ１は補助容量電極１４５と補助容量上部電極１４９との間に形成される容量、Ｃｓ２は補助容量電極１４５と補助容量下部電極１３９との間に形成される容量である。Ａは、補助容量電極１４５の基板面内における占有面積を表し、ε1は第１層間絶縁層１１８の誘電率、ｄ1は補助容量電極１４５と補助容量上部電極１４９との間の距離ｄ、ε2はゲート絶縁層１１６の誘電率、ｄ2は補助容量電極１４５と補助容量下部電極１３９との間の距離（ゲート絶縁層１１６の厚さ）を表している。 Here, Cs1 is a capacitance formed between the auxiliary capacitance electrode 145 and the auxiliary capacitance upper electrode 149, and Cs2 is a capacitance formed between the auxiliary capacitance electrode 145 and the auxiliary capacitance lower electrode 139. A represents the occupied area in the substrate surface of the auxiliary capacitance electrode 145, ε 1 is the dielectric constant of the first interlayer insulating layer 118, d 1 is the distance d between the auxiliary capacitance electrode 145 and the auxiliary capacitance upper electrode 149, ε 2 represents the dielectric constant of the gate insulating layer 116, and d 2 represents the distance between the auxiliary capacitance electrode 145 and the auxiliary capacitance lower electrode 139 (the thickness of the gate insulating layer 116).
　例えば、第１層間絶縁層１１８をゲート絶縁層１１６と同じ材料で形成し、補助容量電極１４５と補助容量上部電極１４９との間の距離ｄをゲート絶縁層１１６の厚さと同じにした場合、上記式より、補助容量上部電極１４９を形成しない場合に比べて、２倍の容量Ｃｓを得ることができる。あるいは同じ容量Ｃｓを得るために、補助容量電極１４５の占有面積Ａを半分にすることができる。 For example, when the first interlayer insulating layer 118 is formed of the same material as the gate insulating layer 116 and the distance d between the auxiliary capacitance electrode 145 and the auxiliary capacitance upper electrode 149 is the same as the thickness of the gate insulating layer 116, From the equation, it is possible to obtain twice the capacitance Cs compared to the case where the auxiliary capacitance upper electrode 149 is not formed. Alternatively, the area A occupied by the auxiliary capacitance electrode 145 can be halved in order to obtain the same capacitance Cs.
　また、例えば、第１層間絶縁層１１８を窒化シリコン（Ｓｉ3Ｎ4）で形成し、ゲート絶縁層１１６を酸化シリコン（ＳｉＯ2）で形成した場合、両材料の比誘電率εr1およびεr2はそれぞれ約７．０および約３．９であるので、ε1およびε2はそれぞれ約７．０＊ε0および約３．９＊ε0となる（ε0：真空の誘電率）。したがって凹部１６０の下の第１層間絶縁層１１８の厚さｄ1をゲート絶縁層１１６の厚さｄ2とほぼ等しくした場合、補助容量上部電極１４９を形成しない場合に比べて約３倍の容量Ｃｓを得ることができる。あるいは同じ容量Ｃｓを得るために、補助容量電極１４５の占有面積を約１／３にまで小さくすることができる。 For example, when the first interlayer insulating layer 118 is formed of silicon nitride (Si 3 N 4 ) and the gate insulating layer 116 is formed of silicon oxide (SiO 2 ), the relative dielectric constants ε r1 and ε r2 of both materials Are about 7.0 and about 3.9, respectively, so ε 1 and ε 2 are about 7.0 * ε 0 and about 3.9 * ε 0 , respectively (ε 0 : dielectric constant of vacuum). Therefore, when the thickness d 1 of the first interlayer insulating layer 118 under the recess 160 is substantially equal to the thickness d 2 of the gate insulating layer 116, the capacitance is about three times that when the auxiliary capacitance upper electrode 149 is not formed. Cs can be obtained. Alternatively, in order to obtain the same capacitance Cs, the area occupied by the auxiliary capacitance electrode 145 can be reduced to about ３.
　絶縁層としての機能を果たした上でより大きな容量（例えば、ゲート絶縁膜のみで構成する場合の２倍）を得るために、酸化シリコンによるゲート絶縁層１１６の厚さは１０～１００ｎｍであることが好ましく、３０～８０ｎｍであることが実用的により好ましい。最適なゲート絶縁層１１６の厚さは約５０ｎｍである。第１層間絶縁層１１８を酸化シリコンで形成した場合、絶縁層としての機能を果たした上でより大きな容量を得るためには、凹部１６０の下の第１層間絶縁層１１８の厚さｄを、例えば１０～１００ｎｍとすることが好ましく、３０～８０ｎｍとすることが実用的により好ましい。最適な厚さｄの値は約５０ｎｍである。 The thickness of the gate insulating layer 116 made of silicon oxide is 10 to 100 nm in order to obtain a larger capacity (for example, twice that of the case where only the gate insulating film is used) while functioning as an insulating layer. It is more preferable that the thickness is 30 to 80 nm. The optimum thickness of the gate insulating layer 116 is about 50 nm. When the first interlayer insulating layer 118 is formed of silicon oxide, in order to obtain a larger capacity while functioning as an insulating layer, the thickness d of the first interlayer insulating layer 118 under the recess 160 is set to For example, the thickness is preferably 10 to 100 nm, more preferably 30 to 80 nm. The optimum value of thickness d is about 50 nm.
　第１層間絶縁層１１８を窒化シリコンで形成した場合には、凹部１６０の下の第１層間絶縁層１１８の厚さｄは、例えば１０～２００ｎｍであることが好ましく、３０～１６０ｎｍとすることが実用的により好ましい。最適な厚さｄの値は約１００ｎｍである。 When the first interlayer insulating layer 118 is formed of silicon nitride, the thickness d of the first interlayer insulating layer 118 under the recess 160 is preferably 10 to 200 nm, for example, and preferably 30 to 160 nm. Practically more preferable. The optimum thickness d is about 100 nm.
　次に、アクティブマトリクス基板１００の製造方法を説明する。 Next, a method for manufacturing the active matrix substrate 100 will be described.
　図５（ａ）～（ｇ）はアクティブマトリクス基板１００の製造方法を模式的に表した断面図である。なお、図５（ａ）～（ｇ）には、アクティブマトリクス基板１００に含まれるドライバＴＦＴ部１０７の製造工程も示している。ドライバＴＦＴ部１０７は、複数の画素１１０からなる表示領域の外側の周辺領域に配置されたドライバＴＦＴの形成領域である。ドライバＴＦＴには、図２に示した走査線駆動回路５４０のＴＦＴ、信号線駆動回路５５０のＴＦＴなど、周辺領域に形成されるＴＦＴが含まれる。 FIGS. 5A to 5G are cross-sectional views schematically showing a method for manufacturing the active matrix substrate 100. 5A to 5G also show the manufacturing process of the driver TFT portion 107 included in the active matrix substrate 100. The driver TFT portion 107 is a driver TFT formation region arranged in a peripheral region outside the display region composed of a plurality of pixels 110. The driver TFT includes TFTs formed in the peripheral region such as the TFT of the scanning line driver circuit 540 and the TFT of the signal line driver circuit 550 shown in FIG.
　まず、ガラス基板等の基板１０１の上に、図示しない下地膜を成膜し、その上に結晶質シリコンまたはポリシリコンによる半導体層１１４を積層する。下地膜は、例えば窒化シリコン膜と酸化シリコン膜の多層膜である。半導体層１１４は、アモルファスシリコンを成膜した後、アモルファスシリコンを、エキシマレーザ等を照射するなど公知の技術によって結晶化またはポリシリコン化することによって得られる。 First, a base film (not shown) is formed on a substrate 101 such as a glass substrate, and a semiconductor layer 114 made of crystalline silicon or polysilicon is laminated thereon. The base film is, for example, a multilayer film of a silicon nitride film and a silicon oxide film. The semiconductor layer 114 can be obtained by depositing amorphous silicon and then crystallizing or polysiliconizing the amorphous silicon by a known technique such as irradiation with an excimer laser or the like.
　次に、フォトリソグラフィ法によって半導体層１１４をパターニングして、ＴＦＴ部１０３、Ｃｓ部１０５、およびドライバＴＦＴ部１０７に選択的に半導体層１１４を残す。その後、半導体層１１４を覆うようにゲート絶縁層１１６を成膜して、図５（ａ）に示す構造を得る。ゲート絶縁層１１６の成膜後には、上方からゲート絶縁層１１６を介して、残された半導体層１１４に低濃度のｐ型不純物１９０がイオン注入される。 Next, the semiconductor layer 114 is patterned by photolithography to selectively leave the semiconductor layer 114 in the TFT portion 103, the Cs portion 105, and the driver TFT portion 107. Thereafter, a gate insulating layer 116 is formed so as to cover the semiconductor layer 114, and the structure shown in FIG. After the gate insulating layer 116 is formed, a low-concentration p-type impurity 190 is ion-implanted into the remaining semiconductor layer 114 through the gate insulating layer 116 from above.
　次に、図５（ｂ）に示すように、ＴＦＴ部１０３の領域、およびドライバＴＦＴ部１０７におけるドライバＴＦＴのチャネル部３３０となる領域をレジスト１８５で覆い、上方からリンなどのｎ型不純物１９１をドープする。これにより、レジスト１８５で覆われない領域の半導体層１１４がＳｉ（ｎ－）半導体部となる。 Next, as shown in FIG. 5B, the region of the TFT portion 103 and the region of the driver TFT portion 107 that becomes the channel portion 330 of the driver TFT are covered with a resist 185, and an n-type impurity 191 such as phosphorus is applied from above. Dope. Thereby, the semiconductor layer 114 in a region not covered with the resist 185 becomes a Si (n−) semiconductor portion.
　続いて、レジスト１８５を除去した後、ゲート絶縁層１１６の上にスパッタ法またはＣＶＤ法などを用いて金属層を成膜する。金属層の材料には、高融点金属のＷ、Ｔａ、Ｔｉ、Ｍｏまたはその合金材料のいずれかを用いることが望ましい。 Subsequently, after removing the resist 185, a metal layer is formed on the gate insulating layer 116 by sputtering or CVD. As the material of the metal layer, it is desirable to use any of refractory metals W, Ta, Ti, Mo or alloy materials thereof.
　その後金属層をフォトリソグラフィ法によりパターニングして、図５（ｃ）に示すように、Ｃｓ部１０５の補助容量電極１４５、ＴＦＴ部１０３のゲート電極１４０、およびドライバＴＦＴ部１０７のゲート電極３４０を得る。このとき、ここには図示していない走査線１４１および補助容量線１４２も同時に形成される。その後、補助容量電極１４５、ゲート電極１４０、およびゲート電極３４０をマスクとして、半導体層１１４にリンなどのｎ型不純物１９１をドープする。これによりＴＦＴ部１０３におけるＴＦＴのチャネル部１３０が得られる。 Thereafter, the metal layer is patterned by photolithography to obtain the auxiliary capacitance electrode 145 of the Cs portion 105, the gate electrode 140 of the TFT portion 103, and the gate electrode 340 of the driver TFT portion 107 as shown in FIG. . At this time, the scanning line 141 and the auxiliary capacitance line 142 not shown here are also formed at the same time. After that, the semiconductor layer 114 is doped with an n-type impurity 191 such as phosphorus using the auxiliary capacitance electrode 145, the gate electrode 140, and the gate electrode 340 as a mask. As a result, a TFT channel portion 130 in the TFT portion 103 is obtained.
　その後、さらに選択的にｎ型不純物のドープを行って、図５（ｄ）に示すようにＴＦＴ部１０３およびドライバＴＦＴ部１０７の半導体層１１４を得る。すなわち、ＴＦＴ部１０３においては、ゲート電極１４０の下のチャネル部１３０、チャネル部１３０両端に接するＳｉ（ｎ－）部１３１および１３２、ならびにＳｉ（ｎ－）部１３１および１３２それぞれの外端に接するＳｉ（ｎ＋）部１３３および１３４が形成される。また、ドライバＴＦＴ部１０７においては、ゲート電極３４０の下のチャネル部３３０、チャネル部３３０両端に接するＳｉ（ｎ－）部３３１および３３２、ならびにＳｉ（ｎ－）部３３１および３３２それぞれの外端に接するＳｉ（ｎ＋）部３３３および３３４が形成される。また、Ｃｓ部１０５の半導体層１１４はＳｉ（ｎ－）部１３７となり、そのうちの補助容量電極１４５の下の部分が補助容量下部電極１３９となる。 Thereafter, the n-type impurity is further selectively doped to obtain the semiconductor layer 114 of the TFT portion 103 and the driver TFT portion 107 as shown in FIG. That is, in the TFT portion 103, the channel portion 130 under the gate electrode 140, the Si (n−) portions 131 and 132 in contact with both ends of the channel portion 130, and the outer ends of the Si (n−) portions 131 and 132, respectively. Si (n +) portions 133 and 134 are formed. In the driver TFT portion 107, the channel portion 330 below the gate electrode 340, the Si (n−) portions 331 and 332 in contact with both ends of the channel portion 330, and the outer ends of the Si (n−) portions 331 and 332, respectively. Si (n +) portions 333 and 334 in contact are formed. Further, the semiconductor layer 114 of the Cs portion 105 becomes the Si (n−) portion 137, and a portion below the auxiliary capacitance electrode 145 among them becomes the auxiliary capacitance lower electrode 139.
　なお別途、半導体層１１４に対して選択的にｐ型不純物をドープする工程を加えて、ＴＦＴ部１０３およびドライバＴＦＴ部１０７のＴＦＴの一方をＰ型ＴＦＴとし、他方をＮ型ＴＦＴとすることや、ドープされる不純物の濃度を変えて両ＴＦＴの閾値電圧を異ならせることも行ない得る。ＴＦＴ部１０３およびドライバＴＦＴ部１０７のＴＦＴの両方をＰ型ＴＦＴとしてもよい。また、ドライバＴＦＴ部１０７に形成される複数のＴＦＴにＮ型ＴＦＴとＰ型ＴＦＴの両方を含ませてもよい。ドライバＴＦＴ部１０７の複数のＴＦＴの全てをＮ型ＴＦＴとしてもよく、その全てをＰ型ＴＦＴとしてもよい。 Separately, a step of selectively doping the semiconductor layer 114 with a p-type impurity is added, so that one of the TFTs of the TFT portion 103 and the driver TFT portion 107 is a P-type TFT and the other is an N-type TFT. It is also possible to change the threshold voltage of both TFTs by changing the concentration of doped impurities. Both TFTs of the TFT portion 103 and the driver TFT portion 107 may be P-type TFTs. Further, both the N-type TFT and the P-type TFT may be included in the plurality of TFTs formed in the driver TFT portion 107. All of the plurality of TFTs in the driver TFT unit 107 may be N-type TFTs, and all of them may be P-type TFTs.
　その後、補助容量電極１４５、ゲート電極１４０、およびゲート電極３４０を覆うように、ゲート絶縁層１１６の上に例えば窒化シリコンを積層して、第１層間絶縁層１１８を得る。次に、第１層間絶縁層１１８の上にレジスト１８５を塗布し、補助容量電極１４５の上のレジスト１８５を除去して開口を形成し、図５（ｄ）に示す積層構造を得る。 Thereafter, for example, silicon nitride is laminated on the gate insulating layer 116 so as to cover the auxiliary capacitance electrode 145, the gate electrode 140, and the gate electrode 340, thereby obtaining the first interlayer insulating layer 118. Next, a resist 185 is applied on the first interlayer insulating layer 118, and the resist 185 on the auxiliary capacitance electrode 145 is removed to form an opening, thereby obtaining a stacked structure shown in FIG.
　続いて、レジスト１８５の開口の下の第１層間絶縁層１１８を選択的にエッチングして、補助容量電極１４５の上方に凹部１６０を形成する。その後、レジスト１８５を除去して、図５（ｅ）に示す積層構造を得る。このあと、図示を省略しているが、フォトリソグラフィ法により第１層間絶縁層１１８およびゲート絶縁層１１６を選択的に除去して、Ｓｉ（ｎ＋）部１３３、１３４、３３３、および３３４のそれぞれの上にコンタクトホールが形成される。 Subsequently, the first interlayer insulating layer 118 under the opening of the resist 185 is selectively etched to form a recess 160 above the auxiliary capacitance electrode 145. Thereafter, the resist 185 is removed to obtain a stacked structure shown in FIG. Thereafter, although not shown, the first interlayer insulating layer 118 and the gate insulating layer 116 are selectively removed by photolithography, and the Si (n +) portions 133, 134, 333, and 334 are respectively removed. A contact hole is formed on top.
　次に、第１層間絶縁層１１８の上に金属層を積層する。金属層は、例えばＴｉ／Ａｌ／Ｔｉの３層構成である。金属層を、Ａｌ／Ｔｉ、Ｃｕ／Ｔｉ、Ｃｕ／Ｍｏ（モリブデン）等の２層構成としてもよく、これらの金属の１つを用いた単層構成としてもよい。その後、金属層をフォトリソグラフィ法によってパターニングして、図５（ｆ）に示すように、補助容量上部電極１４９、金属層１４７、ソース電極１４３および３４３、ならびにドレイン電極１４４および３４４を得る。このとき、ここには図示していない信号線１４６も同時に形成される。 Next, a metal layer is stacked on the first interlayer insulating layer 118. The metal layer has, for example, a three-layer structure of Ti / Al / Ti. The metal layer may have a two-layer structure such as Al / Ti, Cu / Ti, Cu / Mo (molybdenum), or a single-layer structure using one of these metals. Thereafter, the metal layer is patterned by photolithography to obtain the auxiliary capacitor upper electrode 149, the metal layer 147, the source electrodes 143 and 343, and the drain electrodes 144 and 344, as shown in FIG. At this time, a signal line 146 not shown here is also formed at the same time.
　次に、第１層間絶縁層１１８の上に平坦化膜として機能する第２層間絶縁層１１９を積層し、ドレイン電極１４４の上の第２層間絶縁層１１９にコンタクトホールを形成する。その後、第２層間絶縁層１１９の上にＩＴＯを積層し、フォトリソグラフィ法によりパターニングして画素電極１２０を形成し、図５（ｇ）に示すアクティブマトリクス基板１００が完成する。 Next, a second interlayer insulating layer 119 functioning as a planarizing film is stacked on the first interlayer insulating layer 118, and a contact hole is formed in the second interlayer insulating layer 119 above the drain electrode 144. Thereafter, ITO is stacked on the second interlayer insulating layer 119 and patterned by photolithography to form the pixel electrode 120, whereby the active matrix substrate 100 shown in FIG. 5G is completed.
　このようにして形成されたアクティブマトリクス基板１００では、補助容量電極１４５と補助容量下部電極１３９との間の容量に加えて、補助容量電極１４５と補助容量上部電極１４９との間にも容量が形成されるので、より大きな容量の補助容量１５０を画素毎に形成することができる。また、補助容量上部電極１４９が凹部１６０の底面に形成されるため、凹部１６０以外の第１層間絶縁層１１８を十分な厚さに形成したとしても、大きな容量を得ることができる。よって、表示品質および信頼性の両方に優れたアクティブマトリクス基板を提供することができる。また、補助容量電極１４５の占有面積を小さくしても比較的大きな補助容量を得ることができるので、画素の高密度化、開口率の向上を図ることができる。さらに、補助容量上部電極１４９は、ソース電極１４３、ドレイン電極１４４等と同じ製造工程にて形成されるので、製造工程を複雑化することなく大きな補助容量を得ることができる。また、アクティブマトリクス基板１００によれば、信号線と走査線が交わる部位には、十分な厚さの第１層間絶縁層１１８が形成されるため、両線間の絶縁機能を十分に確保し、両線の信号品質を低下させることなく、大きな補助容量を確保することができる。 In the active matrix substrate 100 formed in this way, in addition to the capacitance between the auxiliary capacitance electrode 145 and the auxiliary capacitance lower electrode 139, a capacitance is also formed between the auxiliary capacitance electrode 145 and the auxiliary capacitance upper electrode 149. Therefore, the auxiliary capacitor 150 having a larger capacity can be formed for each pixel. In addition, since the auxiliary capacitor upper electrode 149 is formed on the bottom surface of the recess 160, a large capacity can be obtained even if the first interlayer insulating layer 118 other than the recess 160 is formed to a sufficient thickness. Therefore, an active matrix substrate excellent in both display quality and reliability can be provided. In addition, since a relatively large auxiliary capacitance can be obtained even if the area occupied by the auxiliary capacitance electrode 145 is reduced, it is possible to increase the density of the pixels and improve the aperture ratio. Furthermore, since the auxiliary capacitor upper electrode 149 is formed in the same manufacturing process as the source electrode 143, the drain electrode 144, etc., a large auxiliary capacity can be obtained without complicating the manufacturing process. Further, according to the active matrix substrate 100, since the first interlayer insulating layer 118 having a sufficient thickness is formed at a portion where the signal line and the scanning line intersect, a sufficient insulating function between the two lines is ensured, A large auxiliary capacity can be ensured without degrading the signal quality of both lines.
　次に、本発明による他の実施形態（実施形態２～５）を説明する。以下の説明においては、実施形態１と同じ構成要素には同じ参照番号を付け、その詳細な説明を省略する。実施形態２～５において説明する部分以外は、基本的に実施形態１と同じであり、同じ構成要素からは同様の効果を得ることができる。 Next, other embodiments (embodiments 2 to 5) according to the present invention will be described. In the following description, the same reference numerals are assigned to the same components as those in the first embodiment, and detailed descriptions thereof are omitted. The parts other than those described in the second to fifth embodiments are basically the same as those in the first embodiment, and the same effects can be obtained from the same components.
　（実施形態２）
　図６は、実施形態２によるアクティブマトリクス基板１００の構成を模式的に示す断面図である。図６に示すように、実施形態２によるアクティブマトリクス基板１００は、基板１０１の上に順次積層された半導体層１１４、ゲート絶縁層１１６、追加絶縁層１１７、第１層間絶縁層１１８、第２層間絶縁層１１９、および画素電極１２０を備えている。 (Embodiment 2)
FIG. 6 is a cross-sectional view schematically showing the configuration of the active matrix substrate 100 according to the second embodiment. As shown in FIG. 6, the active matrix substrate 100 according to the second embodiment includes a semiconductor layer 114, a gate insulating layer 116, an additional insulating layer 117, a first interlayer insulating layer 118, and a second interlayer sequentially stacked on the substrate 101. An insulating layer 119 and a pixel electrode 120 are provided.
　追加絶縁層１１７は、補助容量電極１４５およびゲート電極１４０を覆うようにゲート絶縁層１１６の上に形成されている。実施形態１と同様、補助容量電極１４５の上方の第１層間絶縁層１１８には凹部１６０が形成されている。ただし、実施形態２においては、補助容量電極１４５と補助容量上部電極１４９との間は追加絶縁層１１７で埋められている。つまり、補助容量電極１４５の上面は追加絶縁層１１７の下面と接し、補助容量上部電極１４９の下面は追加絶縁層１１７の上面と接している。補助容量電極１４５の上面と補助容量上部電極１４９の下面（凹部１６０の底面）との間の距離ｄは、両電極間の追加絶縁層１１７の厚さに相当する。 The additional insulating layer 117 is formed on the gate insulating layer 116 so as to cover the auxiliary capacitance electrode 145 and the gate electrode 140. As in the first embodiment, a recess 160 is formed in the first interlayer insulating layer 118 above the auxiliary capacitance electrode 145. However, in the second embodiment, the space between the auxiliary capacitance electrode 145 and the auxiliary capacitance upper electrode 149 is filled with the additional insulating layer 117. That is, the upper surface of the auxiliary capacitance electrode 145 is in contact with the lower surface of the additional insulating layer 117, and the lower surface of the auxiliary capacitance upper electrode 149 is in contact with the upper surface of the additional insulating layer 117. A distance d between the upper surface of the auxiliary capacitance electrode 145 and the lower surface of the auxiliary capacitance upper electrode 149 (the bottom surface of the recess 160) corresponds to the thickness of the additional insulating layer 117 between the two electrodes.
　追加絶縁層１１７は、例えば窒化シリコンからなり、第１層間絶縁層１１８は、例えば酸化シリコンからなる。第１層間絶縁層１１８をエッチングして凹部１６０を形成する場合、追加絶縁層１１７はエッチングストッパの役割を果たす。 The additional insulating layer 117 is made of, for example, silicon nitride, and the first interlayer insulating layer 118 is made of, for example, silicon oxide. When the recess 160 is formed by etching the first interlayer insulating layer 118, the additional insulating layer 117 serves as an etching stopper.
　補助容量電極１４５の上面から補助容量上部電極１４９の下面までの距離ｄ（あるいは追加絶縁層１１７の厚さ）は、１０ｎｍ以上２００ｎｍ以下である。距離ｄは６０～１６０ｎｍであることがより好ましく、その最適な値は約１００ｎｍである。 The distance d (or the thickness of the additional insulating layer 117) from the upper surface of the auxiliary capacitance electrode 145 to the lower surface of the auxiliary capacitance upper electrode 149 is 10 nm or more and 200 nm or less. The distance d is more preferably 60 to 160 nm, and the optimum value is about 100 nm.
　次に、アクティブマトリクス基板１００の製造方法を説明する。 Next, a method for manufacturing the active matrix substrate 100 will be described.
　図７（ａ）～（ｄ）は、実施形態２によるアクティブマトリクス基板１００の製造方法を模式的に表した断面図である。図７（ａ）～（ｄ）には、アクティブマトリクス基板１００に含まれるドライバＴＦＴ部１０７の製造工程も示している。 7A to 7D are cross-sectional views schematically showing a method for manufacturing the active matrix substrate 100 according to the second embodiment. 7A to 7D also show a manufacturing process of the driver TFT portion 107 included in the active matrix substrate 100. FIG.
　まず、図５（ａ）～（ｃ）に示した実施形態１の製造工程と同様の工程を経て、図７（ａ）に示す積層構造を得る。その後、半導体層１１４にｎ型不純物をドープして、Ｓｉ（ｎ＋）部１３３、１３４、３３３、および３３４を含む、図７（ｂ）に示す構成の半導体層１１４を得る。 First, the laminated structure shown in FIG. 7A is obtained through steps similar to the manufacturing steps of the first embodiment shown in FIGS. 5A to 5C. Thereafter, the semiconductor layer 114 is doped with an n-type impurity to obtain the semiconductor layer 114 having the structure shown in FIG. 7B including the Si (n +) portions 133, 134, 333, and 334.
　次に、補助容量電極１４５、ゲート電極１４０、およびゲート電極３４０を覆うように、ゲート絶縁層１１６の上に例えば窒化シリコンを積層して追加絶縁層１１７とし、その上に酸化シリコンを積層して第１層間絶縁層１１８を得る。その後、第１層間絶縁層１１８の上にレジスト１８５を塗布し、補助容量電極１４５の上のレジスト１８５を除去して開口を形成し、図７（ｂ）に示す積層構造を得る。 Next, for example, silicon nitride is stacked on the gate insulating layer 116 so as to cover the auxiliary capacitance electrode 145, the gate electrode 140, and the gate electrode 340 to form an additional insulating layer 117, and silicon oxide is stacked thereon. A first interlayer insulating layer 118 is obtained. Thereafter, a resist 185 is applied on the first interlayer insulating layer 118, and the resist 185 on the auxiliary capacitance electrode 145 is removed to form an opening, thereby obtaining a stacked structure shown in FIG. 7B.
　続いて、レジスト１８５の開口の下の第１層間絶縁層１１８をエッチングして、補助容量電極１４５の上方に凹部１６０を形成する。このとき、窒化シリコンに対して酸化シリコンよりも低いエッチングレートを示すエッチャントを用いることにより、窒化シリコンをエッチングストッパとして機能させることができる。その後、レジスト１８５を除去して、図７（ｃ）に示す積層構造を得る。このあと、図示を省略しているが、フォトリソグラフィ法により第１層間絶縁層１１８、追加絶縁層１１７、およびゲート絶縁層１１６を選択的に除去して、Ｓｉ（ｎ＋）部１３３、１３４、３３３、および３３４のそれぞれの上にコンタクトホールが形成される。 Subsequently, the first interlayer insulating layer 118 under the opening of the resist 185 is etched to form a recess 160 above the auxiliary capacitance electrode 145. At this time, silicon nitride can function as an etching stopper by using an etchant that exhibits an etching rate lower than that of silicon oxide. Thereafter, the resist 185 is removed to obtain a laminated structure shown in FIG. Thereafter, although not shown, the first interlayer insulating layer 118, the additional insulating layer 117, and the gate insulating layer 116 are selectively removed by photolithography, and Si (n +) portions 133, 134, 333 are removed. , And 334 are formed on each of the contact holes.
　次に、第１層間絶縁層１１８の上に金属層を積層し、フォトリソグラフィ法によってパターニングして、図７（ｄ）に示すように、補助容量上部電極１４９、金属層１４７、ソース電極１４３および３４３、ならびにドレイン電極１４４および３４４を得る。このとき、ここには図示していない信号線１４６も同時に形成される。 Next, a metal layer is stacked on the first interlayer insulating layer 118 and patterned by photolithography, and as shown in FIG. 7D, the auxiliary capacitor upper electrode 149, the metal layer 147, the source electrode 143, and 343 and drain electrodes 144 and 344 are obtained. At this time, a signal line 146 not shown here is also formed at the same time.
　その後、第１層間絶縁層１１８の上に第２層間絶縁層１１９を積層し、ドレイン電極１４４の上の第２層間絶縁層１１９にコンタクトホールを形成する。その後、第２層間絶縁層１１９の上にＩＴＯを積層し、フォトリソグラフィ法によりパターニングして画素電極１２０を形成して、図７（ｄ）に示すアクティブマトリクス基板１００が完成する。 Thereafter, a second interlayer insulating layer 119 is stacked on the first interlayer insulating layer 118, and a contact hole is formed in the second interlayer insulating layer 119 on the drain electrode 144. Thereafter, ITO is laminated on the second interlayer insulating layer 119 and patterned by photolithography to form the pixel electrode 120, thereby completing the active matrix substrate 100 shown in FIG. 7D.
　この製造方法によれば、追加絶縁層１１７が凹部１６０を形成する際のエッチングストッパの役割を果たすので、エッチング時間を厳密に管理することなく、複数の画素に対して均一な深さの凹部１６０を形成することができる。これにより、複数の画素間における輝度のばらつきが抑えられた、高品質の表示を提供することが可能となる。 According to this manufacturing method, since the additional insulating layer 117 serves as an etching stopper when forming the recess 160, the recess 160 having a uniform depth for a plurality of pixels without strictly controlling the etching time. Can be formed. Thereby, it is possible to provide a high-quality display in which variation in luminance among a plurality of pixels is suppressed.
　（実施形態３）
　図８（ａ）～（ｆ）は、実施形態３によるアクティブマトリクス基板１００の製造方法を模式的に示す断面図である。実施形態３によるアクティブマトリクス基板１００の断面構成は実施形態２のものと基本的に同じであるので、ここでは図示を省略し、製造方法のみを説明する。 (Embodiment 3)
8A to 8F are cross-sectional views schematically showing a method for manufacturing the active matrix substrate 100 according to the third embodiment. Since the cross-sectional configuration of the active matrix substrate 100 according to the third embodiment is basically the same as that of the second embodiment, the illustration is omitted here, and only the manufacturing method will be described.
　まず、図５（ａ）～（ｃ）に示した実施形態１の製造工程と同様の工程を経て、図８（ａ）に示す積層構造を得る。その後、半導体層１１４にｎ型不純物をドープして、Ｓｉ（ｎ＋）部１３３、１３４、３３３、および３３４を含む半導体層１１４を得る。 First, the laminated structure shown in FIG. 8A is obtained through the same process as the manufacturing process of the first embodiment shown in FIGS. 5A to 5C. Thereafter, the semiconductor layer 114 is doped with n-type impurities to obtain the semiconductor layer 114 including Si (n +) portions 133, 134, 333, and 334.
　次に、補助容量電極１４５、ゲート電極１４０、およびゲート電極３４０を覆うように、ゲート絶縁層１１６の上に例えば窒化シリコンを積層して追加絶縁層１１７とし、その上に酸化シリコンを積層して第１層間絶縁層１１８を得る。その後、第１層間絶縁層１１８の上にレジスト１８５を塗布する。 Next, for example, silicon nitride is stacked on the gate insulating layer 116 so as to cover the auxiliary capacitance electrode 145, the gate electrode 140, and the gate electrode 340 to form an additional insulating layer 117, and silicon oxide is stacked thereon. A first interlayer insulating layer 118 is obtained. Thereafter, a resist 185 is applied on the first interlayer insulating layer 118.
　次に、図８（ｂ）に示すように、レジスト１８５の上方にマスク１８７を配置する。マスク１８７はグレートーンマスクであり、ハーフトーン露光を行なうために、低い光透過率を示す第１窓（半透過部）１８８と、第１窓１８８よりも高い光透過率を示す第２窓（全透過部）１８９を含む。マスク１８７の第１窓１８８および第２窓１８９以外の部分は、実質的に光を透過させない遮光部である。第１窓１８８は補助容量電極１４５の上方に配置され、第２窓１８９はＳｉ（ｎ＋）部１３３、１３４、３３３、および３３４それぞれの上方に配置される。 Next, as shown in FIG. 8B, a mask 187 is disposed above the resist 185. The mask 187 is a gray-tone mask, and in order to perform halftone exposure, a first window (semi-transmissive portion) 188 that exhibits a low light transmittance and a second window (a light transmittance that is higher than the first window 188). Total transmission part) 189. Portions other than the first window 188 and the second window 189 of the mask 187 are light shielding portions that do not substantially transmit light. The first window 188 is disposed above the auxiliary capacitance electrode 145, and the second window 189 is disposed above each of the Si (n +) portions 133, 134, 333, and 334.
　次に、マスク１８７の上方から光が照射され、第１窓１８８を透過した光によって補助容量電極１４５の上方のレジスト１８５が露光され、第２窓１８９を透過した光によってＳｉ（ｎ＋）部１３３、１３４、３３３、および３３４の上方のレジスト１８５が露光される。その後、露光された部分のレジスト１８５が除去され、図８（ｃ）に示すように、補助容量電極１４５の上方のレジスト１８５に凹部（窪み）１８４が形成されるとともに、Ｓｉ（ｎ＋）部１３３、１３４、３３３、および３３４の上方のレジスト１８５に開口１８６が形成される。 Next, light is irradiated from above the mask 187, the resist 185 above the auxiliary capacitance electrode 145 is exposed by the light transmitted through the first window 188, and the Si (n +) portion 133 is exposed by the light transmitted through the second window 189. , 134, 333, and 334 are exposed. Thereafter, the exposed portion of the resist 185 is removed, and as shown in FIG. 8C, a recess (depression) 184 is formed in the resist 185 above the auxiliary capacitance electrode 145, and an Si (n +) portion 133 is formed. , 134, 333, and 334, openings 186 are formed in the resist 185.
　次に、レジスト１８５を介して第１層間絶縁層１１８を選択的にエッチングし、図８（ｄ）に示すように、開口１８６の下に第１層間絶縁層１１８の窪みが形成される。このとき、開口１８６の下以外の第１層間絶縁層１１８はエッチングされることなく残される。 Next, the first interlayer insulating layer 118 is selectively etched through the resist 185 to form a recess in the first interlayer insulating layer 118 under the opening 186 as shown in FIG. At this time, the first interlayer insulating layer 118 other than under the opening 186 is left without being etched.
　次に、レジスト１８５を酸素プラズマ等でアッシングすることにより、レジスト１８５全体を薄くして、凹部１８４の底に第１層間絶縁層１１８を露出させる。このとき、凹部１８４および開口１８６以外の部分のレジスト１８５は残され、その下の第１層間絶縁層１１８は露出しない。その後、再度エッチングを行い、図８（ｅ）に示すように、補助容量電極１４５の上方に第１層間絶縁層１１８の凹部１６０が形成されるとともに、Ｓｉ（ｎ＋）部１３３、１３４、３３３、および３３４に通じるコンタクトホールが形成される。 Next, the entire resist 185 is thinned by ashing the resist 185 with oxygen plasma or the like, and the first interlayer insulating layer 118 is exposed at the bottom of the recess 184. At this time, a portion of the resist 185 other than the recess 184 and the opening 186 is left, and the first interlayer insulating layer 118 therebelow is not exposed. Thereafter, etching is performed again, and as shown in FIG. 8E, a recess 160 of the first interlayer insulating layer 118 is formed above the auxiliary capacitance electrode 145, and Si (n +) portions 133, 134, 333, And a contact hole leading to 334 is formed.
　ここでも、実施形態２と同様、追加絶縁層１１７はエッチングストッパとして用いられるため、凹部１６０の底部には追加絶縁層１１７が露出する。コンタクトホールは第１層間絶縁層１１８、追加絶縁層１１７、およびゲート絶縁層１１６を貫通して形成される。その後、レジスト１８５は除去される。 Here, as in the second embodiment, since the additional insulating layer 117 is used as an etching stopper, the additional insulating layer 117 is exposed at the bottom of the recess 160. The contact hole is formed through the first interlayer insulating layer 118, the additional insulating layer 117, and the gate insulating layer 116. Thereafter, the resist 185 is removed.
　次に、実施形態２と同様、第１層間絶縁層１１８の上に金属層を積層し、フォトリソグラフィ法によってパターニングして、補助容量上部電極１４９、金属層１４７、ソース電極１４３および３４３、ならびにドレイン電極１４４および３４４を得る。その後、第１層間絶縁層１１８の上に第２層間絶縁層１１９を積層し、ドレイン電極１４４の上の第２層間絶縁層１１９にコンタクトホールを形成する。次に、第２層間絶縁層１１９の上にＩＴＯを積層し、フォトリソグラフィ法によりパターニングして画素電極１２０を形成し、図８（ｆ）に示すアクティブマトリクス基板１００が完成する。 Next, as in the second embodiment, a metal layer is stacked on the first interlayer insulating layer 118 and patterned by a photolithography method to form an auxiliary capacitor upper electrode 149, a metal layer 147, source electrodes 143 and 343, and a drain. Electrodes 144 and 344 are obtained. Thereafter, a second interlayer insulating layer 119 is stacked on the first interlayer insulating layer 118, and a contact hole is formed in the second interlayer insulating layer 119 on the drain electrode 144. Next, ITO is laminated on the second interlayer insulating layer 119 and patterned by photolithography to form the pixel electrode 120, whereby the active matrix substrate 100 shown in FIG. 8F is completed.
　この製造方法によれば、追加絶縁層１１７が凹部１６０を形成する際のエッチングストッパの役割を果たすので、エッチング時間を厳密に管理することなく、複数の画素に対して均一な深さの凹部１６０を形成することができる。これにより、複数の画素間における輝度のばらつきが抑えられた、高品質の表示を提供することが可能となる。また、ハーフトーン露光を利用することにより、１枚のレジストで第１層間絶縁層１１８に凹部１６０およびコンタクトホールを形成することができるので、製造効率の向上および製造コストの低減が可能となる。なお、ここで用いたハーフトーン露光は、実施形態１の製造方法に適用することも可能である。 According to this manufacturing method, since the additional insulating layer 117 serves as an etching stopper when forming the recess 160, the recess 160 having a uniform depth for a plurality of pixels without strictly controlling the etching time. Can be formed. Thereby, it is possible to provide a high-quality display in which variation in luminance among a plurality of pixels is suppressed. Further, by using halftone exposure, the recess 160 and the contact hole can be formed in the first interlayer insulating layer 118 with one resist, so that the manufacturing efficiency can be improved and the manufacturing cost can be reduced. The halftone exposure used here can be applied to the manufacturing method of the first embodiment.
　（実施形態４）
　図９は、実施形態４によるアクティブマトリクス基板１００の構成を模式的に示す断面図であり、図１０はアクティブマトリクス基板１００における画素の構成を表す回路図である。 (Embodiment 4)
FIG. 9 is a cross-sectional view schematically showing the configuration of the active matrix substrate 100 according to Embodiment 4, and FIG. 10 is a circuit diagram showing the configuration of the pixels in the active matrix substrate 100.
　実施形態４によるアクティブマトリクス基板１００は、基板１０１の上に順次積層された半導体層１１４、ゲート絶縁層１１６、追加絶縁層１１７、第１層間絶縁層１１８、第２層間絶縁層１１９、および画素電極１２０を備えている。 The active matrix substrate 100 according to the fourth embodiment includes a semiconductor layer 114, a gate insulating layer 116, an additional insulating layer 117, a first interlayer insulating layer 118, a second interlayer insulating layer 119, and a pixel electrode, which are sequentially stacked on the substrate 101. 120.
　追加絶縁層１１７は、補助容量電極１４５およびゲート電極１４０を覆うようにゲート絶縁層１１６の上に形成されている。実施形態２と同様、補助容量電極１４５の上方には第１層間絶縁層１１８の凹部１６０が形成されており、凹部１６０の底部には追加絶縁層１１７が露出している。実施形態４においては、Ｃｓ部１０５には半導体層１１４は含まれず、補助容量下部電極は形成されない。よって、補助容量１５０は補助容量電極１４５と補助容量上部電極１４９と、両電極の間の追加絶縁層１１７によって構成される。それ以外の構成は、実施形態２と基本的に同じである。 The additional insulating layer 117 is formed on the gate insulating layer 116 so as to cover the auxiliary capacitance electrode 145 and the gate electrode 140. Similar to the second embodiment, the concave portion 160 of the first interlayer insulating layer 118 is formed above the auxiliary capacitance electrode 145, and the additional insulating layer 117 is exposed at the bottom of the concave portion 160. In the fourth embodiment, the Cs portion 105 does not include the semiconductor layer 114, and no auxiliary capacitance lower electrode is formed. Therefore, the auxiliary capacitor 150 includes the auxiliary capacitor electrode 145, the auxiliary capacitor upper electrode 149, and the additional insulating layer 117 between the two electrodes. Other configurations are basically the same as those of the second embodiment.
　このような補助容量１５０の構成であっても、凹部１６０を形成することにより、補助容量電極１４５と補助容量上部電極１４９との距離を短くすることができるので、比較的大きな補助容量を得ることができる。また、追加絶縁層１１７に高誘電率の部材を用いることにより、より大きな補助容量を得ることができる。なお実施形態１のように、追加絶縁層１１７を形成せずに凹部１６０を形成する構成も実施形態４に含まれるものとする。 Even in such a configuration of the auxiliary capacitor 150, by forming the recess 160, the distance between the auxiliary capacitor electrode 145 and the auxiliary capacitor upper electrode 149 can be shortened, so that a relatively large auxiliary capacitor can be obtained. Can do. Further, by using a member having a high dielectric constant for the additional insulating layer 117, a larger auxiliary capacitance can be obtained. A configuration in which the concave portion 160 is formed without forming the additional insulating layer 117 as in the first embodiment is also included in the fourth embodiment.
　次に、実施形態４によるアクティブマトリクス基板１００の製造方法を説明する。 Next, a method for manufacturing the active matrix substrate 100 according to Embodiment 4 will be described.
　図１１（ａ）～（ｆ）は、実施形態４によるアクティブマトリクス基板１００の製造方法を模式的に表した断面図である。 FIGS. 11A to 11F are cross-sectional views schematically showing a method for manufacturing the active matrix substrate 100 according to the fourth embodiment.
　まず、基板１０１の上に、実施形態１と同様、図示しない下地膜を成膜し、その上に結晶質シリコンまたはポリシリコンによる半導体層１１４を積層する。次に、フォトリソグラフィ法によって半導体層１１４をパターニングして、ＴＦＴ部１０３およびドライバＴＦＴ部１０７に選択的に半導体層１１４を残す。このとき、Ｃｓ部１０５には半導体層１１４は残されない。 First, as in the first embodiment, a base film (not shown) is formed on the substrate 101, and a semiconductor layer 114 made of crystalline silicon or polysilicon is stacked thereon. Next, the semiconductor layer 114 is patterned by photolithography, and the semiconductor layer 114 is selectively left in the TFT portion 103 and the driver TFT portion 107. At this time, the semiconductor layer 114 is not left in the Cs portion 105.
　その後、半導体層１１４を覆うようにゲート絶縁層１１６を成膜して、図１１（ａ）に示すように、残された半導体層１１４にｐ型不純物１９０がイオン注入される。 Thereafter, a gate insulating layer 116 is formed so as to cover the semiconductor layer 114, and p-type impurities 190 are ion-implanted into the remaining semiconductor layer 114 as shown in FIG.
　次に、図１１（ｂ）に示すように、ＴＦＴ部１０３の領域、およびドライバＴＦＴ部１０７におけるドライバＴＦＴのチャネル部３３０となる領域の上方にレジスト１８５を形成し、上方からｎ型不純物１９１をドープする。これにより、ドライバＴＦＴ部１０７におけるレジスト１８５で覆われない領域の半導体層１１４がＳｉ（ｎ－）半導体部となる。 Next, as shown in FIG. 11B, a resist 185 is formed above the region of the TFT portion 103 and the region of the driver TFT portion 107 that becomes the channel portion 330 of the driver TFT, and the n-type impurity 191 is applied from above. Dope. Thereby, the semiconductor layer 114 in the region not covered with the resist 185 in the driver TFT portion 107 becomes the Si (n−) semiconductor portion.
　続いて、レジスト１８５を除去した後、実施形態１と同様、ゲート絶縁層１１６の上に金属層を成膜し、フォトリソグラフィ法によりパターニングして、図１１（ｃ）に示すように、Ｃｓ部１０５の補助容量電極１４５、ＴＦＴ部１０３のゲート電極１４０、およびドライバＴＦＴ部１０７のゲート電極３４０を得る。その後、補助容量電極１４５、ゲート電極１４０、およびゲート電極３４０をマスクとして、半導体層１１４にｎ型不純物をドープする。これによりＴＦＴ部１０３におけるＴＦＴのチャネル部１３０が得られる。 Subsequently, after removing the resist 185, as in the first embodiment, a metal layer is formed on the gate insulating layer 116, and is patterned by photolithography. As shown in FIG. The auxiliary capacitance electrode 145 of 105, the gate electrode 140 of the TFT portion 103, and the gate electrode 340 of the driver TFT portion 107 are obtained. Thereafter, the semiconductor layer 114 is doped with an n-type impurity using the auxiliary capacitance electrode 145, the gate electrode 140, and the gate electrode 340 as a mask. As a result, a TFT channel portion 130 in the TFT portion 103 is obtained.
　その後、実施形態２と同様、補助容量電極１４５、ゲート電極１４０、およびゲート電極３４０を覆うように追加絶縁層１１７を積層し、その上に第１層間絶縁層１１８を積層する。次に、第１層間絶縁層１１８の上にレジスト１８５を塗布し、補助容量電極１４５の上のレジスト１８５を除去して開口を形成し、図１１（ｄ）に示す積層構造を得る。 Thereafter, as in the second embodiment, an additional insulating layer 117 is stacked so as to cover the auxiliary capacitance electrode 145, the gate electrode 140, and the gate electrode 340, and the first interlayer insulating layer 118 is stacked thereon. Next, a resist 185 is applied on the first interlayer insulating layer 118, and the resist 185 on the auxiliary capacitance electrode 145 is removed to form an opening, thereby obtaining a stacked structure shown in FIG.
　続いて、レジスト１８５の開口の下の第１層間絶縁層１１８をエッチングして、図１１（ｅ）に示すように、補助容量電極１４５の上方に凹部１６０を形成する。このとき、実施形態２と同様、追加絶縁層１１７はエッチングストッパとして機能する。 Subsequently, the first interlayer insulating layer 118 under the opening of the resist 185 is etched to form a recess 160 above the auxiliary capacitance electrode 145 as shown in FIG. At this time, as in the second embodiment, the additional insulating layer 117 functions as an etching stopper.
　次に、レジスト１８５を除去した後、実施形態２と同様に、補助容量上部電極１４９、金属層１４７、ソース電極１４３および３４３、ならびにドレイン電極１４４および３４４を形成し、その上に第２層間絶縁層１１９、画素電極１２０を順次形成して、図１１（ｆ）に示すアクティブマトリクス基板１００が完成する。 Next, after removing the resist 185, the storage capacitor upper electrode 149, the metal layer 147, the source electrodes 143 and 343, and the drain electrodes 144 and 344 are formed as in the second embodiment, and the second interlayer insulation is formed thereon. The layer 119 and the pixel electrode 120 are sequentially formed to complete the active matrix substrate 100 shown in FIG.
　（実施形態５）
　図１２（ａ）～（ｄ）および図１３（ｅ）～（ｇ）は、実施形態５によるアクティブマトリクス基板１００の製造方法を模式的に示す断面図である。実施形態５によるアクティブマトリクス基板１００の断面構成は実施形態４のものと基本的に同じであるので、ここでは図示を省略し、製造方法のみを説明する。 (Embodiment 5)
12 (a) to 12 (d) and FIGS. 13 (e) to (g) are cross-sectional views schematically showing a method for manufacturing the active matrix substrate 100 according to the fifth embodiment. Since the cross-sectional configuration of the active matrix substrate 100 according to the fifth embodiment is basically the same as that of the fourth embodiment, the illustration is omitted here, and only the manufacturing method will be described.
　まず、基板１０１の上に、実施形態４と同様の方法によって半導体層１１４を積層し、フォトリソグラフィ法によってパターニングして、ＴＦＴ部１０３およびドライバＴＦＴ部１０７の半導体層１１４を残す。このとき、Ｃｓ部１０５には半導体層１１４は残されない。次に、半導体層１１４を覆うようにゲート絶縁層１１６を成膜した後、図１２（ａ）に示すように、残された半導体層１１４に低濃度のｐ型不純物１９０がイオン注入される。 First, the semiconductor layer 114 is stacked on the substrate 101 by the same method as in the fourth embodiment, and is patterned by photolithography to leave the semiconductor layer 114 of the TFT portion 103 and the driver TFT portion 107. At this time, the semiconductor layer 114 is not left in the Cs portion 105. Next, after forming a gate insulating layer 116 so as to cover the semiconductor layer 114, a low-concentration p-type impurity 190 is ion-implanted into the remaining semiconductor layer 114 as shown in FIG.
　次に、ゲート絶縁層１１６の上に金属層を成膜し、フォトリソグラフィ法によりパターニングして、図１２（ｂ）に示すように、Ｃｓ部１０５の補助容量電極１４５、ＴＦＴ部１０３のゲート電極１４０、およびドライバＴＦＴ部１０７のゲート電極３４０を得る。ただしこのとき、補助容量電極１４５、ゲート電極１４０、およびゲート電極３４０は、その幅が最終的な幅よりも広くなるように形成される。その後、補助容量電極１４５、ゲート電極１４０、およびゲート電極３４０の上に残されたレジスト１８５を除去することなく、上方から半導体層１１４にリンなどのｎ型不純物１９１をドープする。これにより、レジスト１８５で覆われない領域の半導体層１１４がＳｉ（ｎ＋）半導体部となる。 Next, a metal layer is formed on the gate insulating layer 116 and patterned by photolithography, and as shown in FIG. 12B, the auxiliary capacitance electrode 145 of the Cs portion 105 and the gate electrode of the TFT portion 103 are formed. 140 and the gate electrode 340 of the driver TFT portion 107 are obtained. However, at this time, the auxiliary capacitor electrode 145, the gate electrode 140, and the gate electrode 340 are formed so that the width thereof is wider than the final width. Thereafter, the semiconductor layer 114 is doped with an n-type impurity 191 such as phosphorus from above without removing the resist 185 left on the storage capacitor electrode 145, the gate electrode 140, and the gate electrode 340. Thereby, the semiconductor layer 114 in a region not covered with the resist 185 becomes a Si (n +) semiconductor portion.
　次に、補助容量電極１４５、ゲート電極１４０、およびゲート電極３４０を、例えばウェットエッチングによってサイドエッチングして、これらの電極の幅を減少させる。レジスト１８５が残されていることから、サイドエッチングによって、これらの電極は上部から削られることはなく、側面からのみ削られ、図１２（ｃ）に示すように、幅が減少する。 Next, the auxiliary capacitor electrode 145, the gate electrode 140, and the gate electrode 340 are side-etched by, for example, wet etching to reduce the width of these electrodes. Since the resist 185 is left, these electrodes are not etched from the top by side etching, but only from the side surface, and the width is reduced as shown in FIG.
　次に、図１２（ｄ）に示すように、レジスト１８５を除去し、補助容量電極１４５、ゲート電極１４０、およびゲート電極３４０をマスクとして、半導体層１１４にｎ型不純物１９１をドープする。これにより、ＴＦＴ部１０３におけるチャネル部１３０、Ｓｉ（ｎ－）部１３１および１３２、Ｓｉ（ｎ＋）部１３３および１３４、ならびにドライバＴＦＴ部１０７におけるチャネル部３３０、Ｓｉ（ｎ－）部３３１および３３２、Ｓｉ（ｎ＋）部３３３および３３４が完成する。 Next, as shown in FIG. 12D, the resist 185 is removed, and the semiconductor layer 114 is doped with an n-type impurity 191 using the auxiliary capacitance electrode 145, the gate electrode 140, and the gate electrode 340 as a mask. Accordingly, the channel portion 130, Si (n−) portions 131 and 132, Si (n +) portions 133 and 134 in the TFT portion 103, and the channel portion 330, Si (n−) portions 331 and 332 in the driver TFT portion 107, Si (n +) portions 333 and 334 are completed.
　次に、実施形態３において図８（ｂ）および（ｃ）を用いて説明したものと同様の方法により、ハーフトーン露光およびエッチングを行なって、図１３（ｅ）に示すように、補助容量電極１４５の上方のレジスト１８５に凹部１８４が形成されるとともに、Ｓｉ（ｎ＋）部１３３、１３４、３３３、および３３４の上方のレジスト１８５に開口１８６が形成される。開口１８６の下方の第１層間絶縁層には窪みが形成されるが、凹部１８４の下の第１層間絶縁層１１８はエッチングされることなく残される。 Next, halftone exposure and etching are performed by the same method as described with reference to FIGS. 8B and 8C in the third embodiment, and as shown in FIG. A recess 184 is formed in the resist 185 above 145, and an opening 186 is formed in the resist 185 above the Si (n +) portions 133, 134, 333, and 334. Although a depression is formed in the first interlayer insulating layer below the opening 186, the first interlayer insulating layer 118 under the recess 184 is left without being etched.
　次に、図８（ｄ）を用いて説明したものと同様の方法によりレジスト１８５をアッシングした後、再度エッチングを行って、図１３（ｆ）に示すように、補助容量電極１４５の上方に第１層間絶縁層１１８の凹部１６０を形成するとともに、Ｓｉ（ｎ＋）部１３３、１３４、３３３、および３３４に通じるコンタクトホールが形成される。このとき、追加絶縁層１１７はエッチングストッパとして用いられる。 Next, after ashing the resist 185 by the same method as that described with reference to FIG. 8D, etching is performed again, and as shown in FIG. A recess 160 is formed in one interlayer insulating layer 118, and contact holes that lead to Si (n +) portions 133, 134, 333, and 334 are formed. At this time, the additional insulating layer 117 is used as an etching stopper.
　次に、第１層間絶縁層１１８の上に金属層を積層し、フォトリソグラフィ法によってパターニングして、補助容量上部電極１４９、金属層１４７、ソース電極１４３および３４３、ならびにドレイン電極１４４および３４４を得る。その後、第１層間絶縁層１１８の上に第２層間絶縁層１１９を積層し、ドレイン電極１４４の上の第２層間絶縁層１１９にコンタクトホールを形成する。次に、第２層間絶縁層１１９の上にＩＴＯを積層し、フォトリソグラフィ法によりパターニングして画素電極１２０を形成し、図１３（ｇ）に示すアクティブマトリクス基板１００が完成する。 Next, a metal layer is stacked on the first interlayer insulating layer 118 and patterned by photolithography to obtain the auxiliary capacitor upper electrode 149, the metal layer 147, the source electrodes 143 and 343, and the drain electrodes 144 and 344. . Thereafter, a second interlayer insulating layer 119 is stacked on the first interlayer insulating layer 118, and a contact hole is formed in the second interlayer insulating layer 119 on the drain electrode 144. Next, ITO is laminated on the second interlayer insulating layer 119 and patterned by photolithography to form the pixel electrode 120, whereby the active matrix substrate 100 shown in FIG. 13G is completed.
　実施形態５の製造方法によれば、追加絶縁層１１７が凹部１６０を形成する際のエッチングストッパの役割を果たすので、エッチング時間を厳密に管理することなく、複数の画素に対して均一な深さの凹部１６０を形成することができる。これにより、複数の画素間における輝度のばらつきが抑えられた、高品質の表示を提供することが可能となる。また、ハーフトーン露光を利用することにより、１枚のレジストで第１層間絶縁層１１８に凹部１６０およびコンタクトホールを形成することができるので、製造効率の向上および製造コストの低減が可能となる。 According to the manufacturing method of the fifth embodiment, since the additional insulating layer 117 serves as an etching stopper when forming the recess 160, a uniform depth is provided to a plurality of pixels without strictly controlling the etching time. The concave portion 160 can be formed. Thereby, it is possible to provide a high-quality display in which variation in luminance among a plurality of pixels is suppressed. Further, by using halftone exposure, the recess 160 and the contact hole can be formed in the first interlayer insulating layer 118 with one resist, so that the manufacturing efficiency can be improved and the manufacturing cost can be reduced.
　また、実施形態５の製造方法によれば、ＴＦＴ部１０３およびドライバＴＦＴ部１０７の両方にＮ型ＴＦＴが形成される。ドライバＴＦＴ部１０７にＰ型ＴＦＴを形成する場合には、追加のフォトリソグラフィ工程および半導体層１１４に対するｐ型不純物のドープ工程が必要となるが、上記の製造方法によれば、そのような工程を追加する必要がなく、製造効率が向上する。 Further, according to the manufacturing method of Embodiment 5, N-type TFTs are formed in both the TFT portion 103 and the driver TFT portion 107. When a P-type TFT is formed in the driver TFT portion 107, an additional photolithography step and a p-type impurity doping step for the semiconductor layer 114 are required. According to the above manufacturing method, such a step is performed. There is no need to add, and manufacturing efficiency is improved.
　また、実施形態５の製造方法によれば、図１２（ｂ）～（ｄ）を用いて説明したように、ｎ型不純物１９１の２回のドープ工程の間に、レジスト１８５を残したまま補助容量電極１４５、ゲート電極１４０、およびゲート電極３４０に対してウェットエッチングが施される。ｎ型不純物１９１の２回のドープ工程の間に、フォトリソグラフィ工程は１度しか必要とされない。したがって、ＴＦＴ部１０３におけるチャネル部１３０、Ｓｉ（ｎ－）部１３１および１３２、Ｓｉ（ｎ＋）部１３３および１３４、ならびにドライバＴＦＴ部１０７におけるチャネル部３３０、Ｓｉ（ｎ－）部３３１および３３２、Ｓｉ（ｎ＋）部３３３および３３４を、少ない工程で製造効率よく完成させることができる。 Further, according to the manufacturing method of the fifth embodiment, as described with reference to FIGS. 12B to 12D, the auxiliary process is performed while the resist 185 is left between the two doping steps of the n-type impurity 191. Wet etching is performed on the capacitor electrode 145, the gate electrode 140, and the gate electrode 340. Between the two doping steps of the n-type impurity 191, a photolithography step is only required once. Therefore, the channel portion 130, Si (n−) portions 131 and 132, Si (n +) portions 133 and 134 in the TFT portion 103, and the channel portion 330, Si (n−) portions 331 and 332 in the driver TFT portion 107, Si The (n +) parts 333 and 334 can be completed with few steps and with high production efficiency.
　本発明は、液晶表示装置、有機ＥＬ表示装置、フレキシブルディスプレイなど、多種の表示装置に好適に用いられ得る。 The present invention can be suitably used for various display devices such as liquid crystal display devices, organic EL display devices, and flexible displays.
　１００、２００　　アクティブマトリクス基板
　１０１、２０１　　基板
　１０３、２０３　　ＴＦＴ部
　１０５、２０５　　Ｃｓ部
　１０７　　ドライバＴＦＴ部
　１１０　　画素
　１１４、２１４　　半導体層
　１１６、２１６　　ゲート絶縁層
　１１７　　追加絶縁層
　１１８、２１８　　第１層間絶縁層
　１１９、２１９　　第２層間絶縁層
　１２０、２２０　　画素電極
　１２５　　ＴＦＴ
　１３０、２３０、３３０　　チャネル部
　１３１、１３２、１３７、２３１、２３２、２３７　　Ｓｉ（ｎ－）部
　１３３、１３４、２３３、２３４　　Ｓｉ（ｎ＋）部
　１３９、２３９　　補助容量下部電極
　１４０、２４０、３４０　　ゲート電極
　１４１　　走査線
　１４２　　補助容量線
　１４３、２４３　　ソース電極
　１４４、２４４　　ドレイン電極
　１４５、２４５　　補助容量電極
　１４６、２４６　　信号線
　１４７　　金属層
　１４９　　補助容量上部電極
　１５０　　補助容量
　１６０、１８４　　凹部
　１７０　　対向電極
　１８０　　液晶
　１８５　　レジスト
　１８６　　開口
　１８８　　第１窓
　１８９　　第２窓
　１８７　　マスク
　１９０　　ｐ型不純物
　１９１　　ｎ型不純物
　５００　　対向基板
　５１０、５２０　　偏光板
　５３０　　バックライトユニット
　５４０　　走査線駆動回路
　５５０　　信号線駆動回路
　５６０　　制御部
　１０００　　液晶表示装置 100, 200 Active matrix substrate 101, 201 Substrate 103, 203 TFT unit 105, 205 Cs unit 107 Driver TFT unit 110 Pixel 114, 214 Semiconductor layer 116, 216 Gate insulating layer 117 Additional insulating layer 118, 218 First interlayer insulating layer 119 219 Second interlayer insulating layer 120, 220 Pixel electrode 125 TFT
130, 230, 330 Channel portion 131, 132, 137, 231, 232, 237 Si (n−) portion 133, 134, 233, 234 Si (n +) portion 139, 239 Auxiliary capacitance lower electrode 140, 240, 340 Gate electrode 141 Scan line 142 Auxiliary capacitance line 143, 243 Source electrode 144, 244 Drain electrode 145, 245 Auxiliary capacitance electrode 146, 246 Signal line 147 Metal layer 149 Auxiliary capacitance upper electrode 150 Auxiliary capacitance 160, 184 Recess 170 Counter electrode 180 Liquid crystal 185 Resist 186 opening 188 first window 189 second window 187 mask 190 p-type impurity 191 n-type impurity 500 counter substrate 510 520 polarizing plate 530 backlight unit 540 scanning line driving circuit 550 signal line driving circuit 56 Control unit 1000 a liquid crystal display device

Claims (15)

  1. 　半導体層と、
    　前記半導体層の上に形成された絶縁層と、
    　前記絶縁層の上に形成された補助容量電極と、
    　前記補助容量電極の上に形成された第１層間絶縁層と、
    　前記補助容量電極の上方の前記第１層間絶縁層に形成された凹部と、
    　前記凹部の底面の上に形成された補助容量上部電極と、
    　前記補助容量上部電極の上に形成された第２層間絶縁層と、
    　前記第２層間絶縁層の上に形成された画素電極と、を備えたアクティブマトリクス基板。     A semiconductor layer;
    An insulating layer formed on the semiconductor layer;
    An auxiliary capacitance electrode formed on the insulating layer;
    A first interlayer insulating layer formed on the auxiliary capacitance electrode;
    A recess formed in the first interlayer insulating layer above the auxiliary capacitance electrode;
    A storage capacitor upper electrode formed on the bottom surface of the recess;
    A second interlayer insulating layer formed on the auxiliary capacitor upper electrode;
    An active matrix substrate comprising: a pixel electrode formed on the second interlayer insulating layer.
  2. 　前記補助容量電極の上面と前記補助容量上部電極との間に酸化シリコンからなる層が配置され、
    　前記補助容量電極の上面から前記補助容量上部電極の下面までの距離が、１０ｎｍ以上１００ｎｍ以下である、請求項１に記載のアクティブマトリクス基板。     A layer made of silicon oxide is disposed between the upper surface of the auxiliary capacitance electrode and the upper electrode of the auxiliary capacitance,
    2. The active matrix substrate according to claim 1, wherein a distance from an upper surface of the auxiliary capacitance electrode to a lower surface of the auxiliary capacitance upper electrode is 10 nm or more and 100 nm or less.
  3. 　前記補助容量電極の上面と前記補助容量上部電極との間に窒化シリコンからなる層が配置され、
    　前記補助容量電極の上面から前記補助容量上部電極の下面までの距離が、１０ｎｍ以上２００ｎｍ以下である、請求項１に記載のアクティブマトリクス基板。     A layer made of silicon nitride is disposed between the upper surface of the auxiliary capacitance electrode and the auxiliary capacitance upper electrode,
    2. The active matrix substrate according to claim 1, wherein a distance from an upper surface of the auxiliary capacitance electrode to a lower surface of the auxiliary capacitance upper electrode is 10 nm or more and 200 nm or less.
  4. 　前記補助容量上部電極と前記半導体層とが、前記絶縁層および前記第１層間絶縁層に形成されたコンタクトホールを介して電気的に接続されており、
    　前記補助容量上部電極と前記画素電極とが、前記第２層間絶縁層に形成されたコンタクトホールを介して電気的に接続されている、請求項１から３のいずれかに記載のアクティブマトリクス基板。     The auxiliary capacitor upper electrode and the semiconductor layer are electrically connected via a contact hole formed in the insulating layer and the first interlayer insulating layer,
    4. The active matrix substrate according to claim 1, wherein the auxiliary capacitor upper electrode and the pixel electrode are electrically connected through a contact hole formed in the second interlayer insulating layer. 5.
  5. 　前記半導体層が、前記補助容量電極の下部に形成され、不純物をドープした半導体からなる補助容量下部電極を含む、請求項１から４のいずれかに記載のアクティブマトリクス基板。 The active matrix substrate according to any one of claims 1 to 4, wherein the semiconductor layer includes an auxiliary capacitance lower electrode made of a semiconductor doped with an impurity and formed under the auxiliary capacitance electrode.
  6. 　前記補助容量電極の上に追加絶縁層が形成されており、
    　前記補助容量電極の上面が前記追加絶縁層の下面と接し、前記補助容量上部電極の下面が前記追加絶縁層の上面と接している、請求項１に記載のアクティブマトリクス基板。     An additional insulating layer is formed on the auxiliary capacitance electrode,
    2. The active matrix substrate according to claim 1, wherein an upper surface of the auxiliary capacitance electrode is in contact with a lower surface of the additional insulating layer, and a lower surface of the auxiliary capacitance upper electrode is in contact with an upper surface of the additional insulating layer.
  7. 　前記追加絶縁層が窒化シリコンからなり、前記第１層間絶縁層が酸化シリコンからなる、請求項６に記載のアクティブマトリクス基板。 The active matrix substrate according to claim 6, wherein the additional insulating layer is made of silicon nitride, and the first interlayer insulating layer is made of silicon oxide.
  8. 　半導体層を形成する工程と、
    　前記半導体層の上に絶縁層を形成する工程と、
    　前記絶縁層の上に補助容量電極を形成する工程と、
    　前記補助容量電極の上に第１層間絶縁層を形成する工程と、
    　前記補助容量電極の上方の前記第１層間絶縁層に凹部を形成する工程と、
    　前記凹部の底面の上に補助容量上部電極を形成する工程と、
    　前記補助容量上部電極の上に第２層間絶縁層を形成する工程と、
    　前記第２層間絶縁層の上に画素電極を形成する工程と、を含むアクティブマトリクス基板の製造方法。     Forming a semiconductor layer;
    Forming an insulating layer on the semiconductor layer;
    Forming an auxiliary capacitance electrode on the insulating layer;
    Forming a first interlayer insulating layer on the auxiliary capacitance electrode;
    Forming a recess in the first interlayer insulating layer above the auxiliary capacitance electrode;
    Forming a storage capacitor upper electrode on the bottom surface of the recess;
    Forming a second interlayer insulating layer on the auxiliary capacitor upper electrode;
    Forming a pixel electrode on the second interlayer insulating layer. A method of manufacturing an active matrix substrate.
  9. 　前記補助容量電極の上面と前記補助容量上部電極との間に酸化シリコンからなる層が形成され、
    　前記補助容量電極の上面から前記凹部の底面までの距離が、１０ｎｍ以上１００ｎｍ以下となるように、前記第１層間絶縁層に前記凹部が形成される、請求項８に記載のアクティブマトリクス基板の製造方法。     A layer made of silicon oxide is formed between the upper surface of the auxiliary capacitance electrode and the auxiliary capacitance upper electrode,
    9. The manufacturing of the active matrix substrate according to claim 8, wherein the recess is formed in the first interlayer insulating layer so that a distance from an upper surface of the auxiliary capacitance electrode to a bottom surface of the recess is not less than 10 nm and not more than 100 nm. Method.
  10. 　前記補助容量電極の上面と前記補助容量上部電極との間に窒化シリコンからなる層が形成され、
    　前記補助容量電極の上面から前記凹部の底面までの距離が、１０ｎｍ以上２００ｎｍ以下となるように、前記第１層間絶縁層に前記凹部が形成される、請求項８に記載のアクティブマトリクス基板の製造方法。     A layer made of silicon nitride is formed between the upper surface of the auxiliary capacitance electrode and the auxiliary capacitance upper electrode,
    9. The manufacturing of the active matrix substrate according to claim 8, wherein the recess is formed in the first interlayer insulating layer so that a distance from an upper surface of the auxiliary capacitance electrode to a bottom surface of the recess is 10 nm or more and 200 nm or less. Method.
  11. 　前記凹部を形成する工程は、
    　前記第１層間絶縁層の上にレジストを形成する工程と、
    　前記補助容量電極の上方に前記レジストの開口を形成する工程と、
    　前記レジストの前記開口の下の前記第１層間絶縁層を選択的にエッチングする工程と、を含む、請求項８から１０のいずれかに記載のアクティブマトリクス基板の製造方法。     The step of forming the recess includes
    Forming a resist on the first interlayer insulating layer;
    Forming the resist opening above the auxiliary capacitance electrode;
    The method for manufacturing an active matrix substrate according to claim 8, further comprising: selectively etching the first interlayer insulating layer under the opening of the resist.
  12. 　前記凹部を形成する工程は、
    　前記第１層間絶縁層の上にレジストを形成する工程と、
    　第１窓と、前記第１窓よりも光透過率の高い複数の第２窓とを有するマスクを前記レジストの上方に配置する工程と、
    　前記第１窓および前記複数の第２窓を介して前記レジストに光を照射する工程と、
    　光を照射された前記レジストを除去して、前記レジストに窪みと複数の開口とを形成する工程と、
    　前記レジストを介して前記第１層間絶縁層を選択的にエッチングして、前記補助容量電極の上に前記第１層間絶縁層の前記凹部を形成するとともに、前記レジストの前記開口の下に前記半導体層に通じるコンタクトホールを形成する工程と、を含む、請求項８から１０のいずれかに記載のアクティブマトリクス基板の製造方法。     The step of forming the recess includes
    Forming a resist on the first interlayer insulating layer;
    Disposing a mask having a first window and a plurality of second windows having a higher light transmittance than the first window above the resist;
    Irradiating the resist with light through the first window and the plurality of second windows;
    Removing the resist irradiated with light, forming a recess and a plurality of openings in the resist;
    The first interlayer insulating layer is selectively etched through the resist to form the concave portion of the first interlayer insulating layer on the auxiliary capacitance electrode, and the semiconductor under the opening of the resist The method for manufacturing an active matrix substrate according to claim 8, further comprising: forming a contact hole that communicates with the layer.
  13. 　前記半導体層に不純物をドープする工程を含み、
    　前記補助容量電極を形成する工程において、前記補助容量電極が、前記不純物をドープされた前記半導体層の上に形成される、請求項８から１２のいずれかに記載のアクティブマトリクス基板の製造方法。     Doping the semiconductor layer with impurities,
    The method of manufacturing an active matrix substrate according to claim 8, wherein in the step of forming the auxiliary capacitance electrode, the auxiliary capacitance electrode is formed on the semiconductor layer doped with the impurity.
  14. 　前記補助容量電極の上に追加絶縁層を形成する工程を含み、
    　前記第１層間絶縁層に前記凹部を形成する工程において、前記追加絶縁層をエッチングストッパとして用いて、前記凹部の底面に前記追加絶縁層が露出するように前記第１層間絶縁層がエッチングされる、請求項８に記載のアクティブマトリクス基板の製造方法。     Forming an additional insulating layer on the auxiliary capacitance electrode;
    In the step of forming the recess in the first interlayer insulating layer, the first interlayer insulating layer is etched using the additional insulating layer as an etching stopper so that the additional insulating layer is exposed on the bottom surface of the recess. A method for manufacturing an active matrix substrate according to claim 8.
  15. 　前記追加絶縁層が窒化シリコンから形成され、前記第１層間絶縁層が酸化シリコンから形成される、請求項１４に記載のアクティブマトリクス基板の製造方法。 15. The method of manufacturing an active matrix substrate according to claim 14, wherein the additional insulating layer is formed from silicon nitride, and the first interlayer insulating layer is formed from silicon oxide.
PCT/JP2012/056411 2011-03-15 2012-03-13 Active matrix substrate and method for manufacturing active matrix substrate WO2012124690A1 (en)

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