WO2012117773A1 - Solid-state memory - Google Patents

Solid-state memory Download PDF

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Publication number
WO2012117773A1
WO2012117773A1 PCT/JP2012/051570 JP2012051570W WO2012117773A1 WO 2012117773 A1 WO2012117773 A1 WO 2012117773A1 JP 2012051570 W JP2012051570 W JP 2012051570W WO 2012117773 A1 WO2012117773 A1 WO 2012117773A1
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solid
state memory
thin film
recording layer
layer
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PCT/JP2012/051570
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French (fr)
Japanese (ja)
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富永　淳二
アレキサンダー コロボフ
ポール フォンズ
俊通 新谷
貴浩 小高
貴博 森川
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独立行政法人産業技術総合研究所
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H10N70/235—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect between different crystalline phases, e.g. cubic and hexagonal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H10N70/026—Formation of switching materials, e.g. deposition of layers by physical vapor deposition, e.g. sputtering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8413—Electrodes adapted for resistive heating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe

Definitions

  • the present invention relates to a solid state memory in which a chalcogen compound containing tellurium (Te) as a main component is used for a recording layer, and the difference in physical properties associated with the phase change in the recording layer is used for recording, erasing, and reproducing data. .
  • Te tellurium
  • phase change random access memory which is one type of solid-state memory, uses a chalcogen compound containing Te as a material constituting the recording layer.
  • the solid-state memory uses a phase change of a crystal structure called a primary phase transformation (herein simply referred to as a phase change) of a crystalline state and an amorphous state of a substance constituting a recording layer.
  • a phase change a phase change of a crystal structure called a primary phase transformation (herein simply referred to as a phase change) of a crystalline state and an amorphous state of a substance constituting a recording layer.
  • a chalcogen compound used for the recording layer a Ge 2 Sb 2 Te 5 alloy is generally used.
  • the two states of data recording and erasing in the solid-state memory are realized, for example, by assigning the crystalline state to the recording state and the amorphous state to the erasing state, and the solid-state memory is designed based on this basic principle (for example, Patent Document 1).
  • the material constituting the recording layer of the solid-state memory is formed between the upper and lower electrodes using a vacuum film formation method such as a sputtering method.
  • a vacuum film formation method such as a sputtering method.
  • sputtering is performed using a target composed of a compound composition used as a recording layer, and a single-layer alloy thin film is formed and used as a recording layer.
  • the recording layer of the solid-state memory is composed of a chalcogen compound polycrystal.
  • the axial orientation of each microcrystal grain is random, and there is an interface resistance at the interface between each microcrystal grain.
  • the interfacial resistance is random depending on the interface state of each microcrystal grain, and as a result, the resistance value of the crystal state in the recording layer of the solid memory has a constant distribution from the average value (non- Patent Document 1).
  • each microcrystal grain has a different direction and a different size due to a volume change of about 10% that occurs during the phase change between crystal and amorphous. Stress is applied. As data is recorded and erased, the crystal-amorphous phase change is repeated, and the stress is repeatedly applied to the recording layer. As a result, it is considered that the solid memory is destroyed by repeated material flow and deformation of the entire film, and the number of repeated record erasures is limited (Non-Patent Document 2).
  • the present inventors have not formed a recording layer on a Ge 2 Te 2 thin film composed of germanium (Ge) atoms and Te atoms, but a Ge 2 Sb 2 Te 5 alloy single layer film. It has been proposed that a superlattice structure is formed by dividing and laminating Sb 2 Te 3 thin films composed of Sb atoms and Te atoms (Patent Document 2).
  • the recording layer made of the superlattice has been called an amorphous state in the conventional Ge 2 Sb 2 Te 5 alloy by returning Ge atoms diffused at the interface into the original Ge 2 Te 2 layer. It returns to the “structure similar to amorphous” having the same electrical resistance value as the structure.
  • This “structure similar to amorphous” state is assigned to, for example, an erased state (generally called a Reset state).
  • Patent Document 2 A memory is provided (Patent Document 2).
  • Non-Patent Document 3 a Ge—Cu—Te alloy is attracting attention in place of the Ge—Sb—Te alloy (for example, Non-Patent Document 3).
  • the composition is a eutectic composition of Ge 2 Te 2 and CuTe 2 , the crystal phase transition temperature is as high as 200 ° C. or more, and the high temperature storage stability is excellent. For this reason, GeCu 2 Te 3 alloy is particularly expected.
  • Japanese Patent Publication Japanese Patent Laid-Open No. 2002-203392 (published on July 19, 2002)” Japanese Patent Publication “JP 2009-59902 A (published on March 19, 2009)”
  • the GeCu 2 Te 3 alloy has a drawback that the resistance value in the amorphous state is an order of magnitude smaller than that of the conventional Ge 2 Sb 2 Te 5 alloy, and the difference from the resistance value in the crystalline state is as small as about two orders of magnitude.
  • the ratio of the resistance values When the ratio of the resistance values is small, the difference between the voltage signals obtained at the time of reproducing the solid-state memory becomes small, and in order to obtain a practical signal / noise ratio, it is necessary to increase the driving current at the time of reproduction.
  • the above drive current increases in various ways in solid-state memory, such as increased power consumption, temperature rise with increased Joule heat, melting or melting of the material constituting the recording layer, and segregation of compounds with different composition ratios associated therewith. Adversely affected.
  • the superlattice made of Ge 2 Sb 2 Te 5 alloy or Ge 2 Te 2 and Sb 2 Te 3 can be used for repeated recording and erasing.
  • the current situation is that it does not reach a solid-state memory using a recording layer.
  • the present invention provides an Sb-free solid memory in which the resistance value changes sufficiently with the phase change, and the number of repeated recording / erasing operations is similar to that of a Ge—Sb—Te solid memory.
  • the purpose is to do.
  • a solid-state memory is a solid-state memory including a recording layer whose electrical characteristics change due to a phase change of a substance, and the recording layer includes germanium and tellurium. It is characterized by being constituted by a superlattice formed by laminating a thin film formed and a thin film formed of copper and tellurium.
  • germanium (Ge) is used as a recording layer of the solid-state memory in order to provide an Sb-free solid-state memory having performance comparable to that of a Ge—Sb—Te solid-state memory.
  • a superlattice structure of a thin film made of copper and tellurium (Te) hereinafter referred to as Ge—Te thin film
  • a thin film formed of copper (Cu) and Te hereinafter referred to as Cu—Te thin film.
  • the volume change accompanying the phase change of the superlattice structure composed of a Ge—Te-based thin film and a Cu—Te-based thin film is extremely small as shown in the examples described later.
  • the volume change accompanying the phase change gives mechanical stress to a structure such as an electrode disposed above and below the recording layer when data recording and erasing are repeated.
  • the stress is repeatedly applied to the solid-state memory, the solid-state memory is destroyed due to shearing or peeling at each layer interface. Therefore, the extremely small volume change accompanying the phase change contributes to extending the repeated life of data recording and erasing.
  • a solid-state memory while being Sb-free, ensuring the change is large enough electrical resistance value of the solid-state memory with a phase change, a solid-state memory also the number of repeated recording erasing data reaching 10 11 times can do. These have performance comparable to that of a solid-state memory using a Ge—Sb—Te alloy as a recording layer.
  • (A) shows the crystal structure of crystal phase A
  • (b) shows the crystal structure of crystal phase B.
  • (A) is sectional drawing which shows the outline of the solid-state memory using the recording layer which consists of a superlattice based on one Embodiment of this invention.
  • (B) is a cross-sectional view schematically showing a superlattice composed of a Ge 2 Te 2 thin film and a CuTe 2 thin film constituting a recording layer.
  • Ge is a sectional view showing a 2 Cu 1 Te 4 schematically solid memory using the recording layer made of an alloy.
  • the recording layer of the solid memory according to the present invention includes a superstructure composed of a Ge—Te alloy film and a Cu—Te alloy film.
  • a lattice structure is used.
  • FIG. 1 is a diagram showing a superlattice structure when a Ge 2 Te 2 layer 4 is used as an example of a Ge—Te based alloy film and a CuTe 2 layer 5 is used as an example of a Cu—Te based alloy film.
  • the superlattice structure shown in FIG. 1 is a structure determined using first-principles calculations.
  • the film thicknesses of Ge 2 Te 2 layer 4 and CuTe 2 layer 5 are 0.77 nm and 0.54 nm, respectively. is there.
  • a superlattice is a crystal lattice having a long-period structure artificially formed by regularly laminating a plurality of types of crystal thin films.
  • the superlattice structure means such a crystal lattice structure.
  • the ratio of the number of Ge atoms to Te is more preferably smaller, and the ratio of the number of Ge atoms to the total number of atoms in the Ge—Te-based alloy film is greater than 0 and less than 0.00. More preferably, it is 5 or less.
  • the ratio of the number of Cu atoms to the total number of atoms in the Cu—Te-based alloy film is more preferably greater than 0 and less than or equal to 0.5, and more preferably between 0.2 and 0.4. The following is more preferable, and it is particularly preferable to use a CuTe 2 film as the Cu—Te-based alloy film.
  • a superlattice composed of a stacked structure of a Ge 2 Te 2 layer 4 composed of Ge atoms 1 and Te atoms 2 and a CuTe 2 layer 5 composed of Te atoms 2 and Cu atoms 3 has two stable structures. It has bistability with a certain structure A (FIG. 1A) and structure B (FIG. 1B).
  • the solid-state memory functions as a solid-state memory by utilizing the phase change between the structure A and the structure B in the recording layer.
  • the positions of the Ge layer and the Te layer in the Ge 2 Te 2 layer 4 are interchanged. Further, the intervals between the GeTe layers are slightly different, and the interval of the structure B is wider than that of the structure A.
  • the phase change from the structure A to the structure B or from the structure B to the structure A can be caused by electric energy means.
  • the movement of the GeTe layer accompanying the phase change is unidirectional (perpendicular to the substrate surface) and can be said to have coherency. Therefore, it is possible to efficiently use the input energy for the phase change, and as a result, there is an advantage that less energy is required to cause the phase change.
  • the volume change accompanying the phase change can be made extremely small, and the change in the resistance value accompanying the phase change of the recording layer can be 3 digits. It can be large enough.
  • the bond valence of Ge is tetravalent in the structure A ((a) in FIG. 1).
  • the structure B is hexavalent ((b) in FIG. 1).
  • the bond valence of Ge changes from tetravalent to hexavalent because the Ge layer and the Te layer are interchanged with each other in accordance with the phase change, and the distance between the CuTe 2 layer 5 becomes closer and a bond is formed between Ge and Te. Because. FIG.
  • FIG. 1 is a diagram showing the structure of a basic cell of a superlattice composed of a Ge 2 Te 2 thin film 4 and a CuTe 2 thin film 5.
  • Ge atom 1 becomes hexavalent, electrical characteristics in the direction perpendicular to the substrate surface become metallic, and the resistance value is significantly reduced. Thereby, the change of the resistance value at the time of phase change can be increased more preferably as a solid-state memory.
  • the structure A and the structure B are greatly different not only in electrical characteristics but also in optical characteristics, it is possible to use an optical technique as a means for reproducing recorded data.
  • a pulsed current can be used as an electric energy means for inducing a phase change.
  • the phase change between the structure A and the structure B can be arbitrarily repeated by adjusting the current value of the pulse current flowing at this time and the time (hereinafter referred to as pulse time) for flowing the current.
  • pulse time the time for flowing the current.
  • FIG. 2A is a cross-sectional view schematically showing a solid-state memory 10 using a superlattice thin film composed of a Ge 2 Te 2 thin film 4 and a CuTe 2 thin film 5 as a recording layer 11.
  • a schematic enlarged view of the recording layer 11 is shown in FIG.
  • the recording layer 11 is sandwiched between the upper electrode 14 and the Joule heat generating heater 15. Further, the upper electrode 14 is in electrical contact with the read line 13 and the Joule heat generating heater 15 is in electrical contact with the write line 16, respectively. That is, the Joule heat generating heater 15 serves as a lower electrode as well as a heater.
  • the current is used as the electric energy means.
  • Joule heat is generated in the Joule heat generation heater 15, the recording layer 11 is heated, and the temperature rises.
  • the temperature of the recording layer 11 is controlled, and the phase change between the structure A and the structure B can be repeated.
  • FIG. 2 is a cross-sectional view schematically showing a solid-state memory using a superlattice thin film composed of a Ge 2 Te 2 thin film 4 and a CuTe 2 thin film 5 as a recording layer 11.
  • the solid-state memory according to an embodiment of the present invention can be formed as, for example, a phase change RAM having a general self-resistance heating type configuration (for example, Patent Document 1).
  • a phase change RAM having a general self-resistance heating type configuration
  • the write line 16 and the Joule heat generation heater 15 are formed on the substrate.
  • the recording layer 11, the upper electrode 14, and the readout line 13 may be sequentially formed.
  • a film forming method at this time for example, a general film forming method such as a sputtering method can be used. An example of a method for manufacturing a solid-state memory is described below.
  • a silicon (Si) wafer is used as a substrate, and a writing line 16 and a Joule heat generating heater 15 are formed by sputtering.
  • tungsten can be used for the Joule heat generation heater.
  • a superlattice of a Ge—Te alloy film and a Cu—Te alloy film used for the recording layer is formed by sputtering.
  • a target capable of forming a desired compound for example, Ge 2 Te 2 and CuTe 2 .
  • an upper electrode 14 and a readout line 13 made of tungsten are formed to complete the phase change RAM.
  • the film thickness of the Ge—Te thin film and the Cu—Te thin film constituting the superlattice structure is desirably 0.5 nm or more and 8 nm or less. By setting the film thickness within this range, a superlattice structure can be suitably realized without disturbing the crystal structure of each thin film.
  • a general photolithography process can be used for patterning of the electrode and the recording layer.
  • the present invention can also be expressed as follows.
  • a solid-state memory mainly composed of Cu, Ge, and Te, whose electrical characteristics change due to a phase transformation of a substance, and a material for recording and reproducing data exhibits the phase transformation.
  • a solid-state memory comprising a laminated structure of an artificial superlattice structure of a thin film composed of a parent phase.
  • the stacked structure is formed of a multilayer film in which a Te alloy thin film containing Ge atoms and a Te alloy thin film containing Cu atoms are stacked on each other. memory.
  • Example 1 The crystal structure and various characteristics of the superlattice used for the recording layer have a significant effect on the performance of solid-state memory (change in resistance value due to phase change, required drive current value, and the number of times recording can be repeatedly erased, etc.) So very important.
  • the superlattices of the structure A and the structure B described above were fabricated and confirmed to have the following characteristics.
  • the superlattice composed of the Ge 2 Te 2 layer 4 and the CuTe 2 layer 5 causes a phase change between the structure A and the structure B by applying electrical energy (see FIG. 1). That is, the superlattice selects one of the structure A or the structure B that is bistable in accordance with the applied energy.
  • the energy to be applied is not limited to electrical energy, and it is also possible to select a superlattice structure using thermal energy.
  • the superlattice thin film of the structure A and the structure B was formed using the difference in applied thermal energy.
  • a superlattice thin film having a film thickness of about 40 nm composed of Ge 2 Te 2 layer 4 and CuTe 2 layer 5 is formed on Si wafers having different substrate temperatures by sputtering, and the crystal structure, electrical characteristics, and optical properties are measured. The characteristics were compared.
  • the substrate temperatures during film formation are 150 ° C. and 250 ° C., respectively, and are hereinafter referred to as sample a and sample b.
  • the sample a was about 5 M ⁇ and the sample b was 30 k ⁇ . From this, it was confirmed that when the phase change between the structure A and the structure B is used for the phase change RAM, the signal at the time of reading shows a change of about 170 times.
  • the superlattice composed of the Ge 2 Te 2 layer 4 and the CuTe 2 layer 5 is suitable as a recording layer of a solid-state memory because the change in the resistance value accompanying the phase change is three digits.
  • the superlattice composed of the Ge 2 Te 2 layer 4 and the CuTe 2 layer 5 has a very small volume change due to the phase change, and therefore can be expected to improve the number of repetitions of recording and erasing.
  • Example 2 A solid-state memory according to the present invention was fabricated using the above-described general self-resistance heating type basic configuration (FIG. 2).
  • a Si wafer was used for the substrate, and tungsten was used for the Joule heat generation heater 15 and the upper electrode 14.
  • the film thickness of the recording layer 11 was 26 nm.
  • the cell size of the recording layer was 100 ⁇ 100 nm 2 .
  • the current value required for recording and erasing information and the pulse time for flowing the current were examined by passing a current having a waveform determined by a program in advance through the current path 20 of the solid-state memory.
  • the current value required for the phase change from the structure A to the structure B was 0.1 mA, and the pulse time was 100 ns.
  • the current value required for the phase change from the structure B to the structure A was 0.5 mA, and the pulse time was 50 ns.
  • the current of the above waveform was continuously passed through the solid-state memory to repeatedly measure the number of recording / erasing. As a result, in the solid-state memory used in this example, it was possible to repeat recording and erasing of 10 11 times.
  • the current value required for recording and erasing information was examined by flowing a current having a waveform determined in advance by a program through the current path 20 of the solid-state memory.
  • the pulse time for supplying current was the same as the pulse time described in Example 2.
  • the current value required for the phase change from the crystal phase A to the crystal phase B was 0.3 mA.
  • the current value from the crystal phase B to the crystal phase A was 1.9 mA.
  • a continuous waveform was programmed using the current value obtained here and the pulse time used in Example 2, and a current was passed through the phase change RAM based on the waveform, and the number of times of recording and erasing was measured repeatedly.
  • repeated recording number of times of erasing solid memory using a single layer film of Ge 2 Cu 1 Te 4 alloy as a recording layer 12 was 10 4 times.
  • a solid-state memory is a solid-state memory including a recording layer whose electrical characteristics change due to a phase change of a substance, and the recording layer includes germanium and tellurium. It is characterized by being constituted by a superlattice formed by laminating a thin film formed and a thin film formed of copper and tellurium.
  • germanium (Ge) is used as a recording layer of the solid-state memory in order to provide an Sb-free solid-state memory having performance comparable to that of a Ge—Sb—Te solid-state memory.
  • a superlattice structure of a thin film made of copper and tellurium (Te) hereinafter referred to as Ge—Te thin film
  • a thin film formed of copper (Cu) and Te hereinafter referred to as Cu—Te thin film.
  • the volume change accompanying the phase change of the superlattice structure composed of a Ge—Te-based thin film and a Cu—Te-based thin film is extremely small as shown in the above-described embodiments.
  • the volume change accompanying the phase change gives mechanical stress to a structure such as an electrode disposed above and below the recording layer when data recording and erasing are repeated.
  • the stress is repeatedly applied to the solid-state memory, the solid-state memory is destroyed due to shearing or peeling at each layer interface. Therefore, the extremely small volume change accompanying the phase change contributes to extending the repeated life of data recording and erasing.
  • the thin film formed of germanium and tellurium is a Ge 2 Te 2 thin film
  • the thin film formed of copper and tellurium is a CuTe 2 thin film. It is preferable.
  • each film thickness of the thin film is 0.5 nm or more and 8 nm or less.
  • the thin film formed of germanium and tellurium may change its electric resistance value when the germanium has a tetravalent or hexavalent bond valence. It is preferable that the data recording state or the erasing state is expressed by the electric resistance value.
  • the superlattice structure composed of the Ge—Te-based thin film and the Cu—Te-based thin film has bistability and can take two types of crystal structures.
  • the difference between the two types of crystal structures is mainly the difference in the distance between GeTe layers in the Ge—Te thin film layer, and this also affects the interlayer distance between the GeTe layer and the Cu—Te layer.
  • the bond valence of Ge atoms is tetravalent.
  • the Ge—Te-based thin film layer has a crystal structure in which the GeTe layers are separated from each other (see FIG. 1B), the bond valence of Ge atoms is hexavalent.
  • the phase change in the two types of crystal structures affects the bonding state of Ge atoms in the direction perpendicular to the substrate surface.
  • the Ge atoms of the Ge—Te-based thin film layer undergo a phase change from tetravalent to hexavalent, coupling in the direction perpendicular to the substrate of the superlattice becomes strong, and the electrical resistance value of the recording layer is greatly reduced.
  • the data recording state or erasing state can be expressed by the electric resistance value.
  • the solid-state memory according to the present invention can be successfully functioned as a memory. .
  • the tetravalent and hexavalent bond mutations cause a change in film thickness of about 0.2% in the vertical direction, but 10% of a commonly used phase change material alloy composed of Ge—Sb—Te. Much smaller than the degree of change.
  • data may be reproduced by detecting the electrical resistance value.
  • a sufficiently large value is realized as a change in resistance value accompanying the phase change.
  • the fact that the change in the resistance value accompanying the phase change is large means that the change in the output voltage value is large even if the current value flowing through the solid state memory is set small during reproduction. That is, the solid state memory can be driven with a smaller current value.
  • Joule heat generated by the drive current gives a thermal history to the recording layer and the structure surrounding the recording layer, and this thermal history also causes the solid memory to be destroyed as in the case of the volume change. Therefore, the small driving current of the solid-state memory contributes to extending the repeated life of data recording and erasing.
  • the ratio of the number of germanium atoms to the total number of atoms in the thin film formed of germanium and tellurium is preferably 0.5 or less.
  • the ratio of the number of copper atoms to the total number of atoms is preferably 0.5 or less.
  • a superlattice structure having bistability can be suitably formed.
  • the solid-state memory records or erases information by changing the crystal structure of the recording layer using electric energy means.
  • the solid-state memory can reproduce information by utilizing the change in the electrical characteristics of the recording layer as a result of the phase change.
  • the present invention can be used in the field of manufacturing electronic components.

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  • Crystallography & Structural Chemistry (AREA)
  • Engineering & Computer Science (AREA)
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Abstract

This solid-state memory is provided with a recording layer the electrical properties of which change with the phase transition of matter. The recording layer is produced from a superlattice that is obtained by laminating a thin film formed from germanium and tellurium and a thin film formed from copper and tellurium.

Description

固体メモリSolid memory
　本発明は、テルル（Ｔｅ）を主成分とするカルコゲン化合物を記録層に利用して、上記記録層における相変化に伴う物性の相違を、データの記録、消去、および再生に利用する固体メモリに関する。 The present invention relates to a solid state memory in which a chalcogen compound containing tellurium (Te) as a main component is used for a recording layer, and the difference in physical properties associated with the phase change in the recording layer is used for recording, erasing, and reproducing data. .
　固体メモリの一様式である相変化ランダムアクセスメモリ（相変化ＲＡＭ）は、その記録層を構成する物質として、Ｔｅを含むカルコゲン化合物を利用している。上記固体メモリでは、記録層を構成する物質の結晶状態とアモルファス状態の一次相変態（本明細書では、単に相変化とする）と呼ばれる結晶構造の相変化を利用する。なお、記録層に用いるカルコゲン化合物としては、Ｇｅ２Ｓｂ２Ｔｅ５合金が一般的である。 A phase change random access memory (phase change RAM), which is one type of solid-state memory, uses a chalcogen compound containing Te as a material constituting the recording layer. The solid-state memory uses a phase change of a crystal structure called a primary phase transformation (herein simply referred to as a phase change) of a crystalline state and an amorphous state of a substance constituting a recording layer. As the chalcogen compound used for the recording layer, a Ge 2 Sb 2 Te 5 alloy is generally used.
　上記固体メモリにおけるデータの記録、および消去の２状態は、例えば結晶状態を記録状態に、アモルファス状態を消去状態に割り当てることで実現され、この基本原理に基づいて固体メモリが設計されている（例えば、特許文献１）。 The two states of data recording and erasing in the solid-state memory are realized, for example, by assigning the crystalline state to the recording state and the amorphous state to the erasing state, and the solid-state memory is designed based on this basic principle (for example, Patent Document 1).
　なお、結晶構造の相変化を利用した固体メモリにおいて、相変化を誘起するためには、相変化を誘起するのに十分なエネルギーを記録層に印加する必要がある。エネルギーを印加する方法としては、記録層に電流を流すことによる電気エネルギー手段を用いるのが一般的である。 In a solid-state memory using a phase change of the crystal structure, in order to induce a phase change, it is necessary to apply sufficient energy to the recording layer to induce the phase change. As a method for applying energy, it is common to use electric energy means by passing a current through the recording layer.
　固体メモリの記録層を構成する材料は、スパッタリング法等の真空成膜法を利用して上下の各電極間に形成する。通常は、記録層として用いる化合物組成からなるターゲットを使用してスパッタリングを行い、単層の合金薄膜を成膜して記録層として用いる。 The material constituting the recording layer of the solid-state memory is formed between the upper and lower electrodes using a vacuum film formation method such as a sputtering method. Usually, sputtering is performed using a target composed of a compound composition used as a recording layer, and a single-layer alloy thin film is formed and used as a recording layer.
　スパッタリング法を利用して、記録層に適した２０ｎｍ～５０ｎｍ程度の膜厚を有するカルコゲン化合物の単層膜を成膜した場合、単結晶からなる記録層を得ることは困難である。よって、固体メモリの記録層はカルコゲン化合物の多結晶から構成されている。 When a single layer film of a chalcogen compound having a thickness of about 20 nm to 50 nm suitable for a recording layer is formed by using a sputtering method, it is difficult to obtain a recording layer made of a single crystal. Therefore, the recording layer of the solid-state memory is composed of a chalcogen compound polycrystal.
　多結晶からなる薄膜において、個々の微結晶粒の軸方位はランダムであり、各微結晶粒同士の界面には界面抵抗が存在する。上記界面抵抗は、それぞれの微結晶粒の界面状態に依存してランダムであり、その結果、固体メモリの記録層における結晶状態の抵抗値は、平均値から一定の分布を持つことになる（非特許文献１）。 In the thin film made of polycrystal, the axial orientation of each microcrystal grain is random, and there is an interface resistance at the interface between each microcrystal grain. The interfacial resistance is random depending on the interface state of each microcrystal grain, and as a result, the resistance value of the crystal state in the recording layer of the solid memory has a constant distribution from the average value (non- Patent Document 1).
　また、カルコゲン化合物の多結晶薄膜からなる記録層において、結晶－アモルファス間の相変化の際に発生する１０％程度の体積変化によって、それぞれの微結晶粒には、異なる方向、および、異なる大きさの応力が加えられる。データの記録、および消去に伴い、上記結晶－アモルファス間の相変化が繰り返され、記録層には上記応力が繰り返し加えられることになる。その結果、物質流動と膜全体の変形の繰り返しによって固体メモリが破壊され、繰り返し記録消去回数は制限されると考えられている（非特許文献２）。 Further, in the recording layer formed of a polycrystalline thin film of chalcogen compound, each microcrystal grain has a different direction and a different size due to a volume change of about 10% that occurs during the phase change between crystal and amorphous. Stress is applied. As data is recorded and erased, the crystal-amorphous phase change is repeated, and the stress is repeatedly applied to the recording layer. As a result, it is considered that the solid memory is destroyed by repeated material flow and deformation of the entire film, and the number of repeated record erasures is limited (Non-Patent Document 2).
　これらの問題を解決する手段の一つとして、本発明者らは、記録層をＧｅ２Ｓｂ２Ｔｅ５合金単層膜ではなく、ゲルマニウム（Ｇｅ）原子とＴｅ原子からなるＧｅ２Ｔｅ２薄膜と、Ｓｂ原子とＴｅ原子からなるＳｂ２Ｔｅ３薄膜とに分割し、かつ、積層することによって超格子構造とすることが提案されている（特許文献２）。 As one of means for solving these problems, the present inventors have not formed a recording layer on a Ge 2 Te 2 thin film composed of germanium (Ge) atoms and Te atoms, but a Ge 2 Sb 2 Te 5 alloy single layer film. It has been proposed that a superlattice structure is formed by dividing and laminating Sb 2 Te 3 thin films composed of Sb atoms and Te atoms (Patent Document 2).
　上記Ｇｅ２Ｔｅ２薄膜とＧｅ２Ｔｅ２薄膜とからなる超格子を記録層に用いた固体メモリでは、Ｇｅ２Ｔｅ２層内にあるＧｅ原子をＳｂ２Ｔｅ３層との界面に拡散させることにより結晶状態と同様の構造を、「異方性をもった結晶」として形成することが可能であり、上記「異方性をもった結晶」状態を、例えば記録状態（一般的にＳｅｔ状態とも呼ばれる）に割り当てる。 In the solid-state memory using a superlattice consisting of the Ge 2 Te 2 thin film and the Ge 2 Te 2 thin film in the recording layer, by diffusing Ge atoms in the Ge 2 Te 2 layer in the interface between the Sb 2 Te 3 layer Thus, a structure similar to the crystal state can be formed as an “anisotropic crystal”, and the above “crystal with anisotropy” state can be changed to, for example, a recorded state (generally, the Set state). Assigned).
　また、逆に界面に拡散されたＧｅ原子を元々のＧｅ２Ｔｅ２層内に戻すことによって、上記超格子からなる記録層は、従来のＧｅ２Ｓｂ２Ｔｅ５合金においてアモルファス状態と呼ばれてきた構造と同等の電気抵抗値をもつ「アモルファスに類似した構造」に戻る。この「アモルファスに類似した構造」状態を、例えば消去状態（一般的にＲｅｓｅｔ状態とも呼ばれる）に割り当てる。 On the contrary, the recording layer made of the superlattice has been called an amorphous state in the conventional Ge 2 Sb 2 Te 5 alloy by returning Ge atoms diffused at the interface into the original Ge 2 Te 2 layer. It returns to the “structure similar to amorphous” having the same electrical resistance value as the structure. This “structure similar to amorphous” state is assigned to, for example, an erased state (generally called a Reset state).
　上記のように、本発明者らは、Ｇｅ２Ｔｅ２薄膜とＳｂ２Ｔｅ３薄膜とからなる超格子構造の記録層を用いることにより、これまでの固体メモリの特性を大幅に改善できる新しい固体メモリを提供している（特許文献２）。 As described above, the present inventors have developed a new solid state that can greatly improve the characteristics of a conventional solid memory by using a recording layer having a superlattice structure composed of a Ge 2 Te 2 thin film and an Sb 2 Te 3 thin film. A memory is provided (Patent Document 2).
　一方で、希少金属であるアンチモン（Ｓｂ）フリーである固体メモリを実現したいとの要望がある。Ｓｂフリーな固体メモリを実現するために、Ｇｅ－Ｓｂ－Ｔｅ系合金に代わって注目を集めているのがＧｅ－Ｃｕ－Ｔｅ系合金である（例えば、非特許文献３）。上記Ｇｅ－Ｃｕ－Ｔｅ系合金のなかでは、Ｇｅ２Ｔｅ２とＣｕＴｅ２との共晶組成であること、結晶相転移温度が２００℃以上と高くデータの高温保存性に優れている、などの理由からＧｅＣｕ２Ｔｅ３合金が特に期待されている。 On the other hand, there is a desire to realize a solid memory that is free of antimony (Sb), which is a rare metal. In order to realize an Sb-free solid-state memory, a Ge—Cu—Te alloy is attracting attention in place of the Ge—Sb—Te alloy (for example, Non-Patent Document 3). Among the Ge—Cu—Te alloys, the composition is a eutectic composition of Ge 2 Te 2 and CuTe 2 , the crystal phase transition temperature is as high as 200 ° C. or more, and the high temperature storage stability is excellent. For this reason, GeCu 2 Te 3 alloy is particularly expected.
日本国公開特許公報「特開２００２－２０３３９２号公報（２００２年７月１９日公開）」Japanese Patent Publication “Japanese Patent Laid-Open No. 2002-203392 (published on July 19, 2002)” 日本国公開特許公報「特開２００９－５９９０２号公報（２００９年３月１９日公開）」Japanese Patent Publication “JP 2009-59902 A (published on March 19, 2009)”
　しかし、ＧｅＣｕ２Ｔｅ３合金はアモルファス状態の抵抗値が従来のＧｅ２Ｓｂ２Ｔｅ５合金と比較して一桁小さく、結晶状態との抵抗値との差が二桁程度と小さい欠点をもつ。 However, the GeCu 2 Te 3 alloy has a drawback that the resistance value in the amorphous state is an order of magnitude smaller than that of the conventional Ge 2 Sb 2 Te 5 alloy, and the difference from the resistance value in the crystalline state is as small as about two orders of magnitude.
　上記抵抗値の比が小さい場合、固体メモリの再生時に得られる電圧信号の差が小さくなり、実用に足る信号／ノイズ比を得るためには、再生時の駆動電流を大きくする必要がある。上記駆動電流の増大は、消費電力の増大、ジュール熱の増大に伴う温度上昇、記録層を構成する物質の溶融あるいは融解、および、それに伴う組成比の異なる化合物の偏析など、固体メモリにさまざまな悪影響を与える。 When the ratio of the resistance values is small, the difference between the voltage signals obtained at the time of reproducing the solid-state memory becomes small, and in order to obtain a practical signal / noise ratio, it is necessary to increase the driving current at the time of reproduction. The above drive current increases in various ways in solid-state memory, such as increased power consumption, temperature rise with increased Joule heat, melting or melting of the material constituting the recording layer, and segregation of compounds with different composition ratios associated therewith. Adversely affected.
　また、記録層にＧｅ－Ｃｕ－Ｔｅ系合金を用いた固体メモリにおいて、繰り返し記録消去の回数においても、Ｇｅ２Ｓｂ２Ｔｅ５合金、もしくはＧｅ２Ｔｅ２とＳｂ２Ｔｅ３とからなる超格子を記録層に用いた固体メモリにはおよばないのが現状である。 Further, in a solid-state memory using a Ge—Cu—Te-based alloy for the recording layer, the superlattice made of Ge 2 Sb 2 Te 5 alloy or Ge 2 Te 2 and Sb 2 Te 3 can be used for repeated recording and erasing. The current situation is that it does not reach a solid-state memory using a recording layer.
　上記のことをふまえて、本発明は、相変化に伴う抵抗値の変化が十分にあり、繰り返し記録消去の回数もＧｅ－Ｓｂ－Ｔｅ系の固体メモリと遜色のないＳｂフリーな固体メモリを提供することを目的とする。 Based on the above, the present invention provides an Sb-free solid memory in which the resistance value changes sufficiently with the phase change, and the number of repeated recording / erasing operations is similar to that of a Ge—Sb—Te solid memory. The purpose is to do.
　本発明に係る固体メモリは、上記課題を解決するために、物質の相変化に起因して電気特性が変化する記録層を備えた固体メモリであって、前記記録層が、ゲルマニウムとテルルとから形成されている薄膜、および、銅とテルルとから形成されている薄膜が積層されてなる超格子によって構成されていることを特徴としている。 In order to solve the above problems, a solid-state memory according to the present invention is a solid-state memory including a recording layer whose electrical characteristics change due to a phase change of a substance, and the recording layer includes germanium and tellurium. It is characterized by being constituted by a superlattice formed by laminating a thin film formed and a thin film formed of copper and tellurium.
　このように、本発明に係る固体メモリでは、Ｇｅ－Ｓｂ－Ｔｅ系の固体メモリと遜色のない性能を有するＳｂフリーな固体メモリを提供するために、固体メモリの記録層として、ゲルマニウム（Ｇｅ）とテルル（Ｔｅ）とからなる薄膜（以下、Ｇｅ－Ｔｅ系薄膜とする）、および、銅（Ｃｕ）とＴｅとから形成される薄膜（以下、Ｃｕ－Ｔｅ系薄膜）の超格子構造を用いる。これにより、後述する実施例に示すように、Ｓｂフリーでありながら、非特許文献３に記載の技術とは異なり、相変化に伴う電気抵抗値の変化を十分な大きさにすることができるとともに、単純なＧｅ－Ｃｕ－Ｔｅ系の合金薄膜を記録層に用いた固体メモリと比較して、著しい性能の向上を実現することができる。たとえば、Ｇｅ－Ｔｅ系薄膜とＣｕ－Ｔｅ系薄膜とからなる超格子構造の相変化に伴う体積変化は、後述する実施例に示すように、極めて小さい。上記相変化に伴う体積変化は、データの記録、および消去の繰り返し時に、記録層を取り巻く上下に配置された電極などの構造体に力学的な応力を与える。上記応力が繰り返し固体メモリに加えられることにより、固体メモリには各層界面での剪断や剥離等が生じ破壊される。したがって、相変化に伴う体積変化が極めて小さいことは、データ記録消去の繰り返し寿命を延ばすことに寄与する。 As described above, in the solid-state memory according to the present invention, germanium (Ge) is used as a recording layer of the solid-state memory in order to provide an Sb-free solid-state memory having performance comparable to that of a Ge—Sb—Te solid-state memory. And a superlattice structure of a thin film made of copper and tellurium (Te) (hereinafter referred to as Ge—Te thin film) and a thin film formed of copper (Cu) and Te (hereinafter referred to as Cu—Te thin film). . As a result, as shown in the examples described later, while being Sb-free, unlike the technique described in Non-Patent Document 3, it is possible to make the change in the electrical resistance value accompanying the phase change sufficiently large. Compared with a solid-state memory using a simple Ge—Cu—Te alloy thin film as a recording layer, a significant improvement in performance can be realized. For example, the volume change accompanying the phase change of the superlattice structure composed of a Ge—Te-based thin film and a Cu—Te-based thin film is extremely small as shown in the examples described later. The volume change accompanying the phase change gives mechanical stress to a structure such as an electrode disposed above and below the recording layer when data recording and erasing are repeated. When the stress is repeatedly applied to the solid-state memory, the solid-state memory is destroyed due to shearing or peeling at each layer interface. Therefore, the extremely small volume change accompanying the phase change contributes to extending the repeated life of data recording and erasing.
　以上のように、本発明によれば、Ｇｅ－Ｓｂ－Ｔｅ系の固体メモリと遜色のない性能を有するＳｂフリーな固体メモリを提供することができる。 As described above, according to the present invention, it is possible to provide an Sb-free solid memory having performance comparable to that of a Ge—Sb—Te solid memory.
　本発明の他の目的、特徴、および優れた点は、以下に示す記載によって十分分かるであろう。また、本発明の利点は、添付図面を参照した次の説明で明白になるであろう。 Other objects, features, and superior points of the present invention will be fully understood from the following description. The advantages of the present invention will become apparent from the following description with reference to the accompanying drawings.
　本発明によれば、Ｓｂフリーでありながら、相変化を伴う固体メモリとして十分な大きさの電気抵抗値の変化を確保し、データの繰り返し記録消去の回数も１０１１回に達する固体メモリを提供することができる。これらは、Ｇｅ－Ｓｂ－Ｔｅ系合金を記録層に用いた固体メモリと比較して、遜色のない性能を有する。 According to the present invention, while being Sb-free, ensuring the change is large enough electrical resistance value of the solid-state memory with a phase change, a solid-state memory also the number of repeated recording erasing data reaching 10 11 times can do. These have performance comparable to that of a solid-state memory using a Ge—Sb—Te alloy as a recording layer.
本発明の一実施形態に係る固体メモリの記録層を構成する、Ｇｅ２Ｔｅ２薄膜とＣｕＴｅ２薄膜とからなる超格子の結晶構造を示す図である。（ａ）は結晶相Ａの結晶構造を示し、（ｂ）は結晶相Ｂの結晶構造を示す。Constituting the recording layer of the solid-state memory according to one embodiment of the present invention, showing the crystal structure of a superlattice consisting of Ge 2 Te 2 thin film and CuTe 2 thin film. (A) shows the crystal structure of crystal phase A, and (b) shows the crystal structure of crystal phase B. （ａ）は本発明の一実施形態に係る超格子からなる記録層を用いた固体メモリの概略を示す断面図である。（ｂ）は記録層を構成するＧｅ２Ｔｅ２薄膜とＣｕＴｅ２薄膜とからなる超格子の概略を示す断面図である。(A) is sectional drawing which shows the outline of the solid-state memory using the recording layer which consists of a superlattice based on one Embodiment of this invention. (B) is a cross-sectional view schematically showing a superlattice composed of a Ge 2 Te 2 thin film and a CuTe 2 thin film constituting a recording layer. Ｇｅ２Ｃｕ１Ｔｅ４合金からなる記録層を用いた固体メモリの概略を示す断面図である。Ge is a sectional view showing a 2 Cu 1 Te 4 schematically solid memory using the recording layer made of an alloy.
　以下、本発明に係る固体メモリの一実施形態について、図１～図３を参照して説明する。なお、以下に記述する実施の形態は、本発明の一例に過ぎず、本発明はこれらによって何ら限定されるものではない。 Hereinafter, an embodiment of a solid-state memory according to the present invention will be described with reference to FIGS. The embodiment described below is merely an example of the present invention, and the present invention is not limited by these.
　〔１．記録層について〕
　希少金属であるアンチモン（Ｓｂ）フリーな固体メモリを実現するために、本発明に係る固体メモリの記録層には、Ｇｅ－Ｔｅ系合金膜と、Ｃｕ－Ｔｅ系合金膜とによって構成される超格子構造を用いる。図１は、Ｇｅ－Ｔｅ系合金膜の一例としてＧｅ２Ｔｅ２層４を、Ｃｕ－Ｔｅ系合金膜の一例としてＣｕＴｅ２層５を、それぞれ用いた場合の超格子構造を示す図である。図１に示す超格子構造は、第一原理計算を用いて決定された構造であり、Ｇｅ２Ｔｅ２層４、およびＣｕＴｅ２層５の膜厚は、それぞれ０．７７ｎｍ、および０．５４ｎｍである。 [1. (Recording layer)
In order to realize an antimony (Sb) -free solid memory that is a rare metal, the recording layer of the solid memory according to the present invention includes a superstructure composed of a Ge—Te alloy film and a Cu—Te alloy film. A lattice structure is used. FIG. 1 is a diagram showing a superlattice structure when a Ge 2 Te 2 layer 4 is used as an example of a Ge—Te based alloy film and a CuTe 2 layer 5 is used as an example of a Cu—Te based alloy film. The superlattice structure shown in FIG. 1 is a structure determined using first-principles calculations. The film thicknesses of Ge 2 Te 2 layer 4 and CuTe 2 layer 5 are 0.77 nm and 0.54 nm, respectively. is there.
　本明細書において、超格子とは、複数の種類の結晶薄膜を規則正しく積層することによって、人工的に作られた長周期構造を有する結晶格子である。また、超格子構造とは、このような結晶格子の構造を意味する。 In this specification, a superlattice is a crystal lattice having a long-period structure artificially formed by regularly laminating a plurality of types of crystal thin films. The superlattice structure means such a crystal lattice structure.
　なお、超格子を作製する上で、Ｔｅに対するＧｅの原子数の比は、小さい方がより好ましく、Ｇｅ－Ｔｅ系合金膜中における全原子数に対するＧｅ原子数の比は、０より大きく０．５以下であることがより好ましい。また、超格子を作製する上で、Ｃｕ－Ｔｅ系合金膜中における全原子数に対するＣｕ原子数の比は、０より大きく０．５以下であることがより好ましく、０．２以上０．４以下であることがさらに好ましく、Ｃｕ－Ｔｅ系合金膜としてＣｕＴｅ２膜を用いることが特に好ましい。 It is to be noted that when the superlattice is formed, the ratio of the number of Ge atoms to Te is more preferably smaller, and the ratio of the number of Ge atoms to the total number of atoms in the Ge—Te-based alloy film is greater than 0 and less than 0.00. More preferably, it is 5 or less. Further, in producing a superlattice, the ratio of the number of Cu atoms to the total number of atoms in the Cu—Te-based alloy film is more preferably greater than 0 and less than or equal to 0.5, and more preferably between 0.2 and 0.4. The following is more preferable, and it is particularly preferable to use a CuTe 2 film as the Cu—Te-based alloy film.
　Ｇｅ原子１とＴｅ原子２とからなるＧｅ２Ｔｅ２層４、および、Ｔｅ原子２とＣｕ原子３とからなるＣｕＴｅ２層５の積層構造によって構成される超格子は、２つの安定した構造である構造Ａ（図１の（ａ））と構造Ｂ（図１の（ｂ））とを持つ双安定性を有している。 A superlattice composed of a stacked structure of a Ge 2 Te 2 layer 4 composed of Ge atoms 1 and Te atoms 2 and a CuTe 2 layer 5 composed of Te atoms 2 and Cu atoms 3 has two stable structures. It has bistability with a certain structure A (FIG. 1A) and structure B (FIG. 1B).
　本発明の一実施形態に係る固体メモリは、上記記録層における構造Ａ－構造Ｂ間の相変化を利用することによって固体メモリとして機能する。構造Ａと構造Ｂとでは、Ｇｅ２Ｔｅ２層４内のＧｅ層とＴｅ層との位置が入れ替わっている。また、ＧｅＴｅ層同士の間隔がわずかに異なっており、構造Ｂは構造Ａより上記間隔が広い。 The solid-state memory according to an embodiment of the present invention functions as a solid-state memory by utilizing the phase change between the structure A and the structure B in the recording layer. In the structure A and the structure B, the positions of the Ge layer and the Te layer in the Ge 2 Te 2 layer 4 are interchanged. Further, the intervals between the GeTe layers are slightly different, and the interval of the structure B is wider than that of the structure A.
　本発明の一実施形態に係る固体メモリにおいては、構造Ａから構造Ｂへ、または、構造Ｂから構造Ａへの相変化、すなわちＧｅＴｅ層の移動を、電気エネルギー手段によって起こすことができる。図１の（ａ）、および（ｂ）から分かるように、相変化に伴うＧｅＴｅ層の動きは一方向（基板表面に対して垂直方向）であり、コヒーレント性を持つといえる。そのため、入力したエネルギーを効率良く相変化に利用することが可能であり、その結果、相変化を起こすために必要なエネルギーが少なくてすむという利点を持つ。 In the solid-state memory according to an embodiment of the present invention, the phase change from the structure A to the structure B or from the structure B to the structure A, that is, the movement of the GeTe layer can be caused by electric energy means. As can be seen from FIGS. 1A and 1B, the movement of the GeTe layer accompanying the phase change is unidirectional (perpendicular to the substrate surface) and can be said to have coherency. Therefore, it is possible to efficiently use the input energy for the phase change, and as a result, there is an advantage that less energy is required to cause the phase change.
　また、後述するように、本発明の一実施形態に係る固体メモリでは、相変化に伴う体積変化を非常に小さくすることができるともに、記録層の相変化に伴う抵抗値の変化を３桁と十分に大きなものとすることができる。 As will be described later, in the solid-state memory according to the embodiment of the present invention, the volume change accompanying the phase change can be made extremely small, and the change in the resistance value accompanying the phase change of the recording layer can be 3 digits. It can be large enough.
　また、第一原理計算の結果より、Ｇｅ２Ｔｅ２層４とＣｕＴｅ２層５とからなる超格子構造では、Ｇｅの結合原子価が構造Ａでは４価をとる（図１の（ａ））に対し、構造Ｂでは６価をとる（図１の（ｂ））ことがわかった。Ｇｅの結合価数が４価から６価へ変化するのは、相変化にともない互いにＧｅ層とＴｅ層とが入れ替わることにより、ＣｕＴｅ２層５との距離が近づきＧｅ－Ｔｅ間に結合が生じるためである。なお、図１は、Ｇｅ２Ｔｅ２薄膜４とＣｕＴｅ２薄膜５とからなる超格子の基本セルの構造を示す図である。Ｇｅ原子１が６価となることによって、基板表面に対して垂直方向の電気特性が金属的になり、抵抗値が著しく減少する。これにより、固体メモリとしてさらに好適に、相変化時の抵抗値の変化を大きくすることができる。 Further, from the result of the first principle calculation, in the superlattice structure composed of the Ge 2 Te 2 layer 4 and the CuTe 2 layer 5, the bond valence of Ge is tetravalent in the structure A ((a) in FIG. 1). On the other hand, it was found that the structure B is hexavalent ((b) in FIG. 1). The bond valence of Ge changes from tetravalent to hexavalent because the Ge layer and the Te layer are interchanged with each other in accordance with the phase change, and the distance between the CuTe 2 layer 5 becomes closer and a bond is formed between Ge and Te. Because. FIG. 1 is a diagram showing the structure of a basic cell of a superlattice composed of a Ge 2 Te 2 thin film 4 and a CuTe 2 thin film 5. When the Ge atom 1 becomes hexavalent, electrical characteristics in the direction perpendicular to the substrate surface become metallic, and the resistance value is significantly reduced. Thereby, the change of the resistance value at the time of phase change can be increased more preferably as a solid-state memory.
　よって、記録層の抵抗値の大小に対して、データの記録、および消去状態のどちらか一方を割り当てることが可能である。また、記録層の抵抗値を測定することによって、記録層がデータの記録、および消去状態のどちらにあるか判別すること、すなわち記録したデータの再生が可能である。 Therefore, it is possible to assign either data recording or erasing state to the resistance value of the recording layer. Further, by measuring the resistance value of the recording layer, it is possible to determine whether the recording layer is in the data recording or erasing state, that is, the recorded data can be reproduced.
　また、構造Ａと構造Ｂとでは、電気的な特性だけでなく光学的な特性においても大きく異なるので、記録したデータの再生手段として、光学的な手法を用いることも可能である。 In addition, since the structure A and the structure B are greatly different not only in electrical characteristics but also in optical characteristics, it is possible to use an optical technique as a means for reproducing recorded data.
　なお、相変化を誘起するための電気エネルギー手段としては、例えば、パルス状の電流を流すことが利用できる。この際に流すパルス電流の電流値、および電流を流す時間（以下ではパルス時間とする）を調整することにより、構造Ａ、および構造Ｂ間の相変化を任意に繰り返すことが可能である。このことを利用して、本発明の一実施形態に係る固体メモリでは、データの記憶、および消去を行う。 In addition, as an electric energy means for inducing a phase change, for example, a pulsed current can be used. The phase change between the structure A and the structure B can be arbitrarily repeated by adjusting the current value of the pulse current flowing at this time and the time (hereinafter referred to as pulse time) for flowing the current. By utilizing this fact, the solid-state memory according to the embodiment of the present invention stores and erases data.
　〔２．固体メモリの構成〕
　本発明に係る固体メモリの構成の一例について、以下に説明する。なお、本発明に係る固体メモリの構成は以下のものに限定されるものではない。 [2. (Structure of solid-state memory)
An example of the configuration of the solid-state memory according to the present invention will be described below. The configuration of the solid-state memory according to the present invention is not limited to the following.
　図２の（ａ）は、Ｇｅ２Ｔｅ２薄膜４とＣｕＴｅ２薄膜５とからなる超格子薄膜を記録層１１として用いた固体メモリ１０の概略を示す断面図である。また、記録層１１の概略の拡大図を図２の（ｂ）に示す。 FIG. 2A is a cross-sectional view schematically showing a solid-state memory 10 using a superlattice thin film composed of a Ge 2 Te 2 thin film 4 and a CuTe 2 thin film 5 as a recording layer 11. A schematic enlarged view of the recording layer 11 is shown in FIG.
　上記固体メモリ１０において、記録層１１は上部電極１４、およびジュール熱発生用ヒーター１５に狭持されている。さらに、上部電極１４は読み出し線１３と、ジュール熱発生用ヒーター１５は書き込み線１６と、それぞれ電気的に接触している。すなわち、ジュール熱発生用ヒーター１５はヒーターとしての役割とともに、下部電極の役割を兼ねている。 In the solid-state memory 10, the recording layer 11 is sandwiched between the upper electrode 14 and the Joule heat generating heater 15. Further, the upper electrode 14 is in electrical contact with the read line 13 and the Joule heat generating heater 15 is in electrical contact with the write line 16, respectively. That is, the Joule heat generating heater 15 serves as a lower electrode as well as a heater.
　また、上記構造Ａ、および構造Ｂの間において相変化を起こすために、電気エネルギー手段として電流を用いることを上述したが、その経路を電流経路２０とする。前記電流経路２０に電流を流すことによって、ジュール熱発生用ヒーター１５においてジュール熱が発生し記録層１１は加熱されその温度は上昇する。 Moreover, in order to cause a phase change between the structure A and the structure B, as described above, the current is used as the electric energy means. By passing a current through the current path 20, Joule heat is generated in the Joule heat generation heater 15, the recording layer 11 is heated, and the temperature rises.
　記録層１１に印加する電流値、およびパルス時間を制御することによって、記録層１１の温度を制御し上記構造Ａ、および構造Ｂの間における相変化の繰り返しを可能とする。 By controlling the current value applied to the recording layer 11 and the pulse time, the temperature of the recording layer 11 is controlled, and the phase change between the structure A and the structure B can be repeated.
　〔３．固体メモリの作製方法〕
　本発明の一実施形態に係る固体メモリの作製方法の一例を、図２を参照しながら以下に説明する。図２は、Ｇｅ２Ｔｅ２薄膜４とＣｕＴｅ２薄膜５とからなる超格子薄膜を記録層１１として用いた固体メモリの概略を示す断面図である。 [3. Manufacturing method of solid-state memory]
An example of a method for manufacturing a solid-state memory according to an embodiment of the present invention will be described below with reference to FIG. FIG. 2 is a cross-sectional view schematically showing a solid-state memory using a superlattice thin film composed of a Ge 2 Te 2 thin film 4 and a CuTe 2 thin film 5 as a recording layer 11.
　本発明の一実施形態に係る固体メモリは、例えば、一般的な自己抵抗加熱型の構成を有している相変化ＲＡＭとして形成することができる（例えば、特許文献１）。上記一般的な構成に従って、基板／書き込み線／ジュール熱発生用ヒーター／記録層／上部電極／読み出し線という構成によって相変化ＲＡＭを作製する場合、基板上に書き込み線１６、ジュール熱発生用ヒーター１５、記録層１１、上部電極１４、および読み出し線１３を順次成膜すればよい。この際の成膜方法としては、例えばスパッタリング法などの一般的な成膜方法が使用可能である。以下に、固体メモリの作製方法の一例を示す。 The solid-state memory according to an embodiment of the present invention can be formed as, for example, a phase change RAM having a general self-resistance heating type configuration (for example, Patent Document 1). In the case where a phase change RAM is manufactured by the configuration of the substrate / write line / joule heat generation heater / recording layer / upper electrode / read line according to the above general configuration, the write line 16 and the Joule heat generation heater 15 are formed on the substrate. The recording layer 11, the upper electrode 14, and the readout line 13 may be sequentially formed. As a film forming method at this time, for example, a general film forming method such as a sputtering method can be used. An example of a method for manufacturing a solid-state memory is described below.
　基板にはシリコン（Ｓｉ）ウェハを用い、スパッタリング法により書き込み線１６、およびジュール熱発生用ヒーター１５を成膜する。ジュール熱発生用ヒーターには例えば、タングステンを用いることができる。 A silicon (Si) wafer is used as a substrate, and a writing line 16 and a Joule heat generating heater 15 are formed by sputtering. For example, tungsten can be used for the Joule heat generation heater.
　次に、記録層に用いるＧｅ－Ｔｅ系合金膜と、Ｃｕ－Ｔｅ系合金膜との超格子をスパッタリング法にて成膜する。その場合、所望の化合物（たとえば、Ｇｅ２Ｔｅ２およびＣｕＴｅ２）を成膜可能なターゲットを用意する。 Next, a superlattice of a Ge—Te alloy film and a Cu—Te alloy film used for the recording layer is formed by sputtering. In that case, a target capable of forming a desired compound (for example, Ge 2 Te 2 and CuTe 2 ) is prepared.
　超格子構造を作製するためには、あらかじめ各化合物について、単位時間あたりの成膜される膜厚を測定し、成膜レートを確定しておく必要がある。各化合物の成膜レートが確定していれば、それぞれの化合物の成膜時間を制御することによって、任意の周期構造を有する超格子構造を実現することが可能である。 In order to produce a superlattice structure, it is necessary to determine the film formation rate by measuring the film thickness formed per unit time in advance for each compound. If the film formation rate of each compound is determined, a superlattice structure having an arbitrary periodic structure can be realized by controlling the film formation time of each compound.
　上記方法によって、任意の周期構造、および任意の積層数を有する記録層を成膜した後、例えば、タングステンからなる上部電極１４および読み出し線１３を成膜することによって、相変化ＲＡＭが完成する。 After forming a recording layer having an arbitrary periodic structure and an arbitrary number of layers by the above method, for example, an upper electrode 14 and a readout line 13 made of tungsten are formed to complete the phase change RAM.
　なお、超格子構造を構成するＧｅ－Ｔｅ系薄膜、およびＣｕ－Ｔｅ系薄膜の膜厚は、０．５ｎｍ以上、８ｎｍ以下であることが望ましい。この範囲の膜厚にすることによって、上記各薄膜の結晶構造が乱れることなく、超格子構造を好適に実現することが出来る。 Note that the film thickness of the Ge—Te thin film and the Cu—Te thin film constituting the superlattice structure is desirably 0.5 nm or more and 8 nm or less. By setting the film thickness within this range, a superlattice structure can be suitably realized without disturbing the crystal structure of each thin film.
　また、電極、および記録層などのパターニングには一般的なフォトリソグラフィープロセスを用いることが出来る。 Further, a general photolithography process can be used for patterning of the electrode and the recording layer.
　なお、本発明は、以下のように表現することも可能である。 The present invention can also be expressed as follows.
　（構成１）ＣｕとＧｅおよびＴｅを主成分とする固体メモリであって、物質の相変態に起因して電気特性が変化するものであり、データを記録及び再生する材料が、該相変態を生じる母相からなる薄膜の人工的な超格子構造の積層構造によって構成されることを特徴とする固体メモリ。 (Configuration 1) A solid-state memory mainly composed of Cu, Ge, and Te, whose electrical characteristics change due to a phase transformation of a substance, and a material for recording and reproducing data exhibits the phase transformation. A solid-state memory comprising a laminated structure of an artificial superlattice structure of a thin film composed of a parent phase.
　（構成２）構成１の固体メモリにおいて、前記積層構造は、Ｇｅ原子を含むＴｅ合金薄膜と、Ｃｕ原子を含むＴｅ合金薄膜とが互いに積層された多層膜から構成されることを特徴とする固体メモリ。 (Structure 2) In the solid-state memory according to Structure 1, the stacked structure is formed of a multilayer film in which a Te alloy thin film containing Ge atoms and a Te alloy thin film containing Cu atoms are stacked on each other. memory.
　（構成３）構成１又は構成２の固体メモリにおいて、前記薄膜のそれぞれの膜厚は、０．５ｎｍ以上８ｎｍ以下であることを特徴とする固体メモリ。 (Configuration 3) Solid memory according to Configuration 1 or Configuration 2, wherein each thin film has a thickness of 0.5 nm or more and 8 nm or less.
　（構成４）構成２の固体メモリにおいて、前記Ｇｅ原子を含む合金薄膜においてＧｅ原子の結合原子価が４価または６価の状態をとることで電気抵抗を変化させ、結合原子価の相違によって得られる二つの抵抗値をデータの記録および消去状態のどちらか一方に用いることを特徴とする固体メモリ。 (Configuration 4) In the solid-state memory of Configuration 2, the electrical resistance is changed by taking the bond valence of Ge atoms in a tetravalent or hexavalent state in the alloy thin film containing Ge atoms, and obtained by the difference in bond valences. A solid-state memory characterized in that two resistance values obtained are used for either recording or erasing of data.
　（構成５）構成２の固体メモリにおいて、前記Ｇｅ原子を含むＴｅ合金薄膜の全原子数に対するＧｅ原子数の比が０．５以下であることを特徴とする固体メモリ。 (Configuration 5) The solid-state memory according to Configuration 2, wherein the ratio of the number of Ge atoms to the total number of atoms of the Te alloy thin film containing Ge atoms is 0.5 or less.
　（構成６）構成２の固体メモリにおいて、前記Ｃｕ原子を含むＴｅ合金薄膜の全原子数に対するＣｕ原子数の比が０．５以下であることを特徴とする固体メモリ。 (Configuration 6) The solid-state memory according to Configuration 2, wherein the ratio of the number of Cu atoms to the total number of atoms of the Te alloy thin film containing Cu atoms is 0.5 or less.
　以上、本発明を実施形態に基づいて具体的に説明したが、本発明は、上述した実施形態に限定されるものではなく、請求項に示した範囲において種々の変更が可能であり、異なる実施形態にそれぞれ開示された技術的手段を適宜組み合わせて得られる実施形態についても本発明の技術的範囲に含まれる。 The present invention has been specifically described above based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the claims, and different implementations are possible. Embodiments obtained by appropriately combining the technical means disclosed in each form are also included in the technical scope of the present invention.
　本発明は、以下の実施例によってさらに詳細に説明されるが、これに限定されるべきではない。 The present invention will be described in more detail by the following examples, but should not be limited thereto.
　〔実施例１〕
　記録層に用いる超格子の結晶構造や諸特性は、固体メモリの性能（相変化に伴う抵抗値の変化、必要とされる駆動電流値、および繰り返し記録消去を行える回数など）に大きな影響を及ぼすので非常に重要である。上述した構造Ａおよび構造Ｂの超格子を作製し、以下に示す特性を有することを確認した。 [Example 1]
The crystal structure and various characteristics of the superlattice used for the recording layer have a significant effect on the performance of solid-state memory (change in resistance value due to phase change, required drive current value, and the number of times recording can be repeatedly erased, etc.) So very important. The superlattices of the structure A and the structure B described above were fabricated and confirmed to have the following characteristics.
　Ｇｅ２Ｔｅ２層４とＣｕＴｅ２層５とからなる超格子は、電気的なエネルギーを加えることによって、構造Ａ－構造Ｂ間で相変化を起こす（図１参照）。すなわち上記超格子は、与えられるエネルギーに応じて、双安定である構造Ａ、または構造Ｂのうち一方を選択する。そして、加えるエネルギーは電気的なものに限られず、熱エネルギーを用いて超格子構造を選択することも可能である。 The superlattice composed of the Ge 2 Te 2 layer 4 and the CuTe 2 layer 5 causes a phase change between the structure A and the structure B by applying electrical energy (see FIG. 1). That is, the superlattice selects one of the structure A or the structure B that is bistable in accordance with the applied energy. The energy to be applied is not limited to electrical energy, and it is also possible to select a superlattice structure using thermal energy.
　ここでは、加える熱エネルギーの違いを利用して構造Ａおよび構造Ｂの超格子薄膜を成膜した。異なる基板温度のＳｉウェハ上に、スパッタリング法を用いてＧｅ２Ｔｅ２層４とＣｕＴｅ２層５とからなる膜厚が約４０ｎｍの超格子薄膜を成膜し、結晶構造、電気特性、および光学特性を比較した。成膜時の基板温度は、それぞれ１５０℃、および２５０℃であり、以下ではそれぞれをサンプルａおよびサンプルｂと呼ぶ。 Here, the superlattice thin film of the structure A and the structure B was formed using the difference in applied thermal energy. A superlattice thin film having a film thickness of about 40 nm composed of Ge 2 Te 2 layer 4 and CuTe 2 layer 5 is formed on Si wafers having different substrate temperatures by sputtering, and the crystal structure, electrical characteristics, and optical properties are measured. The characteristics were compared. The substrate temperatures during film formation are 150 ° C. and 250 ° C., respectively, and are hereinafter referred to as sample a and sample b.
　それぞれの超格子薄膜についてＸ線構造解析を行った結果、サンプルａの面間隔は、第一原理計算から求められた構造Ａ（図１の（ａ））の面間隔とよく一致し、サンプルｂの面間隔は上記計算から求められた構造Ｂ（図１の（ｂ））の面間隔とよく一致することを確認した。 As a result of the X-ray structural analysis of each superlattice thin film, the surface spacing of the sample a is in good agreement with the surface spacing of the structure A (FIG. 1A) obtained from the first principle calculation. It was confirmed that the distance between the surfaces closely coincided with the distance between the surfaces of the structure B ((b) in FIG. 1) obtained from the above calculation.
　また両サンプルの抵抗値を、四端子プローブを用いて測定したところ、サンプルａは約５ＭΩであり、サンプルｂは３０ｋΩであった。このことから、構造Ａ－構造Ｂ間における相変化を相変化ＲＡＭに利用した場合、読み出し時の信号は約１７０倍の変化を示すことが確認できた。上記のように、Ｇｅ２Ｔｅ２層４とＣｕＴｅ２層５とからなる超格子は、相変化にともなう抵抗値の変化が３桁となるので、固体メモリの記録層として好適である。 Moreover, when the resistance value of both samples was measured using the four-terminal probe, the sample a was about 5 MΩ and the sample b was 30 kΩ. From this, it was confirmed that when the phase change between the structure A and the structure B is used for the phase change RAM, the signal at the time of reading shows a change of about 170 times. As described above, the superlattice composed of the Ge 2 Te 2 layer 4 and the CuTe 2 layer 5 is suitable as a recording layer of a solid-state memory because the change in the resistance value accompanying the phase change is three digits.
　光学特性を、波長６３３ｎｍのレーザーを用いてエリプソメーターにて測定したところ、サンプルａ（構造Ａ）は３．８１＋３．３９ｊ、またサンプルｂ（構造Ｂ）は３．３８＋４．３７ｊとの結果を得た。この結果より、構造Ｂは構造Ａと比べて複屈折率が０．９８大きく、より金属的な特性を有することがわかった。このことは、上記抵抗値測定の結果と矛盾しない。 When the optical characteristics were measured with an ellipsometer using a laser with a wavelength of 633 nm, the result was 3.81 + 3.39j for sample a (structure A) and 3.38 + 4.37j for sample b (structure B). It was. From this result, it was found that the structure B has a higher birefringence of 0.98 than the structure A, and has more metallic characteristics. This is consistent with the result of the resistance value measurement.
　また、第１原理計算を用いて求めた超格子構造から、次の２点も確認した。
・構造ＡにおいてはＧｅ２Ｔｅ２層４中のＧｅ原子１の結合価数が４価（図１の（ａ））であるのに対して、構造ＢのＧｅ原子１の結合価数が６価（図１の（ｂ））である。
・構造Ａ、および構造Ｂの密度は、それぞれ７．１０３ｇ／ｃｍ３、および７．１０４ｇ／ｃｍ３であり、構造Ａ－構造Ｂ間の相変化に伴う密度変化（体積変化）は０．０２％以下と非常に小さい。 In addition, the following two points were also confirmed from the superlattice structure obtained using the first principle calculation.
In structure A, the valence of Ge atom 1 in Ge 2 Te 2 layer 4 is tetravalent (FIG. 1A), whereas the valence of Ge atom 1 in structure B is 6 It is a value ((b) of FIG. 1).
- Structure A, and density of the structure B, respectively 7.103g / cm 3, and a 7.104g / cm 3, the density change accompanying the phase change between the structure A- structure B (volume change) is 0.02 % And very small.
　上記のように、Ｇｅ２Ｔｅ２層４とＣｕＴｅ２層５とからなる超格子は、相変化に伴う体積変化が非常に小さいので、記録、および消去の繰り返し回数の向上が期待できる。 As described above, the superlattice composed of the Ge 2 Te 2 layer 4 and the CuTe 2 layer 5 has a very small volume change due to the phase change, and therefore can be expected to improve the number of repetitions of recording and erasing.
　〔実施例２〕
　上記の一般的な自己抵抗加熱型の基本構成を用いて、本発明に係る固体メモリを作製した（図２）。基板にはＳｉウェハを使用し、ジュール熱発生用ヒーター１５、および上部電極１４にはタングステンを使用した。記録層１１としてはＧｅ２Ｔｅ２層４とＣｕＴｅ２層５とからなる単位格子を２０層積層した超格子薄膜を使用した。記録層１１の膜厚は２６ｎｍであった。また、記録層のセルの大きさは、１００×１００ｎｍ２とした。 [Example 2]
A solid-state memory according to the present invention was fabricated using the above-described general self-resistance heating type basic configuration (FIG. 2). A Si wafer was used for the substrate, and tungsten was used for the Joule heat generation heater 15 and the upper electrode 14. As the recording layer 11, a superlattice thin film in which 20 unit lattices composed of a Ge 2 Te 2 layer 4 and a CuTe 2 layer 5 were stacked was used. The film thickness of the recording layer 11 was 26 nm. The cell size of the recording layer was 100 × 100 nm 2 .
　この固体メモリの電流経路２０に、あらかじめプログラムにより決定した波形の電流を流して、情報の記録、および消去に必要な電流値、および電流を流すパルス時間を検討した。 The current value required for recording and erasing information and the pulse time for flowing the current were examined by passing a current having a waveform determined by a program in advance through the current path 20 of the solid-state memory.
　その結果、構造Ａから構造Ｂへ相変化させる際に必要な電流値は０．１ｍＡであり、パルス時間は１００ｎｓであった。一方、構造Ｂから構造Ａへ相変化させる際に必要な電流値は０．５ｍＡであり、パルス時間５０ｎｓであった。上記波形の電流を連続的に固体メモリに流すことによって、繰り返し記録消去回数を測定した。その結果、本実施例で用いた固体メモリでは、１０１１回の繰り返し記録消去が可能であった。
〔比較例〕
　記録層に超格子薄膜を用いた固体メモリと比較するために、実施例２と同様の構成を持ち、記録層１２としてＧｅ２Ｃｕ１Ｔｅ４合金の単層膜（膜厚　２６ｎｍ）を用いた固体メモリ１００を作製した（図３）。セルの大きさは、１００×１００ｎｍ２とした。 As a result, the current value required for the phase change from the structure A to the structure B was 0.1 mA, and the pulse time was 100 ns. On the other hand, the current value required for the phase change from the structure B to the structure A was 0.5 mA, and the pulse time was 50 ns. The current of the above waveform was continuously passed through the solid-state memory to repeatedly measure the number of recording / erasing. As a result, in the solid-state memory used in this example, it was possible to repeat recording and erasing of 10 11 times.
[Comparative Example]
In order to compare with a solid-state memory using a superlattice thin film as a recording layer, a single layer film (thickness: 26 nm) of Ge 2 Cu 1 Te 4 alloy having the same configuration as in Example 2 was used as the recording layer 12. A solid-state memory 100 was produced (FIG. 3). The cell size was 100 × 100 nm 2 .
　この固体メモリの電流経路２０に、あらかじめプログラムにより決定した波形の電流を流して、情報の記録、および消去に必要な電流値を検討した。なお、比較のため電流を流すパルス時間は、実施例２に記載したパルス時間と同じとした。 The current value required for recording and erasing information was examined by flowing a current having a waveform determined in advance by a program through the current path 20 of the solid-state memory. For comparison, the pulse time for supplying current was the same as the pulse time described in Example 2.
　その結果、結晶相Ａから結晶相Ｂへ相変化させる際に必要な電流値は０．３ｍＡであった。一方、結晶相Ｂから結晶相Ａへの電流値は１．９ｍＡであった。 As a result, the current value required for the phase change from the crystal phase A to the crystal phase B was 0.3 mA. On the other hand, the current value from the crystal phase B to the crystal phase A was 1.9 mA.
　ここで得られた電流値と、実施例２で用いたパルス時間を用いて連続波形をプログラミングし、その波形に基づいて相変化ＲＡＭに電流を流し、繰り返し記録消去回数を測定した。その結果、記録層１２としてＧｅ２Ｃｕ１Ｔｅ４合金の単層膜を用いた固体メモリの繰り返し記録消去回数は１０４回であった。 A continuous waveform was programmed using the current value obtained here and the pulse time used in Example 2, and a current was passed through the phase change RAM based on the waveform, and the number of times of recording and erasing was measured repeatedly. As a result, repeated recording number of times of erasing solid memory using a single layer film of Ge 2 Cu 1 Te 4 alloy as a recording layer 12 was 10 4 times.
　このように、記録層にＧｅ２Ｔｅ２層とＣｕＴｅ２層とからなる超格子薄膜を用いることにより、ＳｂフリーでありながらＧｅ－Ｓｂ－Ｔｅ系の固体メモリと遜色のない固体メモリを作成可能なことを確認した。 In this way, by using a superlattice thin film composed of a Ge 2 Te 2 layer and a CuTe 2 layer for the recording layer, it is possible to create a solid memory that is comparable to a Ge—Sb—Te solid memory while being Sb-free. I confirmed that.
　また、固体メモリの記録層をＧｅ２Ｃｕ１Ｔｅ４の単層膜からＧｅ２Ｔｅ２薄膜とＣｕＴｅ２薄膜とからなる超格子にすることによって、以下に示すように性能が向上することを確認した。
・相変化に伴う抵抗値の変化は１桁大きくなった。
・相変化を誘起するために必要な電流値は、構造Ａから構造Ｂへの相変化の場合で１／３に、構造Ｂから構造Ａへの相変化の場合で１／４に低減された。
・繰り返し記録消去回数は１０７倍になった。 In addition, it has been confirmed that the performance improves as shown below by changing the recording layer of the solid-state memory from a single layer film of Ge 2 Cu 1 Te 4 to a superlattice made of a Ge 2 Te 2 thin film and a CuTe 2 thin film. did.
・ The change in resistance value accompanying the phase change has increased by an order of magnitude.
The current value required to induce the phase change is reduced to １ ／ in the case of the phase change from the structure A to the structure B, and ¼ in the case of the phase change from the structure B to the structure A. .
• Repeat recording and erasing number of times became 10 seven times.
　本発明に係る固体メモリは、上記課題を解決するために、物質の相変化に起因して電気特性が変化する記録層を備えた固体メモリであって、前記記録層が、ゲルマニウムとテルルとから形成されている薄膜、および、銅とテルルとから形成されている薄膜が積層されてなる超格子によって構成されていることを特徴としている。 In order to solve the above problems, a solid-state memory according to the present invention is a solid-state memory including a recording layer whose electrical characteristics change due to a phase change of a substance, and the recording layer includes germanium and tellurium. It is characterized by being constituted by a superlattice formed by laminating a thin film formed and a thin film formed of copper and tellurium.
　このように、本発明に係る固体メモリでは、Ｇｅ－Ｓｂ－Ｔｅ系の固体メモリと遜色のない性能を有するＳｂフリーな固体メモリを提供するために、固体メモリの記録層として、ゲルマニウム（Ｇｅ）とテルル（Ｔｅ）とからなる薄膜（以下、Ｇｅ－Ｔｅ系薄膜とする）、および、銅（Ｃｕ）とＴｅとから形成される薄膜（以下、Ｃｕ－Ｔｅ系薄膜）の超格子構造を用いる。これにより、前述した実施例に示すように、Ｓｂフリーでありながら、非特許文献３に記載の技術とは異なり、相変化に伴う電気抵抗値の変化を十分な大きさにすることができるとともに、単純なＧｅ－Ｃｕ－Ｔｅ系の合金薄膜を記録層に用いた固体メモリと比較して、著しい性能の向上を実現することができる。たとえば、Ｇｅ－Ｔｅ系薄膜とＣｕ－Ｔｅ系薄膜とからなる超格子構造の相変化に伴う体積変化は、前述した実施例に示すように、極めて小さい。上記相変化に伴う体積変化は、データの記録、および消去の繰り返し時に、記録層を取り巻く上下に配置された電極などの構造体に力学的な応力を与える。上記応力が繰り返し固体メモリに加えられることにより、固体メモリには各層界面での剪断や剥離等が生じ破壊される。したがって、相変化に伴う体積変化が極めて小さいことは、データ記録消去の繰り返し寿命を延ばすことに寄与する。 As described above, in the solid-state memory according to the present invention, germanium (Ge) is used as a recording layer of the solid-state memory in order to provide an Sb-free solid-state memory having performance comparable to that of a Ge—Sb—Te solid-state memory. And a superlattice structure of a thin film made of copper and tellurium (Te) (hereinafter referred to as Ge—Te thin film) and a thin film formed of copper (Cu) and Te (hereinafter referred to as Cu—Te thin film). . Thus, as shown in the above-described embodiment, while being Sb-free, unlike the technique described in Non-Patent Document 3, it is possible to make the change in the electrical resistance value accompanying the phase change sufficiently large. Compared with a solid-state memory using a simple Ge—Cu—Te alloy thin film as a recording layer, a significant improvement in performance can be realized. For example, the volume change accompanying the phase change of the superlattice structure composed of a Ge—Te-based thin film and a Cu—Te-based thin film is extremely small as shown in the above-described embodiments. The volume change accompanying the phase change gives mechanical stress to a structure such as an electrode disposed above and below the recording layer when data recording and erasing are repeated. When the stress is repeatedly applied to the solid-state memory, the solid-state memory is destroyed due to shearing or peeling at each layer interface. Therefore, the extremely small volume change accompanying the phase change contributes to extending the repeated life of data recording and erasing.
　以上のように、本発明によれば、Ｇｅ－Ｓｂ－Ｔｅ系の固体メモリと遜色のない性能を有するＳｂフリーな固体メモリを提供することができる。 As described above, according to the present invention, it is possible to provide an Sb-free solid memory having performance comparable to that of a Ge—Sb—Te solid memory.
　本発明の一実施形態に係る固体メモリでは、前記ゲルマニウムとテルルとから形成されている薄膜は、Ｇｅ２Ｔｅ２薄膜であり、前記銅とテルルとから形成される薄膜は、ＣｕＴｅ２薄膜であることが好ましい。 In the solid-state memory according to an embodiment of the present invention, the thin film formed of germanium and tellurium is a Ge 2 Te 2 thin film, and the thin film formed of copper and tellurium is a CuTe 2 thin film. It is preferable.
　上記の構成によれば、上記記録層に、Ｇｅ２Ｔｅ２薄膜とおよびＣｕＴｅ２薄膜とからなる積層構造を用いることによって、下部電極上における格子欠陥や格子ひずみ等がより少ない、整った周期構造を有した超格子構造を好適に実現することができる。 According to the above configuration, in the recording layer, Ge by using 2 Te 2 thin film and and CuTe consisting of 2 thin film stack, fewer lattice defects and lattice distortion or the like on the lower electrode, equipped periodic structure A superlattice structure with can be suitably realized.
　本発明の一実施形態に係る固体メモリでは、前記薄膜の各々の膜厚は、０．５ｎｍ以上８ｎｍ以下であることが好ましい。 In the solid-state memory according to an embodiment of the present invention, it is preferable that each film thickness of the thin film is 0.5 nm or more and 8 nm or less.
　上記の構成によれば、積層構造の途中において周期構造が乱れることをより好適に防ぐことができる。これにより、積層数の如何に関わらず、超格子構造を有した記録層を首尾よく実現することができる。 According to the above configuration, it is possible to more suitably prevent the periodic structure from being disturbed in the middle of the laminated structure. Thereby, a recording layer having a superlattice structure can be successfully realized regardless of the number of stacked layers.
　本発明の一実施形態に係る固体メモリでは、前記ゲルマニウムとテルルとから形成されている薄膜は、前記ゲルマニウムの結合原子価が４価または６価の状態をとることによって電気抵抗値を変化させるようになっており、前記電気抵抗値によって、データの記録状態または消去状態を表現するようになっていることが好ましい。 In the solid-state memory according to an embodiment of the present invention, the thin film formed of germanium and tellurium may change its electric resistance value when the germanium has a tetravalent or hexavalent bond valence. It is preferable that the data recording state or the erasing state is expressed by the electric resistance value.
　上記の構成によれば、Ｇｅ－Ｔｅ系薄膜とＣｕ－Ｔｅ系薄膜とからなる超格子構造は双安定性を有しており、２種類の結晶構造をとることができる。上記２種類の結晶構造の差異は、主にＧｅ－Ｔｅ系薄膜層におけるＧｅＴｅ層同士の距離の違いであり、このことは、ＧｅＴｅ層とＣｕ－Ｔｅ層との層間距離にも影響を与える。 According to the above configuration, the superlattice structure composed of the Ge—Te-based thin film and the Cu—Te-based thin film has bistability and can take two types of crystal structures. The difference between the two types of crystal structures is mainly the difference in the distance between GeTe layers in the Ge—Te thin film layer, and this also affects the interlayer distance between the GeTe layer and the Cu—Te layer.
　上記Ｇｅ－Ｔｅ系薄膜層において、ＧｅＴｅ層同士が近い結晶構造の場合（図１の（ａ）参照）は、Ｇｅ原子の結合原子価は４価である。一方、上記Ｇｅ－Ｔｅ系薄膜層において、ＧｅＴｅ層同士が離れた結晶構造の場合（図１の（ｂ）参照）は、Ｇｅ原子の結合原子価は６価となる。 In the Ge—Te-based thin film layer, when the GeTe layers are close to each other in the crystal structure (see FIG. 1A), the bond valence of Ge atoms is tetravalent. On the other hand, when the Ge—Te-based thin film layer has a crystal structure in which the GeTe layers are separated from each other (see FIG. 1B), the bond valence of Ge atoms is hexavalent.
　以上のように、上記２種類の結晶構造における相変化は、基板面に対して垂直な方向におけるＧｅ原子の結合状態に影響を及ぼす。上記Ｇｅ－Ｔｅ系薄膜層のＧｅ原子が４価から６価に相変化することによって、上記超格子の基板に対して垂直方向の結合が強くなり、記録層の電気抵抗値は大きく減少する。 As described above, the phase change in the two types of crystal structures affects the bonding state of Ge atoms in the direction perpendicular to the substrate surface. When the Ge atoms of the Ge—Te-based thin film layer undergo a phase change from tetravalent to hexavalent, coupling in the direction perpendicular to the substrate of the superlattice becomes strong, and the electrical resistance value of the recording layer is greatly reduced.
　すなわち、上記Ｇｅ原子価が４価の場合は記録層の抵抗値が大きい状態、６価の場合は記録層の抵抗値が小さい状態に対応する。これにより、前記電気抵抗値によって、データの記録状態または消去状態を表現することができる。例えば、異なる抵抗値を示す２つの結晶構造のうち、一方をデータの記録状態に、もう一方をデータの消去状態に割り当てることによって、本発明に係る固体メモリを首尾よくメモリとして機能させることができる。 That is, when the Ge valence is tetravalent, the resistance value of the recording layer is large, and when it is hexavalent, the resistance value of the recording layer is small. Thus, the data recording state or erasing state can be expressed by the electric resistance value. For example, by assigning one of two crystal structures having different resistance values to a data recording state and the other to a data erasing state, the solid-state memory according to the present invention can be successfully functioned as a memory. .
　また、４価および６価の結合変異によって、垂直方向に約０．２％程度の膜厚変化を生じるが、一般的に用いられているＧｅ－Ｓｂ－Ｔｅからなる相変化材料合金の１０％程度の変化に比較して遥かに小さい。 In addition, the tetravalent and hexavalent bond mutations cause a change in film thickness of about 0.2% in the vertical direction, but 10% of a commonly used phase change material alloy composed of Ge—Sb—Te. Much smaller than the degree of change.
　本発明の一実施形態に係る固体メモリでは、前記電気抵抗値を検出することによって、データが再生されるようになっているものであってもよい。 In the solid state memory according to an embodiment of the present invention, data may be reproduced by detecting the electrical resistance value.
　上記の構成によれば、記録層の抵抗値を測定することによって、その抵抗値の大小より記録層が上記記録状態、または消去状態のいずれかの状態にあることを検出することができる。このことを利用して、本発明に係る固体メモリからデータの再生を行うことができる。 According to the above configuration, by measuring the resistance value of the recording layer, it can be detected from the magnitude of the resistance value that the recording layer is in the recording state or the erasing state. By utilizing this fact, data can be reproduced from the solid-state memory according to the present invention.
　本発明の一実施形態における固体メモリでは、前述した実施例に示すように、上記相変化に伴う抵抗値の変化として十分に大きい値を実現している。上記相変化に伴う抵抗値の変化が大きい、ということは、再生の際に固体メモリに流す電流値を小さく設定したとしても、出力電圧値の変化が大きいことを意味する。すなわち、より小さい電流値で固体メモリを駆動することを可能とする。 In the solid-state memory according to an embodiment of the present invention, as shown in the above-described example, a sufficiently large value is realized as a change in resistance value accompanying the phase change. The fact that the change in the resistance value accompanying the phase change is large means that the change in the output voltage value is large even if the current value flowing through the solid state memory is set small during reproduction. That is, the solid state memory can be driven with a smaller current value.
　駆動電流により生じるジュール熱が、記録層、および記録層を取り巻く構造体に熱履歴を与え、この熱履歴も上記体積変化と同様に、固体メモリを破壊する原因となる。よって、固体メモリの駆動電流が小さいということは、データ記録消去の繰り返し寿命を延ばすことに寄与する。 Joule heat generated by the drive current gives a thermal history to the recording layer and the structure surrounding the recording layer, and this thermal history also causes the solid memory to be destroyed as in the case of the volume change. Therefore, the small driving current of the solid-state memory contributes to extending the repeated life of data recording and erasing.
　本発明の一実施形態に係る固体メモリでは、前記ゲルマニウムとテルルとから形成されている薄膜において、全原子数に対するゲルマニウム原子数の比が０．５以下であることが好ましい。また、前記銅とテルルとから形成されている薄膜において、全原子数に対する銅原子数の比が０．５以下であることが好ましい。 In the solid-state memory according to an embodiment of the present invention, the ratio of the number of germanium atoms to the total number of atoms in the thin film formed of germanium and tellurium is preferably 0.5 or less. In the thin film formed of copper and tellurium, the ratio of the number of copper atoms to the total number of atoms is preferably 0.5 or less.
　上記の構成によれば、双安定性を有した超格子構造を好適に形成することができる。 According to the above configuration, a superlattice structure having bistability can be suitably formed.
　本発明の一実施形態に係る固体メモリでは、電気エネルギー手段により記録、または消去されることが好ましい。 In the solid-state memory according to one embodiment of the present invention, it is preferable that recording or erasing is performed by electric energy means.
　上記の構成によれば、上記固体メモリは、電気エネルギー手段により記録層の結晶構造を相変化させ、情報の記録、または、消去を行う。また、上記固体メモリは、上記相変化の結果、記録層の電気特性が変化することを利用し、情報の再生を行うことができる。 According to the above configuration, the solid-state memory records or erases information by changing the crystal structure of the recording layer using electric energy means. In addition, the solid-state memory can reproduce information by utilizing the change in the electrical characteristics of the recording layer as a result of the phase change.
　発明の詳細な説明の項においてなされた具体的な実施形態または実施例は、あくまでも、本発明の技術内容を明らかにするものであって、そのような具体例にのみ限定して狭義に解釈されるべきものではなく、本発明の精神と次に記載する請求の範囲内で、いろいろと変更して実施することができるものである。 The specific embodiments or examples made in the detailed description section of the invention are merely to clarify the technical contents of the present invention, and are limited to such specific examples and are interpreted in a narrow sense. It should be understood that various modifications may be made within the spirit of the invention and the scope of the following claims.
　本発明は、電子部品の製造分野において利用可能である。 The present invention can be used in the field of manufacturing electronic components.
　１　ゲルマニウム（Ｇｅ）原子
　２　テルル（Ｔｅ）原子
　３　銅（Ｃｕ）原子
　４　Ｇｅ２Ｔｅ２層
　５　ＣｕＴｅ２層
　１０、１００　固体メモリ
　１１、１２　記録層 1 germanium (Ge) atoms 2 tellurium (Te) atoms 3 copper (Cu) atom 4 Ge 2 Te 2 layer 5 CuTe 2 layer 10, 100 solid-state memory 11 recording layer

Claims (8)

  1. 　物質の相変化に起因して電気特性が変化する記録層を備えた固体メモリであって、
    　前記記録層が、ゲルマニウムとテルルとから形成されている薄膜、および、銅とテルルとから形成されている薄膜が積層されてなる超格子によって構成されていることを特徴とする固体メモリ。     A solid-state memory having a recording layer whose electrical characteristics change due to a phase change of a substance,
    A solid-state memory characterized in that the recording layer is composed of a superlattice formed by laminating a thin film formed of germanium and tellurium and a thin film formed of copper and tellurium.
  2. 　前記ゲルマニウムとテルルとから形成されている薄膜は、Ｇｅ２Ｔｅ２薄膜であり、
    　前記銅とテルルとから形成される薄膜は、ＣｕＴｅ２薄膜であることを特徴とする請求項１に記載の固体メモリ。     The thin film formed of germanium and tellurium is a Ge 2 Te 2 thin film,
    The solid-state memory according to claim 1, wherein the thin film formed of copper and tellurium is a CuTe 2 thin film.
  3. 　前記薄膜の各々の膜厚は、０．５ｎｍ以上８ｎｍ以下であることを特徴とする請求項１または２に記載の固体メモリ。 The solid-state memory according to claim 1 or 2, wherein each thin film has a thickness of 0.5 nm or more and 8 nm or less.
  4. 　前記ゲルマニウムとテルルとから形成されている薄膜は、前記ゲルマニウムの結合原子価が４価または６価の状態をとることによって電気抵抗値を変化させるようになっており、
    　前記電気抵抗値によって、データの記録状態または消去状態を表現するようになっていることを特徴とする請求項１～３の何れか１項に記載の固体メモリ。     The thin film formed of germanium and tellurium is adapted to change the electric resistance value when the germanium has a tetravalent or hexavalent bond valence,
    The solid-state memory according to any one of claims 1 to 3, wherein a data recording state or erasing state is expressed by the electric resistance value.
  5. 　前記電気抵抗値を検出することによって、データが再生されるようになっていることを特徴とする請求項４に記載の固体メモリ。 5. The solid state memory according to claim 4, wherein data is reproduced by detecting the electric resistance value.
  6. 　前記ゲルマニウムとテルルとから形成されている薄膜において、全原子数に対するゲルマニウム原子数の比が０．５以下であることを特徴とする請求項１～５の何れか１項に記載の固体メモリ。 6. The solid-state memory according to claim 1, wherein a ratio of the number of germanium atoms to the total number of atoms is 0.5 or less in the thin film formed of germanium and tellurium.
  7. 　前記銅とテルルとから形成されている薄膜において、全原子数に対する銅原子数の比が０．５以下であることを特徴とする請求項１～６の何れか１項に記載の固体メモリ。 The solid-state memory according to any one of claims 1 to 6, wherein in the thin film formed of copper and tellurium, a ratio of the number of copper atoms to the total number of atoms is 0.5 or less.
  8. 　電気エネルギー手段により記録、または消去されることを特徴とする請求項１～７の何れか１項に記載の固体メモリ。 The solid-state memory according to any one of claims 1 to 7, wherein the solid-state memory is recorded or erased by electric energy means.
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