TW201238035A - Solid-state memory - Google Patents

Solid-state memory Download PDF

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Publication number
TW201238035A
TW201238035A TW101103598A TW101103598A TW201238035A TW 201238035 A TW201238035 A TW 201238035A TW 101103598 A TW101103598 A TW 101103598A TW 101103598 A TW101103598 A TW 101103598A TW 201238035 A TW201238035 A TW 201238035A
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Taiwan
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film
solid
state memory
recording layer
layer
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TW101103598A
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Chinese (zh)
Inventor
Junji Tominaga
Alexander Kolobov
Paul Fons
Toshimichi Shintani
Takahiro Odaka
Takahiro Morikawa
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Nat Inst Of Advanced Ind Scien
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Publication of TW201238035A publication Critical patent/TW201238035A/en

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20Multistable switching devices, e.g. memristors
    • H10N70/231Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H10N70/235Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect between different crystalline phases, e.g. cubic and hexagonal
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011Manufacture or treatment of multistable switching devices
    • H10N70/021Formation of switching materials, e.g. deposition of layers
    • H10N70/026Formation of switching materials, e.g. deposition of layers by physical vapor deposition, e.g. sputtering
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801Constructional details of multistable switching devices
    • H10N70/821Device geometry
    • H10N70/826Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801Constructional details of multistable switching devices
    • H10N70/841Electrodes
    • H10N70/8413Electrodes adapted for resistive heating
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801Constructional details of multistable switching devices
    • H10N70/881Switching materials
    • H10N70/882Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828Tellurides, e.g. GeSbTe

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Memories (AREA)
  • Optical Record Carriers And Manufacture Thereof (AREA)

Abstract

This solid-state memory is provided with a recording layer the electrical properties of which change with the phase transition of matter. The recording layer is produced from a superlattice that is obtained by laminating a thin film formed from germanium and tellurium and a thin film formed from copper and tellurium.

Description

201238035 六、發明說明: 【發明所屬之技術領域】 本發明係關於一種固態記憶體,其利用以碲(Te)作 為主成分的硫屬(chalcogen)化合物於記錄層,然後伴隨 上述記錄層中的相變化之物性差異來利用於資料的記錄、 消去及再生。 【先前技術】 為固態記憶體之一態樣的相變化隨機存取記憶體 (random access memory)(相變化 RAM)係利用含有 Te 的硫屬化合物作為構成其記錄層的物質。上述固態記憶體 係利用結晶構造的相變化,其被稱為構成記錄層的物質之 結晶狀態及非晶(amorphous )狀態之一次相變態(於本說 明書,簡單地稱為相變化)。另外,就用於記錄層的硫屬化 合物而言,一般為Ge2Sb2Te5合金。 上述固態記憶體中的資料記錄及消去的兩狀態係例如 將結晶狀態指派為記錄狀態、非晶狀態指派為消去狀態下 可被實現,基於此基本原理的固態記憶體已被設計出來(例 如,專利文獻1)。 另外,於利用結晶構造之相變化的固態記憶體,為了 誘發相變化,有必要於記錄層施加用以誘發相變化充分的 能量。就施加能量的方法而言,一般係使用電能單元於記 錄層通電。 構成固態記憶體之記錄層的材料係利用濺鍍 5 3 201238035 (sputtering)法等真空成膜法而形成於上下各電極間。通 常,使用由作為記錄層的化合物組成而形成之目標來進行 濺鍍,將單層之合金薄膜成膜而作為記錄層使用。 利用藏鍍法,於記錄層上具有20nm〜50nm左右的適當 膜厚之硫屬化合物的單層膜加以成膜的情形,要獲得由單 結晶形成的記錄層係有困難的。因此,固態記憶體之記錄 層一般係由硫屬化合物之多結晶所構成。 於由多結晶而形成的薄膜中,個別微結晶粒之軸方位 為隨機,各微結晶粒彼此之界面存有界面電阻(interface resistance )。上述界面電阻係依存於個別微結晶粒之界面狀 邊而為隨機者^其結果’固怨記憶體之記錄層中的結晶狀 態之電阻値係呈為具有平均値至一定分佈者(非專利文獻 1)。 而且,於由硫屬化合物之多結晶薄膜而形成的記錄層 中,在結晶-非晶間之相變化發生時,10%左右的體積變 化,個別微結晶粒會被施加相異方向及相異大小的應力。 伴隨資料的記錄及消去,會重複上述結晶-非晶間之相變 化,並重複施加上述應力於記錄層。其結果,經由重複物 質流動及膜全體之變形,固態記憶體會被破壞,一般認為 重複記錄消去次數會受限制(非專利文獻2)。 作為解決此等問題之方法之一者,本發明者們已提議 記錄層不用Ge2Sb2Te5合金單層膜,而是分割為鍺(Ge) 原子與Te原子所形成的Ge2Te2薄膜、及Sb原子與Te原 子而形成的Sb2Te3薄膜,且經由層疊而作成超晶格構造者 201238035 (專利文獻2)。 於α己錄層使用由上述Ge〗Te2薄膜及(}e2Te2薄膜而形成 的超aa格之固恶§己憶體中,藉由使層内有的原 子擴散,於與Sb^Teg層之界面可將結晶狀態相同的構造作 為具有異方性的結晶」而形成,將上述「具有異方性的 結晶」狀態分配為例如記錄狀態(一般而言,亦稱為Set 狀悲)。 而且,相反地,藉由在界面被擴散的Ge原子回到原來 的Geje2層内,由上述超晶格所形成的記錄層係回到與習 知的GejbzTe5合金被稱為非晶狀態的構造具有同等電阻 値之「類似晶形的構造」。將此「類似非晶的構造」狀態分 配為例如消去狀態(一般而言,亦稱為尺⑵以狀態)。 如上所述,本發明者們藉由使用由Ge2Te2薄膜及 Sb2Te3薄膜所形成的超晶格構造之記錄層,提供可大幅改 善傳統固態記憶體之特性的新固態記憶體(專利文獻2)。 另一方面,有欲實現不含有稀有金屬銻(antim〇ny ; Sb )的固悲έ己憶體之需求。為了實現不含有%的固能纪 體,Ge-Cu-Te系合金取代了 Ge_Sb_Te系合金而吸引二⑽ 注意(例如,非專利文獻3)。上述Ge_Cu_Te系合金中,由 於Ge2Te2# CuTe2之共晶組成、結晶相轉移溫度為201238035 VI. Description of the Invention: [Technical Field] The present invention relates to a solid state memory using a chalcogen compound containing cerium (Te) as a main component in a recording layer, which is then accompanied by the above recording layer The difference in physical properties of phase changes is used for the recording, erasing and regeneration of data. [Prior Art] A phase change random access memory (phase change RAM) which is one of solid state memories utilizes a chalcogen compound containing Te as a substance constituting its recording layer. The above solid state memory utilizes a phase change of a crystal structure, which is referred to as a crystalline phase of a substance constituting the recording layer and a phase transition state of an amorphous state (referred to simply as a phase change in the present specification). Further, as the chalcogen compound used for the recording layer, it is generally a Ge2Sb2Te5 alloy. The two states in which the data recording and erasing in the above solid state memory are assigned, for example, the crystal state is assigned to the recording state, and the amorphous state is assigned to the erase state, solid state memory based on this basic principle has been designed (for example, Patent Document 1). Further, in order to induce a phase change in a solid state memory in which a phase change of a crystal structure is utilized, it is necessary to apply energy sufficient to induce a phase change in the recording layer. In the case of the method of applying energy, the power unit is generally used to energize the recording layer. The material constituting the recording layer of the solid-state memory is formed between the upper and lower electrodes by a vacuum film formation method such as sputtering 5 3 201238035 (sputtering). Usually, sputtering is performed using a target formed of a compound as a recording layer, and a single-layer alloy thin film is formed into a film to be used as a recording layer. In the case where a single layer film of a chalcogen compound having a suitable film thickness of about 20 nm to 50 nm is formed on the recording layer by a deposit plating method, it is difficult to obtain a recording layer formed of a single crystal. Therefore, the recording layer of the solid state memory is generally composed of polycrystals of a chalcogen compound. In the film formed by polycrystallization, the axial orientation of the individual microcrystalline grains is random, and the interface resistance is present at the interface between the respective microcrystalline particles. The above-mentioned interface resistance is random depending on the interface side of the individual microcrystalline particles. The result is that the resistance enthalpy of the crystalline state in the recording layer of the memory is expressed as having an average 値 to a certain distribution (Non-patent literature) 1). Further, in the recording layer formed of the polycrystalline thin film of the chalcogen compound, when the phase change between the crystal-amorphous occurs, a volume change of about 10% occurs, and the individual microcrystalline particles are applied in different directions and different from each other. The size of the stress. The above-described crystal-amorphous phase change is repeated with the recording and erasing of the data, and the above stress is repeatedly applied to the recording layer. As a result, the solid memory is destroyed by the flow of the repeating material and the deformation of the entire film, and it is considered that the number of times of repeated recording and erasing is limited (Non-Patent Document 2). As one of the methods for solving such problems, the present inventors have proposed that the recording layer is not a Ge2Sb2Te5 alloy single layer film, but is divided into a Ge2Te2 film formed by a germanium (Ge) atom and a Te atom, and a Sb atom and a Te atom. The formed Sb2Te3 film was laminated to form a superlattice structure 201238035 (Patent Document 2). In the α-recording layer, the ultra-aa lattice formed by the above Ge-Te2 film and the (}e2Te2 film is used in the interface of the Sb^Teg layer by diffusing atoms in the layer. The structure having the same crystal state can be formed as a crystal having an anisotropy, and the above-described "crystal having an anisotropy" state is assigned to, for example, a recording state (generally, also called Set-like sadness). By returning the Ge atoms diffused at the interface back to the original Geje2 layer, the recording layer formed by the superlattice is returned to the same structure as the conventional GejbzTe5 alloy, which is called an amorphous state. The "crystal-like structure" is assigned to the "amorphous structure-like" state as, for example, the erased state (generally, also referred to as the ruler (2) in the state). As described above, the inventors use Ge2Te2. The recording layer of the superlattice structure formed by the film and the Sb2Te3 film provides a new solid state memory which can greatly improve the characteristics of the conventional solid state memory (Patent Document 2). On the other hand, it is desired to realize the absence of rare metal lanthanum (antim). 〇ny In order to realize a solid energy particle which does not contain %, the Ge-Cu-Te alloy replaces the Ge_Sb_Te alloy and attracts two (10) attention (for example, Non-Patent Document 3). In the above Ge_Cu_Te alloy, the eutectic composition and the crystal phase transition temperature of Ge2Te2#CuTe2 are

200°C 以上時資料之高溫保存性更為優異等理由,故特別期待 GeCu2Te3 合金。 [先前技術文獻] [專利文獻]The GeCu2Te3 alloy is particularly expected when the data has a high temperature storage property at 200 °C or higher. [Prior Technical Literature] [Patent Literature]

S 5 201238035 [專利文獻1] 曰本國公開專利公報「特開 2002-203392號公報(2002年7月19日公開)」 [專利文獻2] 日本國公開專利公報「特開 2〇〇9_59902號公報(2〇〇9年3月I9日公開)」 [非專利文獻] [非專利文獻1]奥田昌宏監修,「次世代光記錄技術及 材料」,CMC出版,2004年1月31日發行,pi 14 [非專利文獻2]角田義人監修’「光碟儲存器(optical disc storage)之基礎及應用」,電子情報通信學會編,平成 13年6月1日初版第3刷發行,p209 [非專利文獻 3] T.Kamada et.al.,Phase Change Behaviour of GelCu2Te3 Thin Films, Proceedings of the 22nd Symposium on PhaseChange Optical Information Strage PCOS2010, Atami, Shizuoka, 2010 Nov.25-26, pp,21-23 【發明内容】 [發明概要] [發明所欲解決的問題] 然而’ GeCwTe3合金具有下列缺點:非晶狀態之電阻 値與習知的Gedl^Te5合金比較下為小一位數’與結晶狀態 之電阻値的差為小二位數左右。 上述電阻値之比為小的情形,固態記憶體之再生時所 獲得之電壓信號的差變小,為了獲得實際使用上充足的信 號/雜訊比’再生時之驅動電流有必要擴大。上述驅動電流 6 201238035 之增大,伴隨消費電力之增大、焦耳(joule )熱之增大而 溫度上昇,構成記錄層的物質之熔融或融解,及伴隨此之 組成比相異的化合物之偏析(segregation )等,而對固態記 憶體會有各式各樣的不良影響。 又,在記錄層使用了 Ge-Cu-Te系合金的固態記憶體, 在重複記錄消去之次數而言,於現狀上都無法與在記錄層 使用了 Ge2Sb2Te5合金、或由Ge2Te2及Sb2Te3而形成超晶 格的固悲記憶體匹敵。 基於上述理由,本發明之目的係提供伴隨相變化的充 分電阻値變化、重複記錄消去的次數與Ge-Sb-Te系之固態 記憶體相比亦未遜色的不含有Sb的固態記憶體。 [用以解決問題之單元] 與本發明有關的固態記憶體係為了解決上述問題,所 以具備起因於物質之相變化而電氣特性會改變的記錄層之 固態記憶體,其特徵在於,前述記錄層係藉由鍺及碲而形 成的薄膜、及由銅及蹄而形成的薄膜層疊而形成的超晶格 所構成者。 如此,與本發明有關之固態記億體,為了提供具有與 Ge-Sb-Te系之固態記憶體相較下不會遜色之不含有Sb的 固態記憶體,使用由鍺(Ge)及碲(Te)而形成的薄膜(以 下,稱為Ge-Te系薄膜)、及由銅(Cu)及Te而形成的薄 膜(以下,稱為Cu-Te系薄膜)之超晶格構造作為固態記 憶體之記錄層。據此,如後述實施例所示,雖然不含有Sb, 但與非專利文獻3記載之技術並不相同,伴隨相變化可充 201238035 分將電阻値之變化變大,同時與使用單純的Ge-Cu-Te系之 合金薄膜於記錄層的固態記憶體相比較下,可實現顯著的 性能提升。例如,如後述的實施例所示,伴隨由Ge-Te系 薄膜及Cu-Te系薄膜所形成的超晶格構造之相變化的體積 變化係極小的。伴隨上述相變化的體積變化,重複資料記 錄及消去時,對於包圍記錄層上下配置的電極等之構造體 會給予力學上的應力。藉由上述應力重複被施加於固態記 憶體,固態記憶體於各層界面會發生剪斷或剝離等而被破 壞。因此,伴隨相變化的體積變化極小者有助於延長重複 貢料記錄消去的奇命。 如以上所述,依據本發明,可提供具有與Ge-Sb-Te系 之固態記憶體相比不會遜色的性能之不含有Sb的固態記 憶體。 本發明之其他目的、特徵、及優點,藉由以下所示記 載係可充分暸解。而且,本發明之優點參照所附圖式的下 列説明顯然已為清楚。 [發明之效果] 依據本發明,可提供一種固態記憶體,其雖不含有Sb, 但可確保伴隨相變化的固態記憶體充分大的電阻値之變 化,且資料之重複記錄消去的次數亦達到1011次。上述此 等與使用Ge-Sb-Te系合金於記錄層的固態記憶體相比較 下,具有不遜色的性能。 【貫施方式】 8 201238035 [用以實施發明的態樣] 以下,關於與本發明有關之固態記憶體的一實施態 樣,參照第1圖至第3圖加以説明。另外,以下記載之實 施態樣不過是本發明之一範例,本發明並未以任何方式受 限於此等範例。 〔1.關於記錄層〕 為了實現不含有稀少金屬銻(Sb)的固態記憶體,與 本發明有關之固態記憶體的記錄層使用藉由Ge-Te系合金 膜及Cu-Te系合金膜所構成的超晶格構造。第1圖係揭示 以Ge2Te〗層4作為Ge-Te系合金膜之一範例、以CuTe2層 5作為Cu-Te系合金膜之一範例,各自使用的情形之超晶格 構造圖。第1圖所示的超晶格構造係使用第一原理計算而 被決定的構造,Ge2Te2層4及CuTe2層5之膜厚係各為 0.77nm 及 0.54nm。 於本說明書,超晶格係指藉由有規律地層疊複數種類 之結晶薄膜,而具有人為操作的長周期構造的結晶格子。 而且,超晶格構造係意指如此結晶格子之構造。 另外,於製作超晶格時,Ge相對於Te之原子數之比 為小者較佳,Ge原子數相對於Ge-Te系合金膜中的全原子 數的比係大於0且0.5以下者為較佳。而且,於製作超晶 格時,Cu原子數相對於Cu-Te系合金膜中的全原子數之比 係大於0且0.5以下者為較佳,0.2以上且0.4以下者為更 佳,使用CuTe2膜作為Cu-Te系合金膜者為最佳。 藉由Ge原子1及Te原子2所形成的Ge2Te2層4、及 5 9 201238035 由Te原子2及Cu原子3戶斤成的CuTe2層5之層疊構造所 構成的超晶格具有兩個安定的構造(構造A(第1圖之(a)) 及構造B (第1圖之(b)))’且具有雙安定性。 與本發明之一實施態槔有關的固態記憶體係藉由利用 上述t己錄層中的構造A-構造B間之相變化而發揮固態記憶 體的功能。於構造A及構造B ’ Ge〗Te2層4内的Ge層與 Te層之位置係可替換的。而且’ GeTe層彼此的間隔幾乎沒 有差異’於上述間隔’構造B係較構造a為寬。 於與本發明之-實施態樣有關的固態記憶體,由構造 A至構w B或由構造B至構造a之相變化,即GeTe層之 移動,可藉由電能單元引起。由第1圖之(a)及(b)可 知’伴隨相變化的GeTe層之移動為一方向(對於基板表面 為垂直方向),可謂具有黏附(coherent)性。因此,可將 輸入的能量能有效率地用於相變化,其結果,具有為引起 相變化所需之微小能量便足夠的優點。 而且,如後所述’與本發明之一實施態樣有關的固態[Patent Document 1] Japanese Laid-Open Patent Publication No. JP-A-2002-203392 (published on July 19, 2002). (Non-Publication on March 9th, 2009) [Non-patent literature] [Non-Patent Document 1] Onoda Masahiro, "Second Generation Optical Recording Technology and Materials", CMC Publishing, issued on January 31, 2004, pi 14 [Non-Patent Document 2] Kakuda Yoshito's Supervisor's "Basic and Application of Optical Disc Storage", edited by the Institute of Electronic Information and Communication, 3rd issue of the first edition on June 1, 1999, p209 [Non-patent literature 3] T.Kamada et.al., Phase Change Behaviour of GelCu2Te3 Thin Films, Proceedings of the 22nd Symposium on Phase Change Optical Information Strage PCOS2010, Atami, Shizuoka, 2010 Nov.25-26, pp, 21-23 [Summary of the Invention] [Summary of the Invention] [Problems to be Solved by the Invention] However, the 'GeCwTe3 alloy has the following disadvantages: the resistance 非晶 of the amorphous state is the difference between the resistance of the small single digit 'and the resistance 结晶 of the crystalline state compared with the conventional Gedl^Te5 alloy. For the second Number about. When the ratio of the above-mentioned resistance 値 is small, the difference in voltage signals obtained during reproduction of the solid-state memory becomes small, and it is necessary to expand the driving current at the time of reproduction in order to obtain a sufficient signal/noise ratio in actual use. The increase of the above-mentioned driving current 6 201238035 increases with the increase of the power consumption, the increase of the Joule heat, the melting or melting of the substances constituting the recording layer, and the segregation of the compounds having a different composition ratio. (segregation), etc., and there are various adverse effects on solid state memory. Further, in the recording layer, a solid-state memory using a Ge-Cu-Te alloy is used. In the current state, it is impossible to form a Ge2Sb2Te5 alloy or a Ge2Te2 and Sb2Te3 in the recording layer. The crystal lattice's solid memory is rival. For the above reasons, the object of the present invention is to provide a solid-state memory containing no Sb which is not inferior to the Ge-Sb-Te-based solid-state memory, and which has a sufficient resistance 相 change accompanying phase change and repeated recording erasure. [Means for Solving the Problems] In order to solve the above problems, the solid-state memory system according to the present invention has a solid-state memory which is a recording layer which changes electrical characteristics due to a phase change of a substance, and is characterized in that the recording layer is A super-lattice formed by laminating a film formed of tantalum and niobium and laminating a film formed of copper and hoof. Thus, in the case of a solid-state memory containing Sb which is inferior to the Ge-Sb-Te-based solid state memory, the solid-state memory of the present invention is used for the use of germanium (Ge) and germanium ( a superlattice structure of a film formed by Te) (hereinafter referred to as a Ge-Te film) and a film formed of copper (Cu) and Te (hereinafter referred to as a Cu-Te film) as a solid memory The recording layer. Accordingly, as described in the following examples, although Sb is not contained, the technique described in Non-Patent Document 3 is not the same, and the change in the resistance 値 is increased with the phase change at 201238035, and the simple Ge- is used. The Cu-Te alloy film can achieve significant performance improvement in comparison with the solid state memory of the recording layer. For example, as shown in the examples to be described later, the volume change of the phase change accompanying the superlattice structure formed of the Ge-Te-based film and the Cu-Te-based film is extremely small. When the data is recorded and erased in association with the volume change of the phase change described above, mechanical stress is applied to the structure surrounding the electrode disposed above and below the recording layer. By the above-described stress repetition being applied to the solid-state memory, the solid-state memory is broken by shearing or peeling at the interface of each layer. Therefore, the small volume change accompanying the phase change helps to prolong the odds of repeated tribute recording elimination. As described above, according to the present invention, it is possible to provide a solid-state memory body which does not contain Sb which is inferior to the Ge-Sb-Te-based solid state memory. Other objects, features, and advantages of the present invention will be apparent from the appended claims. Further, the advantages of the present invention will be apparent from the following description of the drawings. [Effects of the Invention] According to the present invention, it is possible to provide a solid-state memory which does not contain Sb, but which ensures a sufficiently large resistance enthalpy change of the solid-state memory accompanying the phase change, and the number of repeated recording and erasing of the data is also reached. 1011 times. These are inferior to those of the solid state memory using the Ge-Sb-Te alloy in the recording layer. [Cross-Phase Mode] 8 201238035 [Aspect for embodying the invention] Hereinafter, an embodiment of the solid-state memory according to the present invention will be described with reference to Figs. 1 to 3 . Further, the embodiments described below are merely an example of the present invention, and the present invention is not limited to such examples in any way. [1. Regarding the recording layer] In order to realize a solid memory containing no rare metal bismuth (Sb), the recording layer of the solid memory relating to the present invention is used by a Ge-Te alloy film and a Cu-Te alloy film. The superlattice structure is constructed. Fig. 1 is a view showing a superlattice structure diagram in which Ge2Te layer 4 is used as an example of a Ge-Te alloy film and CuTe2 layer 5 is used as an example of a Cu-Te alloy film. The superlattice structure shown in Fig. 1 is determined by the first principle calculation, and the thicknesses of the Ge2Te2 layer 4 and the CuTe2 layer 5 are 0.77 nm and 0.54 nm, respectively. In the present specification, a superlattice refers to a crystal lattice having a long-period structure which is artificially manipulated by laminating a plurality of types of crystal thin films. Moreover, the superlattice structure means the configuration of such a crystal lattice. Further, in the case of producing a superlattice, the ratio of the number of Ge to the atomic number of Te is preferably small, and the ratio of the number of Ge atoms to the total number of atoms in the Ge-Te alloy film is more than 0 and 0.5 or less. Preferably. Further, in the case of producing a superlattice, the ratio of the number of Cu atoms to the total number of atoms in the Cu-Te-based alloy film is preferably 0 or more, and more preferably 0.2 or more and 0.4 or less, and CuTe2 is used. The film is preferably used as a Cu-Te alloy film. The Ge2Te2 layer 4 formed by the Ge atom 1 and the Te atom 2, and the superlattice composed of the CuTe2 layer 5 formed of the Te atom 2 and the Cu atom 3 have two stable structures. (Structure A (Fig. 1 (a)) and Structure B (Fig. 1 (b)))' have double stability. The solid state memory system related to one embodiment of the present invention functions as a solid state memory by utilizing a phase change between the structure A-structure B in the above-described t-recorded layer. The positions of the Ge layer and the Te layer in the Te 2 layer 4 in the structure A and the structure B ′ Ge are replaceable. Further, there is almost no difference in the interval between the 'GeTe layers'. In the above-described interval, the structure B is wider than the structure a. The solid state memory associated with the embodiment of the present invention, the phase change from the configuration A to the configuration b or from the configuration B to the configuration a, i.e., the movement of the GeTe layer, can be caused by the power unit. It is known from (a) and (b) of Fig. 1 that the movement of the GeTe layer accompanying the phase change is one direction (vertical direction to the substrate surface), and it can be said to have coherent properties. Therefore, the input energy can be efficiently used for the phase change, and as a result, there is an advantage that the minute energy required to cause the phase change is sufficient. Moreover, as will be described later, the solid state related to one embodiment of the present invention

之非常大者。Very big.

造 A ^ 、π,Create A ^, π,

CuTe 之(b))。Ge之鍵、_ 而Ge層及Te層彼$(b)) of CuTe. Ge key, _ and Ge layer and Te layer

g之(a)),於耩造B為6價(第1圖 結價數由4價變成6價係因伴隨相變化 此交換,與CuTea層5之距離近而Ge_T 201238035 間產生鍵結所致。另外,第1圖係揭示由Geje2薄膜4及 CuTe2薄膜5所形成的超晶格之基本晶格之構造圖。藉由 Ge原子1成為6價’對於基板表面為垂直方向的電氣特性 成為金屬性的’電阻値顯著減少。據此,作為固態記憶體 更為合適,可擴大相變化時之電阻値的變化。 因此,相對於記錄層之電阻値的大小,分配資料的記 錄及消去狀態任-者係有可能的。m由測量記錄層 之電阻値’判別記錄層為資料之記錄及消去狀態的任一 者,即δ己錄資料的再生係有可能的。 而且,構造Α及構造Β,不僅電氣特性,而且光學特 I"生易亦有很大不同,故作為記錄資料的再生單元,使 學的手法亦為可能的。 另外’就作為用以誘發相變化的電能單元而言,例如, 可利用脈衝通電。藉由調整此時脈衝通電的電流値及通電 的時間(以下稱為脈衝時間),可任意地重複構造Α及構造 Β間之相變化。利用上述此等’於與本發明之一實施態樣 有關的1¾、記憶體進行資料之記憶及消去。 〔2.固態記憶體之構成〕 關於與本發明有關之固態記憶體的構成之一範例,説 明如下。但與本發明有關之固態記憶體的構成並未限定於 以下任'者。 ^第2圖之(a)係揭示使用由Ge2Te2薄膜4及 薄膜5所形成的超晶格薄膜作為記錄層u的固態記憶㈣ 之概略抽圖。而且’記錄層u之概略擴大關示於第2 201238035 圖之(b)。 於上述固態記憶體1〇 ’記錄層u被包夹於上 14及焦耳熱發生用加鮮…再者,各自於上部電 與輸出線13作電氣接觸、於焦耳熱發生用加熱器^盘輪 入線】6作電氣接觸。即,焦耳熱發生❹熱器15作為: 熱益功能的同時,亦兼具下部電極的功能。 ’”、口 …而且,為了於上述構造A及構造β之間引起相變化, 上边使用電流作為電能單元’其路獲作為電流路徑如 =前述電流路徑2G通電,於焦耳熱發生用加熱器15中 生焦耳熱的s己錄層u被加熱且其溫度會上升。 糟由控制於記錄層U施加的電流似脈 :=:。度’一構造一二 〔3.固態記憶體之製作方法〕 的固第Μ —邊説明與本發明之一實施態樣有關 用广。己思體之製作方法的一範例如下。第2圖係揭示使 =由Ge2Te2薄膜4及CuTe2薄膜5所形成的超晶格薄膜作 為记錄層11的固態記憶體之概略剖面圖。 伽/、本發明之一實施悲樣有關的固態記憶體可形成作為 :’具有-般的自我電阻加熱型之構成的相變化ram 專利文獻1}。依據上述一般的構成,於藉由製作 =基板/輪人線/焦耳熱發生用加熱器/記錄層/上部電極/ =出,的構成之相變化RAM的情形,基板上依序以輪入線 …'耳熱發生用加熱器15、記錄層11、上部電極14、及 12 201238035 輸出線13來成膜為佳。就此時之成膜方法而言,例如可使 用濺鍍法等之一般的成膜方法。以下,揭示固態記憶體之 製作方法的一範例。 基板係使用矽(Si)晶圓,藉由濺鍍法將輸入線16及 焦耳熱發生用加熱器15成膜。焦耳熱發生用加熱器係可使 用例如鶴。 其次,以濺鍍法將記錄層所使用的Ge-Te系合金膜、 Cu-Te系合金膜之超晶格加以成膜。此時,期望的化合物(例 如,Ge2Te2及CuTe2)作為可成膜的目標。 為了製作超晶格構造,預先於各化合物,測量每單位 時間之成膜的膜厚,有必要先確定成膜率。各化合物之成 膜率若確定,藉由控制個別化合物之成膜時間,可實現具 有任意周期構造的超晶格構造。 藉由上述方法,將具有任意之周期構造及任意之層疊 數的記錄層成膜後,例如,藉由將由鎢所形成的上部電極 14及輸出線13加以成膜,而完成相變化RAM。 另外,構成超晶格構造的Ge-Te系薄膜、及Cu-Te系 薄膜之膜厚為〇.5nm以上且8nm以下者是令人期待的。藉 由作成此範圍之膜厚,上述各薄膜之結晶構造不會混亂, 可較佳地實現超晶格構造。 而且,電極及記錄層等之圖案化可使用一般的照相平 版印刷法(photolithography process)。 另外,本發明亦可能表現如下。 (構成1 ) 一種固態記憶體,其係以Cu、Ge及Te作 13 201238035 為主成分的固態記憶體,其特徵為:具有因物質之相變態 而電氣特性會變化者,記錄及再生資料的材料係藉由生^ 該相變態的母相所形成的薄膜之人工的超晶格構造之層疊 構造所構成。 曰且 (構成2)在構成!之固態記憶體中,固態記憶體之特 徵為:前述層疊構造係由含有以原子的^合金薄膜及含 有Cu原子的Te合金薄膜彼此層疊而成的多層膜所構成。 立(構成3)在構成1或構成2之固態記憶體中,固態記 體之特徵為:前述薄膜之個職厚為Q 5nm以上8腿以 下。 (構成4)在構成2之固態記憶體中,固態記憶體之特 含有前述Ge原子的合金薄膜中之&原子的鍵結原 =為4價或6價的狀態下,使電阻變化,藉由鍵結原子 貝、不同,獲得的二個電阻値用於資料之記錄及消去狀態 之任一者。 I構成5)在構成2之18態記憶體#,@態記憶體之特 ==原子數相對於含有前述〜原子的&合金薄膜之 …原子數的比為0.5以下。 構成6)在構成2之固態記憶體中,固態記憶體之特 二二f子數相對於含有前述CU原子的Te合金薄膜之 、似王原子數的比為0.5以下。 来基於實施態樣具體地説明本發明,但本發明並 能的·,,於請求項所示的範圍内有各種可 k田組合相異的實施態樣中個別揭示的技術 201238035 單元所獲得的實施態樣亦包s於本發明之技術範籌。 本發明藉由以下實施例更詳細地被說明,但並未限定 於此等實施例。 [實施例] 〔實施例1〕 記錄層所使用的超晶格之結晶構造或各種特性對於固 態記憶體之性能(伴隨相變化的電阻値變化、所需要的驅 動電流値、及進行重複記錄:肖去的次數等)有極大影塑, 故非常重要。製作上述構造A及構造b之超晶格,並證實 具有以下所示的特性。 由GezTe2層4及CuTe2層5所形成的超晶格,藉由給 予電能,構造A-構造B間會產生相變化(參照第1圖 即,上述超晶格係因應給予的能量,選擇雙安定的構造A、 或構造B中之一者。然後,所給予的能量不限於電能,亦 可使用熱能來選擇超晶格構造。g(a)), in the case of manufacturing B is 6 (the number of valences in Fig. 1 is changed from 4 to 6) due to phase change, and the distance from the CuTea layer 5 is close to that of Ge_T 201238035. Further, Fig. 1 is a structural diagram showing a basic lattice of a superlattice formed by the Geje2 thin film 4 and the CuTe2 thin film 5. The electrical property of the hexagonal surface of the substrate by the Ge atom 1 becomes hexavalent. The metallic 'resistance 値 is remarkably reduced. Accordingly, it is more suitable as a solid-state memory, and the change in the resistance 値 at the time of phase change can be expanded. Therefore, the recording and erasing state of the distribution data with respect to the magnitude of the resistance 値 of the recording layer Any one is possible. m is determined by the resistance 测量' of the measurement recording layer. The recording layer is any one of the recording and erasing state of the data, that is, the regeneration system of the δ recorded data. Moreover, the structure and structure are constructed. Oh, not only the electrical characteristics, but also the optical special I" is easy to make a difference. Therefore, as a regenerative unit for recording data, it is also possible to learn the technique. In addition, it is used as a power unit for inducing phase change. , for example, By pulse energization, the phase change between the structure and the structure can be arbitrarily repeated by adjusting the current 値 of the pulse energization and the time of energization (hereinafter referred to as the pulse time). With the above, The memory of the memory is erased and erased in an embodiment. [2. Configuration of solid memory] An example of the configuration of the solid memory according to the present invention will be described below, but related to the present invention. The configuration of the solid state memory is not limited to the following ones. ^ (a) of Fig. 2 discloses a solid state memory (4) using a superlattice film formed of the Ge2Te2 film 4 and the film 5 as the recording layer u. Fig. and the summary of the recording layer u is shown in the second 201238035 (b). In the above solid state memory, the recording layer u is sandwiched between the upper 14 and the Joule heat generation. Each of the upper electric and the output line 13 is in electrical contact, and the Joule heat generating heater is used to make electrical contact. The Joule heat generating heat exchanger 15 serves as a heat-sensitive function and also has a lower portion. Electrode function In addition, in order to cause a phase change between the above-mentioned structure A and the structure β, a current is used as the electric energy unit, and the path is obtained as a current path, such as the current path 2G is energized, and the heater for the Joule heat generation 15 is used. The sheng sheng layer u of the middle Joule heat is heated and its temperature rises. The current applied by the recording layer U is similar to the pulse: =: degree 'one structure one or two [3. method of manufacturing solid state memory] An example of a method for fabricating an aspect of the present invention is as follows. Fig. 2 is a view showing a supercrystal formed by a Ge2Te2 film 4 and a CuTe2 film 5. The thin film is a schematic cross-sectional view of the solid state memory of the recording layer 11. The solid state memory related to the sadness of one of the present invention can be formed as: "Phase change ram having a structure of a self-resistance heating type" Patent Document 1}. According to the above general configuration, in the case of fabricating a phase change RAM having a structure of a substrate/wheel line/joule heat generating heater/recording layer/upper electrode/=, the substrate is sequentially wheeled... It is preferable that the ear heat generating heater 15, the recording layer 11, the upper electrode 14, and the 12:38038035 output line 13 are formed. In the film forming method at this time, for example, a general film forming method such as a sputtering method can be used. Hereinafter, an example of a method of fabricating a solid state memory will be disclosed. The substrate is formed by using a bismuth (Si) wafer, and the input line 16 and the Joule heat generating heater 15 are formed by sputtering. For the heater for generating Joule heat, for example, a crane can be used. Next, a superlattice of a Ge-Te-based alloy film or a Cu-Te-based alloy film used for the recording layer was formed by sputtering. At this time, a desired compound (e.g., Ge2Te2 and CuTe2) is a target for film formation. In order to produce a superlattice structure, the film thickness per film time is measured in advance for each compound, and it is necessary to determine the film formation rate first. If the film formation rate of each compound is determined, a superlattice structure having an arbitrary periodic structure can be realized by controlling the film formation time of the individual compounds. By forming the recording layer having an arbitrary periodic structure and an arbitrary number of layers by the above method, for example, the phase change RAM is completed by forming the upper electrode 14 and the output line 13 made of tungsten. Further, it is desirable that the Ge-Te thin film and the Cu-Te thin film which constitute the superlattice structure have a thickness of 〇. 5 nm or more and 8 nm or less. By forming the film thickness in this range, the crystal structure of each of the above films is not disturbed, and the superlattice structure can be preferably realized. Further, the patterning of the electrode and the recording layer or the like can be carried out by a general photolithography process. In addition, the present invention may also be expressed as follows. (Configuration 1) A solid-state memory which is a solid-state memory mainly composed of Cu, Ge, and Te as 13 201238035, and is characterized in that it has a change in electrical characteristics due to a phase transition of a substance, and records and reproduces data. The material is composed of a laminated structure of an artificial superlattice structure of a thin film formed by the mother phase of the phase transition. ( (constitution 2) is in composition! In the solid state memory, the solid state memory is characterized in that the laminated structure is composed of a multilayer film in which an alloy thin film containing atoms and a Te alloy thin film containing Cu atoms are laminated on each other. In the solid memory of the configuration 1 or the composition 2, the solid state recording is characterized in that the thickness of the film is Q 5 nm or more and 8 legs or less. (Configuration 4) In the solid memory of the configuration 2, in the alloy thin film containing the Ge atom in the solid memory, the bond of the & atom is changed to a tetravalent or hexavalent state, and the resistance is changed. The two resistors obtained by bonding the atoms and the different ones are used for any of the data recording and erasing states. I constitute 5) In the case of the 18-state memory #2, the @@-memory memory == the atomic number is 0.5 or less with respect to the atomic number of the & alloy film containing the above-mentioned ~ atom. In the solid memory of the configuration 2, the ratio of the number of the special two-two f-number of the solid-state memory to the number of the king-like atoms of the Te alloy thin film containing the CU atom is 0.5 or less. The present invention will be specifically described based on the embodiments, but the present invention is capable of obtaining various techniques disclosed in the various embodiments of the present invention in the scope of the claims. The implementation aspect is also included in the technical scope of the present invention. The invention is illustrated in more detail by the following examples, without being limited thereto. [Examples] [Example 1] The crystal structure or various characteristics of the superlattice used in the recording layer were used for the performance of the solid state memory (resistance change with phase change, required driving current 値, and repeated recording: The number of times Xiao Xiao went, etc.) is extremely important, so it is very important. The superlattice of the above structure A and structure b was produced and confirmed to have the characteristics shown below. The superlattice formed by the GezTe2 layer 4 and the CuTe2 layer 5 generates a phase change between the A-structure B by the application of electric energy (refer to Fig. 1, that is, the above-mentioned superlattice system selects the double stability according to the energy given thereto. One of the construction A, or the construction B. Then, the energy imparted is not limited to electrical energy, and thermal energy can also be used to select the superlattice configuration.

Ί±- 1CG π卬尸/r游丁的熱胃&又差吳,將構造A及構造B 之超晶格薄膜加以成膜。於相異的基板溫度之Si晶圓上, 使,賤鍍法’將由Ge2TeJ 4及CuTe2>! 5所形成的膜厚 為、、々40nm之超晶格薄膜加以成膜,並比較結晶構造、 。 将丨生。成胰時之基板溫度個別為150 C及25〇 以下個別稱為樣品a及樣品b。 實;,個別之超晶格薄膜進行χ射線構造解析的結果,證 a之面_係與由第―朗計算所求得的構造Α(第 之(a))之面間隔非常一致,樣品b之面間隔係與由上 201238035 述計算所求得的構造B (第1圖之(b))之面間隔非常一 致。 而且兩樣品之電阻値使用四端子探針測量的結果,其 中樣品a為約5ΜΩ,樣品b為30kn。因此,將構造A·構 造B間的相變化利用於相變化RAM的情形,證實輸出時 之"ίσ號顯示約倍的變化。如上所述,由GezTe〗層4及Ί±- 1CG π 卬 卬 / r r r r r r r 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热On a Si wafer having a different substrate temperature, a germanium plating method is used to form a superlattice film having a thickness of 々40 nm formed by Ge2TeJ 4 and CuTe2> . Will be born. The substrate temperature at the time of pancreas is individually 150 C and 25 Å. The samples are individually referred to as sample a and sample b. Actually, the results of the X-ray structure analysis of the individual superlattice films prove that the surface of the layer a is very consistent with the surface spacing of the structure Α (the (a)) obtained by the first calculation, sample b The surface spacing is very consistent with the surface spacing of the structure B (Fig. 1(b)) obtained from the calculation of 201238035. Moreover, the resistance of the two samples was measured using a four-terminal probe, wherein sample a was about 5 ΜΩ and sample b was 30 kn. Therefore, the phase change between the construction A and the construction B is utilized in the case of the phase change RAM, and it is confirmed that the "ίσ number at the time of output shows a change of about double. As mentioned above, by GezTe layer 4 and

CuTe2層5所形成的超晶格,伴隨相變化,電阻値之變化成 為三位數,故適合作為固態記憶體之記錄層。 光學特性係使用波長633nm之雷射,以偏光橢圓率計 測器(ellipsometer)測量後,獲得樣品a (構造a)為3 81 + 3.39j ’而且樣品b (構造B)為3.38 + 4.37j之結果。由 此結果可知,構造B與構造A相比,複折射率大0.98,更 具有金屬特性。此結果與上述電阻値測量結果並無矛盾。 而且,由使用第一原理計算而求得的超晶格構造,亦 證實下列兩點。 •於構造A中,相對於Geju層4中之Ge原子!的鍵結 價數為4價(第1圖之(a)),構造B之Ge原子i的鍵結 價數為6價(第1圖之(b))。 •構造A及構造B之密度各自為7.1〇3g/cm3&7 1〇4g/cm3, 伴隨構造A-構造B間之相變化的密度變化(體積變化)係 為0.02%以下,是非常地小。 如上所述’由Ge^層4及〇^層5所形成的超晶 格伴隨相變化的體積變化係非常地小,故可期待提升記錄 及消去的重複次數。 201238035 〔實施例2〕 使用上述之一般的自我電阻加熱型之基本構成,製作 與本發明有關之固態記憶體(第2圖)。基板係使用Si晶 圓,焦耳熱發生用加熱器15、及上部電極14使用鎢。就記 錄層11而言,使用由Ge2Te2層4及CuTe2層5而成的單位 晶格層疊二十層的超晶格薄膜。記錄層11之膜厚為26nm。 而且,記錄層之晶格的大小為lOOxlOOnm2。 於此固態記憶體之電流路徑20,通電預先藉由程式決 定的波形之電流’檢討貢料之記錄及消去所必要的電流 値、及通電的脈衝時間。 此結果,由構造A至構造B進行相變化時所必要的電 流値為0.1mA,脈衝時間為100ns。另一方面,由構造B 至構造A進行相變化時所必要的電流値為0.5mA,脈衝時 間50ns。藉由連續地流通上述波形之電流於固態記憶體, 測量重複記錄消去次數。其結果,本實施例所使用的固態 記憶體係可能重複記錄消去l〇u次。 〔比較例〕 為了與於記錄層使用的超晶格薄膜之固態記憶體比 較,製作使用具有與實施例2相同構成,且使用GesCuJe* 合金之單層膜(膜厚26nm)作為記錄層12的固態記憶體 100 (第3圖)。晶格的大小為lOOxlOOnm2。 於此固態記憶體之電流路徑20,通電預先藉由程式決 定的波形之電流’檢討育料之記錄及消去所必要的電流 値。另外,通電的脈衝時間與實施例2記載的脈衝時間係 17 201238035 相同。 此結果,由結晶相A至結晶相B進行相變化時所必要 的電流値為0.3mA。另一方面,由結晶相B至結晶相A之 電流値為1.9mA。 其中使用所獲得的電流値、實施例2所使用的脈衝時 間而將連續波形程式化,基於此波形,於相變化RAM通 電,測量重複記錄消去次數。其結果,使用GezCuiTe*合金 之單層膜作為記錄層12的固態記憶體之重複記錄消去次數 為104次。 如此,藉由於記錄層使用由Ge2Te2層及CuTe2層所形 成的超晶格薄膜,證實可作成不含Sb的固態記憶體,與 Ge-Sb-Te系之固態記憶體相較並不遜色。 而且,藉由將固態記憶體之記錄層由GezCi^Te#的單層 膜作成由Ge2Te2薄膜及CuTe2薄膜所形成的超晶格,證實 性能提升,如下所示。 •伴隨相變化之電阻値的變化係變大一位數。 •用以誘發相變化所必要的電流値係於由構造A至構造B 之相變化的情形減少到1 /3,由構造B至構造A之相變化 的情形減少到1M。 •重複記錄消去次數成為1〇7倍。 與本發明有關之固態記憶體係為了解決上述問題,而 具備因物質之相變化而電氣特性會變化的記錄層之固態記 憶體,前述記錄層之特徵為:前述記錄層係藉由鍺及碲所 形成的薄膜、及銅及碲所形成的薄膜層疊而成的超晶格所 18 201238035 構成者。 如此,與本發明有關之固態記憶體,為了提供具有與The superlattice formed by the CuTe2 layer 5 has a three-digit change in resistance 伴随 with phase change, and is suitable as a recording layer of a solid-state memory. The optical characteristics were measured using a laser with a wavelength of 633 nm and measured by a polarized ellipticity meter (ellipsometer) to obtain a sample a (structure a) of 3 81 + 3.39j ' and a sample b (structure B) of 3.38 + 4.37j. . From this result, it is understood that the structure B has a complex refractive index of 0.98 and a metal property as compared with the structure A. This result does not contradict the above resistance 値 measurement results. Moreover, the following two points were confirmed by the superlattice structure obtained by the first principle calculation. • In Structure A, relative to the Ge atoms in Geju Layer 4! The bond valence is 4 (Fig. 1 (a)), and the bond valence of the Ge atom i of the structure B is 6 (Fig. 1 (b)). • The density of the structure A and the structure B are each 7.1 〇 3 g/cm 3 & 7 1 〇 4 g/cm 3 , and the density change (volume change) accompanying the phase change between the structure A and the structure B is 0.02% or less, which is very small. . As described above, the volume change of the superlattice formed by the Ge^ layer 4 and the ruthenium layer 5 with the phase change is extremely small, so that the number of repetitions of recording and erasing can be expected to be improved. [2012] [Embodiment 2] A solid-state memory according to the present invention (Fig. 2) was produced by using the basic configuration of the above-described general self-resistance heating type. The substrate is made of Si crystal, the Joule heat generating heater 15 and the upper electrode 14 are made of tungsten. For the recording layer 11, a superlattice film of twenty layers of a unit lattice formed of a Ge2Te2 layer 4 and a CuTe2 layer 5 was used. The film thickness of the recording layer 11 was 26 nm. Moreover, the size of the crystal lattice of the recording layer is 100 x 100 nm. In the current path 20 of the solid state memory, the current of the waveform determined by the program is pre-charged to review the recording of the tribute and the necessary current 値 and the pulse time of the energization. As a result, the current 値 necessary for the phase change from the configuration A to the configuration B was 0.1 mA, and the pulse time was 100 ns. On the other hand, the current 値 necessary for the phase change from the configuration B to the configuration A is 0.5 mA, and the pulse time is 50 ns. The number of repeated recording erasures is measured by continuously flowing the current of the above waveform to the solid state memory. As a result, the solid-state memory system used in the present embodiment may repeatedly record and erase l〇u times. [Comparative Example] In order to prepare a single layer film (film thickness: 26 nm) having the same configuration as that of Example 2 and using a GesCuJe* alloy as the recording layer 12, in comparison with the solid state memory of the superlattice film used in the recording layer. Solid state memory 100 (Fig. 3). The size of the crystal lattice is lOOxlOOnm2. In the current path 20 of the solid state memory, the current of the waveform determined by the program is pre-charged to review the recording of the feed and eliminate the necessary current 値. Further, the pulse time for energization is the same as the pulse time system 17 201238035 described in the second embodiment. As a result, the current 必要 necessary for the phase change from the crystal phase A to the crystal phase B was 0.3 mA. On the other hand, the current 由 from the crystal phase B to the crystal phase A was 1.9 mA. The continuous waveform was programmed using the obtained current 値 and the pulse time used in the second embodiment, and based on this waveform, the phase change RAM was turned on, and the number of repeated recording erasures was measured. As a result, the number of times of repeated recording and erasing using the single layer film of the GezCuiTe* alloy as the solid state memory of the recording layer 12 was 104 times. Thus, since the superlattice film formed of the Ge2Te2 layer and the CuTe2 layer is used for the recording layer, it is confirmed that the solid-state memory containing no Sb can be made, which is inferior to the solid-state memory of the Ge-Sb-Te system. Further, the performance improvement was confirmed by forming a recording layer of a solid memory from a single layer film of GezCi^Te# into a superlattice formed of a Ge2Te2 film and a CuTe2 film, as shown below. • The change in resistance 伴随 with phase change is a large one-digit number. • The current necessary to induce a phase change is reduced to 1/3 of the phase change from the construction A to the construction B, and the phase change from the construction B to the construction A is reduced to 1 M. • The number of repeated records is 1〇7 times. In order to solve the above problems, a solid-state memory system according to the present invention has a solid-state memory of a recording layer whose electrical characteristics change due to a phase change of a substance, and the recording layer is characterized in that the recording layer is made by a sputum and a sputum A formed film and a superlattice formed by laminating a film formed of copper and tantalum 18 201238035. Thus, the solid memory associated with the present invention is provided with

Ge-Sb-Te系之固態記憶體相較並不遜色的性能之不含% 的固態記憶體,而使用由鍺(Ge)及蹄(Te)所形成的薄 膜(以下,稱為Ge-Te系薄膜)、及由銅(Cu)及。所形 成的薄膜(以下’ Cu_Te系薄膜)之超晶格構造作為固態記 憶體之記錄層。據此,如前述實施例所示,雖然不含Sb, 但與非專敎獻3記載之技術不同,其可充分增大伴隨相 變化的電阻値的變化,同時與將單純以^系之合金薄 膜用於記錄層的固態記憶體作比較,可實現顯著的性能提 升。例如,伴隨由Ge_Te系薄膜及Cu_Te系薄膜所形成的 超晶格構造之相變化的體積變化’如前述實施例所示,係 極小的。伴隨上述相變化的體積變化係於重複資料記錄及 消去時,於包圍記錄層而上下配置的電極#之構造體賦予 力學上的應力。藉由上述應力被重複施加於㈣記情體, ^態記憶财,各層界面之剪斷_轉讀生而被破 壞。因此,伴隨相變化的體積變化極小有助 錄消去重複之壽命。 貝枓5己 如以上所述,依據本發明,可提供具有與以备 ^固態記憶.體相比並不遜色的性能之不含sb_態記憶、 本發m態樣有關的固態記憶體中, 鍺及碲所形成的薄膜為G T薄 ,,_ ^ 2哥聘刖述由銅及硫所形 的薄膜為CuTe2薄膜者較佳。 y 201238035 依據上述之構成,於上述記錄層中,藉由使用由Ge2Te2 薄膜及CuTe2薄膜所形成的層疊構造,在下部電極上可適 當地實現較少的晶格缺陷或晶格歪斜等,且具有調整的周 期構造之超晶格構造。 與本發明之一實施態樣有關之固態記憶體中,前述薄 膜之各個膜厚為〇.5nm以上8nm以下者較佳。 依據上述構成,可更適當地防止於層疊構造途中周期 構造混亂。據此,不論層疊數為何,可成功地實現具有超 晶格構造的記錄層。 與本發明之一實施態樣有關的固態記憶體中,前述由 鍺及碲所形成的薄膜係藉由前述鍺之鍵結原子價作為4價 或6價的狀態而使電阻値變化的方式,藉由前述電阻値, 實現表現資料之記錄狀態或消去狀態者為較佳。 若依據上述構成,由Ge-Te系薄膜及Cu-Te系薄膜所 形成的超晶格構造具有雙安定性,可作成兩種類之結晶構 造。上述兩種類之結晶構造的差異,主要係Ge-Te系薄膜 層中的GeTe層彼此距離的差異,此亦對GeTe層及Cu-Te 層之層間距離有影響。 於上述Ge-Te系薄膜層,GeTe層彼此為鄰近的結晶構 造之情形(參照第1圖之(a)),Ge原子之鍵結原子價為4 價。另一方面,於上述Ge-Te系薄膜層,GeTe層彼此為分 離的結晶構造的情形(參照第1圖之(b)),Ge原子之鍵 結原子價成為6價。 如以上所述,上述兩種類之結晶構造中的相變化,對 20 201238035 於基板面之垂直方向中的Ge原子的結合狀態有影響。上述 Ge-Te系薄膜層之Ge原子藉由相變化由4價至6價,對於 上述超晶格之基板的垂直方向的結合變強,記錄層之電阻 値會大幅減少。 即,上述Ge原子價為4價的情形,對應記錄層之電阻 値為大的狀態,6價的情形,對應記錄層之電阻値為小的狀 態。因此,藉由前述電阻値,可表現資料之記錄狀態或消 去狀態。例如,顯示相異電阻値的2個結晶構造中,藉由 一者指派為資料之記錄狀態,另一者指派為資料之消去狀 態,可將與本發明有關之固態記憶體成功地作為記憶體。 而且,藉由4價及6價鍵結的變異,於垂直方向發生 約0.2%左右的膜厚變化,但遠小於一般使用之由Ge-Sb-Te 所形成的相變化材料合金之10%左右的變化。 與本發明之一實施型態有關之固態記憶體中,藉由檢 測前述電阻値,可成為使資料再生的方式。 依據上述之構成,藉由測量記錄層之電阻値,由其電 阻値大小可檢測記錄層為上述記錄狀態或消去狀態任一者 的狀態。利用此等,可進行自與本發明有關之固態記憶體 進行資料的再生。 於本發明之一實施態樣中的固態記憶體,如前述實施 例所示,實現作成伴隨上述相變化之電阻値變化為充分大 的値。伴隨上述相變化的電阻値之變化大,意指即使將再 生時通電固態記憶體的電流値變小來設定,輸出電壓値之 變化仍為大的。即,以較小的電流値可驅動固態記憶體。 21 藉由驅動電流所產生的焦耳熱對於記錄層及包覆記錄 層的構造體會賦予熱經歷’此熱經歷亦與上述體積變化相 同地,成為破壞固態記憶體的原因。因此,所謂固態記憶 體之驅動電流小者,有助於延長資料記錄消去之重複壽命C 與本發明之-實施型態有關之固態記憶體中,於前述 2鍺及碲所形錢_,㈣於㈣子數,鍺原子數之比 為〇,5以下者較佳。而且,於前述由鋼及締所形成的薄膜, 相對於總原子數的銅原子數之比為G5以下者較佳。、 格構ί據上述之構成,可適當地形成具有雙衫性的超晶 一與本發明之—實施㈣有關之_記㈣係藉 早元而被記錄或消去者為較佳。 匕 依據上述之構成,上述固態記憶體係藉由電能 記錄層之結晶構造相變化,而進行資料的記錄_去使 二彳述固態記憶體係利用上述相變化之結果、利:: 層之電氣躲會變化,可進行資料料生。I己錄 於發明之詳細説明項次中已具體之實 例,絕對僅係為了清楚說明本發明之技術内容% 定於如此具體例而被狹義地解釋,本發明之精:應僅限 載的申請專利範圍内中,可變更每一者來實施。如下記 [產業上之利用可能性] 本發明可利用於電子構件之製造領域。 【圖式簡單説明】 22 201238035 第1圖=示構成與本發明之-實施態樣有關的固態記憶 口己錄層的由Ge2Te2薄膜及薄膜所形成的 :晶格之結晶構造圖。(a)揭示結晶相A之結晶構 ^ 造’揭示結晶相B之結晶構造。 第2圖的曰(a)係揭示與本發明之—實施態樣有關的使用由 超晶格所形成的記錄層之固態記憶體的概略剖面 圖。(b)係揭示構成記錄層之由Ge2Te2薄膜及cuTe2 溥膜所形成的超晶格之概略剖面圖。 第3圖係揭不使用由⑸必心合金所形成的記錄層之固 態記憶體的概略剖面圖。 【元件符號説明】 1 錯(Ge)原子 2 碌(Te)原子 3 銅(Cu)原子 4 Ge2Te2 層 5 CuTe2 層 1〇 、 1〇〇 固態記憶體 11、12 記錄層 13 輸出線 14 上部電極 15 焦耳熱發生用加熱器 16 輸入線 20 電流路徑The solid-state memory of the Ge-Sb-Te system uses a film formed of germanium (Ge) and hoof (Te) compared to a solid memory containing no inferior performance (hereinafter, referred to as Ge-Te). Thin film), and copper (Cu) and. The superlattice structure of the formed thin film (hereinafter, the 'Cu_Te-based thin film) was used as a recording layer of a solid-state memory. Accordingly, as shown in the foregoing embodiment, although Sb is not contained, unlike the technique described in Non-Special Note 3, it is possible to sufficiently increase the change in the resistance 伴随 accompanying the phase change, and at the same time, the alloy which will be simply The film is used for comparison of solid-state memory of the recording layer to achieve significant performance improvement. For example, the volume change of the phase change accompanying the superlattice structure formed of the Ge_Te-based film and the Cu_Te-based film is extremely small as shown in the foregoing embodiment. The volume change accompanying the above-described phase change is a mechanical stress applied to the structure of the electrode # which is disposed above and below the recording layer in the case of repeated data recording and erasing. By the above-mentioned stress being repeatedly applied to the (4) sympathetic body, the state memory is cut, and the shearing of each layer interface is destroyed. Therefore, the small volume change accompanying the phase change helps to eliminate the life of the repetition. Belle 5 has been described above, and according to the present invention, it is possible to provide a solid-state memory having no sb_state memory and a local m-like state which is inferior to the performance of the solid-state memory. The film formed by bismuth and bismuth is thinner than GT, and it is preferred that the film formed by copper and sulfur is a CuTe2 film. y 201238035 According to the above configuration, in the recording layer, by using a laminated structure formed of a Ge2Te2 film and a CuTe2 film, a small lattice defect or lattice skew can be appropriately realized on the lower electrode, and The superlattice structure of the adjusted periodic structure. In the solid state memory according to an embodiment of the present invention, it is preferable that each of the film thicknesses of the film is 〇.5 nm or more and 8 nm or less. According to the above configuration, it is possible to more appropriately prevent the cycle structure from being disordered in the middle of the laminated structure. According to this, the recording layer having the superlattice structure can be successfully realized regardless of the number of layers. In the solid state memory according to an embodiment of the present invention, the film formed of ruthenium and osmium is a method in which the enthalpy of the bond enthalpy is changed to a tetravalent or hexavalent state to change the resistance 値. It is preferable that the recording state or the erasing state of the performance data is realized by the aforementioned resistance 値. According to the above configuration, the superlattice structure formed of the Ge-Te thin film and the Cu-Te thin film has double stability and can be formed into two kinds of crystal structures. The difference in the crystal structures of the above two types is mainly due to the difference in the distance between the GeTe layers in the Ge-Te thin film layer, which also affects the interlayer distance between the GeTe layer and the Cu-Te layer. In the case where the Ge-Te thin film layer and the GeTe layer are adjacent to each other (see Fig. 1(a)), the bond atomic valence of the Ge atom is 4 valence. On the other hand, in the above Ge-Te thin film layer, when the GeTe layers are separated from each other (see Fig. 1(b)), the bond valence of the Ge atom is hexavalent. As described above, the phase change in the crystal structure of the above two types has an influence on the bonding state of Ge atoms in the vertical direction of the substrate surface of 20 201238035. The Ge atom of the Ge-Te thin film layer is tetravalent to hexavalent by a phase change, and the bonding in the vertical direction of the substrate of the superlattice becomes strong, and the electric resistance 记录 of the recording layer is greatly reduced. In other words, when the Ge atom has a valence of 4, the resistance 値 of the recording layer is large, and in the case of hexavalent, the resistance 値 of the recording layer is small. Therefore, by the aforementioned resistance 値, the recording state or the erasing state of the data can be expressed. For example, in the two crystal structures showing the different resistance 値, the solid state memory related to the present invention can be successfully used as the memory by one being assigned as the recording state of the data and the other as the erased state of the data. . Moreover, by the variation of the tetravalent and hexavalent bonds, a film thickness change of about 0.2% occurs in the vertical direction, but is much smaller than about 10% of the phase change material alloy formed by Ge-Sb-Te which is generally used. The change. In the solid state memory according to an embodiment of the present invention, by detecting the aforementioned resistance 値, it is possible to reproduce data. According to the above configuration, by measuring the resistance 値 of the recording layer, the state of the recording layer or the erasing state can be detected by the size of the resistor 値. With these, it is possible to perform reproduction of data from the solid state memory related to the present invention. The solid state memory in one embodiment of the present invention, as shown in the foregoing embodiment, achieves a sufficiently large enthalpy change in the resistance enthalpy accompanying the phase change. The large change in the resistance 伴随 accompanying the above phase change means that the change in the output voltage 仍 is large even if the current 値 of the solid-state memory is reduced when the regeneration is performed. That is, the solid state memory can be driven with a small current. The Joule heat generated by the driving current imparts a thermal history to the recording layer and the structure covering the recording layer. This thermal history is also the same as the volume change described above, which causes destruction of the solid state memory. Therefore, the driving current of the solid-state memory is small, which contributes to prolonging the repeat life of the data recording erasure C. In the solid-state memory related to the embodiment of the present invention, the above-mentioned 2锗 and 碲 are shaped _, (4) In the (four) sub-number, the ratio of the number of germanium atoms is 〇, and those below 5 are preferred. Further, in the film formed of steel and the like, the ratio of the number of copper atoms to the total number of atoms is preferably 5 or less. According to the above configuration, it is preferable to form a super-crystal having a double-shirt property. It is preferable that the _- (four) relating to the invention (4) is recorded or erased by the early element.匕 According to the above configuration, the solid-state memory system records the data by changing the crystal structure of the electric energy recording layer _ to make the second solid-state memory system use the result of the phase change, and the:: electrical hiding of the layer Changes can be made to the data. I have recorded the specific examples in the detailed description of the invention, and are only narrowly explained for the purpose of clearly indicating that the technical content of the present invention is determined to be such a specific example, and the essence of the present invention should be limited to the application. Within the scope of patents, each can be changed to implement. As described below [Industrial Applicability] The present invention can be utilized in the field of manufacturing electronic components. BRIEF DESCRIPTION OF THE DRAWINGS 22 201238035 Fig. 1 shows a crystal structure diagram of a crystal lattice formed of a Ge2Te2 film and a film which constitute a solid state memory recording layer relating to the embodiment of the present invention. (a) revealing the crystal structure of the crystal phase A to reveal the crystal structure of the crystal phase B. Fig. 2(a) is a schematic cross-sectional view showing a solid state memory using a recording layer formed of a superlattice in connection with an embodiment of the present invention. (b) is a schematic cross-sectional view showing a superlattice formed of a Ge2Te2 film and a cuTe2 film constituting a recording layer. Fig. 3 is a schematic cross-sectional view showing the solid state memory of the recording layer formed of (5) a core alloy. [Description of Component Symbols] 1 (Ge) Atom 2 Te (Te) Atom 3 Copper (Cu) Atom 4 Ge2Te2 Layer 5 CuTe2 Layer 1〇, 1〇〇 Solid Memory 11, 12 Recording Layer 13 Output Line 14 Upper Electrode 15 Joule heat generation heater 16 input line 20 current path

Claims (1)

201238035 七、申請專利範圍: 1. 一種固態記憶體’其係具有因物f之㈣化而電特性 化的記錄層之固態記憶體,其特徵為: 一 …該記錄層储由錯及碲卿成的薄膜、及由銅及 形成的薄膜所層疊的超晶格所構成。 2. 如申請專利範圍第1項所述之固態記憶體,其中該由鍺及 蹄所形成的薄膜為Ge2Te2薄膜’該由銅及碲所形成的薄膜 係CuTe2薄膜。 ' 3. 如+申請專利㈣第1項或第2項所狀㈣記憶體,其中 。亥薄膜之個別膜厚為〇.5nm以上8nm以下。 4. 如申請專利範圍第丨項或第2項所述之固態記憶體,其中 該由鍺及碲所形成的薄膜係藉由該鍺之鍵結原子價成為4 價或6價之狀態,而使電阻値產生變化, 藉由該電阻値,而表現資料之記錄狀態或消去狀態。 5. 如申凊專利範圍第4項所述之固態記憶體,其藉由檢測該 電阻値,而使資料再生。 6·如申清專利範圍第1項或第2項所述之固態記憶體,其中 該由鍺及碲所形成的薄膜’鍺原子數相對於總原子數之比 為0.5以下。 7·如申請專利範圍第1項或第2項所述之固態記憶體,其中 該由銅及碲所形成的薄膜,銅原子數相對於總原子數之比 為0.5以下。 8.如申請專利範圍第丨項或第2項所述之固態記憶體,其係 藉由電能單元而被記錄或消去。 24201238035 VII. Patent application scope: 1. A solid-state memory, which is a solid-state memory having a recording layer electrically characterized by the (four) of the material f, which is characterized by: The formed film and the superlattice laminated by copper and the formed film. 2. The solid state memory according to claim 1, wherein the film formed by the enamel and the hoof is a Ge2Te2 film. The film formed of copper and ruthenium is a CuTe2 film. ' 3. For example, if you apply for a patent (4), item 1 or item 2 (4), where. The individual film thickness of the film is 〇5 nm or more and 8 nm or less. 4. The solid memory according to claim 2 or 2, wherein the film formed by the crucible and the crucible is in a state of being a tetravalent or a hexavalent state by the bond valence of the crucible. The resistance 値 is changed, and the recording state or the erasing state of the data is expressed by the resistance 値. 5. The solid state memory of claim 4, wherein the data is regenerated by detecting the resistance enthalpy. 6. The solid state memory according to the first or second aspect of the invention, wherein the ratio of the number of germanium atoms to the total number of atoms formed by the tantalum and niobium is 0.5 or less. 7. The solid memory according to claim 1 or 2, wherein the film formed of copper and bismuth has a ratio of the number of copper atoms to the total number of atoms of 0.5 or less. 8. The solid state memory of claim 2 or 2, which is recorded or erased by a power unit. twenty four
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