WO2012111848A1

WO2012111848A1 - Mixer circuit

Info

Publication number: WO2012111848A1
Application number: PCT/JP2012/054336
Authority: WO
Inventors: 岸本　修也
Original assignee: 日本電気株式会社
Priority date: 2011-02-16
Filing date: 2012-02-16
Publication date: 2012-08-23
Also published as: JPWO2012111848A1; JP5803944B2

Abstract

Provided is a mixer circuit, comprising: a differential motion amplifier (10) which is configured of a one-stage differential motion amplifier transistor pair (111, 112), wherein a first differential motion signal is inputted, and the first differential motion signal is amplified and outputted via first matching circuits (121, 122); a multiplier (20), which is configured of one-stage differential motion switching transistor pairs (211, 212, 213, 214), wherein a second differential motion signal, and the first differential motion signal which the differential motion amplifier has amplified and outputted, are inputted, the first differential motion signal being inputted via second matching circuits (221, 222), the second differential motion signal and the first differential motion signal which the differential motion amplifier has amplified and outputted are multiplied and outputted as a third differential motion signal; and a capacitance coupling unit (30) which connects the first matching circuits of the differential motion amplifier and the second matching circuits of the multiplier, and galvanically isolates the differential motion amplifier and the multiplier. Power is supplied to the differential motion amplifier transistor pair of the differential motion amplifier and the differential motion switching transistor pairs of the multiplier in isolation from one another, thus providing a mixer circuit which operates at low voltage and has strong power saturation and conversion gain.

Description

Mixer circuit

The present invention relates to a mixer circuit that performs frequency conversion, and more particularly to a mixer circuit that operates at a low power supply voltage.

The mixer circuit is a circuit used for up conversion for frequency conversion from low frequency to high frequency and down conversion for frequency conversion from high frequency to low frequency in a communication system. The mixer circuit preferably has high conversion gain and high saturation power, and Gilbert cell mixer circuits are widely used. The conversion gain is the ratio of the signal amplitude at the frequency of the output signal to the signal amplitude at the frequency of the signal input to the mixer circuit. Therefore, the larger the conversion gain, the larger the amplitude of the signal output for the same input signal amplitude.
The Gilbert cell mixer circuit is configured by stacking a constant current circuit, a transistor to which a first signal is input, a transistor to which a second signal is input, and an impedance circuit, between a ground terminal and a power supply voltage terminal. It is done.
Several Gilbert cell mixer circuits are described with reference to the figures.
FIG. 1 is a block diagram showing the configuration of a typical Gilbert cell mixer circuit. This mixer circuit is a mixer circuit on the premise of being used in a device on the receiving side that performs down conversion. Hereinafter, the mixer circuit used in the device on the receiving side will be described.
The Gilbert cell mixer circuit shown in FIG. 1 comprises one differential amplification transistor pair (M2, M3) and a circuit in which two differential switching transistor pairs (M4, M5), (M6, M7) are cross-connected. Connected in series. M1 is a current source transistor. The differential radio frequency signal RF (Radio Frequency) input to + RF and −RF is amplified by the differential amplification transistor pair (M2, M3). The output signal is multiplied by a differential switch transistor pair by a frequency signal LO (Local Oscillator) that is input to + LO and -LO from a local oscillator mounted on a device on the receiving side. As a result, an intermediate frequency signal IF (Intermediate Frequency) of the frequency difference between the respective signals is output to + IF and −IF.
The Gilbert cell mixer circuit shown in FIG. 1 is configured by stacking three stages of transistors. Further, in the Gilbert cell mixer circuit shown in FIG. 1, the current source transistor M1 is omitted, and each source terminal of the transistor pair (M2, M3) is grounded to operate as a mixer circuit of the circuit configuration shown in FIG. You can also.
Patent Document 1 discloses a mixer circuit that operates stably without reducing the gain even under a low power supply voltage (see FIG. 3). The mixer circuit disclosed in Patent Document 1 has a first input signal as one input, and a transistor receiving the first input signal and between two emitter differential pairs for differentially amplifying the second input signal. Is connected to the balun (mutual inductance).
The balun causes a current corresponding to the input signal to be generated at the emitter common node of the first emitter differential pair, and a current in reverse phase to be generated at the emitter common node of the second emitter differential pair. Then, mutually complementary differential currents generated by this balun are used as operating currents of the two emitter differential pairs.
Patent Document 2 discloses a mixer circuit operable at low voltage (see FIG. 4). The mixer circuit disclosed in Patent Document 2 operates even when the power supply voltage is set low by setting the active element formed of transistors to only one stage.
Patent Document 3 discloses an active mixer circuit which operates at low voltage and has low noise and low power consumption (see FIG. 5). The active mixer circuit disclosed in Patent Document 3 includes a voltage-current conversion amplifier, a transformer, and a multiplier, and a transformer is connected between the voltage-current conversion amplifier and the multiplier. This isolates between the voltage-to-current conversion type amplifier and the multiplier for direct current inside the transformer. In addition, the voltage-current conversion type amplifier and the multiplier are respectively configured by vertically stacked single-stage transistors.

JP 2000-315919 A JP, 2008-172601, A JP, 2009-206890, A

In general, a circuit configuration in which transistors are stacked in multiple stages has a problem that the voltage range in which linear operation can be performed is narrow, and the output signal tends to be saturated.
Therefore, in order to increase the saturation power of the output signal, it is necessary to widen the voltage range in which this linear operation is possible. However, in order to widen the voltage range capable of linear operation, the power supply voltage must be increased. On the other hand, in a complementary metal oxide semiconductor (CMOS) that can operate in a high frequency band such as a microwave or a millimeter wave band, the power supply voltage is suppressed to about 1 V, so a sufficiently large power supply voltage can not be applied. It is difficult to obtain saturated power.
In the mixer circuit disclosed in Patent Document 1, a balun is used instead of the current source transistor M1, and the number of transistor stages is reduced. However, the configuration is still such that two stages of transistors are stacked, and the linear operation range is limited by the two stages of transistors.
The mixer circuit disclosed in Patent Document 2 has one transistor stage, and can increase the linear operation range. However, no current flows in the transistor of this circuit, and the conversion gain can not be increased.
The mixer circuit disclosed in Patent Document 3 is a circuit similar to the Gilbert cell mixer circuit shown in FIG. 1 except that a differential amplification transistor pair (M2, M3) and two switching transistor pairs (M4, M5), A transformer is connected between M6 and M7). The middle point of the transformer coil connected to the switching transistor pair side is grounded, and the middle point of the transformer coil connected to the differential amplification transistor pair side is connected to VDD. The LO signal input from the LO terminal is amplified by a differential amplifier configured by a differential amplification transistor pair, input to a multiplier configured by a switching transistor pair through a transformer, and mixed with an RF signal in the multiplier And an IF signal is generated. On the other hand, the power supply voltage is separated by the transformer into the differential amplification transistor pair side and the switching transistor pair side. Therefore, the mixer circuit disclosed in Patent Document 3 can reduce the number of transistor stages, and can improve the saturation characteristics while increasing the conversion gain.
However, it is difficult to design a transformer used in a circuit that handles high frequency bands such as microwaves and millimeter waves, and it is also difficult to match the differential amplification transistor pair and the switching transistor pair only with the transformer. Therefore, even in the mixer circuit disclosed in Patent Document 3, it is difficult to sufficiently transmit the power from the differential amplifier to the multiplier with the transformer alone, and as a result, the conversion gain of the mixer circuit can not be increased. The problem is inherent.
An object of the present invention is to solve the problems as described above, and to provide a mixer circuit which can operate at a low voltage and has high saturation power and conversion gain.

In order to achieve the above object, a mixer circuit according to an aspect of the present invention is formed of a single differential amplification transistor pair, and receives a first differential signal and outputs the first differential signal. A differential amplifier for amplifying and outputting through a first matching circuit, and a differential switching transistor pair in one stage, the second differential signal, and the differential amplifier through a second matching circuit Inputs the first differential signal amplified and output, multiplies the second differential signal and the first differential signal amplified and output by the differential amplifier, and outputs as a third differential signal , And a capacitive coupling unit for connecting the first matching circuit of the differential amplifier and the second matching circuit of the multiplier and DC-wise separating the differential amplifier and the multiplier. And the differential amplification transistor pair of the differential amplifier and the differential of the multiplier Switch ing transistor pair, power independently is characterized in that it is supplied.

According to the present invention, a mixer circuit operating at low voltage and having high saturation power and high conversion gain is realized.

FIG. 2 is a block diagram showing a configuration of a representative Gilbert cell mixer circuit. FIG. 6 is a block diagram showing the configuration of another representative Gilbert cell mixer circuit. It is a block diagram which shows the structure of the mixer circuit disclosed by patent document 1. FIG. FIG. 6 is a block diagram showing a configuration of a mixer circuit disclosed in Patent Document 2. FIG. 6 is a block diagram showing a configuration of a mixer circuit disclosed in Patent Document 3. It is a block diagram showing composition of a mixer circuit concerning a 1st embodiment of the present invention. It is a block diagram showing composition of a mixer circuit concerning a 2nd embodiment of the present invention. It is a figure which shows the effect of the mixer circuit which concerns on the 2nd Embodiment of this invention. It is a block diagram showing composition of a mixer circuit concerning a 3rd embodiment of the present invention. It is a block diagram which shows the structure of the mixer circuit which concerns on the 4th Embodiment of this invention.

An embodiment for carrying out the present invention will be described with reference to the drawings.
FIG. 6 is a block diagram showing the configuration of the mixer circuit according to the first embodiment of the present invention.
Note that the embodiment is an example, and the disclosed apparatus and system are not limited to the configurations of the following embodiments.
The mixer circuit of the first embodiment is configured to include a differential amplifier 10, a multiplier 20, and a capacitive coupling unit 30.
The differential amplifier 10 includes a single differential amplification transistor pair (transistors 111 and 112), receives a first differential signal, amplifies the first differential signal, and generates a first matching circuit. Output via 121 and 122.
The differential signal refers to two signals in opposite phase to each other.
The multiplier 20 is configured of a single-stage differential switching transistor pair (

transistors

211, 212, 213, and 214), and the second differential signal and the first differential signal amplified and output by the differential amplifier 10 are generated. input. At this time, the first differential signal amplified and output by the differential amplifier 10 is input through the

second matching circuits

221 and 222. Then, the multiplier 20 multiplies the second differential signal and the first differential signal amplified and output by the differential amplifier 10 and outputs the result as a third differential signal.
The capacitive coupling unit 30 connects the

first matching circuits

121 and 122 of the differential amplifier 10 and the

second matching circuits

221 and 222 of the multiplier 20 to separate the differential amplifier 10 and the multiplier 20 in a DC manner. Do. That is, the

first matching circuits

121 and 122 of the differential amplifier 10 are connected to the

second matching circuits

221 and 222 of the multiplier 20 via the

capacitors

301 and 302 of the capacitive coupling unit 30, but in terms of direct current It is separated.
The differential amplification transistor pair (transistors 111 and 112) of the differential amplifier 10 and the differential switching transistor pair (

transistors

211, 212, 213, and 214) of the multiplier 20 are independently supplied with power.
The

first matching circuits

121 and 122 have an impedance viewed from the transistor side from the output terminal (the drain terminal in FIG. 6) of each of the

transistors

111 and 112 of the differential amplifier 10 and a multiplier from the capacitive coupling unit 30 on the output side. Match the impedance with the impedance when looking at the 20 side.
In addition, the

second matching circuits

221 and 222 are impedances viewed from the transistor side of the first differential signal input terminal of each transistor of the multiplier 20 and the differential amplifier 10 from the capacitive coupling unit 30 which is the input side. Match the impedance with the impedance when looking at the side. That is, the source terminals of the

transistors

211 and 212 and the

transistors

213 and 214 of the multiplier 20 are input terminals of the first differential signal amplified and output by the differential amplifier 10.
Thus, in the mixer circuit of the first embodiment, the differential amplifier 10 and the multiplier 20 are connected via the

first matching circuits

121 and 122 and the

second matching circuits

221 and 222. ing. Therefore, impedance matching is achieved between differential amplifier 10 and multiplier 20, and the first differential signal power output from differential amplifier 10 to multiplier 20 can be sufficiently transmitted. In the mixer circuit of the first embodiment, the capacitive coupling unit 30 separates the differential amplifier 10 and the multiplier 20 in a direct current manner. The transistors for the operation of the differential amplifier 10 and the multiplier 20 are independently supplied with power. Therefore, the power supply voltage supplied to each of differential amplifier 10 and multiplier 20 can widen the voltage range capable of linear operation even at low voltage, operates at low voltage, and has a high saturation power and high conversion gain. Can be provided.
The

first matching circuits

121 and 122 and the

second matching circuits

221 and 222 may be connected to one another as an example of a configuration in which power is independently supplied to the transistors for operation of the differential amplifier 10 and the multiplier 20, respectively. It is configured as follows. The power supply voltages (VDD) of the

transistors

111 and 112 constituting the differential amplification transistor pair of the differential amplifier 10 are supplied from the

first matching circuits

121 and 122. Further, the

second matching circuits

221 and 222 are configured to have a connection for grounding the current supplied to the

transistors

211, 212, 213 and 214 constituting the differential switching transistor pair of the multiplier 20.
Next, a mixer circuit of a second embodiment will be described.
FIG. 7 is a block diagram showing the configuration of the mixer circuit according to the second embodiment.
The mixer circuit of the second embodiment is configured to include a differential amplifier 11, a multiplier 21, and a capacitive coupling unit 30.
The differential amplifier 11 includes

transistors

111 and 112 forming a differential amplification transistor pair. In each of the

transistors

111 and 112, an

input matching circuit

131 and 132 composed of a transmission line and a capacitor and an

output matching circuit

141 and 142 are connected to the base terminal and the drain terminal, respectively. The

output matching circuits

141 and 142 correspond to the

first matching circuits

121 and 122 in the first embodiment.
The

input matching circuits

131 and 132 perform impedance matching between the impedance viewed from the gate terminal of each of the

transistors

111 and 112 and the impedance of the circuit connected to the input side of the differential amplifier 11. The

input matching circuits

131 and 132 are also circuits for applying the first differential signals (+ SIG1, −SIG1) and the gate bias voltage V1 to the

transistors

111 and 112.
The

output matching circuits

141 and 142 perform impedance matching between the impedance viewed from the drain terminal of each of the

transistors

111 and 112 and the impedance viewed from the capacitive coupling unit 30 to the multiplier 21 side. The

output matching circuits

141 and 142 are also circuits that supply the power supply voltage (VDD) of the

transistors

111 and 112.
As transmission lines and capacitors that constitute each matching circuit, elements of appropriate values are used according to the required impedance.
The multiplier 21 includes

transistors

211, 212, 213, and 214 that constitute a differential switching transistor pair.

Input matching circuits

231 and 232 on the gate terminal side and

input matching circuits

241 and 242 on the source terminal side are connected to the

transistors

211, 212, 213, and 214, respectively. The

input matching circuits

241 and 242 on the source terminal side correspond to the

second matching circuits

221 and 222 in the first embodiment.
The

input matching circuits

231 and 232 on the gate terminal side are impedance matching between the impedance seen from the gate terminal of each of the

transistors

211, 212, 213 and 214 and the impedance of the circuit connected to the input side of the multiplier 21. Plan. The

input matching circuits

231 and 232 on the gate terminal side are also circuits for applying the second differential signals (+ SIG2 and -SIG2) and the gate bias voltage V2 to the

transistors

211, 212, 213 and 214.
The

input matching circuits

241 and 242 on the source terminal side have an impedance when the

transistors

211 and 212 and the

transistors

213 and 214 look at the transistor side from the source terminal, and an impedance when the capacitive coupling portion 30 looks at the differential amplifier 11 side Impedance matching. In addition, the

input matching circuits

241 and 242 on the source terminal side are configured to flow the current supplied from the power supply voltage (VDD) to the

transistors

211, 212, 213 and 214 by grounding.
The differential amplifier 11 and the multiplier 21 are connected by the capacitive coupling unit 30, but the

capacitors

301 and 302 separate the differential amplifier 11 and the multiplier 21 in a direct current manner.
In addition, drain terminals of the

respective transistors

211, 212, 213, and 214 of the multiplier 21 are connected to the power supply voltage (VDD) via the load unit 261 at the connection unit 251 formed of a transmission line, and the third difference Dynamic signals (+ SIG3, -SIG3) are taken out.
The differential amplifier 11 is supplied with the power supply voltage (VDD) from the

output matching circuits

141 and 142, and is applied with the first differential signal (+ SIG1, -SIG1) and the gate bias voltage V1 from the

input matching circuits

131 and 132. . The input first differential signal is amplified by the

transistors

111 and 112, and transmitted to the multiplier 21 through the

capacitors

301 and 302 of the capacitive coupling unit 30. Here, the amplification factor of the differential amplifier 11 is determined by the gate bias voltage V1.
In the multiplier 21, the

input matching circuits

241 and 242 on the source side of the

transistors

211, 212, 213, and 214 that make up the differential switching transistor pair are grounded.
Therefore, the current supplied from the power supply voltage (VDD) to each of the

transistors

211, 212, 213, 214 flows from the

input matching circuit

241, 242 on the source side to the ground. Further, the second differential signals (+ SIG2, -SIG2) and the gate bias voltage V2 are applied to the gate terminals of the

respective transistors

211, 212, 213, 214 from the

input matching circuits

231, 232 on the gate side.
The first differential signal input from the differential amplifier 11 via the capacitive coupling unit 30 is multiplied with the second differential signal by the

transistors

211, 212, 213, and 214 that form a differential switching transistor pair, It is mixed. A signal generated by this mixing is extracted as a third differential signal (+ SIG3, −SIG3) by the load of the load unit 261. Here, the conversion gain of the multiplier 21 is determined by the gate bias voltage V2.
As described above, in the mixer circuit of the second embodiment, the differential amplifier 11 and the multiplier 21 are separated in a direct current by the capacitive coupling unit 30. The differential amplifier 11 is configured to receive supply of operating power of each of the

transistors

111 and 112 from the

output matching circuits

141 and 142. Further, the multiplier 21 is configured to ground the

input matching circuits

241 and 242 on the source side and to flow the current supplied from the power source to the

transistors

211, 212, 213 and 214 to the ground. That is, the power supply voltage is applied independently of each other by the differential amplifier 11 and the multiplier 21.
As a result, the current flowing to each transistor increases, and as a result, the saturation power increases. Further, by the

output matching circuits

141 and 142 of the differential amplifier 11 and the

input matching circuits

241 and 242 of the multiplier 21, impedance matching between the differential amplifier 11 and the multiplier 21 is achieved, and multiplication from the differential amplifier 11 is performed. The signal power output to unit 21 can be sufficiently transmitted.
That is, the second embodiment can provide a mixer circuit which operates at low voltage and has high saturation power and high conversion gain.
FIG. 8 is a diagram showing the effect of the mixer circuit according to the second embodiment. A calculation result 41 in the down conversion operation of the mixer circuit according to the second embodiment and a calculation result 42 in the down conversion operation of the generally used Gilbert cell mixer circuit shown in FIGS.
This is performed by fixing the power of the low frequency LO signal which is the second differential signal and changing the power of the high frequency RF signal which is the first differential signal, and then down converting the third down converted signal. The input-output characteristics which calculated the electric power of IF signal of the intermediate frequency which is a differential signal are represented.
As apparent from FIG. 8, it can be seen that the calculation result 41 has larger output power relative to input power and smaller conversion loss in all operation regions than the calculation result 42. Further, while the saturation power of the calculation result 41 is -5 dBm, the saturation power of the calculation result 42 is -12 dBm.
Thus, the mixer circuit according to the second embodiment has improved conversion loss as saturation output increases.
The load unit 261 of the multiplier 21 generally has a configuration using a resistance element. However, the configuration may have a filter function, including a capacitor and an inductor. That is, in the case of the configuration using the resistance element, the conversion loss is constant and output without depending on the frequency. In the case of the configuration provided with the filter function, it is possible to reduce the conversion loss of the necessary frequency band and increase the conversion loss of the signal of the unnecessary frequency band for output.
Next, a third embodiment will be described.
FIG. 9 is a block diagram showing a configuration of a mixer circuit according to a third embodiment of the present invention.
The mixer circuit of the third embodiment is configured to include a differential amplifier 12, a multiplier 22 and a capacitive coupling unit 30.
The differential amplifier 12 includes

transistors

111 and 112,

input matching circuits

131 and 132 including a transmission line and a capacitor are connected to gate terminals, and

output matching circuits

151 and 152 are connected to drain terminals. The

output matching circuits

151 and 152 correspond to the

first matching circuits

121 and 122 in the first embodiment. The differential amplifier 12 differs in the configuration of the differential amplifier 11 and the output matching circuit in the second embodiment. The

output matching circuits

151 and 152 are configured to include a transmission line, a capacitor and an inductor.
The

input matching circuits

131 and 132 have the same configuration as the input matching circuit of the differential amplifier 11 in the second embodiment. That is, the

input matching circuits

transistors

111 and 112 and the impedance of the circuit connected to the input side of the differential amplifier 12. The

input matching circuits

transistors

111 and 112.
The

output matching circuits

151 and 152 have a configuration in which the transmission line to which a voltage is applied in the output matching circuit of the differential amplifier 11 in the second embodiment is changed to an inductor. The

output matching circuits

151 and 152 perform impedance matching between the impedance viewed from the drain terminal of the

transistors

111 and 112 and the impedance viewed from the capacitive coupling unit 30 to the multiplier 22. The

output matching circuits

151 and 152 are also circuits that supply the power supply voltage (VDD) of the

transistors

111 and 112.
As transmission lines and capacitors that constitute each matching circuit, elements of appropriate values are used according to the required impedance.
The multiplier 22 includes

transistors

211, 212, 213, and 214 that form a differential switching transistor pair. The

input matching circuits

231 and 232 on the gate terminal side and the

input matching circuits

271 and 272 on the source terminal side are connected to the

transistors

211, 212, 213, and 214, respectively. The

input matching circuits

271 and 272 on the source terminal side correspond to the

second matching circuits

221 and 222 in the first embodiment. The multiplier 22 is different from the multiplier 21 in the second embodiment in the configuration of the input matching circuit on the source terminal side. The

input matching circuits

271 and 272 on the source terminal side are configured to include a transmission line and an inductor.
The

input matching circuits

231 and 232 on the gate terminal side have the same configuration as the input matching circuit on the gate terminal side of the multiplier 21 in the second embodiment. That is, in the

input matching circuits

231 and 232 on the gate terminal side, the impedance seen from the gate terminal of each of the

transistors

211, 212, 213, and 214 and the impedance of the circuit connected to the input side of the multiplier 22. Make impedance matching. The

input matching circuits

transistors

211, 212, 213 and 214.
The

input matching circuits

271 and 272 on the source terminal side are configured such that the transmission line grounded in the input matching circuit on the source terminal side of the multiplier 21 in the second embodiment is changed to an inductor.
The

input matching circuits

271 and 272 on the source terminal side have an impedance as viewed from the source terminals of the

transistors

211, 212, 213, and 214, and an impedance as viewed from the capacitive coupling unit 30 to the differential amplifier 12 side. Make impedance matching. The

input matching circuits

271 and 272 on the source terminal side ground the power supply voltage (VDD) supplied to the

transistors

211, 212, 213 and 214.
The differential amplifier 12 and the multiplier 22 are connected by the capacitive coupling unit 30, but the

capacitors

301 and 302 separate the differential amplifier 12 and the multiplier 22 in a direct current manner.
As described above, in the mixer circuit of the third embodiment, the

output matching circuits

151 and 152 of the differential amplifier 12 and the

input matching circuits

271 and 272 on the source terminal side of the multiplier 22 are configured to use inductors, respectively. There is. The differential amplifier 12 and the multiplier 22 are inductively coupled by the mutual inductances of these inductors.
In addition, drain terminals of the

respective transistors

211, 212, 213, and 214 of the multiplier 22 are connected to the power supply voltage (VDD) via the load unit 261 at the connection unit 251 formed of a transmission line, and the third difference Dynamic signals (+ SIG3, -SIG3) are taken out.
The differential amplifier 12 is supplied with the power supply voltage (VDD) from the

output matching circuits

151 and 152, and is applied with the first differential signal (+ SIG1, -SIG1) and the gate bias voltage V1 from the

input matching circuits

131 and 132. . The input first differential signal is amplified by the

transistors

111 and 112 and multiplied by the

capacitors

301 and 302 of the capacitive coupling unit 30 and the inductors of the

output matching circuits

151 and 152 and the inductors of the

input matching circuits

271 and 272. To the vessel 22. Here, the amplification factor of the differential amplifier 12 is determined by the gate bias voltage V1.
In the multiplier 22, the

input matching circuits

271 and 272 on the source side of the

transistors

211, 212, 213, and 214 forming the differential switching transistor pair are grounded.
Therefore, the current supplied from the power supply voltage (VDD) to each transistor flows from the

input matching circuits

271 and 272 at the source terminal side to the ground. A second differential signal (+ SIG2, -SIG2) and a gate bias voltage V2 are applied to the gate terminals of the

transistors

211, 212, 213, and 214 from the

input matching circuit

231, 232 on the gate terminal side.
The first differential signal input from the differential amplifier 12 via the capacitive coupling portion 30 and the mutual inductance is multiplied with the second differential signal by the

transistors

211, 212, 213, and 214 that constitute the differential switching transistor pair. And be mixed. A signal generated by this mixing is extracted as a third differential signal (+ SIG3, −SIG3) by the load of the load unit 261. Here, the conversion gain of the multiplier 20 is determined by the gate bias voltage V2.
As described above, in the mixer circuit of the third embodiment, the differential amplifier 12 and the multiplier 22 are DC-separated by the capacitive coupling unit 30, and the differential amplifier 12 and the multiplier 22 have mutual inductance Is configured to be inductively coupled. Then, the differential amplifier 12 receives the supply of operating power of each transistor from the

output matching circuits

151 and 152, and the multiplier 22 grounds the

input matching circuits

271 and 272 on the source terminal side to connect the power transistors to the respective transistors. The supplied current is supplied to the ground. That is, the configuration enables control to increase or decrease the amount of signal transmitted from differential amplifier 12 to multiplier 22 according to the frequency, and differential amplifier 12 and multiplier 22 respectively. The power supply voltage is applied independently.
As a result, the current flowing to each transistor increases, and as a result, the saturation power increases. Further, the

output matching circuits

151 and 152 of the differential amplifier 12 and the

input matching circuits

271 and 272 of the multiplier 22 achieve impedance matching between the differential amplifier 12 and the multiplier 22, and multiplication from the differential amplifier 12 is performed. The signal power output to unit 22 can be sufficiently transmitted. That is, the third embodiment can provide a mixer circuit which operates at a low voltage and has high saturation power and high conversion gain.
Subsequently, a fourth embodiment will be described.
FIG. 10 is a block diagram showing a configuration of a mixer circuit according to a fourth embodiment of the present invention.
The mixer circuit of the fourth embodiment is configured to include a differential amplifier 11, a multiplier 23, and a capacitive coupling unit 30. That is, in the mixer circuit of the fourth embodiment, the multipliers are different in the mixer circuit of the second embodiment.
The multiplier 23 is different in the configuration of the load unit 271 to which the drain terminals of the

respective transistors

211, 212, 213, and 214 constituting the differential switching transistor pair are connected. An output matching circuit for the drain terminals of the

transistors

211, 212, 213, and 214 is formed by the transmission line and the capacitor that constitute the load portion 271 and the connection portion 251.
The differential amplifier 11 is supplied with the power supply voltage (VDD) from the

output matching circuits

input matching circuits

131 and 132. . The input first differential signal is amplified by the

transistors

111 and 112 and transmitted to the multiplier 23 through the

capacitors

301 and 302 of the capacitive coupling unit 30.
In the multiplier 23, the

input matching circuits

241 and 242 on the source side of the

transistors

211, 212, 213, and 214 that make up the differential switching transistor pair are grounded.
Therefore, the current supplied from the power supply voltage (VDD) to each transistor flows from the

input matching circuits

241 and 242 on the source side to the ground. A second differential signal (+ SIG2, -SIG2) and a gate bias voltage V2 are applied to the gate terminals of the

transistors

211, 212, 213, 214 from the

input matching circuits

transistors

211, 212, 213, and 214, and mixed. A signal generated by this mixing is taken out as a third differential signal (+ SIG3, -SIG3) by the output matching circuit formed by the load unit 271 and the connection unit 251.
As described above, in the mixer circuit of the fourth embodiment, the differential amplifier 11 and the multiplier 23 are separated in a direct current by the capacitive coupling unit 30. Then, the differential amplifier 11 receives supply of operating power of each transistor from the

output matching circuits

141 and 142, and the multiplier 23 grounds the

input matching circuits

241 and 242 on the source side and supplies power to each transistor from the power supply. The configuration is such that the current is supplied to the ground. That is, the power supply voltage is applied independently of each other by the differential amplifier 11 and the multiplier 23.
As a result, the current flowing to each transistor increases, and as a result, the saturation power increases. Further, by the

output matching circuits

141 and 142 of the differential amplifier 11 and the

input matching circuits

241 and 242 of the multiplier 23, impedance matching between the differential amplifier 11 and the multiplier 23 is achieved, and multiplication from the differential amplifier 11 is performed. The signal power output to the converter 23 can be sufficiently transmitted. That is, the fourth embodiment can provide a mixer circuit which operates at low voltage and has high saturation power and high conversion gain.
Furthermore, in the mixer circuit of the fourth embodiment, the signal generated by mixing is extracted from the output matching circuit on the drain terminal side of the

transistors

211, 212, 213, and 214 that constitute the differential switching transistor pair of the multiplier 23. It has become. Therefore, the frequency necessary for the output signal generated by mixing can be finely tuned and output. In particular, the mixer circuit of the fourth embodiment is a configuration suitable for a mixer circuit of a device on the transmission side that needs to be up-converted to obtain an output signal with a high frequency.
Although the above description has been made by taking the field effect transistor as an example, it may be a configuration using a bipolar transistor. In that case, the source is replaced with the emitter and the drain is replaced with the collector.
Although the present invention has been described above with reference to the embodiments, the present invention is not limited to the above embodiments. The configurations and details of the present invention can be modified in various ways that can be understood by those skilled in the art within the scope of the present invention.
This application claims priority based on Japanese Patent Application No. 2011-031046 filed Feb. 16, 2011, the entire disclosure of which is incorporated herein.

Claims

A differential amplifier configured of a single-stage differential amplification transistor pair, which receives a first differential signal, amplifies the first differential signal, and outputs the amplified signal via a first matching circuit;
A second differential signal and the first differential signal amplified and output by the differential amplifier through a second matching circuit, which is constituted by a single-stage differential switching transistor pair, are input; A multiplier that multiplies the first differential signal amplified by the differential amplifier and outputs the result as a third differential signal;
A capacitive coupling unit that connects the first matching circuit of the differential amplifier and the second matching circuit of the multiplier and separates the differential amplifier and the multiplier in a DC manner;
A mixer circuit characterized in that power is supplied to the differential amplification transistor pair of the differential amplifier and the differential switching transistor pair of the multiplier independently.
The power supply voltage of the differential amplification transistor pair of the differential amplifier is supplied from the first matching circuit, and the second matching circuit grounds the current supplied to the differential switching transistor pair of the multiplier. The mixer circuit of claim 1 having a connection.
Each of the first matching circuit and the second matching circuit includes a conductor as a circuit element, and the first matching circuit and the second matching circuit are inductively coupled by the mutual inductance of the conductor. The mixer circuit according to claim 2, characterized in that:
A first input matching circuit connected to respective input terminals of the differential amplification transistor pair of the differential amplifier to which the first differential signal is input, and applying the first differential signal and a bias voltage; ,
A second input matching circuit connected to each input terminal of the differential switching transistor pair of the multiplier to which the second differential signal is input, for applying the second differential signal and a bias voltage; The mixer circuit according to any one of claims 1 to 3, further comprising:
The mixer circuit according to claim 4, wherein the third differential signal is output through a load unit having a filter function including a capacitor and an inductor.
The third differential signal is output through an output matching circuit composed of a transmission line and a capacitor connected to the output terminal of the differential switching transistor pair of the multiplier. The mixer circuit according to 4.