JP2008252284A - High frequency receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a circuit area, to eliminate the influence of a DC cut capacitor on frequency characteristics, and to provide sufficient gain and saturation characteristics. <P>SOLUTION: The high frequency receiver includes: a mixing circuit 4 directly DC-connected in parallel with load resistors 3a and 3b, for mixing first and second LO signals and first and second RF amplified by a differential variable gain low noise amplifier 2 and down-converting the first and second RF signals to first and second BB signals; and a current value setting circuit 10 constituting a current mirror with respect to the mixing circuit 4 and the load resistors 3a and 3b and for setting the value of a current flowing through the mixing circuit 4. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a high-frequency receiver that mixes a high-frequency signal with a local oscillation signal and down-converts the high-frequency signal into a baseband signal.

A conventional high-frequency receiver is disclosed in Non-Patent Document 1 below, for example.
FIG. 5 is a block diagram showing a high-frequency receiver disclosed in Non-Patent Document 1 below.
In the figure, a differential variable gain low noise amplifier 100 amplifies a differential RF signal which is a differential high frequency signal.
The mixing circuit 200 mixes a differential LO signal, which is a differential local oscillation signal, and a differential RF signal amplified by the differential variable gain low noise amplifier 100, and uses the differential RF signal as a differential baseband signal. Down-converted to a differential BB signal.

Next, the operation will be described.
The differential RF signals input from the differential RF signal input terminals 101a and 101b are amplified by the n-type MOS transistors 102a and 102b of the differential variable gain low noise amplifier 100, and then the gain-switching n-type MOS transistors 103a and 103b are connected. Control is performed by a control signal input from the control terminal 105 of the gain switching n-type MOS transistor so that a desired gain can be obtained at 103b, 104a, and 104b.

The differential RF signal amplified by the differential variable gain low noise amplifier 100 is input to the sources of the p-type MOS transistors 201a, 201b, 202a, 202b of the mixing circuit 200 through the DC cut capacitors 150a, 150b.
The p-type MOS transistors 201a, 201b, 202a, and 202b switch in accordance with the differential LO signal to down-convert the differential RF signal into a differential BB signal.
That is, the differential RF signal is down-converted to the difference frequency between the differential RF signal and the differential LO signal, and a differential BB signal is output.

In this high frequency receiver, the current flowing through the p-type MOS transistors 201a, 201b, 202a, 202b of the mixing circuit 200 is determined by the constant current sources 203a, 203b controlled by the bias signal input from the control terminals 204a, 204b. The flicker noise is known to be proportional to the current flowing through the p-type MOS transistors 201a, 201b, 202a, 202b.
However, the differential RF signal is sent from the differential variable gain low noise amplifier 100 through the DC cut capacitors 150a and 150b to the constant current sources 203a and 203b of the mixing circuit 200 and the p-type MOS transistors 201a, 201b, 202a and 202b. Therefore, if the current flowing through the p-type MOS transistors 201a, 201b, 202a, 202b is reduced, the saturation characteristic of the mixing circuit 200 is lowered, and it is difficult to obtain the saturation characteristic of the high-frequency receiver. May be.

“A Compact Dual-Band Direct-Conversion CMOS Transceiver for 802.11a / b / g WLAN”, ISSCC2005 Dig. Tech. Papers, pp.98-99, Feb., 2005

Since the conventional high-frequency receiver is configured as described above, when the current flowing through the p-type MOS transistors 201a, 201b, 202a, and 202b is reduced, the saturation characteristic of the mixing circuit 200 is lowered, and the saturation characteristic of the high-frequency receiver is reduced. There is a problem that sometimes becomes difficult to obtain.
In addition, since the constant current sources 203a and 203b are provided between the power supply VDD and the sources of the p-type MOS transistors 201a, 201b, 202a, and 202b, the number of circuit elements constituting the constant current sources 203a and 203b increases. There was a problem that the area became large.
Since the differential variable gain low noise amplifier 100 and the mixing circuit 200 are connected via DC cut capacitors 150a and 150b having sufficiently low impedance at the frequency of the differential RF signal, the DC cut capacitors 150a and 150b are connected. There is a problem that the circuit area increases by the amount of the circuit element.

Furthermore, the frequency characteristics of the DC cut capacitors 150a and 150b may be affected.
Also, DC cut capacitors 150a and 150b are connected between the differential variable gain low noise amplifier 100 and the mixing circuit 200, and constant current sources 203a and 203b are connected to the input side of the mixing circuit 200. The parasitic capacitance of the element is added. Therefore, there is a problem that the impedance between the differential variable gain low noise amplifier 100 and the mixing circuit 200 becomes low and it is difficult to obtain the gain of the high frequency receiver.

  The present invention has been made to solve the above-described problems, and eliminates the constant current source of the mixing circuit and the DC cut capacitor between the stages of the differential variable gain low noise amplifier and the mixing circuit, thereby reducing the circuit area. An object of the present invention is to obtain a high-frequency receiver capable of reducing the size, eliminating the influence of the frequency characteristics due to the DC cut capacitor, and obtaining sufficient gain and saturation characteristics.

  The high frequency receiver according to the present invention is connected to the first and second loads in parallel, and the first and second local oscillation signals which are differential signals and the first and second amplified by the differential amplifier. A mixing circuit that mixes the high-frequency signals and down-converts the first and second high-frequency signals into the first and second baseband signals and a current mirror for the mixing circuit and the load are configured to flow through the mixing circuit. A current value setting circuit for setting a current value is provided.

  According to this invention, the first and second high frequency signals amplified by the differential amplifier and the first and second local oscillation signals which are connected in parallel with the first and second loads are differential signals. A mixing circuit that mixes and down-converts the first and second high-frequency signals into the first and second baseband signals and a current mirror for the mixing circuit and the load are configured, and the value of the current flowing through the mixing circuit Therefore, the circuit area can be reduced and the influence of the frequency characteristic due to the DC cut capacitor can be eliminated. In addition, there is an effect that sufficient gain and saturation characteristics can be obtained.

Embodiment 1 FIG.
1 is a block diagram showing a high-frequency receiver according to Embodiment 1 of the present invention. In the figure, a differential RF signal input terminal 1a is a terminal for inputting a first RF signal (first high-frequency signal). The differential RF signal input terminal 1b is a terminal for inputting a second RF signal (second high frequency signal).
Note that the first RF signal is a differential positive-phase signal, and the second RF signal is a differential negative-phase signal.
The differential variable gain low noise amplifier 2 amplifies the first and second RF signals input from the differential RF signal input terminals 1a and 1b.

The load resistor 3a is a first load connected between the differential variable gain low noise amplifier 2 and the power supply VDD, and sets the gain of the first RF signal amplified by the differential variable gain low noise amplifier 2. It is an element to do.
The load resistor 3b is a second load connected between the differential variable gain low noise amplifier 2 and the power supply VDD, and sets the gain of the second RF signal amplified by the differential variable gain low noise amplifier 2. It is an element to do.

The mixing circuit 4 is directly connected in direct current in parallel with the load resistors 3a and 3b, and the first and second LO signals (first and second local oscillation signals) which are differential signals and the differential variable gain are low. The first and second RF signals amplified by the noise amplifier 2 are mixed, and the first and second RF signals are reduced to the first and second BB signals (first and second baseband signals). Convert.
The first LO signal is a differential positive-phase signal, and the second LO signal is a differential negative-phase signal.
The first BB signal is a differential positive-phase signal, and the second BB signal is a differential negative-phase signal.

The differential LO signal input terminal 5a is a terminal for inputting a first LO signal, and the differential LO signal input terminal 5b is a terminal for inputting a second LO signal.
The p-type MOS transistor 6a is a first transistor that receives the first RF signal amplified by the differential variable gain low noise amplifier 2 from the source and performs switching according to the first LO signal input from the gate.
The p-type MOS transistor 6b is a second transistor that receives the first RF signal amplified by the differential variable gain low noise amplifier 2 from the source and performs switching according to the second LO signal input from the gate.

The p-type MOS transistor 7a is a third transistor that receives the second RF signal amplified by the differential variable gain low noise amplifier 2 from the source and performs switching according to the first LO signal input from the gate.
The p-type MOS transistor 7b is a fourth transistor that receives the second RF signal amplified by the differential variable gain low noise amplifier 2 from the source and switches in accordance with the second LO signal input from the gate.

The output load resistor 8a is a first output load resistor having one end connected to the drains of the p-type MOS transistors 6a and 7b and the other end grounded.
The output load resistor 8b is a second output load resistor having one end connected to the drains of the p-type MOS transistors 6b and 7a and the other end grounded.
The differential BB signal output terminal 9a is a terminal to which the drains of the p-type MOS transistors 6a and 7b are connected to output the first BB signal.
The differential BB signal output terminal 9b is connected to the drains of the p-type MOS transistors 6b and 7a and outputs a second BB signal.

The current value setting circuit 10 constitutes a current mirror for the mixing circuit 4 and the load resistors 3a and 3b (the portion surrounded by a dotted line in the drawing constitutes the current mirror circuit 20). The value of the current flowing through the type MOS transistors 6a, 6b, 7a, 7b is set.
The isolation resistor 11a is a first isolation resistor having one end connected to the gates of the p-type MOS transistors 6a and 7a.
The isolation resistor 11b is a second isolation resistor having one end connected to the gates of the p-type MOS transistors 6b and 7b.

The reference resistor 12 has one end connected to the power supply VDD and the other end connected to the source of the p-type MOS transistor 13.
The p-type MOS transistor 13 is a fifth transistor whose source is connected to the other end of the reference resistor 12, and whose gate and drain are connected to the other ends of the isolation resistors 11a and 11b.

The current mirror circuit 14 is connected between the constant current source 17 and the ground, and includes two n-type MOS transistors 15 and 16.
The n-type MOS transistor 15 has a drain connected to the gate and drain of the p-type MOS transistor 13, and a source grounded.
The gate and drain of the n-type MOS transistor 16 are connected to the gate of the n-type MOS transistor 15 and the constant current source 17, and the source is grounded.

Next, the operation will be described.
When the first and second RF signals are input from the differential RF signal input terminals 1a and 1b, the differential variable gain low noise amplifier 2 sets the first and second RF signals by the load resistors 3a and 3b. Amplifies the gain.

When the differential variable gain low noise amplifier 2 amplifies the first and second RF signals, the mixing circuit 4 receives the amplified first and second RF signals and the differential LO signal input terminals 5a and 5b. The first and second LO signals are mixed, and the first and second RF signals are down-converted into first and second BB signals.
The specific operation of the mixing circuit 4 is as follows.

The first RF signal amplified by the differential variable gain low noise amplifier 2 is input to the sources of the p-type MOS transistors 6a and 6b, and the second RF signal amplified by the differential variable gain low noise amplifier 2 is Are input to the sources of the p-type MOS transistors 7a and 7b.
When the first RF signal amplified by the differential variable gain low noise amplifier 2 is input from the source to the p-type MOS transistor 6a, the p-type MOS transistor 6a performs switching according to the first LO signal input from the gate, thereby A signal having a frequency difference between the frequency of the RF signal and the frequency of the first LO signal is output from the drain.
Further, when the second RF signal amplified by the differential variable gain low noise amplifier 2 is input from the source to the p-type MOS transistor 7b, the p-type MOS transistor 7b is switched according to the second LO signal input from the gate, thereby A signal having a frequency difference between the frequency of the second RF signal and the frequency of the second LO signal is output from the drain.
As a result, the first BB signal, which is the sum of the signal output from the drain of the p-type MOS transistor 6a and the signal output from the drain of the p-type MOS transistor 7b, is output from the differential BB signal output terminal 9a. The

When the first RF signal amplified by the differential variable gain low noise amplifier 2 is input from the source to the p-type MOS transistor 6b, the p-type MOS transistor 6b performs switching according to the second LO signal input from the gate, thereby A signal having a frequency difference between the frequency of the RF signal and the frequency of the second LO signal is output from the drain.
Further, when the second RF signal amplified by the differential variable gain low noise amplifier 2 is input from the source to the p-type MOS transistor 7a, the p-type MOS transistor 7a is switched according to the first LO signal input from the gate. A signal having a frequency difference between the frequency of the RF signal 2 and the frequency of the first LO signal is output from the drain.
As a result, the second BB signal, which is the sum of the signal output from the drain of the p-type MOS transistor 6b and the signal output from the drain of the p-type MOS transistor 7a, is output from the differential BB signal output terminal 9b. The

Here, the flicker noise in the high-frequency receiver of FIG. 1 is proportional to the current flowing through the p-type MOS transistors 6a, 6b, 7a, 7b of the mixing circuit 4.
In the first embodiment, the current value setting circuit 10 sets the value of the current flowing through the p-type MOS transistors 6a, 6b, 7a, 7b of the mixing circuit 4.
That is, with reference to the current flowing through the p-type MOS transistor 13, the resistance value of the reference resistor 12, the transistor size of the p-type MOS transistor 13, the resistance values of the load resistors 3a and 3b, and the p-type MOS transistors 6a and 6b , 7a, 7b, the current proportional to the transistor size is folded, and the folded current flows through the p-type MOS transistors 6a, 6b, 7a, 7b as the current mirror circuit 20 current.

The current flowing through the p-type MOS transistor 13 is supplied from the n-type MOS transistor 15 constituting the current mirror circuit 14.
The current flowing through the n-type MOS transistor 15 is a current supplied from the constant current source 17. That is, the current proportional to the transistor size of the n-type MOS transistors 15 and 16 is folded based on the current flowing through the n-type MOS transistor 16, and the folded current flows through the n-type MOS transistor 15.

  Therefore, in the current value setting circuit 10, the current flowing through the p-type MOS transistors 6a, 6b, 7a, 7b of the mixing circuit 4 is set by appropriately setting the resistance value of the reference resistor 12 and the resistance values of the load resistors 3a, 3b. Therefore, it is not necessary to mount the constant current sources 203a and 203b as in the conventional example (see FIG. 5).

  As apparent from the above, according to the first embodiment, the direct current is directly connected in parallel with the load resistors 3a and 3b, and is amplified by the first and second LO signals and the differential variable gain low noise amplifier 2. The mixing circuit 4 that mixes the first and second RF signals and downconverts the first and second RF signals into the first and second BB signals, and the mixing circuit 4 and the load resistors 3a and 3b. Since the current mirror is configured and the current value setting circuit 10 for setting the value of the current flowing through the mixing circuit 4 is provided, the circuit area can be reduced and the frequency characteristics by the DC cut capacitor can be achieved. The effect which can eliminate the influence of is produced. In addition, there is an effect that sufficient gain and saturation characteristics can be obtained.

That is, the current value setting circuit 10 does not need to be equipped with the constant current sources 203a and 203b as in the conventional example, so that the circuit area can be made smaller than in the conventional example.
Since there is no need to connect the differential variable gain low noise amplifier 2 and the mixing circuit 4 via the DC cut capacitors 150a and 150b as in the conventional example, the circuit area can be made smaller than in the conventional example. it can.
Further, since there are no DC cut capacitors 150a and 150b, there is no influence of the frequency characteristics of the DC cut capacitors 150a and 150b.

Further, unlike the conventional example, since the constant current sources 203a and 203b and the DC cut capacitors 150a and 150b are not mounted, the parasitic capacitance due to the circuit elements between the stages of the differential variable gain low noise amplifier 2 and the mixing circuit 4 is reduced. Can be reduced. For this reason, it becomes easy to obtain the gain of the high frequency receiver.
In addition, since the high impedance mixing circuit 4 is directly connected in direct current in parallel with the load resistors 3a and 3b of the differential variable gain low noise amplifier 2, the current flowing through the p-type MOS transistors 6a, 6b, 7a and 7b is reduced. Even if it is narrowed down, the saturation characteristics of the high-frequency receiver can be easily obtained.

  In the first embodiment, the mixing circuit 4 and the current value setting circuit 10 are configured using MOS transistors. However, the mixing circuit 4 and the current value setting circuit 10 are configured using bipolar transistors. It may be.

Embodiment 2. FIG.
FIG. 2 is a block diagram showing a high frequency receiver according to Embodiment 2 of the present invention. In the figure, the same reference numerals as those in FIG.
The load inductor 31a is a first load connected between the differential variable gain low noise amplifier 2 and the power supply VDD, and sets the gain of the first RF signal amplified by the differential variable gain low noise amplifier 2. It is an element to do.
The load inductor 31b is a second load connected between the differential variable gain low noise amplifier 2 and the power supply VDD, and sets the gain of the second RF signal amplified by the differential variable gain low noise amplifier 2. It is an element to do.

  The current value setting circuit 32 constitutes a current mirror for the mixing circuit 4 and the load inductors 31a and 31b (the portion surrounded by a dotted line in the drawing constitutes the current mirror circuit 20). The values of the currents flowing through the type MOS transistors 6a, 6b, 7a and 7b are set. Unlike the current value setting circuit 10 of FIG. 1, the reference resistor 12 is omitted, and the source of the p-type MOS transistor 13 is connected to the power supply VDD. Connected directly.

Next, the operation will be described.
In the first embodiment, the load resistors 3a and 3b function as the load of the differential variable gain low noise amplifier 2. However, since the load inductors 31a and 31b have sufficiently high impedance at high frequencies, It functions as a load of the dynamic variable gain low noise amplifier 2.
On the other hand, in terms of direct current, the resistance values of the load inductors 31a and 31b are so small that they are almost negligible. .
Therefore, in the second embodiment, it is not necessary to arrange the reference resistor 12 between the p-type MOS transistor 13 that is a reference for folding the current mirror circuit 20 and the power supply VDD.
Others are the same as those in the first embodiment, and the description thereof is omitted.

  As apparent from the above, according to the second embodiment, the direct current is directly connected in parallel with the load inductors 31a and 31b, and is amplified by the first and second LO signals and the differential variable gain low noise amplifier 2. The mixing circuit 4 that mixes the first and second RF signals and downconverts the first and second RF signals into the first and second BB signals, and the mixing circuit 4 and the load resistors 3a and 3b. Since the current mirror is configured and the current value setting circuit 32 for setting the value of the current flowing through the mixing circuit 4 is provided, the circuit area can be reduced and the frequency characteristics by the DC cut capacitor can be achieved. The effect which can eliminate the influence of is produced. In addition, there is an effect that sufficient gain and saturation characteristics can be obtained.

Embodiment 3 FIG.
FIG. 3 is a block diagram showing a high-frequency receiver according to Embodiment 3 of the present invention. In the figure, the same reference numerals as those in FIG.
However, in the third embodiment, the mixing circuit 4 constitutes a first mixing circuit, and the current value setting circuit 32 constitutes a first current value setting circuit.
The mixing circuit 41 which is the second mixing circuit is directly connected in direct current in parallel with the load inductors 31a and 31b, and the third and fourth LO signals (third and fourth local oscillation signals) which are differential signals. ) And the first and second RF signals amplified by the differential variable gain low noise amplifier 2, and the first and second RF signals are mixed with the third and fourth BB signals (third and fourth). Down-convert to the baseband signal).
The third LO signal is a differential positive-phase signal, and the fourth LO signal is a differential negative-phase signal. The third and fourth LO signals are signals that are 90 ° out of phase with the first and second LO signals.
The third BB signal is a differential positive-phase signal, and the fourth BB signal is a differential negative-phase signal.

The differential LO signal input terminal 42a is a terminal for inputting a third LO signal, and the differential LO signal input terminal 42b is a terminal for inputting a fourth LO signal.
The p-type MOS transistor 43a is a first transistor that receives the first RF signal amplified by the differential variable gain low noise amplifier 2 from the source and switches in accordance with the third LO signal input from the gate.
The p-type MOS transistor 43b is a second transistor that receives the first RF signal amplified by the differential variable gain low noise amplifier 2 from the source and switches in accordance with the fourth LO signal input from the gate.

The p-type MOS transistor 44a is a third transistor that receives the second RF signal amplified by the differential variable gain low noise amplifier 2 from the source and switches in accordance with the third LO signal input from the gate.
The p-type MOS transistor 44b is a fourth transistor that receives the second RF signal amplified by the differential variable gain low noise amplifier 2 from the source and performs switching according to the fourth LO signal input from the gate.

The output load resistor 45a is a first output load resistor having one end connected to the drains of the p-type MOS transistors 43a and 44b and the other end grounded.
The output load resistor 45b is a second output load resistor having one end connected to the drains of the p-type MOS transistors 43b and 44a and the other end grounded.
The differential BB signal output terminal 46a is a terminal that is connected to the drains of the p-type MOS transistors 43a and 44b and outputs a third BB signal.
The differential BB signal output terminal 46b is connected to the drains of the p-type MOS transistors 43b and 44a and outputs a fourth BB signal.

A current value setting circuit 47, which is a second current value setting circuit, constitutes a current mirror for the mixing circuit 41, and sets the value of the current flowing through the p-type MOS transistors 43a, 43b, 44a, 44b of the mixing circuit 41.
The isolation resistor 48a is a first isolation resistor having one end connected to the gates of the p-type MOS transistors 43a and 44a.
The isolation resistor 48b is a second isolation resistor having one end connected to the gates of the p-type MOS transistors 43b and 44b.
The p-type MOS transistor 49 is a fifth transistor whose source is connected to the power supply VDD and whose gate and drain are connected to the other ends of the isolation resistors 48a and 48b.
In the n-type MOS transistor 50, the drain is connected to the gate and drain of the p-type MOS transistor 49, and the source is grounded.

Next, the operation will be described.
In the third embodiment, the parameters of the circuit elements constituting the mixing circuit 4 and the parameters of the circuit elements constituting the mixing circuit 41 are all the same.
It is assumed that the transistor size of the p-type MOS transistor 13 in the current value setting circuit 32 and the transistor size of the p-type MOS transistor 49 in the current value setting circuit 47 are the same.
It is assumed that the transistor size of the n-type MOS transistor 15 in the current value setting circuit 32 and the transistor size of the n-type MOS transistor 50 in the current value setting circuit 47 are the same.

The differential variable gain low noise amplifier 2 sets the first and second RF signals by the load inductors 31a and 31b when the first and second RF signals are input from the differential RF signal input terminals 1a and 1b. Amplifies the gain.
The first and second RF signals amplified by the differential variable gain low noise amplifier 2 are supplied to the sources of the p-type MOS transistors 6a, 6b, 7a, 7b, 43a, 43b, 44a, 44b of the mixing circuits 4, 41. Input in phase.

When the differential variable gain low noise amplifier 2 amplifies the first and second RF signals, the mixing circuit 4 differs from the amplified first and second RF signals in the same manner as in the first embodiment. The first and second LO signals input from the LO signal input terminals 5a and 5b are mixed, and the first and second RF signals are down-converted to the first and second BB signals.
Further, when the differential variable gain low noise amplifier 2 amplifies the first and second RF signals, the mixing circuit 41 receives the amplified first and second RF signals from the differential LO signal input terminals 42a and 42b. The inputted third and fourth LO signals are mixed, and the first and second RF signals are down-converted into third and fourth BB signals.
The specific operation of the mixing circuit 41 is as follows.

When the first RF signal amplified by the differential variable gain low noise amplifier 2 is input from the source to the p-type MOS transistor 43a, the p-type MOS transistor 43a performs switching according to the third LO signal input from the gate, thereby A signal having a frequency difference between the frequency of the RF signal and the frequency of the third LO signal is output from the drain.
Further, when the second RF signal amplified by the differential variable gain low noise amplifier 2 is input from the source to the p-type MOS transistor 44b, the p-type MOS transistor 44b performs switching according to the fourth LO signal input from the gate. A signal having a frequency difference between the frequency of the second RF signal and the frequency of the fourth LO signal is output from the drain.
As a result, the third BB signal (90 ° in phase with the first BB signal) is the sum of the signal output from the drain of the p-type MOS transistor 43a and the signal output from the drain of the p-type MOS transistor 44b. A different signal) is output from the differential BB signal output terminal 46a.

When the first RF signal amplified by the differential variable gain low noise amplifier 2 is input from the source to the p-type MOS transistor 43b, the p-type MOS transistor 43b performs switching according to the fourth LO signal input from the gate, thereby A signal having a frequency difference between the frequency of the RF signal and the frequency of the fourth LO signal is output from the drain.
Further, when the second RF signal amplified by the differential variable gain low noise amplifier 2 is input from the source to the p-type MOS transistor 44a, the p-type MOS transistor 44a performs switching according to the third LO signal input from the gate. A signal having a frequency that is the difference between the frequency of the second RF signal and the frequency of the third LO signal is output from the drain.
As a result, the fourth BB signal (90 ° in phase with the second BB signal) is the sum of the signal output from the drain of the p-type MOS transistor 43b and the signal output from the drain of the p-type MOS transistor 44a. Different signal) is output from the differential BB signal output terminal 46b.

Here, the flicker noise in the high frequency receiver of FIG. 3 is proportional to the current flowing in the p-type MOS transistors 6a, 6b, 7a, 7b, 43a, 43b, 44a, 44b of the mixing circuits 4, 41.
In the third embodiment, the value of the current flowing through the p-type MOS transistors 6a, 6b, 7a and 7b of the mixing circuit 4 is set by the current value setting circuit 32 as in the first embodiment.
Further, the current value setting circuit 47 sets the value of the current flowing through the p-type MOS transistors 43a, 43b, 44a, 44b of the mixing circuit 41.
That is, the current proportional to the transistor size of the p-type MOS transistor 49 and the transistor sizes of the p-type MOS transistors 43a, 43b, 44a, and 44b is folded back with reference to the current flowing through the p-type MOS transistor 49. This current flows through the p-type MOS transistors 43a, 43b, 44a and 44b.

Note that the current flowing through the p-type MOS transistor 49 is supplied from the n-type MOS transistor 50.
The current flowing through the n-type MOS transistor 50 is a current supplied from the constant current source 17. That is, the current proportional to the transistor size of the n-type MOS transistors 50 and 16 is folded with reference to the current flowing through the n-type MOS transistor 16, and the folded current flows through the n-type MOS transistor 50.

  Therefore, in the current value setting circuit 47, the p-type MOS transistors 43a, 43b, 44a, and 44b of the mixing circuit 41 and the transistor size of the p-type MOS transistor 49 are appropriately set, so that the p-type MOS transistor 43a of the mixing circuit 41 is set. , 43b, 44a, and 44b, the constant current sources 203a and 203b need not be mounted as in the conventional example (see FIG. 5).

  As is apparent from the above, according to the third embodiment, the same effects as those of the first and second embodiments can be obtained, and the third and fourth phases that are 90 degrees out of phase with the first and second LO signals. If the LO signal is input, it can be used as a quadrature demodulator.

Embodiment 4 FIG.
In the third embodiment, the current value setting circuit 32 for the mixing circuit 4 and the current value setting circuit 47 for the mixing circuit 41 are separately provided. However, as shown in FIG. However, the current value setting circuit 47 may also be used to set the value of the current flowing through the mixing circuits 4 and 41.

That is, in the fourth embodiment, the p-type MOS transistors 6a, 6b, 7a, 7b, 43a, 43b, 44a, and 44b of the mixing circuits 4 and 41 and the p-type MOS transistor 13 constitute a current mirror circuit. One p-type MOS transistor 13 serving as a reference for current folding of the current mirror circuit is commonly used in the mixing circuits 4 and 41 (the p-type MOS transistor 49 is omitted).
According to the fourth embodiment, in addition to the same effects as those of the third embodiment, there is an effect that further downsizing can be achieved.

It is a block diagram which shows the high frequency receiver by Embodiment 1 of this invention. It is a block diagram which shows the high frequency receiver by Embodiment 2 of this invention. It is a block diagram which shows the high frequency receiver by Embodiment 3 of this invention. It is a block diagram which shows the high frequency receiver by Embodiment 4 of this invention. It is a block diagram which shows the high frequency receiver currently disclosed by the nonpatent literature 1.

Explanation of symbols

  1a, 1b differential RF signal input terminal, 2 differential variable gain low noise amplifier, 3a load resistance (first load), 3b load resistance (second load), 4 mixing circuit (first mixing circuit), 5a, 5b Differential LO signal input terminal, 6a p-type MOS transistor (first transistor), 6b p-type MOS transistor (second transistor), 7a p-type MOS transistor (third transistor), 7b p-type MOS Transistor (fourth transistor), 8a output load resistance (first output load resistance), 8b output load resistance (second output load resistance), 9a, 9b differential BB signal output terminal, 10 current value setting circuit, 11a isolation resistor (first isolation resistor), 11b isolation resistor (second isolation resistor), 12 groups Semi-resistance, 13 p-type MOS transistor (fifth transistor), 14 current mirror circuit, 15, 16 n-type MOS transistor, 20 current mirror circuit, 31a load inductor (first load), 31b load inductor (second Load), 32 current value setting circuit (first current value setting circuit), 41 mixing circuit (second mixing circuit), 42a, 42b differential LO signal input terminal, 43a p-type MOS transistor (first transistor) 43b p-type MOS transistor (second transistor), 44a p-type MOS transistor (third transistor), 44b p-type MOS transistor (fourth transistor), 45a output load resistor (first output load resistor), 45b Output load resistance (second output load resistance), 46a, 46b Difference BB signal output terminal, 47 current value setting circuit (second current value setting circuit), 48a isolation resistor (first isolation resistor), 48b isolation resistor (second isolation resistor), 49 p-type MOS Transistor (fifth transistor), 50 n-type MOS transistor.

Claims (8)

  A differential amplifier that amplifies first and second high-frequency signals that are differential signals, first and second loads connected between the differential amplifier and a power source, and the first and second loads The first and second high frequency signals amplified by the differential amplifier are mixed with the first and second local oscillation signals which are connected in parallel with each other, and the first and second high frequency signals are mixed. A mixing circuit that down-converts the signal into first and second baseband signals; and a current value setting circuit that configures a current mirror for the mixing circuit and the load and sets a value of a current flowing through the mixing circuit. High frequency receiver.   The mixing circuit receives a first high-frequency signal amplified by a differential amplifier from a source, switches a first transistor to be switched according to a first local oscillation signal input from a gate, and uses the differential amplifier from the source. Amplified first high-frequency signal is input, a second transistor that switches in accordance with a second local oscillation signal input from the gate, and a second high-frequency signal amplified by the differential amplifier is input from the source And a third transistor that switches in accordance with the first local oscillation signal input from the gate, a second high-frequency signal amplified by the differential amplifier from the source, and a second transistor input from the gate. A fourth transistor that switches according to a local oscillation signal, and one end of the first and fourth transistors A first output load resistor connected to the drain and having the other end grounded; a second output load resistor having one end connected to the drains of the second and third transistors and the other end grounded; The high-frequency receiver according to claim 1, comprising:   The high-frequency receiver according to claim 1 or 2, wherein the first and second loads are resistors.   The high-frequency receiver according to claim 1 or 2, wherein the first and second loads are inductors.   The current value setting circuit includes a first isolation resistor having one end connected to the gates of the first and third transistors, and a second isolator having one end connected to the gates of the second and fourth transistors. An isolation resistor, a reference resistor having one end connected to the power supply, a source connected to the other end of the reference resistor, and a gate and a drain connected to the other ends of the first and second isolation resistors. 4. The high-frequency receiver according to claim 3, comprising a fifth transistor and a current mirror circuit connected between the gate and drain of the fifth transistor and the ground.   The current value setting circuit includes a first isolation resistor having one end connected to the gates of the first and third transistors, and a second isolator having one end connected to the gates of the second and fourth transistors. A fifth transistor in which the source is connected to the power supply and the gate and drain are connected to the other ends of the first and second isolation resistors, and the gate, drain and ground of the fifth transistor 5. The high frequency receiver according to claim 4, comprising a current mirror circuit connected therebetween.   A differential amplifier that amplifies first and second high-frequency signals that are differential signals, first and second loads connected between the differential amplifier and a power source, and the first and second loads The first and second high frequency signals amplified by the differential amplifier are mixed with the first and second local oscillation signals which are connected in parallel with each other, and the first and second high frequency signals are mixed. A first mixing circuit for down-converting the signal into first and second baseband signals, a current mirror for the first mixing circuit and the load, and a value of a current flowing through the first mixing circuit; A first current value setting circuit to be set and the first and second local oscillation signals which are differential signals and are connected in parallel with the first and second loads and amplified by the differential amplifier. And the second high frequency signal A second mixing circuit that down-converts the first and second high-frequency signals into third and fourth baseband signals, a current mirror for the second mixing circuit and the load, and the second mixing circuit are configured. A high-frequency receiver comprising: a second current value setting circuit that sets a value of a current flowing through the circuit.   8. The high frequency receiver according to claim 7, wherein the first current value setting circuit also serves as the second current value setting circuit.

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