CN117118361A - Frequency multiplication circuit, frequency multiplier and radio frequency system - Google Patents
Frequency multiplication circuit, frequency multiplier and radio frequency system Download PDFInfo
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- CN117118361A CN117118361A CN202311160535.0A CN202311160535A CN117118361A CN 117118361 A CN117118361 A CN 117118361A CN 202311160535 A CN202311160535 A CN 202311160535A CN 117118361 A CN117118361 A CN 117118361A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B19/00—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
- H03B19/06—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes
- H03B19/14—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes by means of a semiconductor device
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Abstract
The application provides a frequency multiplier circuit, a frequency multiplier and a radio frequency system, and relates to the technical field of electronic circuits. The frequency doubling circuit comprises a differential amplifying unit, a phase shifting unit, a first switch unit and a second switch unit; the two input ends of the differential amplifying unit are respectively connected with the positive input end and the negative input end; the input end of the first resonance unit and the input end of the second resonance unit of the phase shifting unit are respectively connected with two output ends of the differential amplifying unit; the output end of the first resonance unit and the output end of the second resonance unit are respectively connected with the input end of the first switch unit and the input end of the second switch unit; the two output ends of the first switch unit are respectively connected with the positive output end and the negative output end, and the two output ends of the second switch unit are also respectively connected with the positive output end and the negative output end. The frequency doubling circuit replaces the microstrip line with the phase shifting unit, and has wider bandwidth and small occupied area in the circuit.
Description
Technical Field
The present application relates to the field of electronic circuits, and in particular, to a frequency multiplier circuit, a frequency multiplier, and a radio frequency system.
Background
In recent years, with the rapid development of millimeter wave wireless communication, millimeter waves are widely applied in various fields, and the requirements on millimeter wave signal sources are higher.
The frequency multiplier is used as a key unit in the millimeter wave signal source to directly influence the performance of the millimeter wave signal source, one of the existing frequency multipliers is a push-push structure as proposed in patent CN107896091A, the structure is a single-ended output structure, balun is required to convert single-ended signals into differential signals in a pure differential circuit, and the balun has poor output balance and large loss; the other is a Gilbert structure, which solves the problem of the push-push structure, but in order to solve the problem of unbalanced output signal swing, a microstrip line is added, the length of the microstrip line is longer, the occupied area in the circuit is large, and the structure is not suitable for a circuit with high bandwidth.
Disclosure of Invention
The present application is directed to a frequency multiplier circuit, a frequency multiplier and a radio frequency system, which solve the problems of the gilbert-structured frequency multiplier.
In order to achieve the above purpose, the technical scheme adopted by the embodiment of the application is as follows:
in a first aspect, an embodiment of the present application provides a frequency multiplier circuit, including: the differential amplifying unit, the phase shifting unit, the first switching unit and the second switching unit; the differential amplifying unit is used for receiving a positive input radio frequency signal and a negative input radio frequency signal, wherein two input ends of the differential amplifying unit are respectively connected with a positive input end and a negative input end; the phase shift unit includes: the input end of the first resonance unit and the input end of the second resonance unit are respectively connected with two output ends of the differential amplification unit; the output end of the first resonance unit and the output end of the second resonance unit are respectively connected with the input end of the first switch unit and the input end of the second switch unit;
the two control ends of the first switch unit are respectively connected with the positive input end and the negative input end, and the two control ends of the second switch unit are also respectively connected with the positive input end and the negative input end; the two output ends of the first switch unit are respectively connected with a positive output end and a negative output end, the two output ends of the second switch unit are also respectively connected with the positive output end and the negative output end, and the positive output end and the negative output end are respectively used for outputting a positive frequency multiplication signal and a negative frequency multiplication signal.
In an embodiment, the first resonance unit includes: a first inductor and a first capacitor; the second resonance unit includes: the first inductor and the second inductor are respectively a primary coil and a secondary coil of the transformer; center taps of the primary coil and the secondary coil are grounded through the first capacitor and the second capacitor respectively;
the input end and the output end of the first resonance unit are respectively the two ends of the first inductor, and the input end and the output end of the second resonance unit are respectively the two ends of the second inductor.
In an embodiment, the first inductor and the second inductor are arranged in a crossed manner and are symmetrical to each other.
In an embodiment, the differential amplifying unit includes: the differential amplifying unit comprises a first transconductance transistor and a second transconductance transistor, wherein the bias end of the first transconductance transistor and the bias end of the second transconductance transistor are respectively a positive input end and a negative input end of the differential amplifying unit, the grounding end of the first transconductance transistor and the grounding end of the second transconductance transistor are grounded, and the output end of the first transconductance transistor and the output end of the second transconductance transistor are respectively two output ends of the differential amplifying unit.
In one embodiment, the frequency doubling circuit comprises: a third capacitor and a fourth capacitor;
two control ends of the first switch unit are respectively connected with one ends of the third capacitor and the fourth capacitor, and two control ends of the second switch unit are respectively connected with one ends of the third capacitor and the fourth capacitor;
and the other ends of the third capacitor and the fourth capacitor are respectively connected with the positive input end and the negative input end.
In an embodiment, the first switching unit includes: the input end of the first switch transistor and the input end of the second switch transistor are both input ends of the first switch unit, and the output end of the first switch transistor and the output end of the second switch transistor are respectively two output ends of the first switch unit;
the control end of the first switching transistor and the control end of the second switching transistor are respectively two control ends of the first switching unit.
In an embodiment, the second switching unit includes: the input end of the third switching transistor and the input end of the fourth switching transistor are both the input end of the second switching unit, and the output end of the third switching transistor and the output end of the fourth switching transistor are respectively two output ends of the second switching unit;
the control end of the third switching transistor and the control end of the fourth switching transistor are respectively two control ends of the second switching unit.
In an embodiment, the frequency doubling circuit further comprises: a third inductor and a fourth inductor;
one end of the third inductor and one end of the fourth inductor are both connected with a preset power supply, and the other end of the third inductor and the other end of the fourth inductor are respectively connected with the positive output end and the negative output end.
In a second aspect, an embodiment of the present application provides a frequency multiplier, including: the frequency doubling circuit is characterized by comprising a positive input end, a negative input end, a positive output end and a negative output end;
the positive input end and the negative input end are respectively connected with two input ends of a differential amplifying unit in the frequency doubling circuit; the positive output end and the negative output end are respectively connected with two output ends of a first switch unit in the frequency doubling circuit; the positive output end and the negative output end are also respectively connected with two output ends of a second switch unit in the frequency doubling circuit.
In a third aspect, an embodiment of the present application provides a radio frequency system, including: the frequency multiplier described in the above embodiment.
The beneficial effects of the application are as follows: the application provides a frequency doubling circuit, a frequency multiplier and a radio frequency system, wherein the frequency doubling circuit comprises a differential amplifying unit, a phase shifting unit, a first switch unit and a second switch unit; the differential amplifying unit is used for receiving a positive input radio frequency signal and a negative input radio frequency signal; the phase shift unit includes: the input end of the first resonance unit and the input end of the second resonance unit are respectively connected with two output ends of the differential amplification unit; the output end of the first resonance unit and the output end of the second resonance unit are respectively connected with the input end of the first switch unit and the input end of the second switch unit; the two control ends of the first switch unit are respectively connected with the positive input end and the negative input end, and the two control ends of the second switch unit are also respectively connected with the positive input end and the negative input end; the two output ends of the first switch unit are respectively connected with a positive output end and a negative output end, the two output ends of the second switch unit are also respectively connected with the positive output end and the negative output end, and the positive output end and the negative output end are respectively used for outputting a positive frequency multiplication signal and a negative frequency multiplication signal. The frequency doubling circuit replaces a microstrip line in the prior art with the phase shifting unit, has wider bandwidth and small occupied area in the circuit, and solves the problems of the prior frequency multiplier with the Gilbert structure.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a prior art frequency multiplier of Gilbert structure;
FIG. 2 is a schematic diagram of a frequency multiplier circuit according to an embodiment of the present application;
fig. 3 is a schematic layout diagram of a phase shift unit according to an embodiment of the application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application.
Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the description of the present application, it should be noted that, if the terms "upper", "lower", and the like indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, or an azimuth or the positional relationship conventionally put in use of the product of the application, it is merely for convenience of describing the present application and simplifying the description, and it is not indicated or implied that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus should not be construed as limiting the present application.
Furthermore, the terms first, second and the like in the description and in the claims and in the above-described figures, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In the description of the present application, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed" and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, integrally connected, directly connected, indirectly connected through an intermediate medium, or communicating between the two members. The specific meaning of the above terms in the present application can be understood by those skilled in the art according to the specific circumstances.
It should be noted that the features of the embodiments of the present application may be combined with each other without conflict.
In recent years, along with the rapid development of millimeter wave wireless communication, millimeter waves are increasingly widely applied in various fields, and besides the common mobile communication field, millimeter waves are widely applied in astronomy, radar, electronic countermeasure, security imaging, automobile radar and other fields. Because the voltage-controlled oscillator and the later-stage circuit are provided with the frequency multiplier, the phenomenon of frequency traction can be avoided, and in general, the millimeter wave signal source comprises the frequency multiplier, and the millimeter wave is acquired by the millimeter wave signal source in the following way: firstly, a voltage-controlled oscillator (VCO-controlled oscillator) is used for obtaining a low-frequency signal source, and then a frequency multiplier is used for multiplying the low-frequency signal source to obtain a millimeter wave signal source.
Therefore, the frequency multiplier is used as a key unit in the millimeter wave signal source to directly influence the performance of the millimeter wave signal source. Fig. 1 is a schematic diagram of a frequency multiplier with a gilbert structure in the prior art, as shown in fig. 1, in order to solve the problem of unbalanced output signal swing in the prior art, two inductors L are used as microstrip lines, and a 1/4 wavelength microstrip line is used as a 90 ° phase shifting unit.
In order to solve the problems in the prior art, the application provides a frequency doubling circuit, a frequency multiplier and a radio frequency system, and the frequency doubling circuit has the structure that a transformer is used for a 90-degree phase shifting unit, the bandwidth is wider, the occupied area in the circuit is small, and the problems of the prior frequency multiplier with the Gilbert structure can be solved.
The frequency multiplier circuit, the frequency multiplier and the radio frequency system provided by the application are specifically illustrated by a plurality of embodiments with reference to the accompanying drawings.
First, a frequency multiplier circuit provided by the present application is described, and an embodiment of the present application provides a frequency multiplier circuit, including: the differential amplifying unit, the phase shifting unit, the first switching unit and the second switching unit. The differential amplifying unit is used for receiving signals sent by a pre-stage circuit (such as a voltage-controlled oscillator) and amplifying the received signals, the phase shifting unit is used for providing phase delay required by the frequency doubling circuit, and the first switching unit and the second switching unit are used for outputting signals output by the phase shifting unit to a post-stage circuit.
Specifically, two input ends of the differential amplification unit are respectively connected with a positive input end and a negative input end and are used for receiving a positive input radio frequency signal and a negative input radio frequency signal; the phase shift unit includes: the input end of the first resonance unit and the input end of the second resonance unit are respectively connected with two output ends of the differential amplification unit; the output end of the first resonance unit and the output end of the second resonance unit are respectively connected with the input end of the first switch unit and the input end of the second switch unit; the two control ends of the first switch unit are respectively connected with the positive input end and the negative input end, and the two control ends of the second switch unit are also respectively connected with the positive input end and the negative input end; the two output ends of the first switch unit are respectively connected with a positive output end and a negative output end, the two output ends of the second switch unit are also respectively connected with the positive output end and the negative output end, and the positive output end and the negative output end are respectively used for outputting a positive frequency multiplication signal and a negative frequency multiplication signal.
In the frequency doubling circuit, the phase shifting unit comprises the first resonance unit and the second resonance unit, the microstrip line in the prior art is replaced by the phase shifting unit, the bandwidth is wide, the area is small, and the problem of the frequency multiplier with the existing Gilbert structure is solved.
Fig. 2 is a schematic diagram of a frequency multiplier circuit according to an embodiment of the present application, and in detail, the frequency multiplier circuit according to the present application is illustrated with reference to fig. 2.
It should be noted that, the frequency doubling circuit shown in fig. 2 is a frequency doubling circuit, and the signals of the positive input end and the negative input end can be output by the positive output end and the negative output end after frequency doubling.
An embodiment of the present application provides a possible implementation manner of the phase shift unit, as shown in fig. 2, the first resonant unit of the frequency doubling circuit includes a first inductor (Lp) and a first capacitor (C1); the second resonance unit includes a second inductor (Ls) and a second capacitor (C2), where the input end and the output end of the first resonance unit are two ends of the first inductor (the input end is one end connected with M1, the output end is one end connected with M3 and M4), and the input end and the output end of the second resonance unit are two ends of the second inductor (the input end is one end connected with M2, and the output end is one end connected with M5 and M6).
The value calculation formulas of the first inductor and the second inductor are shown as formula (1), and the value formulas of the first capacitor and the second capacitor are shown as formula (2):
f is the working frequency of the frequency doubling circuit, Z 0 The characteristic impedance of the phase shifting unit can be calculated according to the actual requirement by adjusting Z 0 And the impedance value or the capacitance value of the capacitor C is adjusted to realize the adjustment of the conversion gain of the frequency doubling circuit. Wherein the impedance selection depends on the conversion gain of the whole frequency doubling circuit, taking formulas (1) and (2) as examples, for different impedances Z 0 Can obtain a group of L and C meeting the formula, and the different L/C selections can realize 90 DEG phase shift, and how to select Z 0 Depending on the circuit conversion gain.
Fig. 3 is a schematic layout diagram of a phase shift unit according to an embodiment of the present application, as shown in fig. 3, when the phase shift unit includes the first resonant unit and the second resonant unit provided in the above embodiment, the first inductor and the second inductor form a primary coil and a secondary coil of a transformer, and center taps of the primary coil (Lp) and the secondary coil (Ls) of the transformer are grounded through a first capacitor (C1) and a second capacitor (C2), respectively.
As can be seen from fig. 3, the first inductor and the second inductor are arranged in a crossed manner and are symmetrical to each other, and the cross coupling connection mode of the first inductor and the second inductor can ensure symmetry of the transformer, so that the frequency doubling circuit cannot be unbalanced due to asymmetry, and in the transformer of the embodiment, the inductance value of the first inductor is self inductance of the first inductor plus mutual inductance (the inductance value of the second inductor is the same as that of the second inductor), when the frequency doubling circuit of the embodiment and the microstrip line used in the prior art need to obtain the same inductance value, the number of turns of the coil required by the embodiment is smaller, the occupied area in the circuit is smaller, and integrated packaging of the circuit is facilitated.
An embodiment of the present application provides a possible implementation manner of a differential amplifying unit, where the differential amplifying unit may include a first transconductance transistor (M1) and a second transconductance transistor (M2), where a bias end of the first transconductance transistor and a bias end of the second transconductance transistor are respectively a positive input end and a negative input end of the differential amplifying unit, and are configured to receive a signal sent by a front-stage circuit (for example, may be a voltage-controlled oscillator), a ground end of the first transconductance transistor and a ground end of the second transconductance transistor are both grounded, and an output end of the first transconductance transistor and an output end of the second transconductance transistor are respectively two output ends of the differential amplifying unit (an output end of the differential amplifying unit is an output end of M1 and an output end of M2). Wherein the bias terminal refers to the gate of the transconductance transistor, the ground terminal refers to the source of the transconductance transistor, and the output terminal refers to the drain of the transconductance transistor.
An embodiment of the present application provides a possible implementation manner of a first switching unit, where the first switching unit may include a first switching transistor (M3) and a second switching transistor (M4), where an input terminal of the first switching transistor and an input terminal of the second switching transistor are both input terminals of the first switching unit (i.e., there are two input terminals of the first switching unit), and an output terminal of the first switching transistor and an output terminal of the second switching transistor are respectively two output terminals of the first switching unit; the control end of the first switching transistor and the control end of the second switching transistor are respectively two control ends of the first switching unit. Wherein, the input end refers to the source electrode of the switching transistor, the output end refers to the drain electrode of the switching transistor, and the control end refers to the grid electrode of the switching transistor.
An embodiment of the present application provides a possible implementation manner of the second switching unit, where the second switching unit may include a third switching transistor (M5) and a fourth switching transistor (M6), where an input terminal of the third switching transistor and an input terminal of the fourth switching transistor are both input terminals of the second switching unit, and an output terminal of the third switching transistor and an output terminal of the fourth switching transistor are two output terminals of the second switching unit respectively; the control end of the third switching transistor and the control end of the fourth switching transistor are respectively two control ends of the second switching unit. Wherein, the input end refers to the source electrode of the switching transistor, the output end refers to the drain electrode of the switching transistor, and the control end refers to the grid electrode of the switching transistor.
In the application, the output ends of M3 and M5 are connected with the positive output end Vout+, the output ends of M4 and M6 are connected with the positive output end Vout-, the M3 and M5 transistors generate positive ends of even harmonics by fundamental waves of the grid electrode and the source electrode, and the M4 and M6 transistors generate negative ends of even harmonics by fundamental waves of the grid electrode and the source electrode, so that frequency doubling of an input differential signal is realized.
In an embodiment, the frequency doubling circuit may further include a third capacitor (C3) and a fourth capacitor (C4), two control ends of the first switch unit are respectively connected to one ends of the third capacitor and the fourth capacitor, two control ends of the second switch unit are respectively connected to one ends of the third capacitor and the fourth capacitor, and the other ends of the third capacitor and the fourth capacitor are respectively connected to the positive input end and the negative input end.
As shown IN fig. 2, one end of the third capacitor C3 is connected to the positive input terminal in+, the other end of the third capacitor is connected to the control terminal of M3 IN the first switching unit and M6 IN the second switching unit, one end of the fourth capacitor C4 is connected to the negative input terminal IN-, and the other end of the fourth capacitor is connected to the control terminal of M4 IN the first switching unit and M5 IN the second switching unit. The bias voltages of the grid electrodes of the two groups of transistors M1/M2, M3/M4/M5/M6 in the frequency doubling circuit are different, and the third capacitor and the fourth capacitor are arranged in the frequency doubling circuit, so that the bias voltages can be isolated.
In an embodiment, the frequency doubling circuit further includes a third inductor (L1) and a fourth inductor (L2), wherein one end of the third inductor and one end of the fourth inductor are both connected to a preset power supply (VIN), and the other end of the third inductor and the other end of the fourth inductor are respectively connected to the positive output end vout+ and the negative output end Vout-. The preset power supply is used for supplying direct current to each element in the frequency doubling circuit, the third inductor and the fourth inductor can improve the impedance of the frequency doubling circuit, the inductance values of the third inductor and the fourth inductor can be adjusted according to actual requirements, and performance adjustment of the frequency doubling circuit can be conveniently achieved according to the impedance values.
In addition, the capacitors CP1 and CP2 in fig. 2 are parasitic capacitors of the phase shift unit, and the phase shift unit is designed into a transformer form, and the first inductor and the second inductor are coupled, so that the parasitic capacitors can be offset, the size of the parasitic capacitors is reduced, and the influence of the parasitic capacitors on the performance of the frequency doubling circuit is avoided.
On the basis of the frequency multiplier circuit provided by the embodiment, an embodiment of the application also provides a frequency multiplier which comprises a positive input end, a negative input end, a positive output end and a negative output end, and the frequency multiplier circuit provided by the embodiment.
One end of the positive input end and one end of the negative input end are used for being connected with the voltage-controlled oscillator, and the positive input end and the negative input end are also respectively connected with two input ends of a differential amplifying unit in the frequency doubling circuit, so that signals output by the voltage-controlled oscillator can be received by the two input ends of the differential amplifying unit; the positive output end and the negative output end are respectively connected with two output ends of a first switch unit in the frequency doubling circuit; the positive output end and the negative output end are also respectively connected with two output ends of a second switch unit in the frequency doubling circuit, and can output the frequency-doubled signal provided by the frequency doubling circuit to a post-stage circuit.
An embodiment of the present application further provides a radio frequency system, including the frequency multiplier provided in the foregoing embodiment, where a front stage circuit of the frequency multiplier may be a voltage-controlled oscillator, a rear stage circuit of the frequency multiplier may be an amplifying circuit, and a frequency multiplier is disposed between the voltage-controlled oscillator and the amplifying circuit, so that a signal provided by the voltage-controlled oscillator is multiplied by the frequency and then input to the amplifying circuit, and the voltage-controlled oscillator and the amplifying circuit are isolated by the frequency multiplier, so that a frequency pulling phenomenon between the voltage-controlled oscillator and the amplifying circuit in the radio frequency system is avoided.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present application should be included in the scope of the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.
Claims (10)
1. A frequency multiplier circuit, comprising: the differential amplifying unit, the phase shifting unit, the first switching unit and the second switching unit; the differential amplifying unit is used for receiving a positive input radio frequency signal and a negative input radio frequency signal, wherein two input ends of the differential amplifying unit are respectively connected with a positive input end and a negative input end; the phase shift unit includes: the input end of the first resonance unit and the input end of the second resonance unit are respectively connected with two output ends of the differential amplification unit; the output end of the first resonance unit and the output end of the second resonance unit are respectively connected with the input end of the first switch unit and the input end of the second switch unit;
the two control ends of the first switch unit are respectively connected with the positive input end and the negative input end, and the two control ends of the second switch unit are also respectively connected with the positive input end and the negative input end; the two output ends of the first switch unit are respectively connected with a positive output end and a negative output end, the two output ends of the second switch unit are also respectively connected with the positive output end and the negative output end, and the positive output end and the negative output end are respectively used for outputting a positive frequency multiplication signal and a negative frequency multiplication signal.
2. The frequency doubling circuit of claim 1, wherein the first resonant unit comprises: a first inductor and a first capacitor; the second resonance unit includes: the first inductor and the second inductor are respectively a primary coil and a secondary coil of the transformer; center taps of the primary coil and the secondary coil are grounded through the first capacitor and the second capacitor respectively;
the input end and the output end of the first resonance unit are respectively the two ends of the first inductor, and the input end and the output end of the second resonance unit are respectively the two ends of the second inductor.
3. The frequency doubling circuit of claim 2, wherein the first inductance and the second inductance are arranged to cross and are symmetrical to each other.
4. The frequency doubling circuit of claim 1, wherein the differential amplifying unit comprises: the differential amplifying unit comprises a first transconductance transistor and a second transconductance transistor, wherein the bias end of the first transconductance transistor and the bias end of the second transconductance transistor are respectively a positive input end and a negative input end of the differential amplifying unit, the grounding end of the first transconductance transistor and the grounding end of the second transconductance transistor are grounded, and the output end of the first transconductance transistor and the output end of the second transconductance transistor are respectively two output ends of the differential amplifying unit.
5. The frequency doubling circuit of claim 1, wherein the frequency doubling circuit comprises: a third capacitor and a fourth capacitor;
two control ends of the first switch unit are respectively connected with one ends of the third capacitor and the fourth capacitor, and two control ends of the second switch unit are respectively connected with one ends of the third capacitor and the fourth capacitor;
and the other ends of the third capacitor and the fourth capacitor are respectively connected with the positive input end and the negative input end.
6. The frequency doubling circuit of claim 1, wherein the first switch unit comprises: the input end of the first switch transistor and the input end of the second switch transistor are both input ends of the first switch unit, and the output end of the first switch transistor and the output end of the second switch transistor are respectively two output ends of the first switch unit;
the control end of the first switching transistor and the control end of the second switching transistor are respectively two control ends of the first switching unit.
7. The frequency doubling circuit of claim 1, wherein the second switching unit comprises: the input end of the third switching transistor and the input end of the fourth switching transistor are both the input end of the second switching unit, and the output end of the third switching transistor and the output end of the fourth switching transistor are respectively two output ends of the second switching unit;
the control end of the third switching transistor and the control end of the fourth switching transistor are respectively two control ends of the second switching unit.
8. The frequency doubling circuit of claim 1, wherein the frequency doubling circuit further comprises: a third inductor and a fourth inductor;
one end of the third inductor and one end of the fourth inductor are both connected with a preset power supply, and the other end of the third inductor and the other end of the fourth inductor are respectively connected with the positive output end and the negative output end.
9. A frequency multiplier, comprising: positive input, negative input, positive output and negative output, frequency doubling circuit according to any of the preceding claims 1-8;
the positive input end and the negative input end are respectively connected with two input ends of a differential amplifying unit in the frequency doubling circuit; the positive output end and the negative output end are respectively connected with two output ends of a first switch unit in the frequency doubling circuit; the positive output end and the negative output end are also respectively connected with two output ends of a second switch unit in the frequency doubling circuit.
10. A radio frequency system, comprising: the frequency multiplier of claim 9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311160535.0A CN117118361A (en) | 2023-09-08 | 2023-09-08 | Frequency multiplication circuit, frequency multiplier and radio frequency system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311160535.0A CN117118361A (en) | 2023-09-08 | 2023-09-08 | Frequency multiplication circuit, frequency multiplier and radio frequency system |
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| CN202311160535.0A Pending CN117118361A (en) | 2023-09-08 | 2023-09-08 | Frequency multiplication circuit, frequency multiplier and radio frequency system |
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