WO2012111586A1

WO2012111586A1 - Semiconductor device and display apparatus

Info

Publication number: WO2012111586A1
Application number: PCT/JP2012/053222
Authority: WO
Inventors: 佐々木　寧; 村上　祐一郎; 卓也鉢田; 悦雄山本; 大河　寛幸
Original assignee: シャープ株式会社
Priority date: 2011-02-18
Filing date: 2012-02-13
Publication date: 2012-08-23

Abstract

A circuit (10) is provided with a transistor (T1), a transistor (T2), and a capacitor (TC1) installed between a node (n1) and a CK terminal. The frequency of a clock signal is higher than the frequency of an output signal (OUT), and the capacitance of the capacitor (TC1) becomes smaller as the electric potential of the node (n1) drops, and becomes greater as the electric potential of the node (n1) rises.

Description

Semiconductor device and display device

The present invention relates to a semiconductor device composed of transistors of the same conductivity type.

In a liquid crystal display device, for example, a shift register that generates a signal for sequentially driving pixels arranged in an array is used in a scanning signal line driving circuit and a data signal line driving circuit. The liquid crystal display device uses a level shifter that converts the power supply voltage level and a so-called buffer that outputs a broad amplification signal with a low output impedance, such as an amplification circuit that obtains an output equal to the input signal. Yes. If these semiconductor devices such as a shift register and a buffer are composed of CMOS transistors, a process for forming each of the p-channel and the n-channel is required, which complicates the manufacturing process. Therefore, it is preferable to simplify the manufacturing process and to use transistors of the same conductivity type, for example, a unipolar channel such as only a p-channel. A semiconductor device including such a unipolar transistor is disclosed in Patent Document 1, for example.

FIG. 46 is a circuit diagram showing a configuration of the semiconductor device of Patent Document 1. In FIG. This semiconductor device is composed of an n-type MOS transistor.

Specifically, the semiconductor device 100 includes four n-type MOS transistors T101 to T104 and a capacitor C101. The transistor T101 has a drain terminal connected to the power supply VDD and a gate terminal connected to the input terminal IN. The transistor T103 has a source terminal connected to the power supply VSS and a gate terminal to which a STOP signal (control signal) is input. The transistor T102 has a drain terminal connected to the clock terminal φ and a gate terminal connected to the source terminal of the transistor T101 and the drain terminal of the transistor T103. The transistor T104 has a drain terminal connected to the source terminal of the transistor T102, a source terminal connected to the power supply VSS, and a gate terminal connected to the gate terminal of the transistor T103. A connection point between the transistors T101, T102, and T103 is a node N1, and a connection point between the transistors T102 and T104 is a node N2. A capacitor C101 is provided between the node N1 and the node N2. Node N2 is connected to output terminal OUT.

Next, the operation of the semiconductor device 100 will be described. FIG. 47 is a timing chart showing waveforms of various signals in the semiconductor device 100.

When the input signal IN becomes high level, the transistor T101 is turned on, and the potential of the node N1 becomes VDD−Vth when the threshold voltage of the transistor T101 is Vth (precharge operation). When the potential of the node N1 rises, the transistor T102 is turned on. When the clock signal φ is at a low level, a low-level signal is output from the output terminal OUT. The potential of the node N1 is held (floating state) once the charge is precharged until the STOP signal becomes active (high level). When the clock signal φ becomes high level in this floating state, the potential of the node N1 is increased by the α potential by the capacitor C101 and becomes VDD−Vth + α (bootstrap operation). While this potential exceeds VDD + Vth, a signal having a potential level of VDD is output from the output terminal OUT.

Thereafter, when the STOP signal becomes high level, the node N1 is discharged to VSS by the transistor T103, and the transistor T102 is turned off. A signal having a potential level of VSS is output from the output terminal OUT when the transistor T104 is turned on.

As described above, according to the configuration of the semiconductor device, a high-potential signal can be output with a simple configuration by using the bootstrap operation. Therefore, such a semiconductor device can be suitably used in each part in the liquid crystal display device.

However, the above-described semiconductor device has a problem that the potential of the output signal gradually decreases under the influence of an off-leakage (a minute current that flows when the transistor is off).

A technique capable of solving such a problem is disclosed in Patent Document 2. FIG. 48 is a circuit diagram showing a configuration of the semiconductor device of Patent Document 2. The semiconductor device 200 (hereinafter also referred to as a circuit 200) includes three n-type MOS transistors T201 to T203 and a capacitor C201. The transistor T201 has a drain terminal connected to the power supply VDD and a gate terminal connected to the input terminal IN. The transistor T202 has a drain terminal connected to the power supply VDD, a source terminal connected to the output terminal OUT, and a gate terminal connected to the source terminal of the transistor T201. The capacitor C201 has one terminal connected to the clock terminal CK and the other terminal connected to the source terminal of the transistor T201 and the gate terminal of the transistor T202. The transistor T203 has a drain terminal connected to the source terminal of the transistor T201, a gate terminal of the transistor T202, and the other terminal of the capacitor C201, a source terminal connected to the power supply VSS, and a gate terminal connected to the control terminal (STOP). . A connection point (node) of the transistors T201, T202, T203 and the capacitor C201 is n201. Here, the frequency of the clock signal input to the clock terminal CK is set to be higher than the frequency of the output signal output from the output terminal OUT.

According to the configuration of the semiconductor device 200, the potential of the node n201 is pushed up according to the cycle of the clock signal having a frequency higher than that of the output signal. Therefore, even if the potential of the node n201 is lowered due to off-leakage or the like, , Can immediately restore the potential. As a result, the potential of the node n201 can be increased in a shorter cycle than the configuration of Patent Document 1, so that the potential level of the output signal can be stabilized, and the operation of the subsequent circuit that receives the output signal can be stabilized. Can do.

Japanese Patent Gazette “Patent No. 3092506 (registered on July 28, 2000)” International Publication Gazette "WO2009 / 084272 (published July 9, 2009)"

Here, Patent Document 2 discloses a configuration for reducing power consumption in the semiconductor device 200.

The semiconductor device 200 shown in FIG. 48 has a problem that the power consumption increases because the load capacity (clock load) of the clock terminal CK is large. Hereinafter, the clock load will be specifically described with reference to the semiconductor device 200 of FIG.

When the potential of the node n201 is at a high level (VDD−Vth or higher), that is, when the node n201 is in a floating state, the load capacitance of the clock terminal CK is the parasitic capacitance of the transistors T201, T202, and T203. If the total is Ctr,
1 / Load capacity of clock terminal CK = 1 / C201 + 1 / Ctr (1)
It becomes. For convenience of explanation, wiring loads and the like are omitted.

Here, if the potential of the node n201 is greatly increased, C201> Ctr. If the voltage at the node n201 is increased by 2 × Vp / 3 with respect to the amplitude Vp of the clock signal CK, C201: Ctr = 2: 1. Substituting this into equation (1) gives
Load capacity of clock terminal CK = 1/3 × C201 (2)
It becomes.

Next, when the potential of the node n201 is at a low level (VSS), that is, when the node n201 is not in a floating state, the load capacitance of the clock terminal CK is
Load capacity of clock terminal CK = C201 (3)
It becomes.

Thus, it can be seen that the load capacity of the clock terminal CK increases during the period when the node n201 is not in the floating state. In particular, when the semiconductor device 200 is used in a plurality of stages and the same clock signal CK is input to the clock terminal CK, the load capacity becomes very large.

Therefore, as a configuration capable of reducing this clock load, Patent Document 2 discloses a semiconductor device 210 (hereinafter also referred to as a circuit 210) in FIG. The semiconductor device 210 further includes a transistor T208 in the semiconductor device 200 of FIG. The transistor T208 has a gate terminal connected to the input terminal INB, a drain terminal connected to the clock terminal CK, and a source terminal connected to the node n201 via the capacitor C201.

In the semiconductor device 210, the transistor T208 allows the node n201 not to be in a floating state, and the clock terminal CK and the capacitor C201 can be disconnected during a period when the load on the clock terminal CK becomes very large.

Specifically, when the potential of the node n201 is fixed at VSS, the node n201 does not need to be pushed up by the clock signal CK. Therefore, the period is electrically connected between the clock terminal CK and the capacitor C201 by the transistor T208. As a result, the load on the clock terminal CK becomes only the parasitic capacitance of the transistor T208, and thus becomes very small.

Therefore, it is possible to reduce power consumption due to the reduction in driving capability and capacity of the circuit that drives the clock terminal CK.

Further, the semiconductor device 210 includes a transistor T209, a resistor R201, and a transistor T211 in order to stably fix the potential of the node n203 between the transistor T208 and the capacitor C201 while the transistor T208 is in the off state. An inverter 206 is provided (FIG. 49). The transistor T209 has a drain terminal connected to the node n203, a source terminal connected to the power supply VSS, and a gate terminal connected to the input terminal IN of the inverter 206. Accordingly, when the transistors T201 and T208 are turned off, the transistors T203 and T209 are turned on, and the potentials of the nodes n201 and n203 can be fixed to VSS.

However, in the semiconductor device 210, it is necessary to add transistors T208, T209, T211 and a resistor R201 to the semiconductor device 200 shown in FIG. 48 in order to achieve low power consumption and stabilization of the potential of the node n203. Downsizing is impeded. Further, the potential of the node n203 has a problem that a sufficient amplitude cannot be obtained because the potential of the clock signal is a potential obtained by dropping the threshold value by the transistor T208.

The present invention has been made in view of the above-described problems, and the object thereof is composed of transistors of the same conductivity type, and with a simple configuration, while reducing power consumption and preventing a decrease in potential level, is stable. It is an object to provide a semiconductor device capable of outputting a signal and a display device including the semiconductor device.

In order to solve the above problems, a semiconductor device according to the present invention provides
A semiconductor device composed of a plurality of transistors of the same conductivity type,
A first transistor in which an on-voltage is applied to the first terminal and an input signal is input to the control terminal;
A second transistor having an on-voltage applied to the first terminal, a second terminal connected to the output terminal, and a control terminal connected to the second terminal of the first transistor;
A capacitor provided between a connection point between the first transistor and the second transistor and a clock terminal for inputting a clock signal;
The frequency of the clock signal is set higher than the frequency of the output signal output from the output terminal,
The capacitance is characterized in that a capacitance value changes according to a change in potential at the connection point.

The transistor includes a first terminal, a second terminal, and a control terminal. The transistor conducts the first terminal and the second terminal by a control signal input to the control terminal, and outputs a signal having a desired potential level. Circuit. The control signal here has a voltage (signal level: VDD) that turns the transistor on when supplied to the control terminal, and a voltage (signal level) that turns the transistor off when supplied to the control terminal. : VSS).

Here, in the conventional semiconductor device 100 (FIG. 46), normally, as described above, the potential of the node connected to the control terminal of the transistor that outputs a signal of a desired potential level gradually decreases due to the influence of off-leakage or the like. .

Therefore, in the semiconductor device of the present invention, a node is connected to a control terminal of a transistor that outputs a signal having a desired potential level, that is, a connection point (node) between the first transistor and the second transistor via a capacitor. Thus, a clock signal having a frequency higher than that of the output signal is input.

According to this configuration, assuming that the threshold voltage of the first transistor is Vth, the potential of the node is first increased by α potential by the clock signal and the capacitance, and then decreased by, for example, β potential by off-leakage or the like, and VDD− Vth + α−β. After that, when the clock signal becomes low level (VSS), the node potential becomes VDD−Vth−β. However, when the input signal is high level (VDD), the node potential becomes VDD−Vth. It is charged until. Then, when the clock signal becomes high level again, the potential of the node is pushed up to VDD−Vth + α again.

Thus, according to the configuration of the semiconductor device of the present invention, the push-up operation is performed according to the cycle of the clock signal having a frequency higher than that of the output signal. Therefore, even when the potential of the node decreases due to off-leakage or the like, the potential can be recovered immediately by the pushing-up operation. As a result, the potential of the node can be increased in a cycle shorter than that of the conventional configuration, so that the potential level of the output signal can be stabilized and the operation of the subsequent circuit that receives the output signal can be stabilized.

Further, by setting the amplitude and capacitance of the clock signal so that the potential of the pushed-up node (VDD−Vth + α) becomes equal to or higher than VDD + Vth (Vth is the threshold voltage of the second transistor), the output signal Can be maintained at VDD.

Also, since a high-potential signal is input to the control terminal of the second transistor, the output signal can maintain a low impedance and is resistant to noise.

Furthermore, in the semiconductor device of the present invention, the capacitance has a configuration in which the capacitance value changes in accordance with a change in the potential of the node. Therefore, for example, when the capacitance is configured such that the capacitance value decreases as the node potential decreases while the capacitance value increases as the node potential increases, the node potential is low level (VSS). In this case, since the capacitance value is small, the load capacitance of the clock terminal can be made smaller than the load capacitance of the clock terminal CK in the conventional semiconductor device 200 (FIG. 48) from the above equation (3). Thereby, the power consumption of the semiconductor device of the present invention can be reduced as compared with the conventional semiconductor device.

Further, in the semiconductor device of the present invention, by replacing the transistors T208 and T209, the inverter 206, and the capacitor C201 in the conventional semiconductor device 210 shown in FIG. Power consumption and potential stabilization of the node n203 (corresponding to the node n1 of the present invention) can be realized. Therefore, the circuit configuration can be simplified as compared with the conventional semiconductor device 210.

Further, in the conventional semiconductor device 210, since the clock terminal CK and the capacitor C201 are connected via the transistor T208, the potential of the clock signal drops to the potential at the node n203. In contrast, in the semiconductor device of the present invention, since the clock terminal and the capacitor are connected without a transistor, the threshold value does not drop. Therefore, the operation margin of the semiconductor device can be increased and the output signal can be further stabilized.

As described above, according to the semiconductor device of the present invention, it is possible to output a stable signal with a simple configuration while reducing power consumption and preventing a decrease in potential level.

In order to solve the above problems, a semiconductor device according to the present invention provides
A semiconductor device composed of a plurality of transistors of the same conductivity type,
A first transistor in which an on-voltage is applied to the first terminal and an input signal is input to the control terminal;
A second transistor having an on-voltage applied to the first terminal, a second terminal connected to the output terminal, and a control terminal connected to the second terminal of the first transistor;
A capacitor provided between a connection point between the first transistor and the second transistor and a clock terminal for inputting a clock signal;
An eighth transistor having a first terminal connected to the connection point and an on-voltage input to the control terminal;
A third transistor having a first terminal connected to the second terminal of the eighth transistor, an off-voltage input to the second terminal, and a control signal input to the control terminal;
The frequency of the clock signal is set higher than the frequency of the output signal output from the output terminal,
The capacitance is characterized in that a capacitance value changes according to a change in potential at the connection point.

Since the potential of the node is pushed up by the clock signal, a high voltage is applied to each transistor connected to the node. Therefore, there is a risk that the transistor will be destroyed if it exceeds its withstand voltage.

Therefore, the semiconductor device includes an eighth transistor between the node and the third transistor. Accordingly, although details will be described later, for example, the potential applied to the third transistor can be lowered, so that a highly reliable circuit can be configured.

As described above, in the semiconductor device according to the present invention, the capacitance value of the capacitor changes according to the change in the potential at the connection point. Accordingly, a semiconductor device that includes transistors of the same conductivity type and can output a stable signal with a simple configuration while reducing power consumption and preventing a decrease in potential level, and a display device including the semiconductor device are provided. There is an effect that can be done.

1 is a circuit diagram illustrating a configuration of a circuit according to a first embodiment. 2 is a timing chart showing waveforms of various signals in the circuit shown in FIG. (A) is a figure which shows the structure of the capacity | capacitance in the circuit shown in FIG. 1, (b) is a graph which shows the relationship between the applied voltage and capacity value in a capacity | capacitance. (A) is a figure which shows the structure of the capacity | capacitance in the conventional circuit shown in FIG. 46, (b) is a graph which shows the relationship between the applied voltage and capacity value in a capacity | capacitance. 2 is a timing chart showing waveforms of various signals when affected by off-leakage or the like in the circuit shown in FIG. FIG. 45 is a timing chart showing waveforms of various signals when affected by off-leakage or the like in the conventional circuit shown in FIG. 44. FIG. 2 is a timing chart showing waveforms of various signals when a clock signal φ is input to the drain terminal of a transistor T2 in the circuit shown in FIG. FIG. 6 is a circuit diagram illustrating a configuration of a circuit according to a second embodiment. It is a timing chart which shows the waveform of various signals in the circuit shown in FIG. FIG. 6 is a circuit diagram illustrating a configuration of a circuit according to a third embodiment. FIG. 6 is a circuit diagram showing a configuration of a circuit according to a fourth embodiment. 12 is a timing chart showing waveforms of various signals in the circuit shown in FIG. FIG. 12 is a circuit diagram illustrating another configuration of the transistor T6 in the circuit illustrated in FIG. 11. FIG. 12 is a circuit diagram illustrating another configuration of the transistor T6 in the circuit illustrated in FIG. 11. FIG. 10 is a circuit diagram showing a configuration of a circuit according to a fifth embodiment. FIG. 10 is a circuit diagram showing a configuration of a circuit according to a sixth embodiment. FIG. 2 is a circuit diagram showing a configuration when a transistor T1 is diode-connected in the circuit shown in FIG. FIG. 9 is a circuit diagram showing a configuration when a transistor T1 is diode-connected in the circuit shown in FIG. FIG. 11 is a circuit diagram showing a configuration when a transistor T1 is diode-connected in the circuit shown in FIG. FIG. 12 is a circuit diagram showing a configuration when a transistor T1 is diode-connected in the circuit shown in FIG. FIG. 16 is a circuit diagram showing a configuration when a transistor T1 is diode-connected in the circuit shown in FIG. FIG. 17 is a circuit diagram showing a configuration when a transistor T1 is diode-connected in the circuit shown in FIG. 18 is a timing chart showing waveforms of various signals in the circuit shown in FIG. It is a figure which shows the waveform of the clock signal CK in each embodiment of this invention. It is a block diagram which shows the whole structure of the liquid crystal display device which concerns on this Embodiment. FIG. 3 is a block diagram illustrating a configuration of a memory circuit provided in the CS driver according to the first embodiment. FIG. 27 is a circuit diagram showing a configuration of a memory circuit shown in FIG. 26. 27 is a timing chart showing waveforms of various signals in the memory circuit shown in FIG. 26. FIG. 27 is a circuit diagram showing a configuration of an inverter circuit that generates an inverted signal INB from an input signal IN in the memory circuit shown in FIG. 26. FIG. 27 is a circuit diagram illustrating another configuration of an inverter circuit that generates an inverted signal INB from an input signal IN in the memory circuit illustrated in FIG. 26. FIG. 6 is a block diagram illustrating a configuration of a buffer circuit according to a second embodiment. FIG. 32 is a circuit diagram showing a configuration of a buffer circuit shown in FIG. 31. FIG. 32 is a block diagram showing a case where the inverter is configured by a bootstrap circuit in the buffer circuit shown in FIG. 31. FIG. 34 is a circuit diagram showing a configuration of a buffer circuit shown in FIG. 33. FIG. 10 is a block diagram illustrating a configuration of a buffer circuit according to a third embodiment. FIG. 36 is a circuit diagram showing a case where the inverter is configured by a bootstrap circuit in the buffer circuit shown in FIG. 35. FIG. 10 is a block diagram illustrating a configuration of a buffer circuit according to a fourth embodiment. FIG. 38 is a circuit diagram showing a configuration of a buffer circuit shown in FIG. 37. FIG. 10 is a block diagram illustrating a configuration of a unit circuit constituting a shift register according to a fifth embodiment. FIG. 40 is a block diagram illustrating another configuration of the unit circuit that configures the shift register illustrated in FIG. 39. FIG. 40 is a block diagram showing another configuration of the unit circuit configuring the shift register shown in FIG. 39. FIG. 2 is a circuit diagram in the case where the circuit configuration illustrated in FIG. 1 is configured by a p-channel transistor. 42 is a timing chart showing waveforms of various signals in the circuit shown in FIG. 42, where (a) in the figure shows a waveform when VSS is inputted to the source terminal of the transistor T2 ′, and (b) in the figure shows the transistor. The waveform is shown when the clock signal φ is input to the source terminal of T2 ′. (A) is a figure which shows the structure of the capacity | capacitance in the circuit shown in FIG. 42, (b) is a graph which shows the relationship between the applied voltage and capacity value in a capacity | capacitance. (A) is a figure which shows the structure of the capacity | capacitance in the conventional circuit, (b) is a graph which shows the relationship between the applied voltage and capacity | capacitance value in a capacity | capacitance. 10 is a circuit diagram showing a configuration of a conventional semiconductor device according to Patent Document 1. FIG. 47 is a timing chart showing waveforms of various signals in the semiconductor device shown in FIG. 46. FIG. 10 is a circuit diagram showing a configuration of a conventional semiconductor device according to Patent Document 2. FIG. 12 is a circuit diagram showing another configuration of a conventional semiconductor device according to Patent Document 2.

Embodiments of the present invention are described below with reference to the drawings.

An Active signal holding circuit (hereinafter simply referred to as “circuit”) corresponding to the semiconductor device of the present invention is configured using transistors of the same conductivity type, that is, a unipolar channel (n-channel type or p-channel type). Yes. In each embodiment described below, the configuration of an n-channel transistor is described as an example, and the configuration of a p-channel transistor is only illustrated at the end of this column, and detailed description is omitted. As this transistor, for example, a TFT and a field effect transistor formed on a silicon substrate can be used.

[Embodiment 1]
The configuration of the circuit 10 in this embodiment will be described below. FIG. 1 is a circuit diagram showing the configuration of the circuit 10, and FIG. 2 is a timing chart showing waveforms of various signals in the circuit 10.

The circuit 10 includes a transistor T1 (first transistor), a transistor T2 (second transistor), a transistor T3 (third transistor), and a capacitor TC1, and the output signal OUT of the circuit 10 is connected to one end of the capacitor TC1. In this configuration, a clock signal CK having a higher frequency is input. Hereinafter, the voltage (signal level) that turns the transistor on when applied to the gate terminal (control terminal) is referred to as on-voltage (on level), and the voltage that turns the transistor off when applied to the gate terminal (signal level). Signal level) is called off voltage (off level). In an n-channel transistor, a high voltage is an on voltage (high level is an on level), a low voltage is an off voltage (low level is an off level), and vice versa for a p-channel transistor.

As shown in FIG. 1, the transistor T1 has a drain terminal (first terminal) connected to the power supply VDD and a gate terminal (control terminal) connected to the input terminal IN. The transistor T2 has a drain terminal (first terminal) connected to the power supply VDD, a gate terminal (control terminal) connected to the source terminal of the transistor T1, and a source terminal (second terminal) connected to the output terminal OUT. The The transistor T3 has a drain terminal (first terminal) connected to the source terminal of the transistor T1 and the gate terminal of the transistor T2. The capacitor TC1 includes a transistor, and a gate terminal (control terminal) is connected to a source terminal of the transistor T1, a drain terminal of the transistor T3, and a control terminal of the transistor T2, and a drain terminal (first terminal) and A source terminal (second terminal) is connected to the clock terminal CK. Hereinafter, the capacitor TC1 is also referred to as a transistor TC1 as necessary. A connection point between the transistors T1, T2, T3, and TC1 is a node n1.

Here, a specific configuration of the capacitor TC1 will be described. 3A is a diagram illustrating a configuration of the capacitor TC1, and FIG. 3B is a graph illustrating a relationship between an applied voltage and a capacitance value in the capacitor TC1. 4A is a diagram illustrating a configuration of a conventional capacitor C201, and FIG. 4B is a graph illustrating a relationship between an applied voltage and a capacitance value in the capacitor C201.

In the conventional capacitor C201, as shown in FIG. 4A, silicon Si is doped with N +, Si is made low resistance, and a capacitor is formed between the gate electrode GE and Si. In the case of this capacitance C201, as shown in FIG. 4B, the capacitance value is substantially constant regardless of the voltage between the gate electrode and Si.

On the other hand, in the capacitor TC1 of the circuit 10 according to the present embodiment, Si (silicon layer) is not doped with N + as shown in FIG. Thereby, the capacitor TC1 functions as a MOS capacitor and does not function as a capacitor unless a voltage (ON voltage) is applied to the gate electrode GE. That is, the capacitor TC1 functioning as a transistor is turned off when the potential of the node n1 is lower than the potential of the clock terminal CK, while the potential of the node n1 is equal to or higher than the potential of the clock terminal CK (on voltage). Turns on. In FIG. 3B, Von indicates the ON voltage.

Therefore, the capacitance value of the capacitor TC1 changes according to the voltage between the gate electrode and Si, as shown in FIG. That is, as the voltage applied to the gate electrode increases, the capacitance value of the capacitor TC1 increases. More specifically, the capacitance value of the capacitor TC1 decreases as the potential of the node n1 decreases, while the capacitance value of the capacitor TC1 increases as the potential of the node n1 increases.

Next, the operation of the circuit 10 will be described in detail with reference to FIG. Note that the potentials of the internal signals and input / output signals of the circuit 10 are VDD when high and VSS (zero) when low unless otherwise specified.

When the input signal IN becomes high level (VDD), the transistor T1 is turned on, and the potential of the node n1 becomes VDD−Vth when the threshold voltage of the transistor T1 is Vth (precharge operation). When the potential of the node n1 rises, the transistor T2 and the capacitor TC1 (transistor TC1) are turned on. When the input signal IN changes from a high level to a low level (VSS), the node n1 is in a floating state while retaining a high level charge. In this state, when the clock signal CK becomes high level, the potential of the node n1 is increased by the α potential by the clock signal CK and becomes VDD−Vth + α. When this potential exceeds VDD + Vth, the transistor T2 outputs VDD to the output terminal OUT.

Thus, when the potential of the node n1 is pushed up by the clock signal CK, a high potential signal is input to the gate terminal of the transistor T2, and thus a signal having a potential level of VDD from the transistor T2 to the output terminal OUT. Is output and the output impedance is lowered (period t in FIG. 2).

Thereafter, when the STOP signal becomes high level, the transistor T3 is turned on, the charge of the node n1 is discharged, and the transistor T2 and the transistor TC1 are turned off. As a result, the output terminal OUT enters a floating state (shaded area in FIG. 2).

Thus, in the period until the STOP signal becomes high level, the potential decreases due to the influence of off-leakage or the like of the transistor T3 and the like until the potential of the node n1 pushed up by the clock signal CK becomes lower than VDD + Vth. The VDD is normally output from the output terminal OUT.

Further, as shown in FIG. 2, when the high-level input signal IN is input and the node n1 is precharged, the potential of the node n1 rises due to the rise by the clock signal CK, so that the output signal OUT rises quickly. As a result, the driving speed can be improved.

Here, the operation when the circuit 10 is affected by off-leakage or the like will be described in comparison with the conventional configuration. FIG. 5 is a timing chart showing waveforms of various signals when the circuit 10 is affected by off-leakage or the like. FIG. 6 is a timing chart showing waveforms of various signals when the conventional circuit 100 shown in FIG. 46 is affected by off-leakage or the like.

In the conventional circuit 100 shown in FIG. 46, when the node N1 has a leak path, the potential of the node N1 gradually decreases while the clock signal φ continues to be at a high level. At this time, even if the input signal IN becomes high level again, if the potential of the node N1 leaks to VDD−Vth or less, only the voltage of VDD−Vth is charged (the portion surrounded by the dotted line in FIG. 6). . Therefore, the output signal OUT is in a high impedance state and becomes weak against noise. Further, when the output signal OUT has a leak, the potential of the node N2 rises only to VDD−2 × Vth even if it is recharged, so that the operation margin of the subsequent circuit connected to the output terminal OUT is reduced. descend.

On the other hand, in the circuit 10 of the present embodiment, when the potential of the node n1 is pushed up by the clock signal CK and then drops by β potential due to leakage, VDD−Vth + α−β is obtained. After that, when the clock signal CK becomes low level, the potential of the node n1 becomes VDD−Vth−β. However, if the input signal IN is high level here, the potential of the node n1 reaches VDD−Vth. Charged. Therefore, when the clock signal CK becomes high level again, the potential of the node n1 is pushed up to VDD−Vth + α (portion surrounded by a dotted line in FIG. 5). Thus, even when there is a leak in the output signal OUT, the potential of VDD can be stably held. Therefore, a subsequent circuit connected to the output signal OUT can obtain a stable operation. In addition, since a high-potential signal is input to the gate terminal of the transistor T2, the output signal OUT can maintain a low impedance and is resistant to noise.

Thus, according to the configuration of the circuit 10 of the present embodiment, even if a leak or the like occurs in the output signal OUT, the potential of the node n1 can be charged again to VDD−Vth. Since the frequency of the clock signal CK is set higher than the frequency of the output signal, the potential of the node n1 is again increased to VDD + Vth or more by the push-up operation by the clock signal CK until the STOP signal becomes high level. Can be pushed up. Accordingly, it is possible to ensure a period during which VDD can be output and a period during which the impedance is low as compared with the conventional case.

In the circuit 10 of the present embodiment, the clock signal CK having a frequency higher than that of the output signal OUT is input to one end of the capacitor TC1, and the other end of the capacitor TC1 holds the high-level signal in a floating state. It is the structure connected to. With this configuration, it is possible to maintain a potential level and output a stable signal that is hardly affected by noise.

Here, the conventional circuit 200 (FIG. 48) has a problem that the power consumption increases because the capacity (clock load) of the clock terminal CK is large. Specifically, when the potential of the node n201 is high level (VDD−Vth or more), that is, when the STOP signal is low level and the node n201 is in a floating state, the above equation (1) (clock terminal CK The capacity of the clock terminal CK does not increase, so that power consumption does not increase, but the potential of the node n201 is low level (VSS), as shown by the following equation: 1 / (1 / C201 + 1 / Ctr)) In this case, that is, when the STOP signal is at a high level and the node n201 is not in the floating state, the capacity of the clock terminal CK increases as shown in the above equation (3) (capacitance of the clock terminal CK = C201). Power increases.

On the other hand, since the capacitor TC1 of the circuit 10 according to the present embodiment is configured by a transistor and functions as a MOS capacitor, the capacitor TC1 functions as an on-capacitance when the potential of the node n1 is higher than the potential of the clock signal CK. When the potential of the node n1 is lower than the potential of the clock signal CK, it functions as an off-capacitance.

Therefore, when the potential of the node n1 is low level (VSS), that is, when the STOP signal is high level and the node n1 is not in a floating state, the capacitance value becomes small as shown in FIG. Therefore, from the above equation (3), the load capacity of the clock terminal CK can be made smaller than the load capacity of the clock terminal CK in the conventional circuit 200. Thereby, the power consumption of the circuit 10 according to the present embodiment can be reduced as compared with the conventional circuit 200.

In the circuit 10 according to the present embodiment, the transistors T208 and T209, the inverter 206, and the capacitor C201 in the conventional circuit 210 shown in FIG. 49 are replaced with the capacitor TC1 shown in FIG. Thus, it is possible to achieve the effect, that is, low power consumption and potential stabilization of the node n203 (corresponding to between the clock terminal CK and the capacitor TC1 of the circuit 10). Therefore, since the circuit configuration can be simplified as compared with the conventional circuit 210, the circuit 10 and a device incorporating the circuit 10 can be downsized. In the conventional circuit 210, since the clock terminal CK and the capacitor C201 are connected via the transistor T208, the node n203 has a potential at which the potential of the clock signal drops. On the other hand, in the circuit 10 according to the present embodiment, since the clock terminal CK and the capacitor TC1 are connected without using a transistor, the threshold value does not drop. Therefore, the operation margin of the circuit 10 can be increased and the output signal can be further stabilized.

Here, the amplitude of the clock signal CK and the capacitor TC1 are set so that the potential (VDD−Vth + α) of the pushed-up node n1 is equal to or higher than VDD + Vth.

In the configuration of the circuit 10 shown in FIG. 1, the drain terminal of the transistor T2 is connected to the power supply VDD. However, the present invention is not limited to this. For example, the clock signal φ is input to the drain terminal. There may be. FIG. 7 is a timing chart showing waveforms of various signals in the configuration of the circuit 10 when the clock signal φ is input to the drain terminal of the transistor T2. In this configuration as well, as in the configuration of the circuit 10 shown in FIG. 1, since the potential level of the signal input to the transistor T2 can be output, the potential of the clock signal φ is turned on when the transistor T2 is turned on. The level is output.

[Embodiment 2]
The configuration of the circuit 20 in the present embodiment will be described below. FIG. 8 is a circuit diagram showing the configuration of the circuit 20, and FIG. 9 is a timing chart showing waveforms of various signals in the circuit 20. For convenience of explanation, members having the same functions as those shown in the first embodiment are given the same reference numerals, and explanation thereof is omitted. In addition, the terms defined in Embodiment 1 are used in accordance with the definitions in this embodiment unless otherwise specified.

Here, in the configuration of the circuit 10 shown in FIG. 1 (FIG. 1), the output terminal OUT is in a floating state (hatched line in FIG. 2) at the timing when the STOP signal becomes high level and the node n1 becomes low level potential. Therefore, the output signal OUT is easily affected by noise or the like.

Therefore, in order to eliminate this floating state, the circuit 20 of this embodiment further includes a transistor T4 (fourth transistor) in the circuit 10. As shown in FIG. 8, the transistor T4 has a drain terminal (first terminal) connected to the source terminal and the output terminal OUT of the transistor T2, a source terminal (second terminal) connected to the power source VSS, and a gate terminal. (Control terminal) is connected to the gate terminal of the transistor T3. The gate terminals of the transistors T3 and T4 are connected to the input terminal IN2, and an input signal IN2 for controlling on / off of the transistors T3 and T4 is input. A connection point between the transistors T2 and T4 and the output terminal OUT is a node n2.

According to the above configuration, as shown in FIG. 9, the transistors T3 and T4 are turned on by inputting the high-level input signal IN2 at the timing when the node n1 becomes the low-level potential. The electric charge of n1 can be surely discharged and the potential level of the output signal OUT can be fixed to the low level (VSS).

Note that the signal input to the gate terminal of the transistor T4 is not particularly limited as long as the potential level of the output signal OUT can be fixed to a low level (VSS), and another control signal may be input.

[Embodiment 3]
The configuration of the circuit 30 in the present embodiment will be described below. FIG. 10 is a circuit diagram showing the configuration of the circuit 30. For convenience of explanation, members having the same functions as those shown in the first and second embodiments are given the same reference numerals, and explanation thereof is omitted. Further, the terms defined in

Embodiments

1 and 2 are used in accordance with the definitions in this embodiment unless otherwise specified.

The circuit 30 of the present embodiment further includes a transistor T5 (fifth transistor) that plays a role of a refresh function in the circuit 20 shown in FIG. As shown in FIG. 10, the transistor T5 has a drain terminal (first terminal) connected to the power supply VDD, a source terminal (second terminal) connected to the node n1, and a gate terminal (control terminal) connected to the node n2. Connected to.

According to the above configuration, since the output signal OUT is input to the gate terminal of the transistor T5, the input signal IN1 is at a low level and the transistor T1 is off while the output signal OUT is at a high level. In some cases, even if the potential of the node n1 is decreased due to off-leakage or the like, the transistor T5 is charged again to VDD-Vth (refresh operation). Thus, the potential of the node n1 can be pushed up to VDD−Vth + α during the period when the clock signal CK outputs a high level. Therefore, the output signal OUT can stably output VDD, and can operate normally without malfunction during low frequency operation.

[Embodiment 4]
The configuration of the circuit 40 in the present embodiment will be described below. 11 is a circuit diagram showing the configuration of the circuit 40, and FIG. 12 is a timing chart showing waveforms of various signals in the circuit 40. As shown in FIG. For convenience of explanation, members having the same functions as those shown in the first to third embodiments are given the same reference numerals, and explanation thereof is omitted. Further, the terms defined in Embodiments 1 to 3 are used in accordance with the definitions in this embodiment unless otherwise specified.

In the circuit 40 of the present embodiment, in the circuit 20 shown in FIG. 8, a transistor T6 (sixth transistor) is further provided between the input terminal IN1 and the transistor T1. As shown in FIG. 11, the transistor T6 has a drain terminal (first terminal) connected to the input terminal IN1, a source terminal (second terminal) connected to the gate terminal of the transistor T1, and a gate terminal (control terminal). ) Is input with an enable signal EN. The source terminal of the transistor T6 is also connected to a connection point (node n2) between the transistors T2 and T4.

According to the above configuration, once the enable signal EN becomes high level, even if the enable signal EN subsequently becomes low level, if the output signal OUT is high level, the gate terminal of the transistor T1 is always high level. Can be input. Thereby, the circuit 40 can be kept in the active state.

In addition, since the output terminal OUT and the gate terminal of the transistor T1 are connected to each other, the transistor T1 is turned on when the potential of the node n1 is equal to or lower than VDD−Vth while the output signal OUT is at a high level. become. Note that when the potential of the node n1 becomes higher than VDD−Vth, the transistor T1 is turned off and the node n1 is in a floating state.

As a result, while the output signal OUT is outputting a high level, the potential of the node n1 is charged again to VDD-Vth by the transistor T1 (refresh operation) even if the potential of the node n1 decreases due to off-leakage or the like. Thus, during the period when the clock signal CK is outputting a high level, the potential of the node n1 can be pushed up to VDD−Vth + α, so that the output signal OUT can stably output VDD, It can operate normally without malfunction during low frequency operation.

Here, the transistor T6 is not limited to the configuration of FIG. 11 described above, and other configurations include, for example, a configuration in which the source terminal floats when the input signal IN1 becomes a low level potential. Includes the configuration shown in FIG. 13 and the configuration shown in FIG. 14. In the configuration shown in FIG. 13, the power supply VDD is connected to the drain terminal of the transistor T6, and the input signal IN1 is input to the gate terminal. In the configuration shown in FIG. 14, the input signal IN1 is input to the drain terminal and the gate terminal of the transistor T6. In these configurations, once the input signal IN1 becomes active (high level) regardless of other signals (for example, the enable signal EN), the active state is maintained even if the input signal IN1 subsequently becomes low level. Suitable for configuration.

[Embodiment 5]
The configuration of the circuit 50 in the present embodiment will be described below. FIG. 15 is a circuit diagram showing a configuration of the circuit 50. For convenience of explanation, members having the same functions as those shown in Embodiments 1 to 4 are given the same reference numerals, and explanation thereof is omitted. Further, the terms defined in Embodiments 1 to 4 are used in accordance with the definitions in this embodiment unless otherwise specified.

Here, in the circuit configurations shown in Embodiments 1 to 4, when the input signal IN is at a low level in the initial state, the amount of charge accumulated in the capacitor TC1 is not known, and the potential of the node n1 is in an indefinite state. It has become. Therefore, there is a problem that the initial state becomes unstable.

Therefore, in order to stabilize the initial state, the circuit 50 of the present embodiment further includes a transistor T7 (seventh transistor) in each of the circuits shown in the first to fourth embodiments. A circuit 50 illustrated in FIG. 15 includes a transistor T7 in addition to the circuit 10 illustrated in FIG. 1, and the transistor T7 receives an initialization signal INI at a gate terminal (control terminal) and a source terminal (first terminal). 2 terminal) is connected to the power supply VSS, and the drain terminal (first terminal) is connected to the node n1.

According to the above configuration, by inputting the high-level initialization signal INI in the initial state, the potential of the node n1 can be fixed to VSS, so that the initial state can be stabilized.

It should be noted that the initial state can be stabilized for each circuit of the second to fourth embodiments by providing the transistor T7 as described above.

[Embodiment 6]
The configuration of the circuit 60 in this embodiment will be described below. FIG. 16 is a circuit diagram showing the configuration of the circuit 60. For convenience of explanation, members having the same functions as those shown in the first to fifth embodiments are given the same reference numerals, and the explanation thereof is omitted. Is omitted. Further, the terms defined in Embodiments 1 to 5 are used in accordance with the definitions in this embodiment unless otherwise specified.

Here, in the circuit configurations described in Embodiments 1 to 5, since the node n1 is set to a high potential of VDD−Vth + α by the push-up operation of the clock signal CK, the transistor connected to the node n1 is connected between the gate and the source. A high voltage is applied between the gate and the drain and between the source and the drain. In some cases, the transistor exceeds its own withstand voltage, and there is a risk of being destroyed.

Specifically, in the circuit 10, a high voltage is applied particularly between the gate and drain and between the source and drain of the transistor T3. When the potential of the node n1 is raised when the input signal IN is VSS, VDD−Vth + α is obtained. Therefore, the voltage between the gate and the drain and between the source and the drain of the transistor T3 is VDD−Vth + α−VSS. Here, if VDD = 10V, VSS = −10V, α = 15V,
VDD-Vth + α-VSS = 35V-Vth
It becomes. On the other hand, a potential difference of 20 V between VDD and VSS is applied to other nodes. Thus, a high voltage is applied to the transistor connected to the node n1.

Therefore, as a countermeasure against the breakdown voltage of the transistor, the circuit 60 of this embodiment further includes a transistor T8 (eighth transistor) in each of the circuits shown in the first to fifth embodiments. A circuit 60 illustrated in FIG. 16 includes a transistor T8 in addition to the circuit 10 illustrated in FIG. 1. The transistor T8 includes a gate terminal (control terminal) connected to the power supply VDD and a drain terminal (first terminal). Terminal) is connected to the node n1, and the source terminal (second terminal) is connected to the drain terminal of the transistor T3. A connection point between the transistors T3 and T8 is a node n4.

According to the above configuration, when the input signal IN is VSS, the potential of the node n1 rises to VDD−Vth + α, but the node n4 rises only to VDD−Vth. Therefore, the voltage between the gate and the drain and between the source and the drain of the transistor T3 is VDD−Vth−VSS = 20V−Vth, and the applied voltage is lower by the α potential than in the case of the circuit 10.

Further, the gate-drain potential of the transistor T8 is α-Vth = 15V-Vth, the gate-source potential is Vth, and the source-drain potential is α = 15V, both of which are low voltages.

Accordingly, even when the potential of the node n1 in the floating state is raised by the clock signal CK, the voltage load applied to the transistor connected to the node n1 can be reduced, so that a highly reliable circuit can be configured. .

The above-described configuration of the present embodiment in which the transistor T8 takes measures against the withstand voltage of the transistor can be similarly applied to each circuit shown in the first to fifth embodiments.

Here, in each of the circuits shown in the first to sixth embodiments, the drain terminal of the transistor T1 is connected to the power supply VDD. However, the configuration of the circuit of the present invention is not limited to this, and may be a so-called diode-connected configuration in which the drain terminal and the gate terminal of the transistor T1 are connected to each other. 17 to 22 are circuits showing the configurations of the

circuits

11, 21, 31, 41, 51, and 61 when the transistor T1 is diode-connected in the

circuits

10, 20, 30, 40, 50, and 60 described above, respectively. FIG. For example, in the case where the transistor T1 is configured as in the circuit 10, when the transistor T3 is in an on state and a low level is input to the input terminal IN and the noise is generated in the input signal, the transistor T1 is instantaneously As a result, there is a problem that a through current flows from the power supply VDD to the power supply VSS via the transistors T1 and T3, resulting in an increase in current consumption or a malfunction. In this respect, according to the diode-connected configuration, since the gate terminal and the drain terminal of the transistor T1 are connected, even if noise occurs in the input terminal IN and the transistor T1 is turned on, the source − The potential difference between the drains is only the potential of noise, and the through current is reduced because the potential difference is small compared to the case where the power supply VDD is connected to the drain terminal. Further, since the transistor T3 is in the on state, even if the transistor T1 is turned on due to noise, the potential changed by the noise of the input terminal IN is pulled to the power supply VSS via the transistor T3. The action of turning off works. Therefore, malfunction of the transistor T1 due to the influence of noise can be prevented.

FIG. 23 is a timing chart showing waveforms of various signals in the circuit 11 shown in FIG. 17 among the respective circuits when the transistor T1 is diode-connected. As shown in FIG. 23, as in the configuration of the circuit 10 shown in FIG. 1, since the potential level of the signal input to the drain terminal of the transistor T2 can be output and held, the VDD is applied when the transistor T2 is turned on. Is output.

In the first embodiment, the configuration in which the clock signal φ is input to the drain terminal of the transistor T2 has been described. However, this configuration can also be applied to the circuit described in each embodiment. When turned on, the potential level of the clock signal φ is output.

Incidentally, as shown in FIG. 24, the clock signal CK input to the Active signal holding circuit of the present invention has a waveform in which a high level and a low level are periodically repeated. As described above, the output signal OUT of the Active signal holding circuit has a particularly low impedance when the clock signal CK is at a high level (period T). Therefore, as shown in FIG. 24, when the duty ratio of the clock signal CK is 50%, for example, the output signal OUT has a low impedance during this 50% period. That is, the low impedance period of the output signal OUT can be adjusted by adjusting the duty ratio of the clock signal CK.

Here, a preferable value for the duty ratio of the clock signal CK is examined with reference to the configuration of FIG. As described above, when the clock signal CK becomes low level, the potential of the node n1 decreases due to off-leakage or the like, and becomes VDD−Vth−β. Here, assuming that the time until the potential of the node n1 is recharged to VDD−Vth is tβ and the period is T1, the high period: low period = T1−tβ: tβ is an ideal duty ratio. Further, the period during which the clock signal CK shifts from the high level to the low level is determined by the time constant of the load (capacitance and resistance) of the clock CK terminal. If the period during which the clock signal CK transitions from the high level to the low level (or vice versa) is tck, if the tck period is not included as the pulse width, the desired push-up voltage is increased with respect to the push-up of the node n1. Since α cannot be obtained, from the viewpoint of the time constant, the ideal duty ratio is high period: low period = T1−tck: tck.

In actual operation, recharging due to off-leakage and the like and the transition of the clock signal CK from high level to low level are performed simultaneously. Therefore, if both are taken into consideration and the time until VDD−Vth is reached when the clock signal CK is at a low level is tβ ′, the high period: low period = T1−tβ ′: tβ ′ is the ideal duty ratio. Become. As a result, the output impedance of the transistor T2 can be lowered while normally maintaining the active state of the circuit.

According to the above consideration, the duty ratio of the clock signal is such that the low level period of one cycle of the clock signal CK is the period until the potential of the node n1 is saturated after the clock signal CK changes from the high level to the low level. It is preferable to set so as to be.

The duty ratio is preferably set so that the low impedance period of the transistor T2 is longer.

When the transition time in the clock signal CK exceeds 50%, the transition to the next high level is ensured without the low level after the transition. Therefore, in order to obtain the push-up voltage α, the capacitance TC1 is further increased. It is necessary to correct (correct). As a result, the circuit scale becomes large, or the capacity load increases, so that the transition time is further increased. In order to avoid this, the transition time is generally within 50% by slowing the frequency of the clock signal or by designing the load to be driven by the clock signal CK to be small. The duty ratio is preferably 50% or more so that the period of low impedance is as long as possible.

The clock signal CK_H in FIG. 24 is an example of a waveform when the high-level period T is lengthened (duty ratio is increased). This makes it possible to lengthen the low impedance period of the output signal OUT of the Active signal holding circuit. And since the period of low impedance can be lengthened, it becomes more resistant to noise and the load can be driven quickly. Thus, it is preferable that the clock signal CK has a higher frequency than the output signal OUT and has a high level (active side potential) period.

Note that in the case of using a p-channel transistor, since the logic is completely reversed, it is preferable that the low level period of the clock signal CK is long for the same reason.

Each circuit (Active signal holding circuit) shown in the first to sixth embodiments can be preferably used particularly in a liquid crystal display device (display device). FIG. 25 is a block diagram showing the overall configuration of the liquid crystal display device.

The liquid crystal display device 151 includes a pixel region 153, a source driver 154, a gate / CS driver 155, a BUFF / level shifter circuit 156, a power supply circuit 157, and a terminal 158 on the panel 152. The source driver 154 includes an output circuit 154 a and outputs a data signal to each source bus line in the pixel region 153. The gate / CS driver 155 includes an output circuit 155 a, outputs a selection signal to the gate bus line to write a data signal output from the source driver 154 to each pixel in the pixel region 153, and In order to increase the write potential to each pixel, a CS signal is output to the CS bus line. The

output circuits

154a and 155a are composed of a buffer which is an amplifier circuit with a low output impedance that generates a data signal of the same magnification from the input signal. The BUFF / level shifter circuit 156 includes buffers that are amplifier circuits with low output impedance, such as an equal magnification amplifier circuit that corrects signal attenuation such as an inverter, and a level shifter circuit that converts a power supply voltage level of the signal. The signal that has passed through the buffer is supplied to the source driver 154 and the gate driver 155. The power supply circuit 157 generates a power supply for a logic circuit, a reference voltage for a data signal, a counter voltage, an auxiliary capacitance voltage, and the like. Terminals 158... Are terminals for inputting signals and power to the above-described circuits on the panel 152. The liquid crystal display device may be configured by a demultiplexer instead of the source driver.

Each circuit shown in the first to sixth embodiments can be applied to each part in the liquid crystal display device 151, and in particular, a switch, a buffer circuit, a level shifter circuit, a source driver (data signal) in the CS driver. Line driver circuit) and a shift register in a gate driver (scanning signal line driver circuit). Further, the present invention can be applied to a common electrode driving circuit (COM driver). In the following, as an example, an example applied to a memory circuit provided in a CS driver (Example 1), an example applied to a buffer circuit and a level shifter circuit (Examples 2 to 4), and an example applied to a shift register (Example 1) Example 5) will be described.

[Example 1]
FIG. 26 is a block diagram showing a configuration of the memory circuit 1 provided in the CS driver in the present embodiment, and FIG. 27 is a circuit diagram of the memory circuit 1. FIG. 28 is a timing chart showing waveforms of various signals in the memory circuit 1. The memory circuit 1 includes the two circuits (Active signal holding circuits) described in the above embodiments. Specifically, in the memory circuit 1, for example, the STOP terminal of one circuit 10 (denoted as the circuit 10b) shown in FIG. 1 and the output terminal OUT of the other circuit 10 (denoted as the circuit 10a) are connected. It is constituted by. The memory circuit only needs to have at least the configuration of the circuit 10 shown in FIG. 1. In the memory circuit 1 of this embodiment, in addition to the configuration of the circuit 10, the transistor T4 (transistors Ta4 and Tb4 in FIG. 26). And includes the configuration of the circuit 20 shown in FIG.

Next, the operation of the memory circuit 1 will be described. In this example, when the enable signal EN is at a high level, a high-level input signal IN is input to the circuit 10a, and a low-level input signal INB (an inverted signal of IN) is input to the circuit 10b. I will give you a description.

The circuit 10a to which a high-level signal is input is in an active state, and the node na1 holds charges while the clock signal is input. Therefore, the output signal OUT of VDD is output from the circuit 10a as described in the above embodiments. The output signal OUT is input to the STOP terminal (FIG. 26) of the other circuit 10b.

The circuit 10b in which the VDD signal is input to the STOP terminal becomes inactive, and VSS is output from the transistor Tb4. Since IN and INB have opposite polarities, when one outputs VDD, the other outputs VSS. Thus, while the clock signal CK is being input, the potentials of the

circuits

10a and 10b are held until the next enable signal EN becomes high level.

In the memory circuit 1 of FIG. 26, the inverted signal INB of the input signal IN is input from the outside. However, the configuration is not limited to this, and other configurations are shown in FIGS. 29 and 30, for example. As described above, the inverter circuit may be configured in the memory circuit 1 to generate the inverted signal INB from the input signal IN. FIG. 29 shows an inverter constituted by a resistor R1 and a transistor T11, and FIG. 30 shows an inverter constituted by a bootstrap circuit. According to these configurations, when the input signal IN is at a high level (VDD), a low level (VSS) signal is output as the inverted signal INB, and when the input signal IN is at a low level (VSS), the high level is output. The signal (VDD) is output as the inverted signal INB.

In the memory circuit 1 of FIG. 26, for example, the transistor T7 (FIG. 15) shown in the fifth embodiment may be provided in each of the

circuits

10a and 10b in order to stabilize the initial state. In the transistor Ta7 of the circuit 10a and the transistor Tb7 of the circuit 10b, the initialization signal INI is input to the gate terminal, the respective drain terminals are connected to the node na1 and the node nb1, and the respective source terminals are the power supply VSS and the power supply Connected to each of VDD. Thus, the initial state can be stabilized by inputting the high-level initialization signal INI in the initial state.

Note that, since the memory circuit 1 has the refresh function described in the above embodiment, it is possible to normally hold a value even at low frequency driving.

In this example, the memory circuit 1 configured by the circuit 20 of the second embodiment has been described. However, the memory circuit 1 according to another embodiment (for example, the

circuit

30, 40, or 50) may be configured. In these configurations, the same effect can be obtained.

[Example 2]
FIG. 31 is a block diagram showing the configuration of the buffer circuit 2 in the present embodiment, and FIG. 32 is a circuit diagram of the buffer circuit 2. The buffer circuit 2 includes the circuit (Active signal holding circuit) shown in each of the above embodiments. Specifically, the buffer circuit 2 only needs to have at least the configuration of the circuit 10 shown in FIG. 1. In the buffer circuit 2 of this embodiment, a transistor T4 is provided in addition to the configuration of the circuit 10, and FIG. 8 includes the configuration of the circuit 20 shown in FIG.

Here, the inverter that generates the signal INB input to the circuit 10 is composed of a resistor R1 and a transistor T11. Therefore, when the input signal IN of the inverter is at a high level, a steady current (through current) flows from the power supply VDD to the power supply VSS, and power consumption increases. Therefore, in order to reduce power consumption, it is conceivable to configure the resistor R to have a high resistance. However, in this case, there arises a problem that the drive capability is lowered and a new problem that the resistance becomes weak against noise. .

In this regard, in the buffer circuit 2 of the present embodiment, since the output terminal INB of the inverter is connected only to the gate terminal of the transistor T1 of the circuit 10, the load becomes very small. Therefore, even if the drive capability of the inverter is reduced (even if the resistor R1 is set to a high resistance), the load at the gate terminal of the transistor T1 can be driven quickly, so that high-speed operation is possible and operation of the circuit 10 As a result, the driving capability of the buffer circuit 2 itself can be increased. Therefore, according to the above configuration, a buffer circuit with low power consumption and high driving capability can be configured.

In addition, although the buffer circuit 2 comprised by the circuit 20 of the said Embodiment 2 was demonstrated in the present Example, you may comprise by the circuit (for example,

circuit

30, 40 or 50) in other embodiment. In these configurations, the same effect can be obtained.

In the buffer circuit 2 of this embodiment, when the voltage of the input signal IN is input with a voltage other than VDD / VSS (for example, when the High voltage is lower than VDD and the Low voltage is VSS), the level shifter Functions as a circuit.

In the buffer circuit and the level shifter circuit, as shown in FIGS. 33 and 34, the inverter may be constituted by a bootstrap circuit. Also in this configuration, when the input signal IN is at a high level, a steady current (through current) flows from the power supply VDD to the power supply VSS through the transistors T12 and T13, and power consumption increases. Therefore, in order to reduce power consumption, it is conceivable to reduce the size of the transistors T12 and T13. In this case, however, the problem is that the driving capability is reduced, as in the case of an inverter using resistors, and noise. A new problem of weakening.

In this regard, in the buffer circuit and the level shifter circuit shown in FIGS. 33 and 34, since the output terminal INB of the inverter is connected only to the gate terminal of the transistor T1 of the circuit 10, it is configured by the inverter using the above-described resistor. The same effect as the buffer can be obtained.

Example 3
Next, another configuration example of the buffer circuit will be described. FIG. 35 is a circuit diagram showing a configuration of the buffer circuit 3 in the present embodiment. The buffer circuit 3 includes the inverter shown in FIG. 29 and a configuration obtained by modifying the circuit 20 shown in FIG. Specifically, in the circuit 20 shown in FIG. 8, the transistor T3 is omitted, and the transistor T1 has a gate terminal connected to the power supply VDD and a drain terminal connected to the output terminal INB of the inverter. The gate terminal of the transistor T3 is connected to the input terminal IN of the inverter.

Here, the operation of the buffer circuit 3 of this embodiment will be described.

First, when the input signal IN of the inverter is at a low level, the inverted signal INB becomes VDD. When the inverted signal INB of VDD is input to the transistor T1, the potential of the node n1 is charged to VDD−Vth, and the potential of the node n1 rises to VDD−Vth + α by the push-up operation by the clock signal CK. Since the node n1 is connected to the gate terminal of the transistor T2, the potential of the output signal OUTB is VDD with no threshold drop.

Next, when the input signal IN of the inverter becomes high level, the inverted signal INB becomes VSS, and the potential of the node n1 is discharged to VSS. At this time, since the input signal IN is at a high level, the transistor T3 is turned on, and the potential of the output signal OUTB becomes VSS.

According to this configuration, when the potential of the node n1 is high due to the push-up operation of the clock signal CK, the transistor T2 has low impedance, so that it is resistant to noise and can drive the load quickly.

Even when the node n1 is discharged due to leakage, if the potential of the node n1 becomes lower than VDD−Vth, the transistor T1 is turned on and recharged, so that a margin for malfunction during low frequency operation is ensured. be able to.

Even if the resistance R1 is made high, the load charged by this terminal is only the parasitic capacitances of the transistors T1 and T2 and the capacitance TC1, so that high-speed driving is possible and low power consumption can be achieved. it can.

Furthermore, as compared with the configuration of the buffer circuit 2 of the second embodiment, the transistor T3 for discharging the node n1 is not necessary, so that the circuit scale can be reduced.

Also in the buffer circuit 3 of the present embodiment, when the voltage of the input signal IN is input with a voltage other than VDD / VSS (for example, when the High voltage is lower than VDD and the Low voltage is VSS), Functions as a level shifter circuit.

Further, in the buffer circuit and the level shifter circuit, the inverter may be constituted by a bootstrap circuit as in the second embodiment. FIG. 36 is a circuit diagram showing a configuration of a buffer circuit including an inverter configured by a bootstrap circuit.

Note that the buffer circuit 2 of the second embodiment can operate normally even when the input signal IN is a DC signal.

In the buffer 3 of the third embodiment, even when the input signal IN is a DC signal, the voltage at the gate terminal of the transistor T12 becomes VDD−Vth due to off-leakage. Therefore, since the voltage at the output terminal of the inverter is VDD-2 × Vth, the node n1 is VDD-2 × Vth. Although the potential of the node n1 becomes VDD−2 × Vth + α due to the rising of the clock signal CK, if the capacitor TC1 is set so that it becomes larger than VDD + Vth, it operates normally even when the input signal IN is a DC signal. It is possible.

Example 4
Furthermore, another configuration example of the buffer circuit will be described. FIG. 37 is a block diagram showing a configuration of the buffer circuit 4 in the present embodiment, and FIG. 38 is a circuit diagram of the buffer circuit 4. The buffer circuit 4 includes the inverter shown in FIG. 29 and the circuit 10 shown in FIG. Specifically, as shown in FIG. 38, the output terminal INB of the inverter is connected to the gate terminal of the transistor T1 and the output terminal OUTB of the buffer circuit 4, and the gate terminal of the transistor T3 is connected to the input terminal IN of the inverter. Connected.

According to the buffer circuit 4 of the present embodiment, when the input signal IN of the inverter is at a low level, the inverted signal INB is output from the high resistance R1, and thus becomes the high impedance VDD, but the output signal of the circuit 10 (transistor With the output signal T2), the output signal OUTB can obtain a low impedance VDD.

In the buffer circuit 4, since the output terminals INB and OUTB are connected to each other, even when the clock signal CK is stopped, it is possible to output a signal having a potential of VDD that does not drop the threshold value.

Further, the same effect can be obtained even when the circuit shown in another embodiment is used instead of the circuit 10.

Also in the buffer circuit 4 of this embodiment, when the voltage of the input signal IN is input with a voltage other than VDD / VSS (for example, when the High voltage is lower than VDD and the Low voltage is VSS), Functions as a level shifter circuit.

The buffer circuit 4 of this embodiment can operate normally even when the input signal IN is a DC signal, like the

buffer circuits

2 and 3 of the second and third embodiments.

Here, in the buffer circuits shown in the first to fourth embodiments, the input signal IN and the inverted signal INB may be interchanged.

Example 5
FIG. 39 is a block diagram showing the configuration of the unit circuit 5 constituting the shift register in this embodiment. The shift register is configured by cascade connection of the unit circuits 5 shown in FIG. 39, and the unit circuit 5 is configured to include the circuit (Active signal holding circuit) 10 shown in the first embodiment. A conventional configuration can be applied to the configuration excluding the circuit 10.

Here, in the configuration of the conventional unit circuit of the shift register, when both the input signals On-1 and On + 1 are at the low level, the node n5 is in a floating state, so that the margin for leakage and noise is reduced. There's a problem.

In this respect, in the configuration of the unit circuit 5 of the shift register of the present embodiment, the output signal of the circuit 10 is fed back to the input side of the circuit 10. Accordingly, since the node n5 can be held at a high level that is not in a floating state, the disabled state of the shift register can be held. Therefore, the problem with respect to leakage and noise can be solved.

In the shift register to which the unit circuit 5 is cascade-connected, the clock signal CK1 is input to the clock terminal CK of the even-numbered unit circuit 5 among the clock signals CK1 and CK2 that do not become high level at the same time. The clock signal CK2 is input to the clock terminal CK of the unit circuit 5 in the stage, the input signal On-1 is an output signal from the unit circuit 5 in the previous stage, and the input signal On + 1 is an output signal from the unit circuit 5 in the subsequent stage.

In the above configuration, when the input signal On-1 becomes high level, charges are stored in the bootstrap capacitor C2 via the transistor T14, and the node n6 remains in the high level state even after the input signal On-1 becomes low level. Hold. Further, when the transistor T16 is turned on, the node n5 becomes low level. When the clock signal CK becomes high level, the clock signal CK is output from the output terminal On due to the bootstrap effect. When the input signal On + 1 becomes high level, the node n5 becomes high level via the transistor T15, and the transistor T17 is turned on, so that the output signal On becomes low level.

Further, when the input signal IN of the circuit 10 becomes high level, the transistor T1 is turned on, and electric charge is stored in the capacitor TC1. Thereafter, every time the clock signal CK is input, the potential of the output signal OUT is raised to VDD through the transistor T2, so that the potential of the node n5 does not decrease due to off-leakage or the like. Then, since the output signal OUT of VDD is fed back to the input terminal IN, the potential of the node n5 is held at VDD until the input signal On-1 next becomes the high level.

As described above, by applying the circuit 10 (Active signal holding circuit) of the first embodiment to the conventional shift register, the potential of the node n5, which has been lowered due to a drop in threshold value, leakage, or the like in the past, is obtained. It can be reliably held at VDD.

In the fifth embodiment, the shift register configured by the circuit 10 according to the first embodiment has been described. However, the shift register may be configured by a circuit according to another embodiment. In these configurations, the same effect can be obtained.

Further, the configuration of the shift register to which the circuit in each embodiment can be applied is not particularly limited. As another shift register configuration, for example, as shown in FIGS. 40 and 41, the unit circuit of each stage in the shift register does not use the output signal of the subsequent unit circuit, that is, it A configuration in which a reset signal is generated in a unit circuit of a stage can be given. In these configurations as well, the disabled state can be maintained. Of the clock signals CK1 and CK2 that do not simultaneously become high in any unit circuit, the clock signal CK1 is input to the clock terminal CK of the even-numbered unit circuit, and the clock signal CK2 is input to the clock terminal CKB. , The clock signal CK2 is input to the clock terminal CK of the odd-numbered unit circuit 5, the clock signal CK1 is input to the clock terminal CKB, and the input signal On-1 is the output signal of the unit circuit 5 of the previous stage. It is.

In the unit circuit 5 shown in FIG. 40, charges are stored in the bootstrap capacitor C2 by the output signal On-1 of the preceding unit circuit 5, and after the clock signal CK is output to the output terminal On, the clock signal CKB is at the high level. Then, the transistor T20 is turned on, so that the potential of the node n5 becomes high level by the resistor R2.

In the unit circuit 5 shown in FIG. 41, charges are stored in the bootstrap capacitor C2 by the output signal On-1 of the previous unit circuit 5, and after the clock signal CK is output from the output terminal On, the clock signals CK and CKB For each input, the charge in the capacitor C3 is transferred to the capacitor C4, and the potential of the node n5 goes high.

Similarly, in the unit circuit 5 of FIGS. 40 and 41, the circuit 10 holds the potential of the node n5 at VDD until the next time the input signal On-1 becomes high level.

Finally, an example of the case where the circuit in each of the above embodiments is configured using a p-channel transistor is shown. In order to configure the contents described in Embodiments 1 to 6 and Examples 1 to 5 using p-channel transistors, the power supply VDD is set to the power supply VSS, the power supply VSS is set to the power supply VDD, and the high level is set to the low level. This is possible by reversing all the logic. FIG. 42 is a circuit diagram of a circuit 10 ′ when the circuit 10 is configured by p-channel transistors. FIG. 43 is a timing chart showing waveforms of various signals in the circuit 10 ′. FIG. 43A shows a waveform when VSS is input to the drain terminal of the transistor T2 ′, and FIG. ) Shows a waveform when the clock signal φ is input to the drain terminal of the transistor T2 ′. Even in this configuration, as in the case of the circuit configured by the n-channel transistor described above, a simple configuration can output a stable signal while preventing a decrease in potential level while reducing power consumption. There is an effect.

Here, a specific configuration of the capacitor TC1 ′ in the circuit 10 ′ shown in FIG. 42 will be described. 44A is a diagram showing the configuration of the capacitor TC1 ′, and FIG. 44B is a graph showing the relationship between the applied voltage and the capacitance value in the capacitor TC1 ′. FIG. 45A is a diagram showing a configuration of a conventional capacitor (PNOS type), and FIG. 45B is a graph showing a relationship between an applied voltage and a capacitance value in the capacitor.

As shown in FIG. 45A, the conventional capacitor is formed by doping silicon Si with P + and forming a capacitor between the gate electrode GE and Si. In the case of this capacitance, as shown in FIG. 45B, the capacitance value is substantially constant regardless of the voltage between the gate electrode and Si.

On the other hand, in the capacitor TC1 ′ of the circuit 10 ′ according to the present embodiment, as shown in FIG. 44A, Si (silicon layer) is not doped with P +. As a result, the capacitor TC1 ′ functions as a MOS capacitor, and does not function as a capacitor unless a voltage (ON voltage) is applied to the gate electrode GE. That is, the capacitor TC1 ′ functioning as a transistor is turned off when the potential of the node n1 ′ is higher than the potential of the clock terminal CK, while the potential of the node n1 ′ is equal to or lower than the potential of the clock terminal CK (on voltage). Turns on when there is. In FIG. 44 (b), Von represents the on-voltage.

Therefore, the capacitance value of the capacitor TC1 ′ changes according to the voltage between the gate electrode and Si, as shown in FIG. 44 (b). That is, as the voltage applied to the gate electrode decreases, the capacitance value of the capacitor TC1 ′ increases. More specifically, the capacitance value of the capacitor TC1 ′ increases as the potential of the node n1 ′ decreases, while the capacitance value of the capacitor TC1 ′ decreases as the potential of the node n1 ′ increases.

As described above, the semiconductor device according to the present invention includes a capacitor provided between a connection point between the first transistor and the second transistor and a clock terminal that inputs a clock signal, and the clock signal Is set higher than the frequency of the output signal output from the output terminal, and the capacitance value of the capacitor changes according to the change in the potential at the connection point. That is, when the Si forming the capacitor is an NMOS process, the capacitance decreases as the potential at the connection point decreases, while the capacitance value increases as the potential at the connection point increases. Or (ii) when the Si forming the capacitance is a PMOS process, the capacitance value increases as the potential at the connection point decreases, while the capacitance value increases as the potential at the connection point increases. Therefore, the capacitance value becomes small. When the Si forming the capacitor is an NMOS process, Si is not doped with N +, and when the Si forming the capacitor is a PMOS process, Si is not doped with P +.

The display device according to the present invention includes the semiconductor device.

Accordingly, a semiconductor device that includes transistors of the same conductivity type and can output a stable signal with a simple configuration while reducing power consumption and preventing a decrease in potential level, and a display device including the semiconductor device are provided. There is an effect that can be done.

A semiconductor device according to the present invention is the above semiconductor device,
The capacitance includes silicon, and the capacitance value decreases as the potential at the connection point decreases, and the capacitance value increases as the potential at the connection point increases. it can.

A semiconductor device according to the present invention is the above semiconductor device,
The capacitor includes silicon, and the capacitance value increases as the potential at the connection point decreases, and the capacitance value decreases as the potential at the connection point increases. it can.

A semiconductor device according to the present invention is the above semiconductor device,
The capacitor is composed of a transistor having a control terminal connected to the connection point, and a first terminal and a second terminal connected to the clock terminal,
The transistor constituting the capacitor is turned off when the potential at the connection point is lower than the potential at the clock terminal, and is turned on when the potential at the connection point is equal to or higher than the potential at the clock terminal. It can also be set as the structure which becomes.

According to the above configuration, since the capacitor is formed of a transistor and functions as a MOS capacitor, the capacitor functions as an on-capacitance when the node potential is higher than the clock signal potential, and the node potential is higher than the clock signal potential. When it is low, it functions as an off-capacitance. Since the semiconductor device of the present invention includes the capacitor, the circuit configuration can be simplified.

A semiconductor device according to the present invention is the above semiconductor device,
The capacitor is composed of a transistor having a control terminal connected to the connection point, and a first terminal and a second terminal connected to the clock terminal,
The transistor constituting the capacitor is turned off when the potential of the connection point is higher than the potential of the clock terminal, and is turned on when the potential of the connection point is equal to or lower than the potential of the clock terminal. It can also be set as the structure which becomes.

According to the above configuration, since the capacitor is configured by a transistor and functions as a MOS capacitor, the capacitor functions as an on-capacitance when the node potential is lower than the clock signal potential, and the node potential is higher than the clock signal potential. When it is high, it functions as an off-capacity. Since the semiconductor device of the present invention includes the capacitor, the circuit configuration can be simplified.

A semiconductor device according to the present invention is the above semiconductor device,
The silicon constituting the capacitor may be configured not to be doped with N +.

A semiconductor device according to the present invention is the above semiconductor device,
The silicon constituting the capacitor may be configured not to be doped with P +.

A semiconductor device according to the present invention is the above semiconductor device,
The capacitor is preferably formed between the gate electrode as the control terminal and the silicon as the first terminal and the second terminal.

A semiconductor device according to the present invention is the above semiconductor device,
It is desirable to further include a third transistor in which the first terminal is connected to the connection point, the off voltage is input to the second terminal, and the control signal is input to the control terminal.

According to the above configuration, when the third transistor is turned on by the control signal, the potential of the node can be reliably lowered to VSS.

A semiconductor device according to the present invention is the above semiconductor device,
It is desirable to further include a fourth transistor having a first terminal connected to the output terminal, an off voltage applied to the second terminal, and the control signal input to the control terminal.

According to the above configuration, when the third and fourth transistors are turned on by the control signal, the potential of the node can be reliably lowered to VSS and the potential level of the output signal is set to the low level (off voltage). : VSS).

A semiconductor device according to the present invention is the above semiconductor device,
It is desirable to further include a fifth transistor in which an on-voltage is input to the first terminal, a second terminal is connected to the connection point, and a control terminal is connected to the output terminal.

According to the above configuration, since the output signal is input to the control terminal of the fifth transistor, the input signal becomes low level while the output signal is outputting high level (ON voltage: VDD). When the first transistor is off, the fifth transistor is again charged to VDD-Vth even if the potential of the node is decreased due to off-leakage or the like.

This makes it possible to push the potential of the node up to VDD−Vth + α during the period when the clock signal is outputting a high level. Therefore, the potential level of the output signal can be further stabilized.

A semiconductor device according to the present invention is the above semiconductor device,
A sixth transistor that outputs the input signal;
The sixth transistor has a first terminal connected to the input terminal, a second terminal connected to the control terminal and the output terminal of the first transistor, and an enable signal input to the control terminal. desirable.

According to the above configuration, once the enable signal becomes high level, even if the enable signal subsequently becomes low level, if the output signal is high level, the control signal of the first transistor is always high level. A signal can be input. Thereby, the active state of the semiconductor device can be stably maintained.

In the semiconductor device according to the present invention, in the semiconductor device, the first terminal is connected to the connection point, the off voltage is input to the second terminal, and the initial state of the semiconductor device is stabilized at the control terminal. It is desirable to further include a seventh transistor to which the initialization signal is input.

According to the above configuration, the potential of the node can be fixed to VSS by inputting a high-level initialization signal to the seventh transistor in the initial state, so that the initial state can be stabilized. .

A semiconductor device according to the present invention is the above semiconductor device,
The clock signal has a waveform that periodically repeats a high level and a low level, and the potential at the connection point is saturated after the clock signal changes from a high level to a low level during a low level period in one cycle. It is desirable that the period is set to be a period until.

This makes it possible to reduce the impedance of the output signal while maintaining the active state of the semiconductor device.

A display device according to the present invention includes any one of the above semiconductor devices.

Thereby, it is possible to provide a display device that can prevent a decrease in potential level and output a stable signal.

The display device according to the present invention is preferably a liquid crystal display device.

The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

Since the present invention is a circuit that can stably output without lowering the potential level of an input signal, it can be suitably applied particularly to a display device.

1

memory circuit

2, 3, 4 buffer circuit 5 unit circuit (of shift register) 10, 20, 30, 40, 50, 60 circuit (semiconductor device)
11, 21, 31, 41, 51, 61 Circuit (semiconductor device)
T1 transistor (first transistor)
T2 transistor (second transistor)
T3 transistor (third transistor)
T4 transistor (fourth transistor)
T5 transistor (fifth transistor)
T6 transistor (sixth transistor)
T7 transistor (seventh transistor)
T8 transistor (eighth transistor)
TC1 transistor (capacitance)
151 Liquid crystal display device (display device)
n1, n2, n4, n5, n6 nodes (connection points)
100, 200, 210 circuit (conventional semiconductor device)

Claims

A semiconductor device composed of a plurality of transistors of the same conductivity type,
A first transistor in which an on-voltage is applied to the first terminal and an input signal is input to the control terminal;
A second transistor having an on-voltage applied to the first terminal, a second terminal connected to the output terminal, and a control terminal connected to the second terminal of the first transistor;
A capacitor provided between a connection point between the first transistor and the second transistor and a clock terminal for inputting a clock signal;
The frequency of the clock signal is set higher than the frequency of the output signal output from the output terminal,
The semiconductor device is characterized in that a capacitance value of the capacitor changes according to a change in potential of the connection point.
The capacitor is configured to include silicon, and the capacitance value decreases as the potential at the connection point decreases, while the capacitance value increases as the potential at the connection point increases. The semiconductor device according to claim 1.
The capacitance is configured to include silicon, and the capacitance value increases as the potential at the connection point decreases, while the capacitance value decreases as the potential at the connection point increases. The semiconductor device according to claim 1.
The capacitor is composed of a transistor having a control terminal connected to the connection point, and a first terminal and a second terminal connected to the clock terminal,
The transistor constituting the capacitor is turned off when the potential at the connection point is lower than the potential at the clock terminal, and is turned on when the potential at the connection point is equal to or higher than the potential at the clock terminal. The semiconductor device according to claim 2, wherein
The capacitor is composed of a transistor having a control terminal connected to the connection point, and a first terminal and a second terminal connected to the clock terminal,
The transistor constituting the capacitor is turned off when the potential of the connection point is higher than the potential of the clock terminal, and is turned on when the potential of the connection point is equal to or lower than the potential of the clock terminal. The semiconductor device according to claim 3, wherein
5. The semiconductor device according to claim 2, wherein the silicon constituting the capacitor is not doped with N +.
6. The semiconductor device according to claim 3, wherein the silicon constituting the capacitor is not doped with P +.
8. The semiconductor according to claim 6, wherein the capacitor is formed between a gate electrode as the control terminal and the silicon as the first terminal and the second terminal. apparatus.
The semiconductor device further comprises a third transistor having a first terminal connected to the connection point, an off-voltage input to the second terminal, and a control signal input to the control terminal. 8. The semiconductor device according to 8.
10. The apparatus according to claim 9, further comprising: a fourth transistor having a first terminal connected to the output terminal, an off voltage applied to the second terminal, and the control signal input to a control terminal. A semiconductor device according to 1.
11. The apparatus further comprises a fifth transistor in which an on-voltage is input to the first terminal, a second terminal is connected to the connection point, and a control terminal is connected to the output terminal. A semiconductor device according to 1.
A sixth transistor that outputs the input signal;
The sixth transistor has a first terminal connected to the input terminal, a second terminal connected to the control terminal of the first transistor and the output terminal, and an enable signal input to the control terminal. The semiconductor device according to claim 11.
A seventh transistor having a first terminal connected to the connection point, an off-voltage input to the second terminal, and an initialization signal for stabilizing an initial state of the semiconductor device to the control terminal; The semiconductor device according to claim 12, further comprising:
A semiconductor device composed of a plurality of transistors of the same conductivity type,
A first transistor in which an on-voltage is applied to the first terminal and an input signal is input to the control terminal;
A second transistor having an on-voltage applied to the first terminal, a second terminal connected to the output terminal, and a control terminal connected to the second terminal of the first transistor;
A capacitor provided between a connection point between the first transistor and the second transistor and a clock terminal for inputting a clock signal;
An eighth transistor having a first terminal connected to the connection point and an on-voltage input to the control terminal;
A third transistor having a first terminal connected to the second terminal of the eighth transistor, an off-voltage input to the second terminal, and a control signal input to the control terminal;
The frequency of the clock signal is set higher than the frequency of the output signal output from the output terminal,
The semiconductor device is characterized in that a capacitance value of the capacitor changes according to a change in potential of the connection point.
The clock signal has a waveform that periodically repeats a high level and a low level, and the potential at the connection point is saturated after the clock signal changes from a high level to a low level during a low level period in one cycle. The semiconductor device according to claim 1, wherein the semiconductor device is set so as to have a period until completion.
A display device comprising the semiconductor device according to claim 1.