WO2012108122A1 - Capacitor array and method for installing capacitor array - Google Patents

Capacitor array and method for installing capacitor array Download PDF

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Publication number
WO2012108122A1
WO2012108122A1 PCT/JP2012/000077 JP2012000077W WO2012108122A1 WO 2012108122 A1 WO2012108122 A1 WO 2012108122A1 JP 2012000077 W JP2012000077 W JP 2012000077W WO 2012108122 A1 WO2012108122 A1 WO 2012108122A1
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WO
WIPO (PCT)
Prior art keywords
capacitor
esr
capacitor element
capacitor array
external electrode
Prior art date
Application number
PCT/JP2012/000077
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French (fr)
Japanese (ja)
Inventor
崇 市村
功 山長
貴博 東
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株式会社村田製作所
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Publication of WO2012108122A1 publication Critical patent/WO2012108122A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/38—Multiple capacitors, i.e. structural combinations of fixed capacitors

Definitions

  • the present invention relates to a capacitor array in which a plurality of capacitor elements are arranged in one dielectric body, and a mounting method of the capacitor array.
  • a decoupling capacitor is inserted between the power supply and ground in order to absorb load fluctuations during IC and LSI operation and to eliminate noise.
  • the power source impedance is preferably as low as possible, and therefore the impedance of the decoupling capacitor is preferably low.
  • ESL Equivalent Series Inductance
  • ESR Equivalent Series Resistance
  • ESC Equivalent Series Capacitance
  • the power source impedance decreases as the frequency increases on the low frequency side with respect to the resonance frequency, but tends to increase as the frequency increases on the high frequency side. That is, the power source impedance exhibits a valley-type characteristic near the resonance frequency.
  • the power source impedance increases as the frequency increases on the low frequency side with the anti-resonance frequency as a boundary, but decreases as the frequency increases on the high frequency side. That is, it exhibits a mountain-shaped characteristic near the antiresonance frequency.
  • the impedance is minimized and kept low, so that the voltage fluctuation is small.
  • the anti-resonance frequency the impedance becomes maximum, and the voltage fluctuation is large.
  • Patent Document 1 discloses a composite multilayer ceramic capacitor in which a small capacity multilayer ceramic capacitor element and a large capacity multilayer ceramic capacitor element having a large equivalent series resistance are combined.
  • This composite multilayer ceramic capacitor has a resistance value of an equivalent series resistance of an external electrode of a large-capacity multilayer ceramic capacitor element larger than a resistance value of an equivalent series resistance of an external electrode in a small-capacity multilayer ceramic capacitor element.
  • a ceramic capacitor element and a small-capacity multilayer ceramic capacitor element are combined with a gap of a predetermined distance or more.
  • the equivalent series resistance in the large-capacity multilayer ceramic capacitor element is large, it is possible to show a gentle impedance characteristic with respect to the frequency and to improve the high frequency characteristic.
  • the electrodes of the large-capacity multilayer ceramic capacitor element and the electrodes of the small-capacity multilayer ceramic capacitor element are coupled, the directions of current flowing through both elements are the same. Therefore, when the gap is reduced, electromagnetic coupling occurs, and current flowing in one element may flow in the other element. Therefore, it is difficult to reduce the size of the composite multilayer ceramic capacitor described above.
  • the present invention has been made to solve the above problems, and can reduce the power supply impedance at the anti-resonance frequency while keeping the power supply impedance at the resonance frequency low, and further reduce the size.
  • An object of the present invention is to provide a capacitor array that can be used.
  • a capacitor array according to the present invention is a capacitor array mounted between a power source and a ground of a multilayer board, and includes a dielectric element body, a plurality of capacitor elements disposed in the dielectric element body, and A plurality of capacitor elements including at least two types of capacitor elements having different equivalent series resistance values, and arranged in the arrangement direction of the plurality of capacitor elements.
  • the external electrodes that are adjacent to each other are mounted on the multilayer substrate, the polarities of the connected power sources are different from each other.
  • the plurality of capacitor elements constituting the capacitor array include at least two types of capacitor elements having different equivalent series resistance (ESR) values. That is, a capacitor element having a higher ESR value than other capacitor elements is included. Therefore, when the capacitor array is mounted, the current flowing from the power source to the ground is a capacitor element having a smaller ESR value (hereinafter referred to as “low ESR capacitor”) at a frequency other than the vicinity of the anti-resonance frequency (including the resonance frequency). Element "), and passes through a capacitor element having a higher ESR value (hereinafter also referred to as" high ESR capacitor element ”) at a frequency near the anti-resonance frequency.
  • ESR equivalent series resistance
  • the impedance at the anti-resonance frequency can be lowered while keeping the impedance at the resonance frequency low.
  • the polarities (+, ⁇ ) of the power supplies connected to the external electrodes adjacent in the arrangement direction are different from each other when mounted on the multilayer substrate. Therefore, the directions of the currents flowing through the adjacent capacitor elements are reversed, and the mutual inductance is generated in a direction that cancels out. That is, since the electromagnetic coupling between the capacitor elements can be suppressed, the interval between adjacent capacitor elements can be further reduced. As a result, the power supply impedance at the anti-resonance frequency can be lowered while keeping the power supply impedance at the resonance frequency low, and the size can be further reduced.
  • the capacitor array according to the present invention preferably includes two capacitor elements, and the equivalent series resistance value of one capacitor element is preferably higher than the equivalent series resistance value of the other capacitor element.
  • the current flowing from the power source to the ground passes through the low ESR capacitor element at a frequency (including the resonance frequency) other than the vicinity of the anti-resonance frequency, and the high ESR capacitor element at a frequency near the anti-resonance frequency. Pass through. Therefore, the impedance at the anti-resonance frequency can be lowered while keeping the impedance at the resonance frequency low. Further, since the capacitor array is composed of one low ESR capacitor element and one high ESR capacitor element, the size can be further reduced.
  • the number of capacitor elements having a higher equivalent series resistance value included in the plurality of capacitor elements is equal to or greater than the number of capacitor elements having a lower equivalent series resistance value.
  • the external electrode of the capacitor element having the higher equivalent series resistance value has a base electrode connected to the internal electrode of the capacitor element, and a resistance film formed so as to cover the base electrode And a plating layer formed so as to cover the resistance film.
  • a resistance film is formed on the external electrode of the high ESR capacitor element between the base electrode and the plating layer so as to cover the base electrode. Therefore, the ESR value of the capacitor element can be increased to an appropriate value by adjusting the resistance value of the resistance film.
  • a capacitor array mounting method is any one of the above-described capacitor array mounting methods, wherein the polarities of power supplies connected to adjacent external electrodes along the arrangement direction of the plurality of capacitor elements are different from each other.
  • the capacitor array is mounted between the power source and ground of the multilayer board.
  • the high ESR capacitor element and the low ESR capacitor element are mounted in parallel between the power source and the ground. Therefore, as described above, the current flowing from the power source to the ground passes through the low ESR capacitor element at a frequency other than the vicinity of the anti-resonance frequency (including the resonance frequency) and passes through the high ESR capacitor element at a frequency near the anti-resonance frequency. Pass through. Therefore, the impedance at the anti-resonance frequency can be reduced while keeping the impedance at the resonance frequency low.
  • the power supplies connected to the adjacent external electrodes along the arrangement direction of the capacitor elements are mounted so that the polarities thereof are different from each other, the direction of the current flowing through the adjacent capacitor elements is reversed, and the electromagnetic waves between the capacitor elements are Binding can be suppressed.
  • the power supply impedance at the anti-resonance frequency can be lowered while the power supply impedance at the resonance frequency is kept low, and the size can be further reduced.
  • FIG. 3 is a cross-sectional view taken along line III-III in FIGS.
  • FIG. 4 is a cross-sectional view taken along line IV-IV in FIGS. It is a principal part enlarged view of the multilayer substrate by which the capacitor
  • FIG. 1 is a perspective view showing the external appearance of the capacitor array 1
  • FIG. 2 is a plan view of the capacitor array 1.
  • 3 is a longitudinal sectional view taken along line III-III in FIGS. 1 and 2
  • FIG. 4 is a longitudinal sectional view taken along line IV-IV in FIGS.
  • the capacitor array 1 includes a rectangular parallelepiped ceramic sintered body 10 (corresponding to the dielectric body described in the claims), two multilayer ceramic capacitor elements 20 disposed in the ceramic sintered body 10, 30 (corresponding to the capacitor element recited in the claims).
  • the ceramic sintered body 10 is made of, for example, a dielectric ceramic mainly composed of BaTiO 3 , CaTiO 3 , SrTiO 3 , CaZrO 3 or the like. Note that subcomponents such as a Mn compound, Fe compound, Cr compound, Co compound, and Ni compound may be added to these main components.
  • the two multilayer ceramic capacitor elements 20 and 30 are formed so as to have different values of equivalent series resistance (ESR).
  • ESR equivalent series resistance
  • the multilayer ceramic capacitor element 20 is set to have a higher ESR value than the multilayer ceramic capacitor element 30.
  • the ESR value of the multilayer ceramic capacitor element 20 (hereinafter referred to as “high ESR capacitor element 20”) is higher than 100 m ⁇ , and is set to, for example, about 200 to 700 m ⁇ depending on the desired power supply impedance characteristic.
  • the ESR value of the high ESR capacitor element 20 is set to 400 m ⁇ .
  • the ESR value of the multilayer ceramic capacitor element 30 (hereinafter referred to as “low ESR capacitor element 30”) is set to, for example, 100 m ⁇ or less.
  • the ESR value of the low ESR capacitor element 30 is set to 10 m ⁇ .
  • the high ESR capacitor element 20 has a plurality of internal electrodes 21 and 22 stacked in the thickness direction through ceramic layers.
  • the internal electrodes 21 and the internal electrodes 22 are formed in a substantially rectangular thin film shape, and are alternately stacked so as to face each other with a ceramic layer interposed therebetween.
  • the internal electrodes 21 and 22 are made of, for example, Ni, Cu, Ag, Pd, an Ag—Pd alloy, Au, or the like.
  • a pair of external electrodes 23, 24 are disposed on the side surfaces 11, 12 of the ceramic sintered body 10, and the internal electrode 21 is drawn out to one side surface 11 of the ceramic sintered body 10, It is connected to the electrode 23.
  • the internal electrode 22 is drawn out to the other side surface 12 of the ceramic sintered body 10 and connected to the external electrode 24.
  • the pair of external electrodes 23 and external electrodes 24 are formed on the side surfaces 11 and 12 of the ceramic sintered body 10 so as to face each other with the ceramic sintered body 10 interposed therebetween. Since the external electrode 23 and the external electrode 24 have the same configuration, the external electrode 23 will be mainly described here.
  • the external electrode 23 (24) includes a base electrode 23a (24a) connected to the internal electrode 21 (22), a resistance film 23b (24b) formed so as to cover the base electrode 23a (24a), and the resistance A nickel plating layer 23c (24c) and a tin plating layer 23d (24d) are formed so as to cover the film 23b (24b).
  • the base electrode 23a (24a), the resistance film 23b (24b), the nickel plating layer 23c (24c), and the tin plating layer 23d (24d) constituting the external electrode 23 (24) are respectively formed from the side surface 11 (12). It is formed so as to wrap around the side surface 13 orthogonal to the side surface 11 (12) and the upper and lower main surfaces.
  • the base electrode 23a (24a) connected to the internal electrode 21 (22) is formed by baking a conductive paste containing, for example, Cu, Ni, Ag, Pd, Ag—Pd alloy, Au, or the like.
  • the resistance film 23b (24b) is formed by baking a resistance paste containing a resistance component.
  • a resistance component enters in series with respect to the capacity of the high ESR capacitor element 20, and the ESR of the high ESR capacitor element 20 increases.
  • the resistance component for example, composite oxides such as In—Sn composite oxide (ITO), La—Cu composite oxide, Sr—Fe composite oxide, and Ca—Sr—Ru composite oxide are used.
  • glass such as B—Si glass or B—Si—Zn glass is added to the resistance film 23b (24b).
  • a nickel plating layer 23c (24c) having resistance to solder erosion and the nickel plating layer 23c (24c) are provided so as to cover the resistance film 23b (24b).
  • a tin plating layer 23d (24d) is formed for covering and improving the wettability with respect to the solder.
  • the external electrode 23 becomes a ground terminal connected to the negative ( ⁇ ) pole (ground) of the power supply when mounted on the multilayer substrate.
  • the external electrode 24 serves as a power supply terminal connected to the positive (+) pole of the power supply.
  • the low ESR capacitor element 30 has a plurality of internal electrodes 31 and 32 laminated in the thickness direction via ceramic layers.
  • the internal electrodes 31 and the internal electrodes 32 are formed in a substantially rectangular thin film shape, and are alternately stacked so as to face each other through the ceramic layer.
  • the internal electrodes 31 and 32 are made of, for example, Ni, Cu, Ag, Pd, an Ag—Pd alloy, Au, or the like.
  • a pair of external electrodes 33, 34 are disposed on the side surfaces 11, 12 of the ceramic sintered body 10, and the internal electrode 32 is drawn out to one side surface 11 of the ceramic sintered body 10, It is connected to the electrode 34.
  • the internal electrode 31 is drawn out to the other side surface 12 of the ceramic sintered body 10 and connected to the external electrode 33.
  • the pair of external electrodes 33 and external electrodes 34 are formed on the side surfaces 11 and 12 of the ceramic sintered body 10 so as to face each other with the ceramic sintered body 10 interposed therebetween. Since the external electrode 33 and the external electrode 34 have the same configuration, the external electrode 33 will be mainly described here.
  • the external electrode 33 (34) includes a base electrode 33a (34a) connected to the internal electrode 31 (32), a nickel plating layer 33c (34c) and a tin plating layer formed so as to cover the base electrode 33a (34a). 33d (34d). That is, the external electrode 33 (34) is different from the external electrode 23 (24) described above in that it does not have the resistance film 23b (24b). Therefore, the ESR value of the low ESR capacitor element 30 is smaller than the ESR value of the high ESR capacitor element 20.
  • the base electrode 33a (34a), the nickel plating layer 33c (34c), and the tin plating layer 33d (34d) constituting the external electrode 33 (34) are respectively connected to the side surface 12 (11) and the side surface 12 (11). It is formed so as to wrap around the orthogonal side surface 14 and the upper and lower main surfaces.
  • the base electrode 33a (34a) connected to the internal electrode 31 (32) is a conductive material containing, for example, Cu, Ni, Ag, Pd, an Ag—Pd alloy, Au, etc., like the base electrode 23a (24a) described above. It is formed by baking an adhesive paste.
  • a nickel plating layer 33c (34c) having solder erosion resistance and the nickel plating layer 33c (34c) are provided so as to cover the base electrode 33a (34a).
  • a tin plating layer 33d (34d) is formed to cover and improve the wettability with respect to the solder.
  • the external electrode 33 serves as a ground terminal connected to the negative ( ⁇ ) pole (ground) of the power supply when mounted on the multilayer substrate.
  • the external electrode 34 serves as a power supply terminal connected to the positive (+) pole of the power supply.
  • the external electrode 23 is a ground terminal connected to the negative ( ⁇ ) pole of the power supply
  • the external electrode 24 is a power supply terminal connected to the positive (+) pole of the power supply. Therefore, the external electrodes 23 and the external electrodes 34 adjacent to each other along the arrangement direction of the two capacitor elements, that is, the high ESR capacitor element 20 and the low ESR capacitor element 30 are connected when mounted on the multilayer substrate.
  • the power supplies are mounted so that their polarities are different from each other.
  • the external electrode 24 and the external electrode 33 are mounted so that the polarities of the connected power sources are different when mounted on the multilayer substrate.
  • FIG. 5 is an enlarged view of a main part of the multilayer substrate 100 on which the capacitor array 1 is mounted.
  • electronic components such as a power supply, IC, and LSI are mounted on the multilayer substrate 100.
  • the multilayer substrate 100 includes, as an inner layer, a power plane and a ground plane that is disposed to face the power plane with a dielectric layer interposed therebetween.
  • the multilayer substrate 100 is formed of, for example, copper foil, and printed wirings (power wirings) 110, 111, 112, 113 for connecting the capacitor array 1 between a power source (power source pins such as an IC) and the ground are formed. ing.
  • the external electrode 23 of the capacitor array 1 is connected to one end of the printed wiring 110 by soldering.
  • the other end of the printed wiring 110 is connected to the via 120.
  • the via 120 connects the other end of the printed wiring 110 and the ground plane of the multilayer substrate 100.
  • the external electrode 23 of the capacitor array 1 is connected to the ground.
  • the external electrode 24 of the capacitor array 1 is connected to one end of the printed wiring 111 by soldering.
  • the other end of the printed wiring 111 is connected to the via 121.
  • the via 121 connects the other end of the printed wiring 111 and the power plane of the multilayer substrate 100.
  • the external electrode 24 of the capacitor array 1 is connected to a power supply (IC power supply pin).
  • the external electrode 33 of the capacitor array 1 is connected to one end of the printed wiring 112 by soldering.
  • the other end of the printed wiring 112 is connected to the via 122.
  • the via 122 connects the other end of the printed wiring 112 and the ground plane of the multilayer substrate 100. Thereby, the external electrode 33 of the capacitor array 1 is connected to the ground.
  • an external electrode 34 of the capacitor array 1 is connected to one end of the printed wiring 113 by soldering.
  • the other end of the printed wiring 113 is connected to the via 123.
  • the via 123 connects the other end of the printed wiring 113 and the power plane of the multilayer substrate 100. Thereby, the external electrode 34 of the capacitor array 1 is connected to the power supply (IC power supply pin).
  • the high ESR capacitor element 20 and the low ESR capacitor element 30 are inserted between the power source and the ground in parallel and in the opposite polarity. Therefore, the current flowing from the power source to the ground passes through the low ESR capacitor element 30 having a low ESR at a frequency other than the vicinity of the anti-resonance frequency (including the resonance frequency), and the high ESR capacitor having a low impedance at a frequency near the anti-resonance frequency. It passes through the element 20. Therefore, the impedance at the anti-resonance frequency is reduced while the impedance at the resonance frequency is kept low.
  • the external electrode 23 and the external electrode 34 that are adjacent to each other along the arrangement direction of the high ESR capacitor element 20 and the low ESR capacitor element 30 are connected to each other.
  • the external electrode 24 and the external electrode 33 have different polarities of the connected power sources. Therefore, the direction of the current flowing through the high ESR capacitor element 20 and the direction of the current flowing through the low ESR capacitor element 30 are reversed, as indicated by the one-dot chain line arrow in FIG. As a result, mutual inductance occurs in a direction that cancels out, and electromagnetic coupling between the capacitor elements is suppressed.
  • the power source impedance of the multilayer substrate 100 in which the capacitor array 1 was mounted between the power source and the ground was measured. Further, as a comparative example, the power supply impedance when only a low ESR capacitor was mounted and the power supply impedance when only a high ESR capacitor was mounted were measured.
  • the multilayer substrate 100 one having a power plane-ground plane capacitance of 800 pF and a power plane inductance of 20 pH was used.
  • the capacitor array 1 includes a high ESR capacitor element 20 having an ESL of 200 pH, a capacity of 0.1 ⁇ F, and an ESR of 400 m ⁇ , and a low ESR capacitor element 30 having an ESL of 200 pH, a capacity of 0.1 ⁇ F, and an ESR of 10 m ⁇ . What I have was used.
  • a low ESR capacitor as a comparative example, an ESL having a pH of 200 pH, a capacity of 0.1 ⁇ F, and an ESR of 10 m ⁇ was used.
  • a high ESR capacitor having an ESL of 200 pH, a capacity of 0.1 ⁇ F, and an ESR of 400 m ⁇ was used as a comparative example.
  • FIG. 6 shows frequency characteristics (measurement results) of power supply impedances of the multilayer substrate 100 on which the capacitor array 1 is mounted, the multilayer substrate on which only the low ESR capacitor is mounted, and the multilayer substrate on which only the high ESR capacitor is mounted. .
  • the horizontal axis of the graph shown in FIG. 6 is frequency (Hz), and the vertical axis is impedance ( ⁇ ).
  • the measurement result when the capacitor array 1 according to the embodiment is used is a solid line
  • the measurement result when only the low ESR capacitor is used is a broken line
  • the measurement result when only the high ESR capacitor is used is shown.
  • the measurement results are shown by alternate long and short dash lines.
  • the impedance at the resonance frequency (about 12 MHz) is suppressed to a low level (about 13 m ⁇ ), but the peak is at the anti-resonance frequency (about 500 MHz). As a result, the impedance rapidly increases (about 100 ⁇ ).
  • the impedance at the anti-resonance frequency (about 500 MHz) is relatively low (about 3 ⁇ ).
  • the impedance increases (about 250 to 400 m ⁇ ) on the lower frequency side than the antiresonance frequency, particularly in the frequency region lower than 60 MHz.
  • the impedance at the resonance frequency (about 16 MHz) is relatively low (about 22 m ⁇ ).
  • the impedance at the anti-resonance frequency (about 500 MHz) is also relatively low (about 5.5 ⁇ ).
  • the power supply impedance at the anti-resonance frequency can be reduced while keeping the power supply impedance at the resonance frequency low.
  • the capacitor array 1 includes a high ESR capacitor element 20 having a high ESR value and a low ESR capacitor element 30 having a low ESR value. Therefore, when the capacitor array 1 is mounted, the current flowing from the power source to the ground passes through the low ESR capacitor element 30 having a low ESR at a frequency other than the vicinity of the anti-resonance frequency (including the resonance frequency), and near the anti-resonance frequency. It passes through the high ESR capacitor element 20 having a low impedance at a frequency of. Therefore, the impedance at the anti-resonance frequency can be lowered while keeping the impedance at the resonance frequency low.
  • the external electrode 23 and the external electrode 34 that are adjacent to each other along the arrangement direction of the high ESR capacitor element 20 and the low ESR capacitor element 30 are connected.
  • the external electrode 24 and the external electrode 33 have different polarities of the connected power sources. Therefore, the direction of the current flowing through the high ESR capacitor element 20 and the direction of the current flowing through the low ESR capacitor element 30 are reversed. As a result, mutual inductance occurs in a direction that cancels out, and electromagnetic coupling between the capacitor elements is suppressed. Therefore, the distance between adjacent high ESR capacitor elements 20 and low ESR capacitor elements 30 can be further reduced. As a result, the power impedance at the anti-resonance frequency can be lowered while keeping the power impedance at the resonance frequency low, and the size can be further reduced.
  • the capacitor array 1 is configured by one low ESR capacitor element 30 and one high ESR capacitor element 20, it is possible to further reduce the size.
  • the external electrodes 23 and 24 of the high ESR capacitor element 20 include the resistance film 23b between the base electrodes 23a and 24a and the nickel plating layers 23c and 24c so as to cover the base electrodes 23a and 24a. , 24b are formed. Therefore, the ESR value of the high ESR capacitor element 20 can be increased to an appropriate value relatively easily by adjusting the resistance values of the resistance films 23b and 24b.
  • the capacitor array 1 since the capacitor array 1 is mounted between the power supply and the ground, the power supply impedance at the anti-resonance frequency can be lowered while keeping the power supply impedance at the resonance frequency low. It becomes.
  • the present invention is not limited to the above-described embodiments, and various modifications can be made.
  • the four-terminal capacitor array 1 including the two capacitor elements 20 and 30 has been described as an example.
  • the number of capacitor elements included in the capacitor array is not limited to two.
  • the capacitor array may include three capacitor elements (6 terminals), four capacitor elements (8 terminals), or a larger number of capacitor elements.
  • the electrodes adjacent to each other in the arrangement direction of the capacitor elements are arranged so that the polarities of the power supplies connected when mounted on the multilayer substrate are different from each other.
  • the capacitor array includes one or more high ESR capacitor elements.
  • the number of high ESR capacitor elements is preferably equal to or greater than the number of low ESR capacitor elements. By doing so, the number of high ESR capacitor elements connected in parallel increases. Therefore, ESLs of more high ESR capacitor elements are connected in parallel, and the ESL of the entire high ESR capacitor elements is further reduced. As a result, the power source impedance at the antiresonance frequency can be effectively reduced.
  • the resistance films 23b and 24b are provided on both the external electrode 23 and the external electrode 24.
  • the resistance film may be provided only on one of the external electrodes.
  • the external terminal 23 and the external terminal 34 that are connected to the ground when mounted may be connected internally. At that time, the resistance film is provided only on the external terminal 24 side.
  • the internal electrodes 21 and 22 of the high ESR capacitor element 20 are formed in a substantially rectangular shape.
  • the external electrodes 23 and 24 (underlying electrodes 23a and 24a)
  • An internal electrode having a constricted connection portion may be used.
  • Capacitor Array 10 Ceramic Sintered Body 20 High ESR Capacitor Element 30 Low ESR Capacitor Element 21, 22, 31, 32 Internal Electrode 23, 33 External Electrode (Ground Terminal) 24, 34 External electrode (power supply terminal) 23a, 24a, 33a, 34a Base electrode 23b, 24b Resistance film 23c, 24c, 33c, 34c Nickel plating layer 23d, 24d, 33d, 34d Tin plating layer 100 Multilayer substrate 110, 111, 112, 113 Power supply wiring 120, 121, 122 , 123 Via

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  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Ceramic Capacitors (AREA)

Abstract

Provided is a capacitor array that can reduce the source impedance at the anti-resonant frequency while keeping the source impedance at the resonant frequency low, and that can be further reduced in size. The capacitor array (1) includes: a ceramic sintered element (10); a low-ESR capacitor element (30) and a high-ESR capacitor element (20) that are arranged in the ceramic sintered element (10), the high-ESR capacitor element having a higher ESR than the low-ESR capacitor element (30); and external electrodes (23, 24) and external electrodes (33, 34) provided in pairs for the respective capacitor elements (20, 30) and provided on the side surfaces (11, 12) of the ceramic sintered element (10). At the time of installation onto a multilayer substrate, the external electrode (23) and the external electrode (34), as well as the external electrode (24) and the external electrode (33), that are adjacent to one another in the arrangement direction of the capacitor elements (20, 30) are connected to the opposite polarities of a power source.

Description

コンデンサアレイ、及び、コンデンサアレイの実装方法Capacitor array and capacitor array mounting method
　本発明は、１つの誘電体素体内に複数のコンデンサ素子が配設されたコンデンサアレイ、及び、該コンデンサアレイの実装方法に関する。 The present invention relates to a capacitor array in which a plurality of capacitor elements are arranged in one dielectric body, and a mounting method of the capacitor array.
　ディジタル回路では、ＩＣやＬＳＩの動作中の負荷変動を吸収したり、ノイズを除去するため、電源－グランド間にデカップリングコンデンサが挿入されている。電圧変動を抑制する観点から、電源インピーダンスは可能な限り低い方がよく、よってデカップリングコンデンサのインピーダンスも低いことが望ましい。 In digital circuits, a decoupling capacitor is inserted between the power supply and ground in order to absorb load fluctuations during IC and LSI operation and to eliminate noise. From the viewpoint of suppressing voltage fluctuations, the power source impedance is preferably as low as possible, and therefore the impedance of the decoupling capacitor is preferably low.
　ところで、現実のコンデンサには、容量成分（ＥＳＣ（Ｅｑｕｉｖａｌｅｎｔ　Ｓｅｒｉｅｓ　Ｃａｐａｃｉｔａｎｃｅ））の他、等価直列インダクタンス（ＥＳＬ（Ｅｑｕｉｖａｌｅｎｔ　Ｓｅｒｉｅｓ　Ｉｎｄｕｃｔａｎｃｅ）や等価直列抵抗（ＥＳＲ（Ｅｑｕｉｖａｌｅｎｔ　Ｓｅｒｉｅｓ　Ｒｅｓｉｓｔａｎｃｅ））が存在する。そのため、デカップリングコンデンサが実装された多層プリント基板（以下、単に「多層基板」という）では、デカップリングコンデンサの容量（ＥＳＣ）と、多層基板の配線等のインダクタンス（Ｌ成分）及びデカップリングコンデンサのＥＳＬとによる共振（直列共振）、及び、多層基板の電源プレーン－グランドプレーン間の容量と、多層基板の配線等のインダクタンス（Ｌ成分）及びデカップリングコンデンサのＥＳＬによる反共振（並列共振）が起きる。 By the way, in an actual capacitor, there exist an equivalent series inductance (ESL (Equivalent Series Inductance)) and an equivalent series resistance (ESR (Equivalent Series Resistance)) in addition to a capacitance component (ESC (Equivalent Series Capacitance)). In a multilayer printed circuit board on which a ring capacitor is mounted (hereinafter simply referred to as “multilayer board”), the capacitance (ESC) of the decoupling capacitor, the inductance (L component) of the wiring of the multilayer board, and the ESL of the decoupling capacitor Resonance (series resonance), capacitance between the power supply plane and ground plane of the multilayer board, inductance (L component) and decoupling of wiring etc. of the multilayer board Antiresonance by ESL of ring capacitors (parallel resonance) occurs.
　よって、電源インピーダンスは、共振周波数を境にして、低周波側では、周波数が高くなるに従って低くなるが、高周波側では、周波数が高くなるほど高くなる傾向を示す。すなわち、電源インピーダンスは、共振周波数付近で谷型の特性を示す。一方、電源インピーダンスは、反共振周波数を境にして、低周波側では周波数が高くなるに従って高くなるが、高周波側では周波数が高くなるほど低くなる。すなわち、反共振周波数付近で山型の特性を示す。ここで、共振周波数では、インピーダンスが極小となり低く保たれるため、電圧変動は小さくなるが、反共振周波数では、インピーダンス極大となりが高くなるため、電圧変動が大きくなる。このような反共振を抑制する方法としては、デカップリングコンデンサの等価直列抵抗を大きくする（Ｑ値を低くする）ことが考えられる。 Therefore, the power source impedance decreases as the frequency increases on the low frequency side with respect to the resonance frequency, but tends to increase as the frequency increases on the high frequency side. That is, the power source impedance exhibits a valley-type characteristic near the resonance frequency. On the other hand, the power source impedance increases as the frequency increases on the low frequency side with the anti-resonance frequency as a boundary, but decreases as the frequency increases on the high frequency side. That is, it exhibits a mountain-shaped characteristic near the antiresonance frequency. Here, at the resonance frequency, the impedance is minimized and kept low, so that the voltage fluctuation is small. However, at the anti-resonance frequency, the impedance becomes maximum, and the voltage fluctuation is large. As a method of suppressing such anti-resonance, it is conceivable to increase the equivalent series resistance of the decoupling capacitor (lower the Q value).
　ここで、小容量積層セラミックコンデンサ素子と、等価直列抵抗が大きな大容量積層セラミックコンデンサ素子とを組み合わせた複合積層セラミックコンデンサが特許文献１に開示されている。この複合積層セラミックコンデンサは、大容量積層セラミックコンデンサ素子の外部電極の等価直列抵抗の抵抗値を、小容量積層セラミックコンデンサ素子における外部電極の等価直列抵抗の抵抗値よりも大きくするとともに、大容量積層セラミックコンデンサ素子と小容量積層セラミックコンデンサ素子とを所定の間隔以上の隙間部を設けて結合したものである。 Here, Patent Document 1 discloses a composite multilayer ceramic capacitor in which a small capacity multilayer ceramic capacitor element and a large capacity multilayer ceramic capacitor element having a large equivalent series resistance are combined. This composite multilayer ceramic capacitor has a resistance value of an equivalent series resistance of an external electrode of a large-capacity multilayer ceramic capacitor element larger than a resistance value of an equivalent series resistance of an external electrode in a small-capacity multilayer ceramic capacitor element. A ceramic capacitor element and a small-capacity multilayer ceramic capacitor element are combined with a gap of a predetermined distance or more.
特開２００１－１８５４４６号公報JP 2001-185446 A
　上述した複合積層セラミックコンデンサによれば、大容量積層セラミックコンデンサ素子における等価直列抵抗が大きいため、周波数に対して穏やかなインピーダンス特性を示し、高周波特性を向上させることができる。しかしながら、大容量積層セラミックコンデンサ素子の電極と小容量積層セラミックコンデンサ素子の電極とが結合されているため、両素子を流れる電流の流れる向きが同じになる。そのため、隙間部の間隔を小さくすると、電磁気的な結合が生じ、一方の素子に流れている電流が他方の素子に流れるおそれがある。そのため、上述した複合積層セラミックコンデンサでは、小型化を図ることが困難である。 According to the composite multilayer ceramic capacitor described above, since the equivalent series resistance in the large-capacity multilayer ceramic capacitor element is large, it is possible to show a gentle impedance characteristic with respect to the frequency and to improve the high frequency characteristic. However, since the electrodes of the large-capacity multilayer ceramic capacitor element and the electrodes of the small-capacity multilayer ceramic capacitor element are coupled, the directions of current flowing through both elements are the same. Therefore, when the gap is reduced, electromagnetic coupling occurs, and current flowing in one element may flow in the other element. Therefore, it is difficult to reduce the size of the composite multilayer ceramic capacitor described above.
　本発明は、上記問題点を解消する為になされたものであり、共振周波数での電源インピーダンスを低く保ったまま反共振周波数での電源インピーダンスを下げることができ、かつ、サイズをより小型化することが可能なコンデンサアレイを提供することを目的とする。 The present invention has been made to solve the above problems, and can reduce the power supply impedance at the anti-resonance frequency while keeping the power supply impedance at the resonance frequency low, and further reduce the size. An object of the present invention is to provide a capacitor array that can be used.
　本発明に係るコンデンサアレイは、多層基板の電源－グランド間に実装されるコンデンサアレイであって、誘電体素体と、誘電体素体内に配設された複数のコンデンサ素子と、コンデンサ素子ごとに対となって誘電体素体の側面に設けられた外部電極とを備え、複数のコンデンサ素子が、等価直列抵抗の値が異なる少なくとも２種類のコンデンサ素子を含み、複数のコンデンサ素子の配列方向に沿って隣り合う外部電極が、多層基板に実装される際に、接続される電源の極性が互いに異なることを特徴とする。 A capacitor array according to the present invention is a capacitor array mounted between a power source and a ground of a multilayer board, and includes a dielectric element body, a plurality of capacitor elements disposed in the dielectric element body, and A plurality of capacitor elements including at least two types of capacitor elements having different equivalent series resistance values, and arranged in the arrangement direction of the plurality of capacitor elements. When the external electrodes that are adjacent to each other are mounted on the multilayer substrate, the polarities of the connected power sources are different from each other.
　本発明に係るコンデンサアレイによれば、コンデンサアレイを構成する複数のコンデンサ素子が、等価直列抵抗（ＥＳＲ）の値が異なる少なくとも２種類のコンデンサ素子を含んでいる。すなわち、他のコンデンサ素子よりもＥＳＲの値が高いコンデンサ素子を含んでいる。そのため、該コンデンサアレイが実装された際に、電源からグランドに流れる電流は、反共振周波数の付近以外の周波数（共振周波数を含む）ではＥＳＲの値が小さい方のコンデンサ素子（以下「低ＥＳＲコンデンサ素子」ともいう）を通り、反共振周波数の付近の周波数ではＥＳＲの値が高い方のコンデンサ素子（以下「高ＥＳＲコンデンサ素子」ともいう）を通る。そのため、共振周波数でのインピーダンスを低く保ったまま、反共振周波数でのインピーダンスを下げることができる。また、本発明に係るコンデンサアレイによれば、多層基板に実装される際に、配列方向に沿って隣り合う外部電極に接続される電源の極性（＋、－）が互いに異なる。よって、隣り合うコンデンサ素子を流れる電流の向きが逆になり、相互インダクタンスが打ち消し合う方向に発生する。すなわち、コンデンサ素子間の電磁気的な結合を抑制することができるため、隣り合うコンデンサ素子とコンデンサ素子との間隔をより小さくすることができる。これらの結果、共振周波数での電源インピーダンスを低く保ったまま反共振周波数での電源インピーダンスを下げることができ、かつ、よりサイズを小型化することが可能となる。 According to the capacitor array according to the present invention, the plurality of capacitor elements constituting the capacitor array include at least two types of capacitor elements having different equivalent series resistance (ESR) values. That is, a capacitor element having a higher ESR value than other capacitor elements is included. Therefore, when the capacitor array is mounted, the current flowing from the power source to the ground is a capacitor element having a smaller ESR value (hereinafter referred to as “low ESR capacitor”) at a frequency other than the vicinity of the anti-resonance frequency (including the resonance frequency). Element "), and passes through a capacitor element having a higher ESR value (hereinafter also referred to as" high ESR capacitor element ") at a frequency near the anti-resonance frequency. Therefore, the impedance at the anti-resonance frequency can be lowered while keeping the impedance at the resonance frequency low. In addition, according to the capacitor array of the present invention, the polarities (+, −) of the power supplies connected to the external electrodes adjacent in the arrangement direction are different from each other when mounted on the multilayer substrate. Therefore, the directions of the currents flowing through the adjacent capacitor elements are reversed, and the mutual inductance is generated in a direction that cancels out. That is, since the electromagnetic coupling between the capacitor elements can be suppressed, the interval between adjacent capacitor elements can be further reduced. As a result, the power supply impedance at the anti-resonance frequency can be lowered while keeping the power supply impedance at the resonance frequency low, and the size can be further reduced.
　本発明に係るコンデンサアレイは、２つのコンデンサ素子を含み、一方のコンデンサ素子の等価直列抵抗の値が、他方のコンデンサ素子の等価直列抵抗の値よりも高いことが好ましい。 The capacitor array according to the present invention preferably includes two capacitor elements, and the equivalent series resistance value of one capacitor element is preferably higher than the equivalent series resistance value of the other capacitor element.
　この場合、上述したように、電源からグランドに流れる電流は、反共振周波数の付近以外の周波数（共振周波数を含む）では低ＥＳＲコンデンサ素子を通り、反共振周波数の付近の周波数では高ＥＳＲコンデンサ素子を通る。そのため、共振周波数でのインピーダンスを低く保ったまま、反共振周波数でのインピーダンスを下げることができる。また、１つの低ＥＳＲコンデンサ素子と、１つの高ＥＳＲコンデンサ素子とでコンデンサアレイが構成されるため、より小型化を図ることができる。 In this case, as described above, the current flowing from the power source to the ground passes through the low ESR capacitor element at a frequency (including the resonance frequency) other than the vicinity of the anti-resonance frequency, and the high ESR capacitor element at a frequency near the anti-resonance frequency. Pass through. Therefore, the impedance at the anti-resonance frequency can be lowered while keeping the impedance at the resonance frequency low. Further, since the capacitor array is composed of one low ESR capacitor element and one high ESR capacitor element, the size can be further reduced.
　本発明に係るコンデンサアレイでは、複数のコンデンサ素子に含まれる等価直列抵抗の値が高い方のコンデンサ素子の数が、等価直列抵抗の値が低い方のコンデンサ素子の数以上であることが好ましい。 In the capacitor array according to the present invention, it is preferable that the number of capacitor elements having a higher equivalent series resistance value included in the plurality of capacitor elements is equal to or greater than the number of capacitor elements having a lower equivalent series resistance value.
　このようにすれば、並列に接続される高ＥＳＲコンデンサ素子の数が多くなる。そのため、より多くの高ＥＳＲコンデンサ素子のＥＳＬが並列に接続されることとなり、高ＥＳＲコンデンサ素子全体のＥＳＬがより低減される。その結果、反共振周波数での電源インピーダンスを効果的に低減することができる。 In this way, the number of high ESR capacitor elements connected in parallel increases. Therefore, ESLs of more high ESR capacitor elements are connected in parallel, and the ESL of the entire high ESR capacitor elements is further reduced. As a result, the power source impedance at the antiresonance frequency can be effectively reduced.
　本発明に係るコンデンサアレイでは、等価直列抵抗の値が高い方のコンデンサ素子の外部電極が、該コンデンサ素子の内部電極に接続される下地電極と、該下地電極を覆うように形成される抵抗皮膜と、該抵抗皮膜を覆うように形成されるメッキ層とを有することが好ましい。 In the capacitor array according to the present invention, the external electrode of the capacitor element having the higher equivalent series resistance value has a base electrode connected to the internal electrode of the capacitor element, and a resistance film formed so as to cover the base electrode And a plating layer formed so as to cover the resistance film.
　この場合、高ＥＳＲコンデンサ素子の外部電極には、下地電極とメッキ層との間に、当該下地電極を覆うように抵抗皮膜が形成される。そのため、該抵抗皮膜の抵抗値を調節することにより、コンデンサ素子のＥＳＲ値を適切な値まで高めることができる。 In this case, a resistance film is formed on the external electrode of the high ESR capacitor element between the base electrode and the plating layer so as to cover the base electrode. Therefore, the ESR value of the capacitor element can be increased to an appropriate value by adjusting the resistance value of the resistance film.
　本発明に係るコンデンサアレイの実装方法は、上記いずれかのコンデンサアレイの実装方法であって、複数のコンデンサ素子の配列方向に沿って隣り合う外部電極に接続される電源の極性が互いに異なるように、コンデンサアレイを多層基板の電源－グランド間に実装することを特徴とする。 A capacitor array mounting method according to the present invention is any one of the above-described capacitor array mounting methods, wherein the polarities of power supplies connected to adjacent external electrodes along the arrangement direction of the plurality of capacitor elements are different from each other. The capacitor array is mounted between the power source and ground of the multilayer board.
　本発明に係るコンデンサアレイの実装方法によれば、高ＥＳＲコンデンサ素子と低ＥＳＲコンデンサ素子とが、並列に、電源－グランド間に実装される。そのため、電源からグランドに流れる電流は、上述したように、反共振周波数の付近以外の周波数（共振周波数を含む）では低ＥＳＲコンデンサ素子を通り、反共振周波数の付近の周波数では高ＥＳＲコンデンサ素子を通る。よって、共振周波数でのインピーダンスを低く保ったまま、反共振周波数でのインピーダンスを低減することができる。また、コンデンサ素子の配列方向に沿って隣り合う外部電極に接続される電源の極性が互いに異なるように実装されるため、隣り合うコンデンサ素子を流れる電流の向きが逆になり、コンデンサ素子間の電磁気的な結合を抑制することができる。 According to the capacitor array mounting method of the present invention, the high ESR capacitor element and the low ESR capacitor element are mounted in parallel between the power source and the ground. Therefore, as described above, the current flowing from the power source to the ground passes through the low ESR capacitor element at a frequency other than the vicinity of the anti-resonance frequency (including the resonance frequency) and passes through the high ESR capacitor element at a frequency near the anti-resonance frequency. Pass through. Therefore, the impedance at the anti-resonance frequency can be reduced while keeping the impedance at the resonance frequency low. In addition, since the power supplies connected to the adjacent external electrodes along the arrangement direction of the capacitor elements are mounted so that the polarities thereof are different from each other, the direction of the current flowing through the adjacent capacitor elements is reversed, and the electromagnetic waves between the capacitor elements are Binding can be suppressed.
　本発明によれば、共振周波数での電源インピーダンスを低く保ったまま反共振周波数での電源インピーダンスを下げることができ、かつ、サイズをより小型化することが可能となる。 According to the present invention, the power supply impedance at the anti-resonance frequency can be lowered while the power supply impedance at the resonance frequency is kept low, and the size can be further reduced.
実施形態に係るコンデンサアレイの斜視図である。It is a perspective view of the capacitor array concerning an embodiment. 実施形態に係るコンデンサアレイの平面図である。It is a top view of the capacitor array concerning an embodiment. 図１，２のＩＩＩ－ＩＩＩ線に沿った断面図である。FIG. 3 is a cross-sectional view taken along line III-III in FIGS. 図１，２のＩＶ－ＩＶ線に沿った断面図である。FIG. 4 is a cross-sectional view taken along line IV-IV in FIGS. 実施形態に係るコンデンサアレイが実装された多層基板の要部拡大図である。It is a principal part enlarged view of the multilayer substrate by which the capacitor | condenser array which concerns on embodiment was mounted. 実施形態に係るコンデンサアレイが実装された多層基板の電源インピーダンスの周波数特性を示す図である。It is a figure which shows the frequency characteristic of the power supply impedance of the multilayer board | substrate with which the capacitor | condenser array which concerns on embodiment was mounted.
　以下、図面を参照して本発明の好適な実施形態について詳細に説明する。なお、各図において、同一要素には同一符号を付して重複する説明を省略する。 Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. In addition, in each figure, the same code | symbol is attached | subjected to the same element and the overlapping description is abbreviate | omitted.
　まず、図１～４を併せて用いて、実施形態に係るコンデンサアレイ１の構成について説明する。図１は、コンデンサアレイ１の外観を示す斜視図であり、図２は、コンデンサアレイ１の平面図である。また、図３は、図１，２のＩＩＩ－ＩＩＩ線に沿った縦断面図であり、図４は、図１，２のＩＶ－ＩＶ線に沿った縦断面図である。 First, the configuration of the capacitor array 1 according to the embodiment will be described with reference to FIGS. FIG. 1 is a perspective view showing the external appearance of the capacitor array 1, and FIG. 2 is a plan view of the capacitor array 1. 3 is a longitudinal sectional view taken along line III-III in FIGS. 1 and 2, and FIG. 4 is a longitudinal sectional view taken along line IV-IV in FIGS.
　コンデンサアレイ１は、直方体形状のセラミック焼結体１０（請求の範囲に記載の誘電体素体に相当）と、該セラミック焼結体１０内に配設された２個の積層セラミックコンデンサ素子２０，３０（請求の範囲に記載のコンデンサ素子に相当）を備えている。セラミック焼結体１０は、例えば、ＢａＴｉＯ３、ＣａＴｉＯ３、ＳｒＴｉＯ３、ＣａＺｒＯ３などを主成分とする誘電体セラミックから形成されている。なお、これらの主成分にＭｎ化合物、Ｆｅ化合物、Ｃｒ化合物、Ｃｏ化合物、Ｎｉ化合物などの副成分が添加されていてもよい。 The capacitor array 1 includes a rectangular parallelepiped ceramic sintered body 10 (corresponding to the dielectric body described in the claims), two multilayer ceramic capacitor elements 20 disposed in the ceramic sintered body 10, 30 (corresponding to the capacitor element recited in the claims). The ceramic sintered body 10 is made of, for example, a dielectric ceramic mainly composed of BaTiO 3 , CaTiO 3 , SrTiO 3 , CaZrO 3 or the like. Note that subcomponents such as a Mn compound, Fe compound, Cr compound, Co compound, and Ni compound may be added to these main components.
　２個の積層セラミックコンデンサ素子２０，３０は、互いに等価直列抵抗（ＥＳＲ）の値が異なるように形成されている。具体的には、積層セラミックコンデンサ素子２０は、積層セラミックコンデンサ素子３０よりもＥＳＲ値が高く設定されている。ここで、積層セラミックコンデンサ素子２０（以下「高ＥＳＲコンデンサ素子２０」という）のＥＳＲ値は、１００ｍΩよりも高く、例えば、所望する電源インピーダンス特性に応じて２００～７００ｍΩ程度に設定される。なお、本実施形態では、高ＥＳＲコンデンサ素子２０のＥＳＲ値を４００ｍΩに設定した。一方、積層セラミックコンデンサ素子３０（以下「低ＥＳＲコンデンサ素子３０」という）のＥＳＲ値は、例えば、１００ｍΩ以下に設定される。なお、本実施形態では、低ＥＳＲコンデンサ素子３０のＥＳＲ値を１０ｍΩに設定した。 The two multilayer ceramic capacitor elements 20 and 30 are formed so as to have different values of equivalent series resistance (ESR). Specifically, the multilayer ceramic capacitor element 20 is set to have a higher ESR value than the multilayer ceramic capacitor element 30. Here, the ESR value of the multilayer ceramic capacitor element 20 (hereinafter referred to as “high ESR capacitor element 20”) is higher than 100 mΩ, and is set to, for example, about 200 to 700 mΩ depending on the desired power supply impedance characteristic. In the present embodiment, the ESR value of the high ESR capacitor element 20 is set to 400 mΩ. On the other hand, the ESR value of the multilayer ceramic capacitor element 30 (hereinafter referred to as “low ESR capacitor element 30”) is set to, for example, 100 mΩ or less. In the present embodiment, the ESR value of the low ESR capacitor element 30 is set to 10 mΩ.
　図２，３に示されるように、高ＥＳＲコンデンサ素子２０は、セラミック層を介して厚み方向に積層された複数の内部電極２１，２２を有している。内部電極２１及び内部電極２２は、略矩形の薄膜状に形成されており、セラミック層を介して互いに対向するように、交互に積層されている。内部電極２１，２２は、例えば、Ｎｉ、Ｃｕ、Ａｇ、Ｐｄ、Ａｇ－Ｐｄ合金、Ａｕなどから形成される。ここで、セラミック焼結体１０の側面１１，１２には、一対の外部電極２３，２４が配設されており、内部電極２１は、セラミック焼結体１０の一方の側面１１に引き出され、外部電極２３と接続されている。内部電極２２は、セラミック焼結体１０の他方の側面１２に引き出され、外部電極２４と接続されている。 As shown in FIGS. 2 and 3, the high ESR capacitor element 20 has a plurality of internal electrodes 21 and 22 stacked in the thickness direction through ceramic layers. The internal electrodes 21 and the internal electrodes 22 are formed in a substantially rectangular thin film shape, and are alternately stacked so as to face each other with a ceramic layer interposed therebetween. The internal electrodes 21 and 22 are made of, for example, Ni, Cu, Ag, Pd, an Ag—Pd alloy, Au, or the like. Here, a pair of external electrodes 23, 24 are disposed on the side surfaces 11, 12 of the ceramic sintered body 10, and the internal electrode 21 is drawn out to one side surface 11 of the ceramic sintered body 10, It is connected to the electrode 23. The internal electrode 22 is drawn out to the other side surface 12 of the ceramic sintered body 10 and connected to the external electrode 24.
　一対の外部電極２３と外部電極２４とは、セラミック焼結体１０を挟んで対向するように、該セラミック焼結体１０の側面１１，１２に形成されている。なお、外部電極２３及び外部電極２４の構成は同一であるので、ここでは、外部電極２３を主にして説明する。外部電極２３（２４）は、内部電極２１（２２）に接続される下地電極２３ａ（２４ａ）と、該下地電極２３ａ（２４ａ）を覆うように形成される抵抗皮膜２３ｂ（２４ｂ）と、該抵抗皮膜２３ｂ（２４ｂ）を覆うように形成されるニッケルメッキ層２３ｃ（２４ｃ）及びスズメッキ層２３ｄ（２４ｄ）と含んで構成されている。なお、外部電極２３（２４）を構成する下地電極２３ａ（２４ａ）、抵抗皮膜２３ｂ（２４ｂ）、ニッケルメッキ層２３ｃ（２４ｃ）、及びスズメッキ層２３ｄ（２４ｄ）それぞれは、側面１１（１２）から、該側面１１（１２）と直交する側面１３及び上下の主面に回り込むように形成されている。 The pair of external electrodes 23 and external electrodes 24 are formed on the side surfaces 11 and 12 of the ceramic sintered body 10 so as to face each other with the ceramic sintered body 10 interposed therebetween. Since the external electrode 23 and the external electrode 24 have the same configuration, the external electrode 23 will be mainly described here. The external electrode 23 (24) includes a base electrode 23a (24a) connected to the internal electrode 21 (22), a resistance film 23b (24b) formed so as to cover the base electrode 23a (24a), and the resistance A nickel plating layer 23c (24c) and a tin plating layer 23d (24d) are formed so as to cover the film 23b (24b). The base electrode 23a (24a), the resistance film 23b (24b), the nickel plating layer 23c (24c), and the tin plating layer 23d (24d) constituting the external electrode 23 (24) are respectively formed from the side surface 11 (12). It is formed so as to wrap around the side surface 13 orthogonal to the side surface 11 (12) and the upper and lower main surfaces.
　内部電極２１（２２）に接続される下地電極２３ａ（２４ａ）は、例えば、Ｃｕ、Ｎｉ、Ａｇ、Ｐｄ、Ａｇ－Ｐｄ合金、Ａｕなどを含む導電性ペーストを焼き付けることによって形成される。 The base electrode 23a (24a) connected to the internal electrode 21 (22) is formed by baking a conductive paste containing, for example, Cu, Ni, Ag, Pd, Ag—Pd alloy, Au, or the like.
　抵抗皮膜２３ｂ（２４ｂ）は、抵抗成分を含有する抵抗ペーストを焼き付けることによって形成される。抵抗皮膜２３ｂ（２４ｂ）が形成されることにより高ＥＳＲコンデンサ素子２０の容量に対して抵抗成分が直列に入ることとなり、高ＥＳＲコンデンサ素子２０のＥＳＲが高くなる。なお、抵抗成分としては、例えば、Ｉｎ－Ｓｎ複合酸化物（ＩＴＯ）、Ｌａ－Ｃｕ複合酸化物、Ｓｒ－Ｆｅ複合酸化物、Ｃａ－Ｓｒ－Ｒｕ複合酸化物などの複合酸化物が用いられる。また、抵抗皮膜２３ｂ（２４ｂ）には、例えばＢ－Ｓｉ系ガラス、Ｂ－Ｓｉ－Ｚｎ系ガラスなどのガラスが添加される。さらに、抵抗皮膜２３ｂ（２４ｂ）に、Ｎｉ，Ｃｕ、Ｍｏ、Ｃｒ、Ｎｂなどの金属や、Ａｌ２Ｏ３、ＴｉＯ２、ＺｒＯ２、ＺｎＯ２などの金属酸化物を添加することにより、比抵抗等を調整してもよい。 The resistance film 23b (24b) is formed by baking a resistance paste containing a resistance component. By forming the resistance film 23b (24b), a resistance component enters in series with respect to the capacity of the high ESR capacitor element 20, and the ESR of the high ESR capacitor element 20 increases. As the resistance component, for example, composite oxides such as In—Sn composite oxide (ITO), La—Cu composite oxide, Sr—Fe composite oxide, and Ca—Sr—Ru composite oxide are used. Further, for example, glass such as B—Si glass or B—Si—Zn glass is added to the resistance film 23b (24b). Furthermore, even if a specific resistance or the like is adjusted by adding a metal such as Ni, Cu, Mo, Cr, or Nb or a metal oxide such as Al2O3, TiO2, ZrO2, or ZnO2 to the resistance film 23b (24b). Good.
　抵抗皮膜２３ｂ（２４ｂ）の外表面には、該抵抗皮膜２３ｂ（２４ｂ）を覆うように、耐はんだ喰われ性を有するニッケルメッキ層２３ｃ（２４ｃ）、及び、該ニッケルメッキ層２３ｃ（２４ｃ）を覆い、はんだに対する濡れ性を良好とするためのスズメッキ層２３ｄ（２４ｄ）が形成される。 On the outer surface of the resistance film 23b (24b), a nickel plating layer 23c (24c) having resistance to solder erosion and the nickel plating layer 23c (24c) are provided so as to cover the resistance film 23b (24b). A tin plating layer 23d (24d) is formed for covering and improving the wettability with respect to the solder.
　外部電極２３は、多層基板に実装される際に、電源のマイナス（－）極（グランド）に接続されるグランド端子となる。また、外部電極２４は、電源のプラス（＋）極に接続される電源端子となる。 The external electrode 23 becomes a ground terminal connected to the negative (−) pole (ground) of the power supply when mounted on the multilayer substrate. The external electrode 24 serves as a power supply terminal connected to the positive (+) pole of the power supply.
　一方、図２，４に示されるように、低ＥＳＲコンデンサ素子３０は、セラミック層を介して厚み方向に積層された複数の内部電極３１，３２を有している。内部電極３１及び内部電極３２は、略矩形の薄膜状に形成されており、セラミック層を介して互いに対向するように、交互に積層されている。内部電極３１，３２は、例えば、Ｎｉ、Ｃｕ、Ａｇ、Ｐｄ、Ａｇ－Ｐｄ合金、Ａｕなどから形成されている。ここで、セラミック焼結体１０の側面１１，１２には、一対の外部電極３３，３４が配設されており、内部電極３２は、セラミック焼結体１０の一方の側面１１に引き出され、外部電極３４と接続されている。内部電極３１は、セラミック焼結体１０の他方の側面１２に引き出され、外部電極３３と接続されている。 On the other hand, as shown in FIGS. 2 and 4, the low ESR capacitor element 30 has a plurality of internal electrodes 31 and 32 laminated in the thickness direction via ceramic layers. The internal electrodes 31 and the internal electrodes 32 are formed in a substantially rectangular thin film shape, and are alternately stacked so as to face each other through the ceramic layer. The internal electrodes 31 and 32 are made of, for example, Ni, Cu, Ag, Pd, an Ag—Pd alloy, Au, or the like. Here, a pair of external electrodes 33, 34 are disposed on the side surfaces 11, 12 of the ceramic sintered body 10, and the internal electrode 32 is drawn out to one side surface 11 of the ceramic sintered body 10, It is connected to the electrode 34. The internal electrode 31 is drawn out to the other side surface 12 of the ceramic sintered body 10 and connected to the external electrode 33.
　一対の外部電極３３と外部電極３４とは、セラミック焼結体１０を挟んで対向するように、該セラミック焼結体１０の側面１１，１２に形成されている。なお、外部電極３３及び外部電極３４の構成は同一であるので、ここでは、外部電極３３を主にして説明する。外部電極３３（３４）は、内部電極３１（３２）に接続される下地電極３３ａ（３４ａ）と、該下地電極３３ａ（３４ａ）を覆うように形成されるニッケルメッキ層３３ｃ（３４ｃ）及びスズメッキ層３３ｄ（３４ｄ）と含んで構成されている。すなわち、外部電極３３（３４）は、上述した外部電極２３（２４）とは、抵抗皮膜２３ｂ（２４ｂ）を有しない点で異なっている。そのため、低ＥＳＲコンデンサ素子３０のＥＳＲ値は、高ＥＳＲコンデンサ素子２０のＥＳＲ値よりも小さくなる。 The pair of external electrodes 33 and external electrodes 34 are formed on the side surfaces 11 and 12 of the ceramic sintered body 10 so as to face each other with the ceramic sintered body 10 interposed therebetween. Since the external electrode 33 and the external electrode 34 have the same configuration, the external electrode 33 will be mainly described here. The external electrode 33 (34) includes a base electrode 33a (34a) connected to the internal electrode 31 (32), a nickel plating layer 33c (34c) and a tin plating layer formed so as to cover the base electrode 33a (34a). 33d (34d). That is, the external electrode 33 (34) is different from the external electrode 23 (24) described above in that it does not have the resistance film 23b (24b). Therefore, the ESR value of the low ESR capacitor element 30 is smaller than the ESR value of the high ESR capacitor element 20.
　なお、外部電極３３（３４）を構成する下地電極３３ａ（３４ａ）、ニッケルメッキ層３３ｃ（３４ｃ）、及びスズメッキ層３３ｄ（３４ｄ）それぞれは、側面１２（１１）から、該側面１２（１１）と直交する側面１４及び上下の主面に回り込むように形成されている。 The base electrode 33a (34a), the nickel plating layer 33c (34c), and the tin plating layer 33d (34d) constituting the external electrode 33 (34) are respectively connected to the side surface 12 (11) and the side surface 12 (11). It is formed so as to wrap around the orthogonal side surface 14 and the upper and lower main surfaces.
　内部電極３１（３２）に接続される下地電極３３ａ（３４ａ）は、上述した下地電極２３ａ（２４ａ）と同様に、例えば、Ｃｕ、Ｎｉ、Ａｇ、Ｐｄ、Ａｇ－Ｐｄ合金、Ａｕなどを含む導電性ペーストを焼き付けることによって形成される。 The base electrode 33a (34a) connected to the internal electrode 31 (32) is a conductive material containing, for example, Cu, Ni, Ag, Pd, an Ag—Pd alloy, Au, etc., like the base electrode 23a (24a) described above. It is formed by baking an adhesive paste.
　下地電極３３ａ（３４ａ）の外表面には、該下地電極３３ａ（３４ａ）を覆うように、耐はんだ喰われ性を有するニッケルメッキ層３３ｃ（３４ｃ）、及び、該ニッケルメッキ層３３ｃ（３４ｃ）を覆い、はんだに対する濡れ性を良好とするためのスズメッキ層３３ｄ（３４ｄ）が形成される。 On the outer surface of the base electrode 33a (34a), a nickel plating layer 33c (34c) having solder erosion resistance and the nickel plating layer 33c (34c) are provided so as to cover the base electrode 33a (34a). A tin plating layer 33d (34d) is formed to cover and improve the wettability with respect to the solder.
　外部電極３３は、多層基板に実装される際に、電源のマイナス（－）極（グランド）に接続されるグランド端子となる。また、外部電極３４は、電源のプラス（＋）極に接続される電源端子となる。ここで、上述したように、外部電極２３は、電源のマイナス（－）極に接続されるグランド端子であり、外部電極２４は、電源のプラス（＋）極に接続される電源端子である。よって、２個のコンデンサ素子、すなわち、高ＥＳＲコンデンサ素子２０及び低ＥＳＲコンデンサ素子３０の配列方向に沿って隣り合う外部電極２３と外部電極３４とは、多層基板に実装される際に、接続される電源の極性が互いに異なるように実装される。同様に、外部電極２４と外部電極３３とは、多層基板に実装される際に、接続される電源の極性が互いに異なるように実装される。 The external electrode 33 serves as a ground terminal connected to the negative (−) pole (ground) of the power supply when mounted on the multilayer substrate. The external electrode 34 serves as a power supply terminal connected to the positive (+) pole of the power supply. Here, as described above, the external electrode 23 is a ground terminal connected to the negative (−) pole of the power supply, and the external electrode 24 is a power supply terminal connected to the positive (+) pole of the power supply. Therefore, the external electrodes 23 and the external electrodes 34 adjacent to each other along the arrangement direction of the two capacitor elements, that is, the high ESR capacitor element 20 and the low ESR capacitor element 30 are connected when mounted on the multilayer substrate. The power supplies are mounted so that their polarities are different from each other. Similarly, the external electrode 24 and the external electrode 33 are mounted so that the polarities of the connected power sources are different when mounted on the multilayer substrate.
　ここで、多層基板１００に実装されたコンデンサアレイ１の様子を図５に示す。図５は、コンデンサアレイ１が実装された多層基板１００の要部拡大図である。多層基板１００には、コンデンサアレイ１の他、電源、ＩＣやＬＳＩ等の電子部品（図示省略）が実装されている。多層基板１００は、電源プレーン、及び、該電源プレーンと誘電体層を介して対向して配置されるグランドプレーンを内層として有している。多層基板１００には、例えば銅箔などから形成され、電源（ＩＣなどの電源ピン）－グランド間にコンデンサアレイ１を接続するためのプリント配線（電源配線）１１０，１１１，１１２，１１３が形成されている。 Here, the appearance of the capacitor array 1 mounted on the multilayer substrate 100 is shown in FIG. FIG. 5 is an enlarged view of a main part of the multilayer substrate 100 on which the capacitor array 1 is mounted. In addition to the capacitor array 1, electronic components (not shown) such as a power supply, IC, and LSI are mounted on the multilayer substrate 100. The multilayer substrate 100 includes, as an inner layer, a power plane and a ground plane that is disposed to face the power plane with a dielectric layer interposed therebetween. The multilayer substrate 100 is formed of, for example, copper foil, and printed wirings (power wirings) 110, 111, 112, 113 for connecting the capacitor array 1 between a power source (power source pins such as an IC) and the ground are formed. ing.
　プリント配線１１０の一端には、はんだ付けによってコンデンサアレイ１の外部電極２３が接続されている。このプリント配線１１０の他端は、ビア１２０と接続されている。ビア１２０は、プリント配線１１０の他端と多層基板１００のグランドプレーンとを接続するものである。これにより、コンデンサアレイ１の外部電極２３は、グランドに接続される。また、プリント配線１１１の一端には、はんだ付けによってコンデンサアレイ１の外部電極２４が接続されている。このプリント配線１１１の他端は、ビア１２１と接続されている。ビア１２１は、プリント配線１１１の他端と多層基板１００の電源プレーンとを接続するものである。これにより、コンデンサアレイ１の外部電極２４は、電源（ＩＣの電源ピン）に接続される。 The external electrode 23 of the capacitor array 1 is connected to one end of the printed wiring 110 by soldering. The other end of the printed wiring 110 is connected to the via 120. The via 120 connects the other end of the printed wiring 110 and the ground plane of the multilayer substrate 100. Thereby, the external electrode 23 of the capacitor array 1 is connected to the ground. Further, the external electrode 24 of the capacitor array 1 is connected to one end of the printed wiring 111 by soldering. The other end of the printed wiring 111 is connected to the via 121. The via 121 connects the other end of the printed wiring 111 and the power plane of the multilayer substrate 100. As a result, the external electrode 24 of the capacitor array 1 is connected to a power supply (IC power supply pin).
　同様に、プリント配線１１２の一端には、はんだ付けによってコンデンサアレイ１の外部電極３３が接続されている。このプリント配線１１２の他端は、ビア１２２と接続されている。ビア１２２は、プリント配線１１２の他端と多層基板１００のグランドプレーンとを接続するものである。これにより、コンデンサアレイ１の外部電極３３は、グランドに接続される。また、プリント配線１１３の一端には、はんだ付けによってコンデンサアレイ１の外部電極３４が接続されている。このプリント配線１１３の他端は、ビア１２３と接続されている。ビア１２３は、プリント配線１１３の他端と多層基板１００の電源プレーンとを接続するものである。これにより、コンデンサアレイ１の外部電極３４は、電源（ＩＣの電源ピン）に接続される。 Similarly, the external electrode 33 of the capacitor array 1 is connected to one end of the printed wiring 112 by soldering. The other end of the printed wiring 112 is connected to the via 122. The via 122 connects the other end of the printed wiring 112 and the ground plane of the multilayer substrate 100. Thereby, the external electrode 33 of the capacitor array 1 is connected to the ground. Further, an external electrode 34 of the capacitor array 1 is connected to one end of the printed wiring 113 by soldering. The other end of the printed wiring 113 is connected to the via 123. The via 123 connects the other end of the printed wiring 113 and the power plane of the multilayer substrate 100. Thereby, the external electrode 34 of the capacitor array 1 is connected to the power supply (IC power supply pin).
　上述したようにコンデンサアレイ１が実装されることにより、高ＥＳＲコンデンサ素子２０と低ＥＳＲコンデンサ素子３０とが、並列に、かつ極性が逆向きに電源－グランド間に挿入される。そのため、電源からグランドに流れる電流は、反共振周波数の付近以外の周波数（共振周波数を含む）ではＥＳＲが低い低ＥＳＲコンデンサ素子３０を通り、反共振周波数の付近の周波数ではインピーダンスが低い高ＥＳＲコンデンサ素子２０を通る。よって、共振周波数でのインピーダンスが低く保たれたまま、反共振周波数でのインピーダンスが低減される。 By mounting the capacitor array 1 as described above, the high ESR capacitor element 20 and the low ESR capacitor element 30 are inserted between the power source and the ground in parallel and in the opposite polarity. Therefore, the current flowing from the power source to the ground passes through the low ESR capacitor element 30 having a low ESR at a frequency other than the vicinity of the anti-resonance frequency (including the resonance frequency), and the high ESR capacitor having a low impedance at a frequency near the anti-resonance frequency. It passes through the element 20. Therefore, the impedance at the anti-resonance frequency is reduced while the impedance at the resonance frequency is kept low.
　また、上述したように、多層基板１００に実装される際に、高ＥＳＲコンデンサ素子２０及び低ＥＳＲコンデンサ素子３０の配列方向に沿って隣り合う外部電極２３と外部電極３４とは、接続される電源の極性が互いに異なる。同様に、外部電極２４と外部電極３３とは、接続される電源の極性が互いに異なる。よって、図５に一点鎖線の矢印で示されるように、高ＥＳＲコンデンサ素子２０を流れる電流の向きと、低ＥＳＲコンデンサ素子３０を流れる電流の流れる向きとが逆になる。その結果、相互インダクタンスが打ち消し合う方向に発生し、コンデンサ素子間の電磁気的な結合が抑制される。 As described above, when mounted on the multilayer substrate 100, the external electrode 23 and the external electrode 34 that are adjacent to each other along the arrangement direction of the high ESR capacitor element 20 and the low ESR capacitor element 30 are connected to each other. Are different in polarity. Similarly, the external electrode 24 and the external electrode 33 have different polarities of the connected power sources. Therefore, the direction of the current flowing through the high ESR capacitor element 20 and the direction of the current flowing through the low ESR capacitor element 30 are reversed, as indicated by the one-dot chain line arrow in FIG. As a result, mutual inductance occurs in a direction that cancels out, and electromagnetic coupling between the capacitor elements is suppressed.
　ここで、本実施形態に係るコンデンサアレイ１による電源インピーダンスの低減効果を確認するために、コンデンサアレイ１を電源－グランド間に実装した多層基板１００の電源インピーダンスを測定した。また、比較例として、低ＥＳＲコンデンサのみを実装した場合の電源インピーダンス、及び、高ＥＳＲコンデンサのみを実装したときの電源インピーダンスを併せて測定した。なお、多層基板１００として、電源プレーン－グランドプレーン間容量が８００ｐＦ、電源プレーンのインダクタンスが２０ｐＨのものを用いた。また、コンデンサアレイ１としては、ＥＳＬが２００ｐＨ、容量が０．１μＦ、ＥＳＲが４００ｍΩの高ＥＳＲコンデンサ素子２０と、ＥＳＬが２００ｐＨ、容量が０．１μＦ、ＥＳＲが１０ｍΩの低ＥＳＲコンデンサ素子３０とを有するものを用いた。一方、比較例としての低ＥＳＲコンデンサとして、ＥＳＬが２００ｐＨ、容量が０．１μＦ、ＥＳＲが１０ｍΩのものを用いた。また、比較例としての高ＥＳＲコンデンサとして、ＥＳＬが２００ｐＨ、容量が０．１μＦ、ＥＳＲが４００ｍΩのものを用いた。 Here, in order to confirm the effect of reducing the power source impedance by the capacitor array 1 according to the present embodiment, the power source impedance of the multilayer substrate 100 in which the capacitor array 1 was mounted between the power source and the ground was measured. Further, as a comparative example, the power supply impedance when only a low ESR capacitor was mounted and the power supply impedance when only a high ESR capacitor was mounted were measured. As the multilayer substrate 100, one having a power plane-ground plane capacitance of 800 pF and a power plane inductance of 20 pH was used. The capacitor array 1 includes a high ESR capacitor element 20 having an ESL of 200 pH, a capacity of 0.1 μF, and an ESR of 400 mΩ, and a low ESR capacitor element 30 having an ESL of 200 pH, a capacity of 0.1 μF, and an ESR of 10 mΩ. What I have was used. On the other hand, as a low ESR capacitor as a comparative example, an ESL having a pH of 200 pH, a capacity of 0.1 μF, and an ESR of 10 mΩ was used. As a comparative example, a high ESR capacitor having an ESL of 200 pH, a capacity of 0.1 μF, and an ESR of 400 mΩ was used.
　コンデンサアレイ１が実装された多層基板１００、低ＥＳＲコンデンサのみが実装された多層基板、及び、高ＥＳＲコンデンサのみが実装された多層基板それぞれの電源インピーダンスの周波数特性（測定結果）を図６に示す。図６に示されたグラフの横軸は周波数（Ｈｚ）であり、縦軸はインピーダンス（Ω）である。また、図６のグラフでは、実施形態に係るコンデンサアレイ１を用いたときの測定結果を実線で、低ＥＳＲコンデンサのみを用いたときの測定結果を破線で、高ＥＳＲコンデンサのみを用いたときの測定結果を一点鎖線でそれぞれ示した。 FIG. 6 shows frequency characteristics (measurement results) of power supply impedances of the multilayer substrate 100 on which the capacitor array 1 is mounted, the multilayer substrate on which only the low ESR capacitor is mounted, and the multilayer substrate on which only the high ESR capacitor is mounted. . The horizontal axis of the graph shown in FIG. 6 is frequency (Hz), and the vertical axis is impedance (Ω). In the graph of FIG. 6, the measurement result when the capacitor array 1 according to the embodiment is used is a solid line, the measurement result when only the low ESR capacitor is used is a broken line, and the measurement result when only the high ESR capacitor is used is shown. The measurement results are shown by alternate long and short dash lines.
　図６に破線で示されるように、低ＥＳＲコンデンサのみを用いた場合、共振周波数（約１２ＭＨｚ）でのインピーダンスは低く（約１３ｍΩ）抑えられているが、反共振周波数（約５００ＭＨｚ）ではピークが生じ、インピーダンスが急激に増大（約１００Ω）している。 As shown by the broken line in FIG. 6, when only the low ESR capacitor is used, the impedance at the resonance frequency (about 12 MHz) is suppressed to a low level (about 13 mΩ), but the peak is at the anti-resonance frequency (about 500 MHz). As a result, the impedance rapidly increases (about 100Ω).
　一方、図６に一点鎖線で示されるように、高ＥＳＲコンデンサのみを用いた場合、反共振周波数（約５００ＭＨｚ）でのインピーダンスは比較的低く（約３Ω）抑えられている。しかしながら、反共振周波数よりも低周波数側、特に６０ＭＨｚよりも低い周波数領域で、インピーダンスが増大（約２５０～４００ｍΩ）している。 On the other hand, as shown by the one-dot chain line in FIG. 6, when only the high ESR capacitor is used, the impedance at the anti-resonance frequency (about 500 MHz) is relatively low (about 3Ω). However, the impedance increases (about 250 to 400 mΩ) on the lower frequency side than the antiresonance frequency, particularly in the frequency region lower than 60 MHz.
　図６に実線で示されるように、本実施形態に係るコンデンサアレイ１が実装されている場合、共振周波数（約１６ＭＨｚ）でのインピーダンスは比較的低く（約２２ｍΩ）抑えられている。また、反共振周波数（約５００ＭＨｚ）でのインピーダンスも比較的低く（約５．５Ω）抑えられている。このように、本実施形態に係るコンデンサアレイ１によれば、共振周波数での電源インピーダンスを低く保ったまま反共振周波数での電源インピーダンスを低減できることが確認された。 As shown by a solid line in FIG. 6, when the capacitor array 1 according to the present embodiment is mounted, the impedance at the resonance frequency (about 16 MHz) is relatively low (about 22 mΩ). In addition, the impedance at the anti-resonance frequency (about 500 MHz) is also relatively low (about 5.5Ω). As described above, according to the capacitor array 1 according to the present embodiment, it was confirmed that the power supply impedance at the anti-resonance frequency can be reduced while keeping the power supply impedance at the resonance frequency low.
　本実施形態に係るコンデンサアレイ１は、ＥＳＲ値が高い高ＥＳＲコンデンサ素子２０と、ＥＳＲ値が低い低ＥＳＲコンデンサ素子３０とを有している。そのため、コンデンサアレイ１が実装された場合、電源からグランドに流れる電流は、反共振周波数の付近以外の周波数（共振周波数を含む）ではＥＳＲが低い低ＥＳＲコンデンサ素子３０を通り、反共振周波数の付近の周波数ではインピーダンスが低い高ＥＳＲコンデンサ素子２０を通る。そのため、共振周波数でのインピーダンスを低く保ったまま、反共振周波数でのインピーダンスを下げることができる。また、本実施形態によれば、多層基板１００に実装される際に、高ＥＳＲコンデンサ素子２０及び低ＥＳＲコンデンサ素子３０の配列方向に沿って隣り合う外部電極２３と外部電極３４とは、接続される電源の極性が互いに異なる。同様に、外部電極２４と外部電極３３とは、接続される電源の極性が互いに異なる。よって、高ＥＳＲコンデンサ素子２０を流れる電流の向きと、低ＥＳＲコンデンサ素子３０を流れる電流の流れる向きとが逆になる。その結果、相互インダクタンスが打ち消し合う方向に発生し、コンデンサ素子間の電磁気的な結合が抑制される。よって、隣り合う高ＥＳＲコンデンサ素子２０と低ＥＳＲコンデンサ素子３０との間隔をより小さくすることができる。これらの結果、共振周波数での電源インピーダンスを低く保ったまま反共振周波数での電源インピーダンスを下げることができ、かつ、サイズをより小型化することが可能となる。 The capacitor array 1 according to the present embodiment includes a high ESR capacitor element 20 having a high ESR value and a low ESR capacitor element 30 having a low ESR value. Therefore, when the capacitor array 1 is mounted, the current flowing from the power source to the ground passes through the low ESR capacitor element 30 having a low ESR at a frequency other than the vicinity of the anti-resonance frequency (including the resonance frequency), and near the anti-resonance frequency. It passes through the high ESR capacitor element 20 having a low impedance at a frequency of. Therefore, the impedance at the anti-resonance frequency can be lowered while keeping the impedance at the resonance frequency low. Further, according to the present embodiment, when mounted on the multilayer substrate 100, the external electrode 23 and the external electrode 34 that are adjacent to each other along the arrangement direction of the high ESR capacitor element 20 and the low ESR capacitor element 30 are connected. The power supplies that have different polarities. Similarly, the external electrode 24 and the external electrode 33 have different polarities of the connected power sources. Therefore, the direction of the current flowing through the high ESR capacitor element 20 and the direction of the current flowing through the low ESR capacitor element 30 are reversed. As a result, mutual inductance occurs in a direction that cancels out, and electromagnetic coupling between the capacitor elements is suppressed. Therefore, the distance between adjacent high ESR capacitor elements 20 and low ESR capacitor elements 30 can be further reduced. As a result, the power impedance at the anti-resonance frequency can be lowered while keeping the power impedance at the resonance frequency low, and the size can be further reduced.
　また、本実施形態によれば、１個の低ＥＳＲコンデンサ素子３０と、１個の高ＥＳＲコンデンサ素子２０とでコンデンサアレイ１が構成されるため、より小型化を図ることができる。 In addition, according to the present embodiment, since the capacitor array 1 is configured by one low ESR capacitor element 30 and one high ESR capacitor element 20, it is possible to further reduce the size.
　本実施形態によれば、高ＥＳＲコンデンサ素子２０の外部電極２３，２４には、下地電極２３ａ，２４ａとニッケルメッキ層２３ｃ，２４ｃとの間に、下地電極２３ａ，２４ａを覆うように抵抗皮膜２３ｂ，２４ｂが形成されている。そのため、該抵抗皮膜２３ｂ，２４ｂの抵抗値を調節することにより、比較的容易に高ＥＳＲコンデンサ素子２０のＥＳＲ値を適切な値まで高くすることができる。 According to the present embodiment, the external electrodes 23 and 24 of the high ESR capacitor element 20 include the resistance film 23b between the base electrodes 23a and 24a and the nickel plating layers 23c and 24c so as to cover the base electrodes 23a and 24a. , 24b are formed. Therefore, the ESR value of the high ESR capacitor element 20 can be increased to an appropriate value relatively easily by adjusting the resistance values of the resistance films 23b and 24b.
　本実施形態に係る多層基板１００によれば、コンデンサアレイ１が電源－グランド間に実装されているため、共振周波数での電源インピーダンスを低く保ったまま反共振周波数での電源インピーダンスを下げることが可能となる。 According to the multilayer substrate 100 according to the present embodiment, since the capacitor array 1 is mounted between the power supply and the ground, the power supply impedance at the anti-resonance frequency can be lowered while keeping the power supply impedance at the resonance frequency low. It becomes.
　以上、本発明の実施の形態について説明したが、本発明は、上記実施形態に限定されるものではなく種々の変形が可能である。例えば、上記実施形態では、２個のコンデンサ素子２０，３０を含む４端子のコンデンサアレイ１を例にして説明したが、コンデンサアレイに含まれるコンデンサ素子の数は２個には限られない。例えば、コンデンサアレイは、３個のコンデンサ素子（６端子）、４個のコンデンサ素子（８端子）、又は、それ以上の数のコンデンサ素子を含んでいてもよい。 Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made. For example, in the above embodiment, the four-terminal capacitor array 1 including the two capacitor elements 20 and 30 has been described as an example. However, the number of capacitor elements included in the capacitor array is not limited to two. For example, the capacitor array may include three capacitor elements (6 terminals), four capacitor elements (8 terminals), or a larger number of capacitor elements.
　その際に、コンデンサ素子の配列方向に沿って隣り合う電極は、多層基板に実装される際に接続される電源の極性が互いに異なるように配設される。また、その際に、コンデンサアレイは、１個以上の高ＥＳＲコンデンサ素子を含むものとする。ただし、高ＥＳＲコンデンサ素子の数は、低ＥＳＲコンデンサ素子の数以上であることが好ましい。そのようにすれば、並列に接続される高ＥＳＲコンデンサ素子の数が多くなる。そのため、より多くの高ＥＳＲコンデンサ素子のＥＳＬが並列に接続されることとなり、高ＥＳＲコンデンサ素子全体のＥＳＬがより低減される。その結果、反共振周波数での電源インピーダンスを効果的に低減することができる。 At that time, the electrodes adjacent to each other in the arrangement direction of the capacitor elements are arranged so that the polarities of the power supplies connected when mounted on the multilayer substrate are different from each other. At that time, the capacitor array includes one or more high ESR capacitor elements. However, the number of high ESR capacitor elements is preferably equal to or greater than the number of low ESR capacitor elements. By doing so, the number of high ESR capacitor elements connected in parallel increases. Therefore, ESLs of more high ESR capacitor elements are connected in parallel, and the ESL of the entire high ESR capacitor elements is further reduced. As a result, the power source impedance at the antiresonance frequency can be effectively reduced.
　上記実施形態では、外部電極２３及び外部電極２４の双方に抵抗皮膜２３ｂ，２４ｂを設ける構成としたが、いずれか一方の外部電極にのみ抵抗皮膜を設ける構成としてもよい。 In the above embodiment, the resistance films 23b and 24b are provided on both the external electrode 23 and the external electrode 24. However, the resistance film may be provided only on one of the external electrodes.
　また、実装される際にグランドに接続される外部端子２３と外部端子３４とは、内部で接続されていてもよい。その際に、抵抗皮膜は外部端子２４側にのみ設けられる。 Further, the external terminal 23 and the external terminal 34 that are connected to the ground when mounted may be connected internally. At that time, the resistance film is provided only on the external terminal 24 side.
　上記実施形態では、高ＥＳＲコンデンサ素子２０の内部電極２１，２２として、略矩形に形成されたものを用いたが、ＥＳＲを調節するために、外部電極２３，２４（下地電極２３ａ，２４ａ）との接続部が狭窄された形状の内部電極を用いてもよい。 In the above embodiment, the internal electrodes 21 and 22 of the high ESR capacitor element 20 are formed in a substantially rectangular shape. However, in order to adjust the ESR, the external electrodes 23 and 24 ( underlying electrodes 23a and 24a) An internal electrode having a constricted connection portion may be used.
　１　コンデンサアレイ
　１０　セラミック焼結体
　２０　高ＥＳＲコンデンサ素子
　３０　低ＥＳＲコンデンサ素子
　２１，２２，３１，３２　内部電極
　２３，３３　外部電極（グランド端子）
　２４，３４　外部電極（電源端子）
　２３ａ，２４ａ，３３ａ，３４ａ　下地電極
　２３ｂ，２４ｂ　抵抗皮膜
　２３ｃ，２４ｃ，３３ｃ，３４ｃ　ニッケルメッキ層
　２３ｄ，２４ｄ，３３ｄ，３４ｄ　スズメッキ層
　１００　多層基板
　１１０，１１１，１１２，１１３　電源配線
　１２０，１２１，１２２，１２３　ビア
  1 Capacitor Array 10 Ceramic Sintered Body 20 High ESR Capacitor Element 30 Low ESR Capacitor Element 21, 22, 31, 32 Internal Electrode 23, 33 External Electrode (Ground Terminal)
24, 34 External electrode (power supply terminal)
23a, 24a, 33a, 34a Base electrode 23b, 24b Resistance film 23c, 24c, 33c, 34c Nickel plating layer 23d, 24d, 33d, 34d Tin plating layer 100 Multilayer substrate 110, 111, 112, 113 Power supply wiring 120, 121, 122 , 123 Via

Claims (5)

  1. 　多層基板の電源－グランド間に実装されるコンデンサアレイであって、
    　誘電体素体と、
    　前記誘電体素体内に配設された複数のコンデンサ素子と、
    　前記コンデンサ素子ごとに対となって前記誘電体素体の側面に設けられた外部電極と、を備え、
    　前記複数のコンデンサ素子は、等価直列抵抗の値が異なる少なくとも２種類のコンデンサ素子を含み、
    　前記複数のコンデンサ素子の配列方向に沿って隣り合う前記外部電極は、前記多層基板に実装される際に、接続される電源の極性が互いに異なることを特徴とするコンデンサアレイ。     A capacitor array mounted between the power supply and ground of a multilayer board,
    A dielectric body;
    A plurality of capacitor elements disposed in the dielectric body;
    An external electrode provided on a side surface of the dielectric element body as a pair for each capacitor element;
    The plurality of capacitor elements include at least two types of capacitor elements having different values of equivalent series resistance,
    The capacitor array, wherein the external electrodes adjacent to each other in the arrangement direction of the plurality of capacitor elements have different polarities of power supplies connected when mounted on the multilayer substrate.
  2. 　２つの前記コンデンサ素子を含み、一方のコンデンサ素子の等価直列抵抗の値が、他方のコンデンサ素子の等価直列抵抗の値よりも高いことを特徴とする請求項１に記載のコンデンサアレイ。 2. The capacitor array according to claim 1, comprising two capacitor elements, wherein an equivalent series resistance value of one capacitor element is higher than an equivalent series resistance value of the other capacitor element.
  3. 　前記複数のコンデンサ素子に含まれる等価直列抵抗の値が高い方のコンデンサ素子の数は、等価直列抵抗の値が低い方のコンデンサ素子の数以上であることを特徴とする請求項１に記載のコンデンサアレイ。 2. The number of capacitor elements having a higher equivalent series resistance value included in the plurality of capacitor elements is equal to or greater than the number of capacitor elements having a lower equivalent series resistance value. Capacitor array.
  4. 　等価直列抵抗の値が高い方のコンデンサ素子の外部電極は、該コンデンサ素子の内部電極に接続される下地電極と、該下地電極を覆うように形成される抵抗皮膜と、該抵抗皮膜を覆うように形成されるメッキ層と、を有することを特徴とする請求項１～３のいずれか１項に記載のコンデンサアレイ。 The external electrode of the capacitor element having the higher equivalent series resistance value includes a base electrode connected to the internal electrode of the capacitor element, a resistance film formed to cover the base electrode, and the resistance film The capacitor array according to any one of claims 1 to 3, further comprising: a plating layer formed on the substrate.
  5. 　請求項１～４のいずれか１項に記載のコンデンサアレイの実装方法であって、
    　前記複数のコンデンサ素子の配列方向に沿って隣り合う前記外部電極に接続される電源の極性が互いに異なるように、前記コンデンサアレイを前記多層基板の電源－グランド間に実装することを特徴とするコンデンサアレイの実装方法。
          A method for mounting a capacitor array according to any one of claims 1 to 4,
    The capacitor array is mounted between the power source and the ground of the multilayer board so that the polarities of the power sources connected to the external electrodes adjacent to each other along the arrangement direction of the plurality of capacitor elements are different from each other. Array mounting method.
PCT/JP2012/000077 2011-02-08 2012-01-10 Capacitor array and method for installing capacitor array WO2012108122A1 (en)

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US10250215B2 (en) 2014-12-10 2019-04-02 Nec Corporation Electronic circuit and method for mounting electronic circuit

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JP2005051226A (en) * 2003-07-15 2005-02-24 Murata Mfg Co Ltd Chip-type electronic component and manufacturing method therefor
JP2008021797A (en) * 2006-07-12 2008-01-31 Tdk Corp Laminated capacitor array

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005051226A (en) * 2003-07-15 2005-02-24 Murata Mfg Co Ltd Chip-type electronic component and manufacturing method therefor
JP2008021797A (en) * 2006-07-12 2008-01-31 Tdk Corp Laminated capacitor array

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10250215B2 (en) 2014-12-10 2019-04-02 Nec Corporation Electronic circuit and method for mounting electronic circuit

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