WO2012093504A1 - Convertisseur clampé par le neutre doté d'un générateur de tension variable afin de stabiliser la tension neutre - Google Patents

Convertisseur clampé par le neutre doté d'un générateur de tension variable afin de stabiliser la tension neutre Download PDF

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Publication number
WO2012093504A1
WO2012093504A1 PCT/JP2011/067915 JP2011067915W WO2012093504A1 WO 2012093504 A1 WO2012093504 A1 WO 2012093504A1 JP 2011067915 W JP2011067915 W JP 2011067915W WO 2012093504 A1 WO2012093504 A1 WO 2012093504A1
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Prior art keywords
voltage
neutral point
neutral
point clamped
converter according
Prior art date
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PCT/JP2011/067915
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English (en)
Inventor
Horst Gruening
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Mitsubishi Electric Corporation
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Application filed by Mitsubishi Electric Corporation filed Critical Mitsubishi Electric Corporation
Priority to JP2013515440A priority Critical patent/JP2013539334A/ja
Publication of WO2012093504A1 publication Critical patent/WO2012093504A1/fr

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/487—Neutral point clamped inverters

Definitions

  • the present invention relates to an AC converter for converting electric power to an AC power and, more particularly, to a neutral point clamped converter which can maintain a neutral point voltage of the converter to a predetermined neutral voltage.
  • An AC converter receives a DC voltage which is chopped by a switching circuit according to a desired frequency to produce an AC voltage which varies between a positive voltage Vp and a negative voltage Vn through a neutral voltage Vc.
  • the switching circuit has a positive input, a negative input and a neutral input for receiving the positive voltage Vp, the negative voltage Vn and the neutral voltage Vc, respectively.
  • the DC voltage is also applied to a series connection of two capacitors.
  • the opposite ends of the series connection of the two capacitors provide the positive voltage Vp and the negative voltage Vn, while a junction between the two capacitors provides a center voltage Vc.
  • the junction between the two capacitors is directly connected to the neutral input of the switching circuit.
  • the charges accumulated in the capacitors are alternately discharged in the switching circuit.
  • the voltage across each capacitor changes as the capacitor is discharged.
  • Such a voltage change results in fluctuation or deviation of the center voltage Vc at the junction between the two capacitors.
  • large size capacitors are used, i.e., the capacitors having a large capacitance are used.
  • a neutral point clamped converter comprises: first and second terminals that receives a DC voltage; first and second capacitors connected in series between said first and second terminals and presenting a center junction between the first and second capacitors; a detecting arrangement that detects a deviation of the voltage at the center junction from a predetermined neutral voltage; a control arrangement that produces a control signal representing the deviation of the voltage; a variable voltage generator that has an input and an output, and generates a variable voltage corresponding to the deviation of the voltage upon receipt of the control signal, said center junction being connected to the input of the variable voltage generator to add the generated variable voltage to the voltage at the center junction, said variable voltage generator producing from the output thereof a neutral voltage which is stabilized to be nearly equal to said predetermined neutral voltage; and a switching circuit that converts the DC voltage to an AC voltage, said switching circuit having at least a positive input, a negative input and a neutral input, said positive input and negative input being connected to said first and second terminals, respectively, and said neutral input connected
  • variable voltage generated by the variable voltage generator is added to the center voltage so that the neutral input of the switching circuit is applied with a voltage nearly equal to the neutral voltage, resulting in stable operation of the switching circuit.
  • Figs. 1A, 1 B and 1C are a circuit diagram of a neutral point clamped converter according to the first embodiment of the present invention, particularly showing a current path to a load during a positive level control, a neutral level control and a negative level control, respectively.
  • Figs. 2A and 2B are graphs showing a voltage change observed at output Vout and at junction Jf, respectively.
  • Fig. 2C is a graph showing a voltage generated by a variable voltage generator.
  • Figs. 3A and 3B are a circuit diagram of one example of the variable voltage generator, particularly showing a current path for generating a negative voltage and a positive voltage, respectively.
  • Figs. 4A, 4B, 4C, 4D, 4E and 4F are waveforms observed at major points in the circuit of Fig. 3A or 3B.
  • Fig. 5 is a circuit diagram similar to that shown in Fig. 1A, but particularly showing a modification of a voltage detecting arrangement.
  • Fig. 6 is a circuit diagram similar to that shown in Fig. 3A, but particularly showing a modification thereof.
  • Fig. 7 is a circuit diagram similar to that shown in Fig. 3A, but particularly showing a modification thereof.
  • Fig. 8 is a circuit diagram similar to that shown in Fig. 1A, but particularly showing chargers.
  • Fig. 9 is a circuit diagram similar to that shown in Fig. 3A, but particularly showing a modification thereof.
  • Fig. 10 is a circuit diagram similar to that shown in Fig. 1A, but particularly showing a resonant transfer circuit.
  • Fig. 11 is a circuit diagram of a three-phase switching circuit that can be used in the circuit of Fig. 1.
  • Fig. 12 is a circuit diagram similar to that shown in Fig. 1A, but particularly showing a three phase power source and a switching circuit at the input side.
  • Fig. 13 is a circuit diagram of a 5-level switching circuit that can be used in the circuit of Fig. 1. DESCRIPTION OF EMBODIMENTS
  • a neutral point clamped converter according to a first embodiment of the present invention is shown which includes a power source 2, such as a DC source, two voltage divider blocks 4 and 6, capacitors C1 and C2, a comparator 16, a controller 12, a variable voltage generator 18, a switching circuit 20 and a load 22.
  • a power source 2 such as a DC source
  • two voltage divider blocks 4 and 6 capacitors C1 and C2
  • a comparator 16 a controller 12
  • a variable voltage generator 18 a switching circuit 20 and a load 22.
  • DC source 2 is connected through terminals 8 and 10 to a series connection of voltage divider blocks 4 and 6 and also to a series connection of capacitors C1 and C2.
  • DC source 2 produces a predetermined DC voltage 2V0.
  • Voltage dividers blocks 4 and 6 are formed, for example, by resistors, which have the same resistance. Thus, the potential at a junction Jc between voltage dividers blocks 4 and 6 is always equal to the center of the DC voltage 2V0.
  • Capacitors C1 and C2 have the same capacitance, and thus each of capacitors C1 and C2 is charged at voltage V0. In other words, the charged voltage across capacitor C1 is the same as that across capacitor C2.
  • a potential at a junction Jf between capacitors C1 and C2 is at the center of the DC voltage 2V0.
  • the symbols indicating the junctions or terminals, such as Jc and Jf, are also used for indicating potential levels at such junctions or terminals.
  • DC source 2 can be any DC source, such as a battery, a solar cell or an AC-DC converter which is similar to the switching circuit 20 shown in Fig. 1 A.
  • the comparator 16 compares voltages Jc and Jf, and produces a difference between potentials Jc and Jf. The potential difference is applied to the controller 12 which controls the operation of the variable voltage generator 18.
  • the switching circuit 20 has three inputs terminals (a positive input terminal Vp, a negative input terminal Vn and a neutral input terminal Vc), and one output terminal Vout. Input terminals Vp and Vn are connected to the opposite ends of the series connection of the capacitors C1 and C2 for receiving positive side voltage and negative side voltage, respectively.
  • Neutral input terminal Vc is connected to the output of the variable voltage generator 18.
  • the output terminal Vout of the switching circuit 20 is connected to an input of the load 22.
  • An output of the load 22 is connected to the neutral input terminal Vc.
  • the load incorporates a resistor only.
  • the switching circuit 20 includes transistors T1 , T2, T3, T4 and diodes D1 , D2, D3, D4, D5 and D6. By the control of transistors T1-T4, the switching circuit 20 is arranged to produce from the output terminal Vout three level voltages: a positive level, a neutral level and a negative level.
  • Transistors T1-T4 are controlled by a timing circuit (not shown) in such a manner that, during period P1 in Figs. 2A-2C, transistors T1 and T2 are turned ON; during period P2, transistors T2 and T3 are turned ON; during period P3, transistors T3 and T4 are turned ON; and during period P4, transistors T2 and T3 are turned ON.
  • Periods P1-P4 are repeatedly to produce AC current from switching circuit 20.
  • period P1 as shown in Fig. 1A, since transistors T1 and T2 of the switching circuit 20 are ON, a current (referred to as a positive side current) flows from capacitor C1 through terminal Vp, transistors T1 and T2, load 22, variable voltage generator 18, and back to capacitor C1.
  • a current can flow from load 22 through transistor T3 and diode D6 to variable voltage generator 18, or from variable voltage generator 18 through diode D5 and transistor T2 to load 22, so as to keep the voltage level at Vout equal to Vc during period P2.
  • a current flow is zero.
  • a current (referred to as a negative side current) flows from capacitor C2 through variable voltage generator 18, terminal Vc, load 22, transistors T3 and T4, and back to capacitor C2.
  • period P4 the operation is basically the same as that described for period P2.
  • capacitor C1 has a sufficiently large capacitance, the voltage at capacitor C1 will be maintained constant, as shown by a dotted line in Fig. 2A in period P1 , i.e., during the flow of the positive side current. However, if capacitor C1 has a relatively small capacitance, as acceptable in the present invention, the voltage at the capacitor C1 will be reduced, as shown by a real line in Fig. 2A, during period P . Thus the potential Jf will be undesirably increased, as shown in Fig. 2B, during period P1. Comparator 16 detects the increase of the potential Jf. Controller 12 receives the information of increase of the potential Jf, and produces a control signal to the variable voltage generator 18. The variable voltage generator 18 produces a voltage Vgen, as shown in Fig. 2C, which will be counterbalanced with the potential increased at junction Jf during period P1 , so that the potential at terminal Vc is maintained at the neutral level.
  • capacitor C2 If capacitor C2 has a relatively small capacitance, as acceptable in the present invention, the voltage at the capacitor C2 will be reduced, as shown by a real line in Fig. 2A, during period P3. Thus the potential Jf will be undesirably decreased, as shown in Fig. 2B, during period P3. Comparator 16 detects the decrease of the potential Jf. Controller 12 receives the information of decrease of the potential Jf, and produces a control signal to the variable voltage generator 18. The variable voltage generator 18 produces a voltage Vgen, as shown in Fig. 2C, which will be counterbalanced with the potential decreased at junction Jf during period P3, so that the potential at terminal Vc is maintained at the neutral level.
  • the increase or decrease of potential Jf with respect to potential Jc is referred to as a deviation of potential Jf.
  • the voltage divider blocks 4 and 6 and comparator 16 taken together define a voltage detecting arrangement that detects a deviation of the potential at the center junction Jf.
  • variable voltage generator 18 has a full bridge circuit including transistors T11 , T12, T13 and T14, and diodes D11 , D12, D13 and D14 connected in reverse direction to transistors T11, T12, T13 and T14, respectively.
  • a capacitor C3 is connected parallel to a series connection of transistors T13 and T14.
  • a filter circuit including an inductor L1 and capacitor C4 is connected between the input and output of the variable voltage generator 18.
  • Capacitor C3 is charged by a charger 17, and is always maintained in a charged condition, i.e., having a voltage higher than or equal to a maximum voltage Vmax, during the entire operation.
  • the voltage Vmax is equal to the maximum possible deviation of potential Jf.
  • Charger 17 can be formed by an internal circuit or an external circuit. For the sake of brevity, charger 17 is shown only in Fig. 3A, and is omitted in other circuits of the voltage generator.
  • Controller 12 has four outputs A1 , A2, A3 and A4 which are connected to transistors T12, T11, T13 and T14, respectively.
  • Outputs A1 and A2 each produces a HIGH or LOW signal representing the polarity of the difference signal from the comparator 16, and outputs A3 and A4 each produces a train of pulses representing an amount of deviation.
  • the train of pulses are produced from a high frequency (such as 20-50 KHz) pulse source (not shown) provided in the controller 12, and are culled at a rate determined by the degree or amount of deviation of the potential Jf.
  • Fig. 3A shows a case when the potential Jf is deviated by -Vd1 (Fig. 4A), and Fig. 3B shows a case when the potential Jf is deviated by +Vd2 (Fig. 4A).
  • Fig. 4A shows the output of comparator 16 representing a potential change at junction Jf with respect to potential Jc. It is assumed that during period Q1 , the potential Jf is decreased by an amount Vd1 which is, for example, equal to 2/3 of the voltage Vmax, and during period Q2, the potential Jf is increased by an amount Vd2 which is, for example, equal to 5/6 of the voltage Vmax.
  • the waveforms of Figs. 4B, 4C, 4D and 4E are the outputs of controller 12, and are applied to transistors T11 , T12, T13 and T14, respectively.
  • controller 12 produces from output A1 a HIGH which is applied to transistor T12.
  • a current path is established through the variable voltage generator 18 as shown in Fig. 3A by a real line when transistor T13 is ON within period Q1 , and a dotted line when transistor T14 is ON within period Q1.
  • controller 12 calculates a degree of deviation of the potential Jf which is expressed by a ratio.
  • output A3 produces pulses having a duty cycle of 2/3 during period Q1 (Fig. 4D)
  • output A4 produces the inverse pulses having a duty cycle of 1/3 during period Q1 (Fig. 4E).
  • transistor T13 is turned ON during 2/3 of time during the period Q1 to charge capacitor C4 in forward direction, resulting in the voltage of 2/3 of the voltage Vmax, as shown in Fig. 4F.
  • the potential deviation appearing at junction Jf is counterbalanced with the voltage charged in capacitor C4, resulting in neutral potential at terminal Vc.
  • controller 12 produces from output A2 a HIGH which is applied to transistor T11.
  • a current path is established through the variable voltage generator 18 as shown in Fig. 3B by a real line when transistor T14 is ON within period Q2, and a dotted line when transistor T13 is ON within period Q2.
  • controller 12 calculates a degree of deviation of the potential Jf which is expressed by a ratio.
  • output A4 produces pulses having a duty cycle of 5/6 during period Q2 (Fig. 4D)
  • output A3 produces the inverse pulses having a duty cycle of 1/6 during period Q2 (Fig. 4E).
  • transistor T14 is turned ON during 5/6 of time during the period Q2 to charge capacitor C4 in reverse direction, resulting in the voltage of -5/6 of the voltage Vmax, as shown in Fig. 4F.
  • the potential deviation appearing at junction Jf is counterbalanced with the voltage charged in capacitor C4, resulting in neutral potential at terminal Vc.
  • the potential at terminal Vc is forcibly adjusted to a neutral level even when the voltages across capacitors C1 and C2 fluctuate by generating a voltage corresponding to the deviated amount, and adding the generated voltage to the potential at junction Jf.
  • capacitors C1 and C2 of small capacitance. Also, it is not necessary at the beginning of the operation to precisely balance the charges in the capacitors C1 and C2.
  • a modification of the voltage detecting arrangement is shown.
  • voltage detectors 104 and 106 shown in Fig. 5.
  • Voltage detector 104 detects a voltage across capacitor C1
  • voltage detector 106 detects a voltage across capacitor C2.
  • the outputs of voltage detectors 104 and 106 are applied to comparator 16.
  • Comparator 16 compares the voltages across capacitors C1 and C2, producing a deviation at junction Jf.
  • the voltage detectors 104 and 106 and comparator 16 taken together define a voltage detecting arrangement that detects a deviation of the potential at the center junction Jf.
  • Such voltage detectors 104 and 106 can be inserted at downstream of the variable voltage generator 18.
  • voltage detector 104 can be inserted between terminals Vp and Vc
  • voltage detector 106 can be inserted between terminals Vc and Vn.
  • controller 12 will operate in feedback loop mode, setting voltage of variable voltage generator 18 such as to make output of comparator 16 close to zero.
  • the voltage detectors 104 and 106, comparator 16 and controller 12 taken together then define a voltage control arrangement that generates a counterbalancing signal to keep the potential at terminal Vc close to the center potential.
  • a modification of the variable voltage generator 18 is shown.
  • the first full bridge circuit includes transistors T11a, T12a, T13a and T14a, diodes D11a, D12a, D13a and D14a, and capacitor C3a.
  • the second full bridge circuit includes transistors T 1b, T12b, T13b and T14b, and diodes D11b, D12b, D13b and D14b, and capacitor C3b. In this case, capacitors C3a and C3b each is charged (1/2)Vmax.
  • Each full bridge circuit is controlled individually by controller 12.
  • Controller 12 has eight outputs A1 , A2, A3, A4, A5, A6, A7 and A8, in which outputs A1-A4 are used for controlling transistors T11a-T14a, and outputs A5-A8 are used for controlling transistors T11b-T14b, in a manner similar to that described above in connection with Figs. 3A-3B and 4A-4F.
  • averaging easier.
  • N being an integer equal to "2" or greater
  • the capacitors in the centers are charged (1/N)Vmax.
  • a modification of the variable voltage generator 18 is shown.
  • the half bridge circuit includes transistors T13c and T14c, diodes D13c and D14c, and capacitor C3c. In this case, capacitor C3c is charged 2Vmax.
  • an offset circuit 30 is connected to junction Jf. According to one example, the offset circuit 30 provides an offset voltage of -Vmax between junction Jf and junction Jfa. Notwithstanding the deviation at junction Jf being positive or negative, the potential at junction Jfa will always be in negative voltage. Thus, the half bridge circuit will always produce a positive voltage to counterbalance the voltage at junction Jfa.
  • the controller 12 has only outputs A3 and A4 which produces pulses having a duty cycle representing an amount of counterbalancing voltage needed.
  • outputs A1 and A2 representing the polarity of the difference signal are not necessary in the example of Fig. 7. This is because the polarity at junction Jfa is always negative in the example of Fig. 7.
  • the offset circuit 30 It is possible to have the offset circuit 30 to provide an offset voltage of +Vmax at junction Jfa. In this case, the half bridge will be so arranged to produce a negative voltage.
  • the neutral point clamped converter is further provided with chargers 30 and 32, which are coupled to capacitors C1 and C2, respectively.
  • Chargers 30 and 32 are used at the beginning of operation to forcibly charge capacitors C1 and C2, respectively.
  • Chargers 30 and 32 are useful when the capacitors C1 and C2 have large capacitance so as to quickly achieve the required voltage level across capacitors C1 and C2.
  • Chargers 30 and 32 are used for charging capacitors C1 and C2 at the same voltage when the potential at junction Jf is to be kept at a neutral value, or at different voltages when the potential at junction Jf is to be kept with a predetermined offset from the neutral value, as described in Modification 4.
  • a modification of the variable voltage generator 18 is shown.
  • the two way chopper circuit includes transistors T10 and T11 , diodes D10 and D11 , capacitors C10 and C11 and inductors L10 and L11.
  • a step-down chopper comprises transistor T10, diode D10 and inductor L10
  • a step-up chopper comprises inductor L11 , transistor T11 and diode D11.
  • the step-up chopper will transfer energy from capacitor C10 to capacitor C11 , which means to draw a current from capacitor C10 and step-up the voltage to the level of capacitor C11.
  • voltage at capacitor C10 can be adjusted to any positive level between zero and the voltage Vmax of capacitor C11 , and by operating transistors T10 and T11 , it is possible to make the current direction through the variable voltage generator to be either one of both directions.
  • the neutral point clamped converter is further provided with a resonant transfer circuit 34 which includes transistors T20 and T21 connected in series between terminals Vp and Vc, transistors T22 and T23 connected in series between terminals Vc and Vn, capacitor C6 and inductor L6 connected in series connected between junctions Ja and Jb.
  • Junction Ja is a junction between transistors T20 and T21
  • junction Jb is a junction between transistors T22 and T23.
  • Diodes D20, D21 , D22 and D23 are coupled to transistors T20, T21 , T22 and T23, respectively.
  • Transistors T20, T21 , T22 and T23 are controlled by further outputs on the controller 12.
  • transistor T20 When capacitor C1 is charged to a level greater than a predetermined level, transistor T20 turns ON to transfer a charge in capacitor C1 through transistor T20 to capacitor C6. At this point, a current flows from capacitor C6 to inductor L6, diode D22 and back to capacitor C1 to accumulate energy in inductor L6. Then, transistor T20 turns OFF and transistor T21 turns ON. Thus, the energy in inductor L6 induces a current flow from inductor L6, capacitor C6, transistor T21, capacitor C2, diode D23 and back to inductor L6. Thus, the capacitor C2 is charged up. In this manner, the charges in capacitors C1 and C2 are kept in the desired level in long term.
  • the resonant transfer circuit 34 is inserted in the downstream side of the variable voltage generator 18, but it can be inserted in the upstream side of the variable voltage generator 18.
  • a modification of the switching circuit 20 is shown.
  • the switching circuit 23 is inserted between terminals Vp and Vn and includes transistors T a, T2a, T3a, T4a and diodes D1a, D2a, D3a, D4a, D5a and D6a for the first phase, transistors T1b, T2b, T3b, T4b and diodes D1b, D2b, D3b, D4b, D5b and D6b for the second phase, and transistors T1c, T2c, T3c, T4c and diodes D1c, D2c, D3c, D4c, D5c and D6c for the third phase.
  • the terminal Vc is connected to a junction between diodes D5a and D6a, a junction between diodes D5b and D6b, and a junction between diodes D5c and D6c.
  • the three-phase load 24 is connected to a junction between transistors T2a and T3a, a junction between transistors T2b and T3b, and a junction between transistors T2c and T3c.
  • a modification of the power source is shown.
  • an AC source such as a three-phase power source 26 and an AC-DC converter 25 inserted between terminals Vp and Vn, as shown in Fig. 12.
  • the AC-DC converter 25 includes transistors Tlx, T2x, T3x, T4x and diodes D1x, D2x, D3x, D4x, D5x and D6x for the first phase, transistors T1y, T2y, T3y, T4y and diodes D1y, D2y, D3y, D4y, D5y and D6y for the second phase, and transistors T1z, T2z, T3z, T4z and diodes D1z, D2z, D3z, D4z, D5z and D6z for the third phase.
  • the terminal Vc is connected to a junction between diodes D5x and D6x, a junction between diodes D5y and D6y, and a junction between diodes D5z and D6z.
  • the three-phase power source 26 is connected to a junction between transistors T2x and T3x, a junction between transistors T2y and T3y, and a junction between transistors T2z and T3z.
  • a modification of the switching circuit 20 is shown. Instead of the switching circuit 20 shown in Fig. 1 , it is possible to use a five level diode clamped circuit having a positive input, a negative input and a neutral input.
  • Such circuit comprises transistors T1m, T2m, T3m, T4m, T5m, T6m, T7m and T8m, and diodes Dim, D2m, D3m, D4m, D5m, D6m, D7m, D8m connected in reverse direction to transistors T1m, T2m, T3m, T4m, T5m, T6m, T7m, T8m, clamping diodes D9m, D10m, D11m, D12m, D13m, D14m and power supply circuitry PS1 , PS2.
  • Power supply circuit PS1 generates a voltage level equal to the center of Vp and Vc.
  • Power supply circuit PS2 generates a voltage level equal to the center of Vc and Vn.
  • the 5-level switching circuit can generate one of the five output potential levels V0, (1/2)V0, 0 -(1/2)V0, -V0.
  • the Vout produces V0.
  • transistors T2m, T3m, T4m and T5m are ON, the Vout produces (1/2)V0.
  • transistors T3m, T4m, T5m and T6m are ON, the Vout produces 0.
  • transistors T4m, T5m, T6m and T7m are ON, the Vout produces -(1/2)V0.
  • transistors T5m, T6m, T7m and T8m are ON, the Vout produces -V0.
  • each of the transistors used in the variable voltage generator 18 can be a MOSFET or an IGBT.
  • the transistors and diodes used in the variable voltage generator 18 are preferably made of wideband gap semiconductors, such as silicon carbide (SiC), gallium nitride (GaN), or diamond, which has a wider band gap than the silicon (Si).
  • each of the transistors used in the switching circuit 20 or 23 can be a MOSFET or an IGBT.
  • the transistors and diodes used in the switching circuit 20 or 23 are preferably made of wideband gap semiconductors, such as silicon carbide (SiC), gallium nitride (GaN), or diamond, which has a wider band gap than the silicon (Si).
  • each of the transistors used in the resonant transfer circuit 34 can be a MOSFET or an IGBT.
  • the transistors and diodes used in the resonant transfer circuit 34 are preferably made of wideband gap semiconductors, such as silicon carbide (SiC), gallium nitride (GaN), or diamond, which has a wider band gap than the silicon (Si).
  • each of the transistors used in the AC-DC converter 25 can be a MOSFET or an IGBT.
  • the transistors and diodes used in the AC-DC converter 25 are preferably made of wideband gap semiconductors, such as silicon carbide (SiC), gallium nitride (GaN), or diamond, which has a wider band gap than the silicon (Si).
  • the transistors can be turned on with low voltage, making possible to design the circuit with high reliance and compact in size.
  • the transistors and diodes are made of wideband gap semiconductors, various features, such as the breakdown voltage, the maximum allowable current density, heat resistivity and power loss can be improved. Thus, it is possible to reduce the size of the circuit. Also, the heat dissipation fin for the heat sink can be made small, yet maintaining the efficiency and reliability.
  • the present invention can be used in converters.
  • variable voltage generator 18 variable voltage generator

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  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

L'invention concerne un convertisseur clampé par le neutre, comprenant une source de tension continue (2), un premier et un second condensateur (C1, C2) connectés en série aux bornes de la source de tension continue et un circuit de commutation (20) connecté aux bornes de la source de tension continue pour convertir la tension continue en tension alternative. Le circuit de commutation possède une entrée neutre (Vc). Un montage en série composé d'une première et d'une seconde résistance (4, 6) est en outre connecté à la source de tension continue pour produire une tension neutre à une première jonction (Jc) entre les résistances. La tension neutre est comparée à une tension centrale au niveau d'une seconde jonction (Jf) entre les condensateurs afin d'obtenir une tension de déviation au niveau de la seconde jonction par rapport à la tension neutre. Ledit convertisseur comporte un générateur de tension variable (18) destiné à produire, en fonction du résultat de la comparaison, une tension variable qui représente la tension de déviation. La tension à la seconde jonction est additionnée de la tension variable produite et est ensuite appliquée à l'entrée neutre du circuit de commutation, afin de stabiliser le fonctionnement du circuit de commutation même en cas de déviation de la tension au niveau de la seconde jonction.
PCT/JP2011/067915 2011-01-06 2011-07-29 Convertisseur clampé par le neutre doté d'un générateur de tension variable afin de stabiliser la tension neutre WO2012093504A1 (fr)

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JP2013515440A JP2013539334A (ja) 2011-01-06 2011-07-29 中性点クランプ形コンバータ

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JP2011-000920 2011-01-06
JP2011000920 2011-01-06

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Cited By (3)

* Cited by examiner, † Cited by third party
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JP2014064431A (ja) * 2012-09-24 2014-04-10 Meidensha Corp マルチレベル電力変換装置
DE102018120236A1 (de) * 2018-08-20 2020-02-20 Thyssenkrupp Ag Ladevorrichtung mit steuerbarer Zwischenkreismittelpunktsspannung sowie Antriebssystem mit einer derartigen Ladevorrichtung

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CN103236792A (zh) * 2013-04-28 2013-08-07 北京索德电气工业有限公司 无损耗动态均压电路及电路控制方法
DE102018120236A1 (de) * 2018-08-20 2020-02-20 Thyssenkrupp Ag Ladevorrichtung mit steuerbarer Zwischenkreismittelpunktsspannung sowie Antriebssystem mit einer derartigen Ladevorrichtung
WO2020038747A1 (fr) 2018-08-20 2020-02-27 Thyssenkrupp Ag Dispositif de charge à tension de point médian de circuit intermédiaire contrôlable et système d'entraînement pourvu d'un tel dispositif de charge
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