WO2012090650A1 - Solar cell - Google Patents

Solar cell Download PDF

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Publication number
WO2012090650A1
WO2012090650A1 PCT/JP2011/078070 JP2011078070W WO2012090650A1 WO 2012090650 A1 WO2012090650 A1 WO 2012090650A1 JP 2011078070 W JP2011078070 W JP 2011078070W WO 2012090650 A1 WO2012090650 A1 WO 2012090650A1
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Prior art keywords
solar cell
side electrode
type
layer
amorphous semiconductor
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PCT/JP2011/078070
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French (fr)
Japanese (ja)
Inventor
豪 高濱
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三洋電機株式会社
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Publication of WO2012090650A1 publication Critical patent/WO2012090650A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/054—Optical elements directly associated or integrated with the PV cell, e.g. light-reflecting means or light-concentrating means
    • H01L31/056—Optical elements directly associated or integrated with the PV cell, e.g. light-reflecting means or light-concentrating means the light-reflecting means being of the back surface reflector [BSR] type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/52—PV systems with concentrators

Definitions

  • the present invention relates to a solar cell back junction type solar cell.
  • Patent Document 1 a so-called back junction type solar cell in which p-type and n-type semiconductor regions are arranged on the back side of the solar cell is known (for example, Patent Document 1 below).
  • this back junction solar cell it is not necessary to provide an electrode on the light receiving surface side. For this reason, in the back junction solar cell, the light receiving efficiency can be increased. Therefore, higher photoelectric conversion efficiency can be realized. In addition, the light receiving loss due to the wiring material can be reduced. Therefore, a solar cell module having a higher output can be provided.
  • the present invention has been made in view of such a point, and an object thereof is to provide a solar cell having improved photoelectric conversion efficiency.
  • the solar cell according to the present invention includes a solar cell substrate, a p-side electrode, an n-side electrode, and a reflective layer.
  • the solar cell substrate has a semiconductor substrate. A p-type surface and an n-type surface are exposed on one main surface of the solar cell substrate.
  • the p-side electrode is provided on the p-type surface.
  • the n-side electrode is provided on the n-type surface.
  • the reflective layer is provided so as to cover at least a part of a region where neither the p-side electrode nor the n-side electrode on one main surface of the solar cell substrate is provided.
  • a solar cell having improved photoelectric conversion efficiency can be provided.
  • FIG. 1 is a schematic plan view of the solar cell in the first embodiment.
  • FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG.
  • FIG. 3 is a flowchart showing the manufacturing process of the solar cell in the first embodiment.
  • FIG. 4 is a schematic cross-sectional view for explaining a manufacturing process of the solar cell in the first embodiment.
  • FIG. 5 is a schematic cross-sectional view for explaining a manufacturing process of the solar cell in the first embodiment.
  • FIG. 6 is a schematic cross-sectional view for explaining a manufacturing process of the solar cell in the first embodiment.
  • FIG. 7 is a schematic cross-sectional view for explaining the manufacturing process of the solar cell in the first embodiment.
  • FIG. 8 is a schematic cross-sectional view for explaining the manufacturing process of the solar cell in the first embodiment.
  • FIG. 9 is a schematic cross-sectional view for explaining the manufacturing process of the solar cell in the first embodiment.
  • FIG. 10 is a schematic cross-sectional view for explaining a manufacturing process of the solar cell in the first embodiment.
  • FIG. 11 is a schematic cross-sectional view for explaining the manufacturing process of the solar cell in the first embodiment.
  • FIG. 12 is a schematic cross-sectional view for explaining the manufacturing process of the solar cell in the first embodiment.
  • FIG. 13 is a schematic cross-sectional view of a solar cell in the second embodiment.
  • FIG. 14 is a schematic cross-sectional view of a solar cell in the third embodiment.
  • FIG. 15 is a schematic cross-sectional view of a solar cell in the fourth embodiment.
  • FIG. 16 is a schematic cross-sectional view of a solar cell in the fifth embodiment.
  • FIG. 17 is a schematic cross-sectional view of a solar cell in the sixth embodiment.
  • FIG. 18 is a schematic cross-sectional view of a solar cell in the seventh embodiment.
  • FIG. 19 is a schematic cross-sectional view of a solar cell in the eighth embodiment.
  • FIG. 20 is a schematic cross-sectional view of a solar cell according to the ninth embodiment.
  • FIG. 21 is a schematic cross-sectional view of a solar cell according to the tenth embodiment.
  • the solar cell 1 is a back junction solar cell.
  • the solar cell 1 may be used as a solar cell module in which a plurality of solar cells 1 are connected by a wiring material. .
  • the solar cell 1 includes a solar cell substrate 9.
  • the solar cell substrate 9 includes a semiconductor substrate 10.
  • the semiconductor substrate 10 has a light receiving surface 10a and a back surface 10b.
  • the semiconductor substrate 10 generates carriers by receiving the light 11 on the light receiving surface 10a.
  • the carriers are holes and electrons that are generated when light is absorbed by the semiconductor substrate 10.
  • the semiconductor substrate 10 is made of a crystalline semiconductor having n-type or p-type conductivity.
  • the crystalline semiconductor include crystalline silicon such as single crystal silicon and polycrystalline silicon.
  • the semiconductor substrate is not limited to a crystalline semiconductor substrate.
  • the semiconductor substrate may be made of a compound semiconductor made of, for example, GaAs or InP.
  • the semiconductor substrate 10 is composed of n-type single crystal silicon will be described.
  • an i-type amorphous semiconductor layer 17i made of an intrinsic amorphous semiconductor (hereinafter, the intrinsic semiconductor is referred to as an “i-type semiconductor”) is provided.
  • the i-type amorphous semiconductor layer 17i is specifically made of i-type amorphous silicon containing hydrogen.
  • the thickness of the i-type amorphous semiconductor layer 17i is not particularly limited as long as the thickness does not substantially contribute to power generation.
  • the thickness of the i-type amorphous semiconductor layer 17i can be, for example, about several to 250 inches.
  • amorphous semiconductor includes a microcrystalline semiconductor.
  • a microcrystalline semiconductor refers to a semiconductor having a large number of minute crystal grains.
  • the average particle diameter of the semiconductor crystal precipitated in the amorphous semiconductor is, for example, in the range of 1 nm to 50 nm.
  • the n-type amorphous semiconductor layer 17n having the same conductivity type as that of the semiconductor substrate 10 is provided on the i-type amorphous semiconductor layer 17i.
  • the n-type amorphous semiconductor layer 17n is an amorphous semiconductor layer to which an n-type dopant is added and has an n-type conductivity type.
  • the n-type amorphous semiconductor layer 17n is made of n-type amorphous silicon containing hydrogen.
  • the thickness of the n-type amorphous semiconductor layer 17n is not particularly limited. The thickness of the n-type amorphous semiconductor layer 17n can be, for example, about 20 to 500 mm.
  • an insulating layer 16 having both a function as an antireflection film and a function as a protective film is provided on the n-type amorphous semiconductor layer 17n.
  • the insulating layer 16 can be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like.
  • the thickness of the insulating layer 16 can be appropriately set according to the antireflection characteristics of the antireflection film to be applied.
  • the thickness of the insulating layer 16 can be set to, for example, about 80 nm to 1 ⁇ m.
  • the laminated structure of the i-type amorphous semiconductor layer 17i, the n-type amorphous semiconductor layer 17n, and the insulating layer 16 has a function as a passivation layer of the semiconductor substrate 10 and a function as an antireflection film.
  • the solar cell substrate 9 includes a p-type amorphous semiconductor layer 12p, an n-type amorphous semiconductor layer 13n, and an insulating layer 18 together with the semiconductor substrate 10, the semiconductor layers 17i and 17n, and the insulating layer 16.
  • the p-type amorphous semiconductor layer 12p has a p-type conductivity type different from that of the semiconductor substrate 10.
  • the p-type amorphous semiconductor layer 12p is made of p-type amorphous silicon containing hydrogen.
  • the thickness of the p-type amorphous semiconductor layer 12p is not particularly limited. The thickness of the p-type amorphous semiconductor layer 12p can be, for example, about 20 to 500 mm.
  • the p-type amorphous semiconductor layer 12 p is disposed on a part of the back surface 10 b of the semiconductor substrate 10.
  • the p-type semiconductor region is constituted by the p-type amorphous semiconductor layer 12p.
  • the p-type surface 12p1 is constituted by the surface of the p-type semiconductor region.
  • the i-type amorphous semiconductor layer 12i is made of i-type amorphous silicon containing hydrogen.
  • a reflective layer 40 is provided on the p-type amorphous semiconductor layer 12p.
  • the reflective layer 40 covers the p-type amorphous semiconductor layer 12p.
  • the reflective layer 40 is made of metal or alloy.
  • the reflective layer 40 is made of a metal selected from the group consisting of Ag, Al, Cu, Pt, Au, and Ti, or one or more metals selected from the group consisting of Ag, Al, Cu, Pt, Au, and Ti. It is preferable that it consists of material with high light reflectivity, such as an alloy containing.
  • the thickness of the reflective layer 40 is not particularly limited as long as the light reflectance of the reflective layer 40 becomes sufficiently high.
  • the reflective layer 40 is made of a metal or an alloy and therefore has conductivity.
  • the reflective layer is not necessarily required to have conductivity.
  • the reflective layer may not have conductivity.
  • the insulating layer 18 is provided on both end portions excluding the central portion in the direction x of the reflective layer 40. A central portion in the direction x of the reflective layer 40 is exposed from the insulating layer 18.
  • the width W3 in the direction x of the insulating layer 18 is not particularly limited, and can be, for example, about 1/3 of the width W1. Further, the interval W4 in the direction x between the insulating layers 18 is not particularly limited, and can be, for example, about 3 of the width W1.
  • the material of the insulating layer 18 is not particularly limited.
  • the insulating layer 18 can be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like. Especially, it is preferable that the insulating layer 18 is formed of silicon nitride.
  • the insulating layer 18 preferably contains hydrogen.
  • the n-type amorphous semiconductor layer 13n has the same n-type conductivity type as the semiconductor substrate 10.
  • the n-type amorphous semiconductor layer 13n is made of n-type amorphous silicon containing hydrogen.
  • the thickness of the n-type amorphous semiconductor layer 13n is not particularly limited. The thickness of the n-type amorphous semiconductor layer 13n can be, for example, about 20 to 500 mm.
  • the n-type amorphous semiconductor layer 13n is disposed on a part of the back surface 10b of the semiconductor substrate 10. Specifically, the n-type amorphous semiconductor layer 13n is provided from the portion of the back surface 10b exposed from the p-type amorphous semiconductor layer 12p to the end portion of the insulating layer 18. Therefore, both end portions in the x direction of the n-type amorphous semiconductor layer 13n overlap the p-type amorphous semiconductor layer 12p with the insulating layer 18 in the z direction.
  • an n-type semiconductor region is constituted by the n-type amorphous semiconductor layer 13n.
  • the n-type surface 13n1 is constituted by the surface of the n-type semiconductor region. For this reason, in this embodiment, the p-type surface 12p1 and the n-type surface 13n1 are exposed on one main surface of the solar cell substrate 9.
  • an i-type amorphous material having a thickness that does not substantially contribute to power generation, for example, about several to 250 inches.
  • a quality semiconductor layer 13i is provided.
  • the i-type amorphous semiconductor layer 13i is made of i-type amorphous silicon containing hydrogen.
  • the i-type amorphous semiconductor layer 13i and the i-type amorphous semiconductor layer 12i are not essential constituent elements.
  • the i-type semiconductor layer may not be provided between the semiconductor substrate and the n-type or p-type semiconductor layer.
  • the portions in contact with the back surface 10b of the p-type amorphous semiconductor layer 12p and the portions in contact with the back surface 10b of the n-type amorphous semiconductor layer 13n are alternately arranged in the x direction.
  • the p-type amorphous semiconductor layer 12p and the n-type amorphous semiconductor layer 13n adjacent in the x direction are in contact with each other. Therefore, substantially the entire back surface 10b is covered with the p-type amorphous semiconductor layer 12p and the n-type amorphous semiconductor layer 13n.
  • Each of the width W1 of the p-type amorphous semiconductor layer 12p and the interval W2 of the n-type amorphous semiconductor layer 13n can be, for example, about 100 ⁇ m to 1.5 mm.
  • the width W1 and the interval W2 may be equal to or different from each other, but the width W1 is preferably larger than the width W2.
  • the width W1 is preferably 1.1 times or more of the width W2, and more preferably 1.5 times or more.
  • n-side electrode 15 that collects electrons is provided on the n-type amorphous semiconductor layer 13n.
  • a p-side electrode 14 for collecting holes is provided on the p-type amorphous semiconductor layer 12p.
  • the reflective layer 40 is interposed between the p-type amorphous semiconductor layer 12p and the p-side electrode 14.
  • the present invention is not limited to this configuration.
  • the reflective layer 40 is provided so that a part of the p-type amorphous semiconductor layer 12p is exposed from the reflective layer 40, and the p-type amorphous semiconductor layer 12p and the p-side electrode 14 are in direct contact with each other. Good.
  • the p-side electrode 14 and the n-side electrode 15 are electrically insulated. Specifically, a gap is formed between the p-side electrode 14 and the n-side electrode 15 on the insulating layer 18 so that the p-side electrode 14 and the n-side electrode 15 are electrically insulated. Therefore, in the present embodiment, the region R where neither the p-side electrode nor the n-side electrode 14 or 15 is provided is present on one main surface of the solar cell substrate 9.
  • interval W5 between the n-side electrode 15 and the p-side electrode 14 on the insulating layer 18 can be, for example, about 1/3 of the width W3.
  • each of the n-side electrode 15 and the p-side electrode 14 is composed of a comb-like electrode including a bus bar and a plurality of fingers.
  • each of the n-side electrode 15 and the p-side electrode 14 is composed of only a plurality of fingers, and may be a so-called bus bar-less electrode that does not have a bus bar.
  • Each configuration of the n-side electrode 15 and the p-side electrode 14 is not particularly limited as long as it can collect carriers.
  • each of the n-side electrode 15 and the p-side electrode 14 is composed of a laminated body of first to fourth conductive layers 19a to 19d.
  • the first conductive layer 19a can be formed by, for example, TCO (Transparent Conductive Oxide) such as ITO (Indium Tin Oxide). Specifically, in the present embodiment, the first conductive layer 19a is made of ITO. The thickness of the first conductive layer 19a can be about 50 to 100 nm, for example.
  • the second to fourth conductive layers 19b to 19d can be formed of a metal or alloy such as Cu, for example. Specifically, in the present embodiment, each of the second and third conductive layers 19b and 19c is formed of Cu.
  • the fourth conductive layer 19d is made of Sn.
  • the thicknesses of the second to fourth conductive layers 19b to 19d can be set to, for example, about 50 nm to 1 ⁇ m, about 50 nm to 150 nm, about 10 ⁇ m to 20 ⁇ m, and about 1 ⁇ m to 5 ⁇ m, respectively.
  • the formation method of the first to fourth conductive layers 19a to 19d is not particularly limited, and can be formed by a thin film formation method such as a sputtering method or a CVD method, a plating method, or the like.
  • the first and second conductive layers 19a and 19b are films formed by a thin film forming method
  • the third and fourth conductive layers 19c and 19d are formed by a plating method. It is a membrane.
  • the reflective layer 40 is provided so as to cover at least a part of the region R in which neither the p-side electrode nor the n-side electrode 14, 15 on one main surface of the solar cell substrate 9 is provided. Yes. Specifically, the reflective layer 40 covers the entire region R. More specifically, the reflective layer 40 includes the region R, and is provided from the region where the p-side electrode 14 is disposed to the region where the n-side electrode 15 is disposed. The reflective layer 40 is electrically insulated from the n-side electrode 15 by the insulating layer 18.
  • the semiconductor substrate 10 is prepared.
  • step S1 the light receiving surface 10a and the back surface 10b of the semiconductor substrate 10 are cleaned.
  • the semiconductor substrate 10 can be cleaned using, for example, an HF aqueous solution.
  • step S1 it is preferable to form a texture structure on the light receiving surface 10a.
  • step S2 the i-type amorphous semiconductor layer 17i and the n-type amorphous semiconductor layer 17n are formed on the light receiving surface 10a of the semiconductor substrate 10, and the i-type amorphous semiconductor is formed on the back surface 10b.
  • the formation method of i-type amorphous semiconductor layers 17i and 21 and n-type amorphous semiconductor layers 17n and 22 is not particularly limited.
  • Each of the i-type amorphous semiconductor layers 17i and 21 and the n-type amorphous semiconductor layers 17n and 22 can be formed by, for example, a CVD (Chemical Vapor Deposition) method such as a plasma CVD method.
  • CVD Chemical Vapor Deposition
  • the reflective layer 40 is formed on the p-type amorphous semiconductor layer 22.
  • the reflective layer 40 can be formed by a film forming method such as a vapor deposition method or a sputtering method, for example.
  • the insulating layer 16 is formed on the n-type amorphous semiconductor layer 17n, and the insulating layer 23 is formed on the p-type amorphous semiconductor layer 22 including the reflective layer 40.
  • the formation method of the insulating layers 16 and 23 is not specifically limited.
  • the insulating layers 16 and 23 can be formed by, for example, a thin film forming method such as a sputtering method or a CVD method.
  • step S4 a part of the insulating layer 23 is removed by using an etching method or the like. Specifically, a portion of the insulating layer 23 located on a region where the n-type semiconductor layer is bonded to the semiconductor substrate 10 in a later step is removed.
  • the insulating layer 23 can be etched using an acidic etching solution such as an HF aqueous solution, for example, when the insulating layer 23 is made of silicon oxide, silicon nitride, or silicon oxynitride.
  • step S5 using the insulating layer 23 patterned in step S4 as a mask, the i-type amorphous semiconductor layer 21 and the p-type amorphous semiconductor layer 22 are etched using an alkaline etchant. As a result, portions of the i-type amorphous semiconductor layer 21 and the p-type amorphous semiconductor layer 22 other than the portions covered by the insulating layer 23 are removed. As a result, a portion of the back surface 10b where the insulating layer 23 is not located above is exposed, and the i-type amorphous semiconductor layer 12i and the p-type amorphous semiconductor layer 12p are separated from the semiconductor layers 21 and 22. Form.
  • the insulating layer 23 is made of silicon oxide, silicon nitride, or silicon oxynitride. For this reason, although the etching rate of the insulating layer 23 with an acidic etching solution is high, the etching rate of the insulating layer 23 with an alkaline etching solution is low.
  • the semiconductor layers 21 and 22 are made of amorphous silicon. For this reason, the semiconductor layers 21 and 22 have a low etching rate with an acidic etching solution and a high etching rate with an alkaline etching solution.
  • the insulating layer 23 is etched by the acidic etching solution used in step S4, the semiconductor layers 21 and 22 are not substantially etched.
  • the semiconductor layers 21 and 22 are etched by the alkaline etching solution used in step S5, but the insulating layer 23 is not substantially etched. Therefore, in step S4 and step S5, the insulating layer 23 or the semiconductor layers 21 and 22 can be selectively etched.
  • step S6 the i-type amorphous semiconductor layer 24 and the n-type amorphous semiconductor layer 25 are sequentially formed in this order so as to cover the back surface 10b.
  • a method for forming the amorphous semiconductor layers 24 and 25 is not particularly limited.
  • the amorphous semiconductor layers 24 and 25 can be formed by a thin film forming method such as a CVD method, for example.
  • step S7 a part of the portion located on the insulating layer 23 of the amorphous semiconductor layers 24 and 25 is etched. Thereby, the i-type amorphous semiconductor layer 13 i and the n-type amorphous semiconductor layer 13 n are formed from the amorphous semiconductor layers 24 and 25.
  • a first etchant having an etching rate for the amorphous semiconductor layers 24 and 25 higher than that for the insulating layer 23 is used. For this reason, the amorphous semiconductor layers 24 and 25 are selectively etched out of the insulating layer 23 and the amorphous semiconductor layers 24 and 25.
  • the first etching agent when the amorphous semiconductor layers 24 and 25 are made of silicon and the insulating layer 23 is made of silicon oxide, silicon nitride, or silicon oxynitride, for example, a NaOH aqueous solution containing NaOH, , Alkaline aqueous solution such as KOH aqueous solution containing KOH, mixed acid of nitric acid and ammonia, and the like.
  • the first etching agent is not necessarily a liquid, that is, an etching solution.
  • the first etchant may be a gas, for example. Specific examples of the etching gas preferably used as the first etching agent include a mixed gas of Cl 2 and He, XeF 2 gas, and the like.
  • the “etching solution” includes a pasty etching paste and an etching ink having a viscosity adjusted.
  • step S8 the insulating layer 23 is etched. Specifically, the insulating layer 23 is formed on the amorphous semiconductor layers 13i and 13p including the amorphous semiconductor layers 24 and 25 partially removed by the etching in step S7 using a second etching agent. The exposed part is removed by etching. Thereby, a contact hole is formed in the insulating layer 23 to expose the reflective layer 40, and the insulating layer 18 is formed from the insulating layer 23.
  • step S8 a second etching agent having an etching rate for the insulating layer 23 higher than that for the amorphous semiconductor layers 24 and 25 is used. For this reason, the insulating layer 23 is selectively etched among the insulating layer 23 and the amorphous semiconductor layers 24 and 25.
  • the second etching agent when the amorphous semiconductor layers 24 and 25 are made of silicon and the insulating layer 23 is made of silicon oxide, silicon nitride, or silicon oxynitride, for example, an HF aqueous solution containing HF, And acidic aqueous solution such as phosphoric acid aqueous solution.
  • the second etching agent is not necessarily a liquid, that is, an etching solution, like the first etching agent.
  • the second etchant may be a gas, for example.
  • Specific examples of the etching gas preferably used as the second etching agent include a mixed gas of SF 6 and He, a mixed gas of CF 4 , CHF 3 and He, and HF gas. Of these, an HF aqueous solution is preferably used as the second etching agent.
  • the oxide film on the electrode forming surface can also be removed before the electrode formation in step S9 described below.
  • step S9 by performing an electrode forming step of forming the n-side electrode 15 and the p-side electrode 14 on the p-type amorphous semiconductor layer 12p and the n-type amorphous semiconductor layer 13n, respectively,
  • the battery 1 can be completed.
  • the formation method of the n side electrode 15 and the p side electrode 14 can be suitably selected according to the material of an electrode.
  • the n-side electrode 15 and the p-side electrode 14 can be formed by, for example, selectively etching after forming the electrode layer 26 and the electrode portion 27 by CVD or sputtering.
  • the n-side electrode 15 and the p-side electrode 14 may be formed by forming the electrode portion 27 by a plating method after forming the patterned electrode layer 26.
  • the light that has reached the p-side or n-side electrode formed on the back surface is those Since it is reflected by the electrode, it does not substantially exit from the back surface.
  • the light that reaches the region where neither the p-side electrode nor the n-side electrode on the back surface is provided is emitted from the back surface and is not converted into electrical energy. Therefore, the photoelectric conversion efficiency is lowered by the amount of light emitted from the back surface.
  • the region R is covered with the reflective layer 40.
  • the light reaching the region R in which neither the p-side electrode 14 nor the n-side electrode 15 on the back surface 10b is provided is reflected to the light receiving surface 10a side by the reflective layer 40, so that the light reaching the region R Is prevented from exiting from the back surface 10b. Therefore, it is possible to reduce the light incident from the light receiving surface 10a and emitted from the back surface 10b. Therefore, since the utilization efficiency of incident light can be increased, improved photoelectric conversion efficiency can be realized.
  • the entire region R is covered with the reflective layer 40. For this reason, more improved photoelectric conversion efficiency can be realized.
  • the reflective layer 40 is selected from a metal selected from the group consisting of Ag, Al, Cu, Pt, Au and Ti, or from a group consisting of Ag, Al, Cu, Pt, Au and Ti. Further, it is made of a material having a high light reflectivity called an alloy containing one or more kinds of metals. Therefore, it can suppress more effectively that light radiate
  • the reflective layer 40 includes the region R, and is disposed from the region where the p-side electrode 14 is disposed on the back surface 10b to the region where the n-side electrode 15 is disposed. For this reason, even if the formation position of the reflective layer 40 is shifted, the region R is reliably covered with the reflective layer 40. Therefore, the solar cell 1 having improved photoelectric conversion efficiency can be stably manufactured at a high yield rate.
  • the reflective layer 40 and the n-side electrode 15 are electrically insulated by the insulating layer 18. For this reason, the fall of the photoelectric conversion efficiency resulting from a short circuit current flowing between the p side electrode 14 and the n side electrode 15 is suppressed.
  • FIG. 13 is a schematic cross-sectional view of a solar cell in the second embodiment.
  • FIG. 14 is a schematic cross-sectional view of a solar cell according to the third embodiment.
  • the position of the reflective layer 40 is not particularly limited as long as it is a position that covers at least a part of the region R.
  • the reflective layer 40 is disposed above the p-side electrode 14 and the n-side electrode 15.
  • an insulating layer 41 is provided on the p-side electrode 14 and the n-side electrode 15 so as to cover the entire region R and the p-side electrode 14 and the n-side electrode 15.
  • the reflective layer 40 is provided on the insulating layer 41.
  • the insulating layer 41 covers the region R and the entire p-side electrode 14 and n-side electrode 15.
  • the reflective layer 40 may be provided so as to cover the entire p-side electrode 14 and n-side electrode 15.
  • the insulating layer 41 is not particularly limited, but can be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like.
  • the reflective layer 40 is provided inside the insulating layer 18.
  • the end of the reflective layer 40 is exposed at the end face of the insulating layer 18, but the entire reflective layer 40 may be provided so as to be completely surrounded by the insulating layer 18.
  • the reflective layer 40 is formed, and then, A method of forming the remaining part of the insulating layer 18 is exemplified.
  • FIG. 15 is a schematic cross-sectional view of a solar cell in the fourth embodiment.
  • FIG. 16 is a schematic cross-sectional view of the solar cell in the fifth embodiment.
  • FIG. 17 is a schematic cross-sectional view of the solar cell in the sixth embodiment.
  • FIG. 18 is a schematic cross-sectional view of a solar cell in the seventh embodiment.
  • FIG. 19 is a schematic cross-sectional view of the solar cell in the eighth embodiment.
  • FIG. 20 is a schematic cross-sectional view of the solar cell in the ninth embodiment.
  • the p-type surface 12p1 is constituted by the surface of the p-type amorphous semiconductor layer 12p disposed on the n-type semiconductor substrate 10, and the n-type amorphous semiconductor layer 13n
  • the n-type surface 13n1 is configured by the surface has been described.
  • the present invention is not limited to this configuration.
  • the p-type dopant is thermally diffused into a part of the portion on the back surface 30b side of the n-type crystalline semiconductor substrate 30 to obtain a crystal.
  • a semiconductor region 31p that includes a p-type heat diffusion region and forms the p-type surface 12p1 may be formed on a part of the back surface 30b of the conductive semiconductor substrate 30.
  • the n-type surface 13n1 is composed of the n-type amorphous semiconductor layer 13n provided on the back surface 10b of the semiconductor substrate 10.
  • a semiconductor region 31n which is formed of an n-type thermal diffusion region on a part of the back surface 30b of the crystalline semiconductor substrate 30 and constitutes the n-type surface 13n1, is formed. Further, it may be formed. That is, both the p-type surface 12p1 and the n-type surface 13n1 may be configured by a thermal diffusion region.
  • the reflective layer 40 is disposed immediately above the p-type semiconductor region, as in the first embodiment. .
  • a reflective layer 40 is disposed on the layer 41. The reflective layer 40 covers the region R and the entire p-side electrode 14 and n-side electrode 15.
  • the reflective layer 40 is formed inside the insulating layer 18 as in the third embodiment.
  • FIG. 21 is a schematic cross-sectional view of a solar cell according to the tenth embodiment.
  • the example in which the insulating layer 41 is provided under the reflective layer 40 has been described.
  • the reflective layer 40 has an insulating property, as shown in FIG. It may be provided.
  • the step of forming the insulating layer 41 is not necessary, and the reflective layer 40 can be easily formed by, for example, coating. Therefore, manufacture of the solar cell 1 becomes easy.
  • the reflective layer 40 having insulating properties is not particularly limited, but can be formed of, for example, a white resin composition.
  • a white resin composition include an ethylene / vinyl acetate copolymer (EVA) containing titanium oxide fine particles.

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Abstract

The purpose of the present invention is to provide a solar cell having improved photoelectric conversion efficiency. This solar cell (1) is provided with a solar cell substrate (9), p-side electrode (14), n-side electrode (15), and reflective layer (40). The solar cell substrate (9) has a semiconductor substrate (10), and a p-type surface (12p1) and an n-type surface (13n1) are exposed on one main surface of the solar cell substrate (9). In addition, a p-side electrode (14) is provided on the p-type surface (12p1), and an n-side electrode (15) is provided on the n-type surface (13n1). The reflective layer (40) is provided so as to at least cover at least part of a region (R) on which neither the p-side nor n-side electrode (14, 15) is provided on the one main surface of the solar cell substrate (9). By forming this constitution, light that reaches the region (R) is reflected to the light receiving surface (10a) side by the reflective layer (40); therefore, the utilization efficiency of the incoming light is increased by the light reaching the region (R) being prevented from exiting the back surface (10b).

Description

太陽電池Solar cell
　本発明は、太陽電池裏面接合型の太陽電池に関する。 The present invention relates to a solar cell back junction type solar cell.
　従来、太陽電池の裏面側にｐ型及びｎ型の半導体領域が配されている所謂裏面接合型の太陽電池が知られている（例えば、下記の特許文献１）。この裏面接合型の太陽電池では、受光面側に電極を設ける必要がない。このため、裏面接合型の太陽電池では、光の受光効率を高めることができる。従って、より高い光電変換効率を実現し得る。また、配線材による受光ロスを減らすことができる。従って、より高い出力を有する太陽電池モジュールを提供することができる。 Conventionally, a so-called back junction type solar cell in which p-type and n-type semiconductor regions are arranged on the back side of the solar cell is known (for example, Patent Document 1 below). In this back junction solar cell, it is not necessary to provide an electrode on the light receiving surface side. For this reason, in the back junction solar cell, the light receiving efficiency can be increased. Therefore, higher photoelectric conversion efficiency can be realized. In addition, the light receiving loss due to the wiring material can be reduced. Therefore, a solar cell module having a higher output can be provided.
特開２０１０－８０８８７号公報JP 2010-80887 A
　近年、太陽電池に求められる光電変換効率がさらに高くなってきている。このため、裏面接合型の太陽電池の光電変換効率をさらに高めたいという要望が高まってきている。 In recent years, the photoelectric conversion efficiency required for solar cells has been further increased. For this reason, there is an increasing demand to further increase the photoelectric conversion efficiency of back junction solar cells.
　本発明は、斯かる点に鑑みてなされたものであり、その目的は、改善された光電変換効率を有する太陽電池を提供することにある。 The present invention has been made in view of such a point, and an object thereof is to provide a solar cell having improved photoelectric conversion efficiency.
　本発明に係る太陽電池は、太陽電池基板と、ｐ側電極と、ｎ側電極と、反射層とを備えている。太陽電池基板は、半導体基板を有する。太陽電池基板の一主面には、ｐ型表面及びｎ型表面が露出している。ｐ側電極は、ｐ型表面の上に設けられている。ｎ側電極は、ｎ型表面の上に設けられている。反射層は、太陽電池基板の一主面のｐ側及びｎ側電極のいずれもが設けられていない領域の少なくとも一部を少なくとも覆うように設けられている。 The solar cell according to the present invention includes a solar cell substrate, a p-side electrode, an n-side electrode, and a reflective layer. The solar cell substrate has a semiconductor substrate. A p-type surface and an n-type surface are exposed on one main surface of the solar cell substrate. The p-side electrode is provided on the p-type surface. The n-side electrode is provided on the n-type surface. The reflective layer is provided so as to cover at least a part of a region where neither the p-side electrode nor the n-side electrode on one main surface of the solar cell substrate is provided.
　本発明によれば、改善された光電変換効率を有する太陽電池を提供することができる。 According to the present invention, a solar cell having improved photoelectric conversion efficiency can be provided.
図１は、第１の実施形態における太陽電池の略図的平面図である。FIG. 1 is a schematic plan view of the solar cell in the first embodiment. 図２は、図１の線ＩＩ－ＩＩにおける略図的断面図である。FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. 図３は、第１の実施形態における太陽電池の製造工程を表すフローチャートである。FIG. 3 is a flowchart showing the manufacturing process of the solar cell in the first embodiment. 図４は、第１の実施形態における太陽電池の製造工程を説明するための略図的断面図である。FIG. 4 is a schematic cross-sectional view for explaining a manufacturing process of the solar cell in the first embodiment. 図５は、第１の実施形態における太陽電池の製造工程を説明するための略図的断面図である。FIG. 5 is a schematic cross-sectional view for explaining a manufacturing process of the solar cell in the first embodiment. 図６は、第１の実施形態における太陽電池の製造工程を説明するための略図的断面図である。FIG. 6 is a schematic cross-sectional view for explaining a manufacturing process of the solar cell in the first embodiment. 図７は、第１の実施形態における太陽電池の製造工程を説明するための略図的断面図である。FIG. 7 is a schematic cross-sectional view for explaining the manufacturing process of the solar cell in the first embodiment. 図８は、第１の実施形態における太陽電池の製造工程を説明するための略図的断面図である。FIG. 8 is a schematic cross-sectional view for explaining the manufacturing process of the solar cell in the first embodiment. 図９は、第１の実施形態における太陽電池の製造工程を説明するための略図的断面図である。FIG. 9 is a schematic cross-sectional view for explaining the manufacturing process of the solar cell in the first embodiment. 図１０は、第１の実施形態における太陽電池の製造工程を説明するための略図的断面図である。FIG. 10 is a schematic cross-sectional view for explaining a manufacturing process of the solar cell in the first embodiment. 図１１は、第１の実施形態における太陽電池の製造工程を説明するための略図的断面図である。FIG. 11 is a schematic cross-sectional view for explaining the manufacturing process of the solar cell in the first embodiment. 図１２は、第１の実施形態における太陽電池の製造工程を説明するための略図的断面図である。FIG. 12 is a schematic cross-sectional view for explaining the manufacturing process of the solar cell in the first embodiment. 図１３は、第２の実施形態における太陽電池の略図的断面図である。FIG. 13 is a schematic cross-sectional view of a solar cell in the second embodiment. 図１４は、第３の実施形態における太陽電池の略図的断面図である。FIG. 14 is a schematic cross-sectional view of a solar cell in the third embodiment. 図１５は、第４の実施形態における太陽電池の略図的断面図である。FIG. 15 is a schematic cross-sectional view of a solar cell in the fourth embodiment. 図１６は、第５の実施形態における太陽電池の略図的断面図である。FIG. 16 is a schematic cross-sectional view of a solar cell in the fifth embodiment. 図１７は、第６の実施形態における太陽電池の略図的断面図である。FIG. 17 is a schematic cross-sectional view of a solar cell in the sixth embodiment. 図１８は、第７の実施形態における太陽電池の略図的断面図である。FIG. 18 is a schematic cross-sectional view of a solar cell in the seventh embodiment. 図１９は、第８の実施形態における太陽電池の略図的断面図である。FIG. 19 is a schematic cross-sectional view of a solar cell in the eighth embodiment. 図２０は、第９の実施形態における太陽電池の略図的断面図である。FIG. 20 is a schematic cross-sectional view of a solar cell according to the ninth embodiment. 図２１は、第１０の実施形態における太陽電池の略図的断面図の図である。FIG. 21 is a schematic cross-sectional view of a solar cell according to the tenth embodiment.
　以下、本発明の好ましい実施形態の一例について説明する。但し、下記の実施形態は、単なる一例である。本発明は、下記の実施形態に何ら限定されない。 Hereinafter, an example of a preferred embodiment of the present invention will be described. However, the following embodiment is merely an example. The present invention is not limited to the following embodiments.
　また、実施形態等において参照する各図面において、実質的に同一の機能を有する部材は同一の符号で参照することとする。また、実施形態等において参照する図面は、模式的に記載されたものであり、図面に描画された物体の寸法の比率などは、現実の物体の寸法の比率などとは異なる場合がある。図面相互間においても、物体の寸法比率等が異なる場合がある。具体的な物体の寸法比率等は、以下の説明を参酌して判断されるべきである。 In each drawing referred to in the embodiment and the like, members having substantially the same function are referred to by the same reference numerals. The drawings referred to in the embodiments and the like are schematically described, and the ratio of the dimensions of the objects drawn in the drawings may be different from the ratio of the dimensions of the actual objects. The dimensional ratio of the object may be different between the drawings. The specific dimensional ratio of the object should be determined in consideration of the following description.
　《第１の実施形態》
　（太陽電池１の構成）
　まず、本実施形態に係る太陽電池１の構成について、図１及び図２を参照しながら詳細に説明する。 << First Embodiment >>
(Configuration of solar cell 1)
First, the configuration of the solar cell 1 according to the present embodiment will be described in detail with reference to FIGS. 1 and 2.
　太陽電池１は、裏面接合型の太陽電池である。なお、本実施形態の太陽電池１単体では、十分に大きな出力が得られない場合は、太陽電池１は、複数の太陽電池１が配線材により接続された太陽電池モジュールとして利用されることもある。 The solar cell 1 is a back junction solar cell. In addition, when the solar cell 1 of this embodiment alone cannot obtain a sufficiently large output, the solar cell 1 may be used as a solar cell module in which a plurality of solar cells 1 are connected by a wiring material. .
　太陽電池１は、太陽電池基板９を備えている。太陽電池基板９は、半導体基板１０を備えている。半導体基板１０は、受光面１０ａと、裏面１０ｂとを有する。半導体基板１０は、受光面１０ａにおいて、光１１を受光することによってキャリアを生成する。ここで、キャリアとは、光が半導体基板１０に吸収されることにより生成される正孔及び電子のことである。 The solar cell 1 includes a solar cell substrate 9. The solar cell substrate 9 includes a semiconductor substrate 10. The semiconductor substrate 10 has a light receiving surface 10a and a back surface 10b. The semiconductor substrate 10 generates carriers by receiving the light 11 on the light receiving surface 10a. Here, the carriers are holes and electrons that are generated when light is absorbed by the semiconductor substrate 10.
　半導体基板１０は、ｎ型またはｐ型の導電型を有する結晶性半導体により構成されている。結晶性半導体の具体例としては、例えば、単結晶シリコン、多結晶シリコンなどの結晶シリコンが挙げられる。もっとも、本発明においては、半導体基板は、結晶性半導体基板に限定されない。本発明においては、半導体基板は、例えば、ＧａＡｓやＩｎＰなどからなる化合物半導体などから構成されてもよい。以下、本実施形態では、半導体基板１０がｎ型の単結晶シリコンにより構成されている例について説明する。 The semiconductor substrate 10 is made of a crystalline semiconductor having n-type or p-type conductivity. Specific examples of the crystalline semiconductor include crystalline silicon such as single crystal silicon and polycrystalline silicon. However, in the present invention, the semiconductor substrate is not limited to a crystalline semiconductor substrate. In the present invention, the semiconductor substrate may be made of a compound semiconductor made of, for example, GaAs or InP. Hereinafter, in the present embodiment, an example in which the semiconductor substrate 10 is composed of n-type single crystal silicon will be described.
　半導体基板１０の受光面１０ａの上には、真性な非晶質半導体（以下、真性な半導体を「ｉ型半導体」とする。）からなるｉ型非晶質半導体層１７ｉが設けられている。本実施形態においては、ｉ型非晶質半導体層１７ｉは、具体的には、水素を含むｉ型のアモルファスシリコンからなる。ｉ型非晶質半導体層１７ｉの厚みは、発電に実質的に寄与しない程度の厚みである限りにおいて特に限定されない。ｉ型非晶質半導体層１７ｉの厚みは、例えば、数Å～２５０Å程度とすることができる。 On the light receiving surface 10a of the semiconductor substrate 10, an i-type amorphous semiconductor layer 17i made of an intrinsic amorphous semiconductor (hereinafter, the intrinsic semiconductor is referred to as an “i-type semiconductor”) is provided. In the present embodiment, the i-type amorphous semiconductor layer 17i is specifically made of i-type amorphous silicon containing hydrogen. The thickness of the i-type amorphous semiconductor layer 17i is not particularly limited as long as the thickness does not substantially contribute to power generation. The thickness of the i-type amorphous semiconductor layer 17i can be, for example, about several to 250 inches.
　なお、本発明において、「非晶質半導体」には、微結晶半導体を含むものとする。微結晶半導体とは、多数の微小な結晶粒を有する半導体をいう。非晶質半導体中に析出している半導体結晶の平均粒子径は、例えば１ｎｍ～５０ｎｍの範囲内である。 In the present invention, “amorphous semiconductor” includes a microcrystalline semiconductor. A microcrystalline semiconductor refers to a semiconductor having a large number of minute crystal grains. The average particle diameter of the semiconductor crystal precipitated in the amorphous semiconductor is, for example, in the range of 1 nm to 50 nm.
　ｉ型非晶質半導体層１７ｉの上には、半導体基板１０と同じ導電型を有するｎ型非晶質半導体層１７ｎが設けられている。ｎ型非晶質半導体層１７ｎは、ｎ型のドーパントが添加されており、ｎ型の導電型を有する非晶質半導体層である。具体的には、本実施形態では、ｎ型非晶質半導体層１７ｎは、水素を含むｎ型アモルファスシリコンからなる。ｎ型非晶質半導体層１７ｎの厚みは、特に限定されない。ｎ型非晶質半導体層１７ｎの厚みは、例えば、２０Å～５００Å程度とすることができる。 An n-type amorphous semiconductor layer 17n having the same conductivity type as that of the semiconductor substrate 10 is provided on the i-type amorphous semiconductor layer 17i. The n-type amorphous semiconductor layer 17n is an amorphous semiconductor layer to which an n-type dopant is added and has an n-type conductivity type. Specifically, in the present embodiment, the n-type amorphous semiconductor layer 17n is made of n-type amorphous silicon containing hydrogen. The thickness of the n-type amorphous semiconductor layer 17n is not particularly limited. The thickness of the n-type amorphous semiconductor layer 17n can be, for example, about 20 to 500 mm.
　ｎ型非晶質半導体層１７ｎの上には、反射防止膜としての機能と保護膜としての機能とを兼ね備えた絶縁層１６が設けられている。絶縁層１６は、例えば、酸化ケイ素、窒化ケイ素、酸窒化ケイ素などにより形成することができる。絶縁層１６の厚みは、付与しようとする反射防止膜の反射防止特性などに応じて適宜設定することができる。絶縁層１６の厚みは、例えば８０ｎｍ～１μｍ程度とすることができる。 On the n-type amorphous semiconductor layer 17n, an insulating layer 16 having both a function as an antireflection film and a function as a protective film is provided. The insulating layer 16 can be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like. The thickness of the insulating layer 16 can be appropriately set according to the antireflection characteristics of the antireflection film to be applied. The thickness of the insulating layer 16 can be set to, for example, about 80 nm to 1 μm.
　上記のｉ型非晶質半導体層１７ｉ、ｎ型非晶質半導体層１７ｎ及び絶縁層１６の積層構造は、半導体基板１０のパッシベーション層としての機能及び反射防止膜としての機能を有する。 The laminated structure of the i-type amorphous semiconductor layer 17i, the n-type amorphous semiconductor layer 17n, and the insulating layer 16 has a function as a passivation layer of the semiconductor substrate 10 and a function as an antireflection film.
　太陽電池基板９は、上記半導体基板１０、半導体層１７ｉ、１７ｎ及び絶縁層１６と共に、ｐ型非晶質半導体層１２ｐ、ｎ型非晶質半導体層１３ｎ及び絶縁層１８を備えている。 The solar cell substrate 9 includes a p-type amorphous semiconductor layer 12p, an n-type amorphous semiconductor layer 13n, and an insulating layer 18 together with the semiconductor substrate 10, the semiconductor layers 17i and 17n, and the insulating layer 16.
　ｐ型非晶質半導体層１２ｐは、ｐ型のドーパントが添加されている。このため、ｐ型非晶質半導体層１２ｐは、半導体基板１０とは異なるｐ型の導電型を有する。具体的には、本実施形態では、ｐ型非晶質半導体層１２ｐは、水素を含むｐ型のアモルファスシリコンからなる。ｐ型非晶質半導体層１２ｐの厚みは、特に限定されない。ｐ型非晶質半導体層１２ｐの厚みは、例えば、２０Å～５００Å程度とすることができる。 A p-type dopant is added to the p-type amorphous semiconductor layer 12p. For this reason, the p-type amorphous semiconductor layer 12 p has a p-type conductivity type different from that of the semiconductor substrate 10. Specifically, in this embodiment, the p-type amorphous semiconductor layer 12p is made of p-type amorphous silicon containing hydrogen. The thickness of the p-type amorphous semiconductor layer 12p is not particularly limited. The thickness of the p-type amorphous semiconductor layer 12p can be, for example, about 20 to 500 mm.
　ｐ型非晶質半導体層１２ｐは、半導体基板１０の裏面１０ｂの一部の上に配されている。本実施形態では、このｐ型非晶質半導体層１２ｐによりｐ型半導体領域が構成されている。そして、このｐ型半導体領域の表面によりｐ型表面１２ｐ１が構成されている。 The p-type amorphous semiconductor layer 12 p is disposed on a part of the back surface 10 b of the semiconductor substrate 10. In the present embodiment, the p-type semiconductor region is constituted by the p-type amorphous semiconductor layer 12p. The p-type surface 12p1 is constituted by the surface of the p-type semiconductor region.
　本実施形態では、ｐ型非晶質半導体層１２ｐと裏面１０ｂとの間には、例えば数Å～２５０Å程度の、発電に実質的に寄与しない程度の厚みのｉ型非晶質半導体層１２ｉが設けられている。本実施形態では、ｉ型非晶質半導体層１２ｉは、水素を含むｉ型のアモルファスシリコンからなる。このｉ型非晶質半導体層１２ｉを設けることにより、キャリアの再結合を一層抑制することができる。 In the present embodiment, an i-type amorphous semiconductor layer 12i having a thickness that does not substantially contribute to power generation, for example, about several to 250 inches, is formed between the p-type amorphous semiconductor layer 12p and the back surface 10b. Is provided. In the present embodiment, the i-type amorphous semiconductor layer 12i is made of i-type amorphous silicon containing hydrogen. By providing the i-type amorphous semiconductor layer 12i, carrier recombination can be further suppressed.
　ｐ型非晶質半導体層１２ｐの上には、反射層４０が設けられている。本実施形態では、この反射層４０により、ｐ型非晶質半導体層１２ｐが覆われている。 A reflective layer 40 is provided on the p-type amorphous semiconductor layer 12p. In the present embodiment, the reflective layer 40 covers the p-type amorphous semiconductor layer 12p.
　反射層４０は、金属または合金からなる。反射層４０は、Ａｇ，Ａｌ，Ｃｕ，Ｐｔ，Ａｕ及びＴｉからなる群から選ばれた金属、またはＡｇ，Ａｌ，Ｃｕ，Ｐｔ，Ａｕ及びＴｉからなる群から選ばれた１種以上の金属を含む合金などの光反射率が高い材料からなることが好ましい。 The reflective layer 40 is made of metal or alloy. The reflective layer 40 is made of a metal selected from the group consisting of Ag, Al, Cu, Pt, Au, and Ti, or one or more metals selected from the group consisting of Ag, Al, Cu, Pt, Au, and Ti. It is preferable that it consists of material with high light reflectivity, such as an alloy containing.
　反射層４０の厚みは、反射層４０の光反射率が十分に高くなる限りにおいて、特に限定されない。 The thickness of the reflective layer 40 is not particularly limited as long as the light reflectance of the reflective layer 40 becomes sufficiently high.
　なお、本実施形態では、反射層４０は、金属または合金からなるので、導電性を有している。但し、本発明において、反射層が導電性を有している必要は必ずしもない。例えば、反射層が半導体層と電極との間に介在していない場合は、反射層は、導電性を有していなくてもよい。 In the present embodiment, the reflective layer 40 is made of a metal or an alloy and therefore has conductivity. However, in the present invention, the reflective layer is not necessarily required to have conductivity. For example, when the reflective layer is not interposed between the semiconductor layer and the electrode, the reflective layer may not have conductivity.
　反射層４０の方向ｘにおける中央部を除く両端部の上には、絶縁層１８が設けられている。反射層４０の方向ｘにおける中央部は、絶縁層１８から露出している。絶縁層１８の方向ｘにおける幅Ｗ３は特に限定されず、例えば、幅Ｗ１の約１／３程度とすることができる。また、絶縁層１８間の方向ｘにおける間隔Ｗ４も特に限定されず、例えば、幅Ｗ１の約１／３程度とすることができる。 The insulating layer 18 is provided on both end portions excluding the central portion in the direction x of the reflective layer 40. A central portion in the direction x of the reflective layer 40 is exposed from the insulating layer 18. The width W3 in the direction x of the insulating layer 18 is not particularly limited, and can be, for example, about 1/3 of the width W1. Further, the interval W4 in the direction x between the insulating layers 18 is not particularly limited, and can be, for example, about ３ of the width W1.
　絶縁層１８の材質は、特に限定されない。絶縁層１８は、例えば、酸化ケイ素、窒化ケイ素、酸窒化ケイ素などにより形成することができる。なかでも、絶縁層１８は、窒化ケイ素により形成されていることが好ましい。また、絶縁層１８は、水素を含んでいることが好ましい。 The material of the insulating layer 18 is not particularly limited. The insulating layer 18 can be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like. Especially, it is preferable that the insulating layer 18 is formed of silicon nitride. The insulating layer 18 preferably contains hydrogen.
　ｎ型非晶質半導体層１３ｎには、ｎ型のドーパントが添加されている。このため、ｎ型非晶質半導体層１３ｎは、半導体基板１０と同じｎ型の導電型を有する。具体的には、本実施形態では、ｎ型非晶質半導体層１３ｎは、水素を含むｎ型アモルファスシリコンからなる。ｎ型非晶質半導体層１３ｎの厚みは、特に限定されない。ｎ型非晶質半導体層１３ｎの厚みは、例えば、２０Å～５００Å程度とすることができる。 An n-type dopant is added to the n-type amorphous semiconductor layer 13n. For this reason, the n-type amorphous semiconductor layer 13 n has the same n-type conductivity type as the semiconductor substrate 10. Specifically, in the present embodiment, the n-type amorphous semiconductor layer 13n is made of n-type amorphous silicon containing hydrogen. The thickness of the n-type amorphous semiconductor layer 13n is not particularly limited. The thickness of the n-type amorphous semiconductor layer 13n can be, for example, about 20 to 500 mm.
　ｎ型非晶質半導体層１３ｎは、半導体基板１０の裏面１０ｂの一部の上に配されている。詳細には、ｎ型非晶質半導体層１３ｎは、裏面１０ｂのｐ型非晶質半導体層１２ｐから露出した部分上から絶縁層１８の端部上に跨って設けられている。このため、ｎ型非晶質半導体層１３ｎのｘ方向における両端部は、ｐ型非晶質半導体層１２ｐと、絶縁層１８を介してｚ方向に重なっている。 The n-type amorphous semiconductor layer 13n is disposed on a part of the back surface 10b of the semiconductor substrate 10. Specifically, the n-type amorphous semiconductor layer 13n is provided from the portion of the back surface 10b exposed from the p-type amorphous semiconductor layer 12p to the end portion of the insulating layer 18. Therefore, both end portions in the x direction of the n-type amorphous semiconductor layer 13n overlap the p-type amorphous semiconductor layer 12p with the insulating layer 18 in the z direction.
　本実施形態では、このｎ型非晶質半導体層１３ｎによりｎ型半導体領域が構成されている。そして、このｎ型半導体領域の表面によりｎ型表面１３ｎ１が構成されている。このため、本実施形態では、太陽電池基板９の一主面にｐ型表面１２ｐ１及びｎ型表面１３ｎ１が露出している。 In the present embodiment, an n-type semiconductor region is constituted by the n-type amorphous semiconductor layer 13n. The n-type surface 13n1 is constituted by the surface of the n-type semiconductor region. For this reason, in this embodiment, the p-type surface 12p1 and the n-type surface 13n1 are exposed on one main surface of the solar cell substrate 9.
　本実施形態では、ｎ型非晶質半導体層１３ｎと、裏面１０ｂ及び絶縁層１８との間には、例えば数Å～２５０Å程度の、発電に実質的に寄与しない程度の厚みのｉ型非晶質半導体層１３ｉが設けられている。本実施形態では、ｉ型非晶質半導体層１３ｉは、水素を含むｉ型のアモルファスシリコンからなる。このｉ型非晶質半導体層１３ｉを設けることにより、キャリアの再結合を一層抑制することができる。 In this embodiment, between the n-type amorphous semiconductor layer 13n and the back surface 10b and the insulating layer 18, an i-type amorphous material having a thickness that does not substantially contribute to power generation, for example, about several to 250 inches. A quality semiconductor layer 13i is provided. In the present embodiment, the i-type amorphous semiconductor layer 13i is made of i-type amorphous silicon containing hydrogen. By providing the i-type amorphous semiconductor layer 13i, carrier recombination can be further suppressed.
　なお、本発明において、このｉ型非晶質半導体層１３ｉ及び上記ｉ型非晶質半導体層１２ｉは必須の構成要件ではない。本発明においては、半導体基板とｎ型またはｐ型の半導体層との間に、ｉ型の半導体層が設けられていなくてもよい。 In the present invention, the i-type amorphous semiconductor layer 13i and the i-type amorphous semiconductor layer 12i are not essential constituent elements. In the present invention, the i-type semiconductor layer may not be provided between the semiconductor substrate and the n-type or p-type semiconductor layer.
　本実施形態では、ｐ型非晶質半導体層１２ｐの裏面１０ｂと接触している部分と、ｎ型非晶質半導体層１３ｎの裏面１０ｂと接触している部分とは、ｘ方向に交互に配列されている。ｘ方向において隣り合うｐ型非晶質半導体層１２ｐとｎ型非晶質半導体層１３ｎとは、互いに接触している。従って、ｐ型非晶質半導体層１２ｐとｎ型非晶質半導体層１３ｎとによって裏面１０ｂの実質的に全体が被覆されている。 In the present embodiment, the portions in contact with the back surface 10b of the p-type amorphous semiconductor layer 12p and the portions in contact with the back surface 10b of the n-type amorphous semiconductor layer 13n are alternately arranged in the x direction. Has been. The p-type amorphous semiconductor layer 12p and the n-type amorphous semiconductor layer 13n adjacent in the x direction are in contact with each other. Therefore, substantially the entire back surface 10b is covered with the p-type amorphous semiconductor layer 12p and the n-type amorphous semiconductor layer 13n.
　ｐ型非晶質半導体層１２ｐの幅Ｗ１と、ｎ型非晶質半導体層１３ｎの間隔Ｗ２とのそれぞれは、例えば、１００μｍ～１．５ｍｍ程度とすることができる。幅Ｗ１と間隔Ｗ２とは、互いに等しくてもよいし、異なっていてもよいが、幅Ｗ１が幅Ｗ２よりも大きいことが好ましい。具体的には、幅Ｗ１は、幅Ｗ２の１．１倍以上であることが好ましく、１．５倍以上であることがより好ましい。 Each of the width W1 of the p-type amorphous semiconductor layer 12p and the interval W2 of the n-type amorphous semiconductor layer 13n can be, for example, about 100 μm to 1.5 mm. The width W1 and the interval W2 may be equal to or different from each other, but the width W1 is preferably larger than the width W2. Specifically, the width W1 is preferably 1.1 times or more of the width W2, and more preferably 1.5 times or more.
　ｎ型非晶質半導体層１３ｎの上には、電子を収集するｎ側電極１５が設けられている。一方、ｐ型非晶質半導体層１２ｐの上には、正孔を収集するｐ側電極１４が設けられている。なお、ｐ型非晶質半導体層１２ｐとｐ側電極１４との間には、上記反射層４０が介在している。但し、本発明は、この構成に限定されない。例えば、反射層４０からｐ型非晶質半導体層１２ｐの一部が露出するように反射層４０を設け、ｐ型非晶質半導体層１２ｐとｐ側電極１４とが直接接触するようにしてもよい。 An n-side electrode 15 that collects electrons is provided on the n-type amorphous semiconductor layer 13n. On the other hand, a p-side electrode 14 for collecting holes is provided on the p-type amorphous semiconductor layer 12p. The reflective layer 40 is interposed between the p-type amorphous semiconductor layer 12p and the p-side electrode 14. However, the present invention is not limited to this configuration. For example, the reflective layer 40 is provided so that a part of the p-type amorphous semiconductor layer 12p is exposed from the reflective layer 40, and the p-type amorphous semiconductor layer 12p and the p-side electrode 14 are in direct contact with each other. Good.
　ｐ側電極１４とｎ側電極１５とは、電気的に絶縁されている。具体的には、絶縁層１８上でｐ側電極１４とｎ側電極１５との間にギャップが形成されることによって、ｐ側電極１４とｎ側電極１５とが電気的に絶縁されている。従って、本実施形態では、太陽電池基板９の一主面には、ｐ側及びｎ側電極１４，１５のいずれもが設けられていない領域Ｒが存在している。 The p-side electrode 14 and the n-side electrode 15 are electrically insulated. Specifically, a gap is formed between the p-side electrode 14 and the n-side electrode 15 on the insulating layer 18 so that the p-side electrode 14 and the n-side electrode 15 are electrically insulated. Therefore, in the present embodiment, the region R where neither the p-side electrode nor the n- side electrode 14 or 15 is provided is present on one main surface of the solar cell substrate 9.
　なお、絶縁層１８の上におけるｎ側電極１５とｐ側電極１４との間の間隔Ｗ５は、例えば、幅Ｗ３の１／３程度とすることができる。 Note that the interval W5 between the n-side electrode 15 and the p-side electrode 14 on the insulating layer 18 can be, for example, about 1/3 of the width W3.
　本実施形態においては、ｎ側電極１５及びｐ側電極１４のそれぞれは、バスバー及び複数のフィンガーを含むくし歯状電極により構成されている。もっとも、ｎ側電極１５及びｐ側電極１４のそれぞれは、複数のフィンガーのみにより構成されており、バスバーを有さない所謂バスバーレス型の電極であってもよい。 In the present embodiment, each of the n-side electrode 15 and the p-side electrode 14 is composed of a comb-like electrode including a bus bar and a plurality of fingers. However, each of the n-side electrode 15 and the p-side electrode 14 is composed of only a plurality of fingers, and may be a so-called bus bar-less electrode that does not have a bus bar.
　ｎ側電極１５及びｐ側電極１４のそれぞれの構成は、キャリアを収集できるものである限りにおいて特に限定されない。本実施形態においては、ｎ側電極１５とｐ側電極１４とのそれぞれは、第１～第４の導電層１９ａ～１９ｄの積層体により構成されている。 Each configuration of the n-side electrode 15 and the p-side electrode 14 is not particularly limited as long as it can collect carriers. In the present embodiment, each of the n-side electrode 15 and the p-side electrode 14 is composed of a laminated body of first to fourth conductive layers 19a to 19d.
　第１の導電層１９ａは、例えば、ＩＴＯ（インジウム錫酸化物）などのＴＣＯ（Ｔｒａｎｓｐａｒｅｎｔ　Ｃｏｎｄｕｃｔｉｖｅ　Ｏｘｉｄｅ）等により形成することができる。具体的には、本実施形態では、第１の導電層１９ａは、ＩＴＯにより形成されている。第１の導電層１９ａの厚みは、例えば、５０～１００ｎｍ程度とすることができる。 The first conductive layer 19a can be formed by, for example, TCO (Transparent Conductive Oxide) such as ITO (Indium Tin Oxide). Specifically, in the present embodiment, the first conductive layer 19a is made of ITO. The thickness of the first conductive layer 19a can be about 50 to 100 nm, for example.
　第２～第４の導電層１９ｂ～１９ｄは、例えばＣｕなどの金属や合金により形成することができる。具体的には、本実施形態では、第２及び第３の導電層１９ｂ、１９ｃのそれぞれは、Ｃｕにより形成されている。第４の導電層１９ｄは、Ｓｎにより形成されている。第２～第４の導電層１９ｂ～１９ｄの厚みは、それぞれ、例えば、５０ｎｍ～１μｍ程度、５０ｎｍ～１５０ｎｍ程度、１０μｍ～２０μｍ程度、１μｍ～５μｍ程度とすることができる。 The second to fourth conductive layers 19b to 19d can be formed of a metal or alloy such as Cu, for example. Specifically, in the present embodiment, each of the second and third conductive layers 19b and 19c is formed of Cu. The fourth conductive layer 19d is made of Sn. The thicknesses of the second to fourth conductive layers 19b to 19d can be set to, for example, about 50 nm to 1 μm, about 50 nm to 150 nm, about 10 μm to 20 μm, and about 1 μm to 5 μm, respectively.
　なお、第１～第４の導電層１９ａ～１９ｄの形成方法は特に限定されず、例えば、スパッタリング法やＣＶＤ法などの薄膜形成方法やめっき法などにより形成することができる。具体的には、本実施形態では、第１及び第２の導電層１９ａ、１９ｂが薄膜形成法により形成された膜で、第３及び第４の導電層１９ｃ、１９ｄがめっき法により形成された膜である。 Note that the formation method of the first to fourth conductive layers 19a to 19d is not particularly limited, and can be formed by a thin film formation method such as a sputtering method or a CVD method, a plating method, or the like. Specifically, in the present embodiment, the first and second conductive layers 19a and 19b are films formed by a thin film forming method, and the third and fourth conductive layers 19c and 19d are formed by a plating method. It is a membrane.
　本実施形態において、反射層４０は、太陽電池基板９の一主面のｐ側及びｎ側電極１４，１５のいずれもが設けられていない領域Ｒの少なくとも一部を少なくとも覆うように設けられている。具体的には、反射層４０は、領域Ｒの全体を覆っている。より詳細には、反射層４０は、領域Ｒを含み、ｐ側電極１４が配された領域からｎ側電極１５が配された領域にわたって設けられている。そして、反射層４０は、絶縁層１８によりｎ側電極１５と電気的に絶縁されている。 In the present embodiment, the reflective layer 40 is provided so as to cover at least a part of the region R in which neither the p-side electrode nor the n- side electrode 14, 15 on one main surface of the solar cell substrate 9 is provided. Yes. Specifically, the reflective layer 40 covers the entire region R. More specifically, the reflective layer 40 includes the region R, and is provided from the region where the p-side electrode 14 is disposed to the region where the n-side electrode 15 is disposed. The reflective layer 40 is electrically insulated from the n-side electrode 15 by the insulating layer 18.
　次に、図３～図１２を主として参照しながら、本実施形態の太陽電池１の製造方法について説明する。 Next, a method for manufacturing the solar cell 1 of the present embodiment will be described with reference mainly to FIGS.
　まず、半導体基板１０を用意する。次に、ステップＳ１において、半導体基板１０の受光面１０ａ及び裏面１０ｂの洗浄を行う。半導体基板１０の洗浄は、例えば、ＨＦ水溶液などを用いて行うことができる。なお、このステップＳ１において、受光面１０ａにテクスチャ構造を形成しておくことが好ましい。 First, the semiconductor substrate 10 is prepared. Next, in step S1, the light receiving surface 10a and the back surface 10b of the semiconductor substrate 10 are cleaned. The semiconductor substrate 10 can be cleaned using, for example, an HF aqueous solution. In step S1, it is preferable to form a texture structure on the light receiving surface 10a.
　次に、ステップＳ２において、半導体基板１０の受光面１０ａの上にｉ型非晶質半導体層１７ｉとｎ型非晶質半導体層１７ｎとを形成すると共に、裏面１０ｂの上にｉ型非晶質半導体層２１とｐ型非晶質半導体層２２とを形成する。ｉ型非晶質半導体層１７ｉ，２１及びｎ型非晶質半導体層１７ｎ，２２のそれぞれの形成方法は、特に限定されない。ｉ型非晶質半導体層１７ｉ，２１及びｎ型非晶質半導体層１７ｎ，２２のそれぞれは、例えば、プラズマＣＶＤ法等のＣＶＤ（Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法により形成することができる。 Next, in step S2, the i-type amorphous semiconductor layer 17i and the n-type amorphous semiconductor layer 17n are formed on the light receiving surface 10a of the semiconductor substrate 10, and the i-type amorphous semiconductor is formed on the back surface 10b. A semiconductor layer 21 and a p-type amorphous semiconductor layer 22 are formed. The formation method of i-type amorphous semiconductor layers 17i and 21 and n-type amorphous semiconductor layers 17n and 22 is not particularly limited. Each of the i-type amorphous semiconductor layers 17i and 21 and the n-type amorphous semiconductor layers 17n and 22 can be formed by, for example, a CVD (Chemical Vapor Deposition) method such as a plasma CVD method.
　また、ステップＳ２において、ｐ型非晶質半導体層２２の上に反射層４０を形成する。反射層４０は、例えば、蒸着法、スパッタ法などの膜形成方法により形成することができる。 In step S 2, the reflective layer 40 is formed on the p-type amorphous semiconductor layer 22. The reflective layer 40 can be formed by a film forming method such as a vapor deposition method or a sputtering method, for example.
　次に、ステップＳ３において、ｎ型非晶質半導体層１７ｎの上に絶縁層１６を形成すると共に、反射層４０の上を含め、ｐ型非晶質半導体層２２の上に絶縁層２３を形成する。なお、絶縁層１６，２３の形成方法は特に限定されない。絶縁層１６，２３は、例えば、スパッタリング法やＣＶＤ法等の薄膜形成法などにより形成することができる。 Next, in step S3, the insulating layer 16 is formed on the n-type amorphous semiconductor layer 17n, and the insulating layer 23 is formed on the p-type amorphous semiconductor layer 22 including the reflective layer 40. To do. In addition, the formation method of the insulating layers 16 and 23 is not specifically limited. The insulating layers 16 and 23 can be formed by, for example, a thin film forming method such as a sputtering method or a CVD method.
　次に、ステップＳ４において、エッチング法等の方法を用いて絶縁層２３の一部分を除去する。具体的には、絶縁層２３のうち、後の工程で半導体基板１０にｎ型半導体層を接合させる領域の上に位置する部分を除去する。なお、絶縁層２３のエッチングは、絶縁層２３が酸化シリコン、窒化シリコンまたは酸窒化シリコンからなる場合は、例えば、ＨＦ水溶液等の酸性のエッチング液を用いて行うことができる。 Next, in step S4, a part of the insulating layer 23 is removed by using an etching method or the like. Specifically, a portion of the insulating layer 23 located on a region where the n-type semiconductor layer is bonded to the semiconductor substrate 10 in a later step is removed. The insulating layer 23 can be etched using an acidic etching solution such as an HF aqueous solution, for example, when the insulating layer 23 is made of silicon oxide, silicon nitride, or silicon oxynitride.
　次に、ステップＳ５において、ステップＳ４においてパターニングした絶縁層２３をマスクとして用いて、ｉ型非晶質半導体層２１とｐ型非晶質半導体層２２とを、アルカリ性のエッチング液を用いてエッチングすることにより、ｉ型非晶質半導体層２１及びｐ型非晶質半導体層２２の絶縁層２３により覆われている部分以外の部分を除去する。これにより、裏面１０ｂのうち、上方に絶縁層２３が位置していない部分を露出させると共に、半導体層２１，２２から、ｉ型非晶質半導体層１２ｉとｐ型非晶質半導体層１２ｐとを形成する。 Next, in step S5, using the insulating layer 23 patterned in step S4 as a mask, the i-type amorphous semiconductor layer 21 and the p-type amorphous semiconductor layer 22 are etched using an alkaline etchant. As a result, portions of the i-type amorphous semiconductor layer 21 and the p-type amorphous semiconductor layer 22 other than the portions covered by the insulating layer 23 are removed. As a result, a portion of the back surface 10b where the insulating layer 23 is not located above is exposed, and the i-type amorphous semiconductor layer 12i and the p-type amorphous semiconductor layer 12p are separated from the semiconductor layers 21 and 22. Form.
　ここで、上述の通り、本実施形態では、絶縁層２３が酸化シリコン、窒化シリコンまたは酸窒化シリコンからなる。このため、酸性のエッチング液による絶縁層２３のエッチング速度は高いものの、アルカリ性のエッチング液による絶縁層２３のエッチング速度は低い。一方、半導体層２１，２２は非晶質シリコンからなる。このため、半導体層２１，２２に関しては、酸性のエッチング液によるエッチング速度が低く、アルカリ性のエッチング液によるエッチング速度が高い。このため、ステップＳ４において用いた酸性のエッチング液によって、絶縁層２３はエッチングされるものの、半導体層２１，２２は、実質的にエッチングされない。一方、ステップＳ５において用いたアルカリ性のエッチング液によって半導体層２１，２２はエッチングされるものの、絶縁層２３は実質的にエッチングされない。従って、ステップＳ４及びステップＳ５において、絶縁層２３または半導体層２１，２２を選択的にエッチングすることができる。 Here, as described above, in this embodiment, the insulating layer 23 is made of silicon oxide, silicon nitride, or silicon oxynitride. For this reason, although the etching rate of the insulating layer 23 with an acidic etching solution is high, the etching rate of the insulating layer 23 with an alkaline etching solution is low. On the other hand, the semiconductor layers 21 and 22 are made of amorphous silicon. For this reason, the semiconductor layers 21 and 22 have a low etching rate with an acidic etching solution and a high etching rate with an alkaline etching solution. For this reason, although the insulating layer 23 is etched by the acidic etching solution used in step S4, the semiconductor layers 21 and 22 are not substantially etched. On the other hand, the semiconductor layers 21 and 22 are etched by the alkaline etching solution used in step S5, but the insulating layer 23 is not substantially etched. Therefore, in step S4 and step S5, the insulating layer 23 or the semiconductor layers 21 and 22 can be selectively etched.
　次に、ステップＳ６において、裏面１０ｂを覆うように、ｉ型非晶質半導体層２４とｎ型非晶質半導体層２５とをこの順番で順次形成する。非晶質半導体層２４，２５の形成方法は特に限定されない。非晶質半導体層２４，２５は、例えば、ＣＶＤ法などの薄膜形成法により形成することができる。 Next, in step S6, the i-type amorphous semiconductor layer 24 and the n-type amorphous semiconductor layer 25 are sequentially formed in this order so as to cover the back surface 10b. A method for forming the amorphous semiconductor layers 24 and 25 is not particularly limited. The amorphous semiconductor layers 24 and 25 can be formed by a thin film forming method such as a CVD method, for example.
　次に、ステップＳ７において、非晶質半導体層２４，２５の絶縁層２３の上に位置している部分の一部分をエッチングする。これにより、非晶質半導体層２４，２５からｉ型非晶質半導体層１３ｉとｎ型非晶質半導体層１３ｎとを形成する。 Next, in step S7, a part of the portion located on the insulating layer 23 of the amorphous semiconductor layers 24 and 25 is etched. Thereby, the i-type amorphous semiconductor layer 13 i and the n-type amorphous semiconductor layer 13 n are formed from the amorphous semiconductor layers 24 and 25.
　このステップＳ７においては、非晶質半導体層２４，２５に対するエッチング速度が絶縁層２３に対するエッチング速度よりも大きな第１のエッチング剤を使用する。このため、絶縁層２３と非晶質半導体層２４，２５のうち、非晶質半導体層２４，２５が選択的にエッチングされる。 In this step S 7, a first etchant having an etching rate for the amorphous semiconductor layers 24 and 25 higher than that for the insulating layer 23 is used. For this reason, the amorphous semiconductor layers 24 and 25 are selectively etched out of the insulating layer 23 and the amorphous semiconductor layers 24 and 25.
　第１のエッチング剤の具体例としては、非晶質半導体層２４，２５がシリコンからなり、絶縁層２３が酸化ケイ素、窒化ケイ素または酸窒化ケイ素からなる場合は、例えば、ＮａＯＨを含むＮａＯＨ水溶液や、ＫＯＨを含むＫＯＨ水溶液などのアルカリ性水溶液、硝酸とアンモニアとの混酸などが挙げられる。また、第１のエッチング剤は、液体、すなわちエッチング液である必要は必ずしもない。第１のエッチング剤は、例えばガスであってもよい。第１のエッチング剤として好ましく用いられるエッチングガスの具体例としては、例えば、Ｃｌ２とＨｅとの混合ガスやＸｅＦ２ガスなどが挙げられる。 As a specific example of the first etching agent, when the amorphous semiconductor layers 24 and 25 are made of silicon and the insulating layer 23 is made of silicon oxide, silicon nitride, or silicon oxynitride, for example, a NaOH aqueous solution containing NaOH, , Alkaline aqueous solution such as KOH aqueous solution containing KOH, mixed acid of nitric acid and ammonia, and the like. The first etching agent is not necessarily a liquid, that is, an etching solution. The first etchant may be a gas, for example. Specific examples of the etching gas preferably used as the first etching agent include a mixed gas of Cl 2 and He, XeF 2 gas, and the like.
　なお、本発明において、「エッチング液」には、ペースト状のエッチングペーストや粘度が調製されたエッチングインクが含まれるものとする。 In the present invention, the “etching solution” includes a pasty etching paste and an etching ink having a viscosity adjusted.
　次に、ステップＳ８において絶縁層２３のエッチングを行う。具体的には、ステップＳ７におけるエッチングにより一部分が除去された非晶質半導体層２４，２５からなる非晶質半導体層１３ｉ、１３ｐの上から、第２のエッチング剤を用いて、絶縁層２３の露出部をエッチングにより除去する。これにより、絶縁層２３にコンタクトホールを形成して反射層４０を露出させると共に、絶縁層２３から絶縁層１８を形成する。 Next, in step S8, the insulating layer 23 is etched. Specifically, the insulating layer 23 is formed on the amorphous semiconductor layers 13i and 13p including the amorphous semiconductor layers 24 and 25 partially removed by the etching in step S7 using a second etching agent. The exposed part is removed by etching. Thereby, a contact hole is formed in the insulating layer 23 to expose the reflective layer 40, and the insulating layer 18 is formed from the insulating layer 23.
　このステップＳ８においては、絶縁層２３に対するエッチング速度が非晶質半導体層２４，２５に対するエッチング速度よりも大きな第２のエッチング剤を使用する。このため、絶縁層２３と非晶質半導体層２４，２５のうち、絶縁層２３が選択的にエッチングされる。 In step S8, a second etching agent having an etching rate for the insulating layer 23 higher than that for the amorphous semiconductor layers 24 and 25 is used. For this reason, the insulating layer 23 is selectively etched among the insulating layer 23 and the amorphous semiconductor layers 24 and 25.
　第２のエッチング剤の具体例としては、非晶質半導体層２４，２５がシリコンからなり、絶縁層２３が酸化ケイ素、窒化ケイ素または酸窒化ケイ素からなる場合は、例えば、ＨＦを含むＨＦ水溶液や、リン酸水溶液などの酸性水溶液などが挙げられる。また、第２のエッチング剤も、第１のエッチング剤と同様に、液体、すなわちエッチング液である必要は必ずしもない。第２のエッチング剤は、例えばガスであってもよい。第２のエッチング剤として好ましく用いられるエッチングガスの具体例としては、例えば、ＳＦ６とＨｅとの混合ガスやＣＦ４とＣＨＦ３とＨｅとの混合ガス、ＨＦガスなどが挙げられる。なかでも、第２のエッチング剤としては、ＨＦ水溶液が好ましく用いられる。この場合、下記のステップＳ９における電極形成の前に、電極形成面の酸化皮膜の除去も行うことができるためである。 As a specific example of the second etching agent, when the amorphous semiconductor layers 24 and 25 are made of silicon and the insulating layer 23 is made of silicon oxide, silicon nitride, or silicon oxynitride, for example, an HF aqueous solution containing HF, And acidic aqueous solution such as phosphoric acid aqueous solution. Further, the second etching agent is not necessarily a liquid, that is, an etching solution, like the first etching agent. The second etchant may be a gas, for example. Specific examples of the etching gas preferably used as the second etching agent include a mixed gas of SF 6 and He, a mixed gas of CF 4 , CHF 3 and He, and HF gas. Of these, an HF aqueous solution is preferably used as the second etching agent. In this case, the oxide film on the electrode forming surface can also be removed before the electrode formation in step S9 described below.
　次に、ステップＳ９において、ｐ型非晶質半導体層１２ｐ及びｎ型非晶質半導体層１３ｎのそれぞれの上にｎ側電極１５及びｐ側電極１４を形成する電極形成工程を行うことにより、太陽電池１を完成させることができる。なお、ｎ側電極１５及びｐ側電極１４の形成方法は、電極の材質に応じて適宜選択することができる。ｎ側電極１５及びｐ側電極１４は、例えばＣＶＤ法やスパッタリング法などにより電極層２６、電極部２７を形成した後、選択的にエッチングすることにより形成することができる。この他にも、ｎ側電極１５及びｐ側電極１４は、パターニングされた電極層２６を形成した後、めっき法により電極部２７を形成して形成してもよい。 Next, in step S9, by performing an electrode forming step of forming the n-side electrode 15 and the p-side electrode 14 on the p-type amorphous semiconductor layer 12p and the n-type amorphous semiconductor layer 13n, respectively, The battery 1 can be completed. In addition, the formation method of the n side electrode 15 and the p side electrode 14 can be suitably selected according to the material of an electrode. The n-side electrode 15 and the p-side electrode 14 can be formed by, for example, selectively etching after forming the electrode layer 26 and the electrode portion 27 by CVD or sputtering. In addition to this, the n-side electrode 15 and the p-side electrode 14 may be formed by forming the electrode portion 27 by a plating method after forming the patterned electrode layer 26.
　ところで、例えば、特許文献１に記載の裏面接合型の太陽電池においては、受光面から入射した光のうち、裏面の上に形成されたｐ側またはｎ側の電極に到達した光は、それらの電極により反射されるため、裏面から実質的に出射しない。しかしながら、受光面から入射した光のうち、裏面のｐ側電極及びｎ側電極のいずれも設けられていない領域に到達した光は、裏面から出射され、電気エネルギーに変換されない。従って、裏面から出射する光の分、光電変換効率が低くなってしまう。 By the way, in the back junction solar cell described in Patent Document 1, for example, among the light incident from the light receiving surface, the light that has reached the p-side or n-side electrode formed on the back surface is those Since it is reflected by the electrode, it does not substantially exit from the back surface. However, of the light incident from the light receiving surface, the light that reaches the region where neither the p-side electrode nor the n-side electrode on the back surface is provided is emitted from the back surface and is not converted into electrical energy. Therefore, the photoelectric conversion efficiency is lowered by the amount of light emitted from the back surface.
　それに対して、本実施形態では、領域Ｒの少なくとも一部が反射層４０により覆われている。このため、裏面１０ｂのｐ側電極１４及びｎ側電極１５のいずれも設けられていない領域Ｒに到達した光は、反射層４０によって受光面１０ａ側に反射されるので、領域Ｒに到達した光が裏面１０ｂから出射することが抑制される。よって、受光面１０ａから入射し、裏面１０ｂから出射する光を少なくすることができる。従って、入射光の利用効率を高めることができるので、改善された光電変換効率を実現することができる。 In contrast, in the present embodiment, at least a part of the region R is covered with the reflective layer 40. For this reason, the light reaching the region R in which neither the p-side electrode 14 nor the n-side electrode 15 on the back surface 10b is provided is reflected to the light receiving surface 10a side by the reflective layer 40, so that the light reaching the region R Is prevented from exiting from the back surface 10b. Therefore, it is possible to reduce the light incident from the light receiving surface 10a and emitted from the back surface 10b. Therefore, since the utilization efficiency of incident light can be increased, improved photoelectric conversion efficiency can be realized.
　特に、本実施形態では、領域Ｒの全体が反射層４０により覆われている。このため、より改善された光電変換効率を実現することができる。 In particular, in the present embodiment, the entire region R is covered with the reflective layer 40. For this reason, more improved photoelectric conversion efficiency can be realized.
　また、本実施形態では、反射層４０が、Ａｇ，Ａｌ，Ｃｕ，Ｐｔ，Ａｕ及びＴｉからなる群から選ばれた金属、またはＡｇ，Ａｌ，Ｃｕ，Ｐｔ，Ａｕ及びＴｉからなる群から選ばれた１種以上の金属を含む合金という光反射率の高い材料により形成されている。よって、裏面１０ｂから太陽電池基板９外に光が出射することをより効果的に抑制することができる。従って、より改善された光電変換効率を実現することができる。 In the present embodiment, the reflective layer 40 is selected from a metal selected from the group consisting of Ag, Al, Cu, Pt, Au and Ti, or from a group consisting of Ag, Al, Cu, Pt, Au and Ti. Further, it is made of a material having a high light reflectivity called an alloy containing one or more kinds of metals. Therefore, it can suppress more effectively that light radiate | emits out of the solar cell substrate 9 from the back surface 10b. Therefore, more improved photoelectric conversion efficiency can be realized.
　また、本実施形態では、反射層４０は、領域Ｒを含み、裏面１０ｂのｐ側電極１４が配された領域からｎ側電極１５が配された領域にわたって配されている。このため、反射層４０の形成位置がずれた場合であっても、領域Ｒが反射層４０により確実に覆われる。従って、改善された光電変換効率を有する太陽電池１を高い良品率で安定して製造することができる。 In the present embodiment, the reflective layer 40 includes the region R, and is disposed from the region where the p-side electrode 14 is disposed on the back surface 10b to the region where the n-side electrode 15 is disposed. For this reason, even if the formation position of the reflective layer 40 is shifted, the region R is reliably covered with the reflective layer 40. Therefore, the solar cell 1 having improved photoelectric conversion efficiency can be stably manufactured at a high yield rate.
　また、絶縁層１８により反射層４０とｎ側電極１５とが電気的に絶縁されている。このため、ｐ側電極１４とｎ側電極１５との間を短絡電流が流れることに起因する光電変換効率の低下が抑制されている。 Further, the reflective layer 40 and the n-side electrode 15 are electrically insulated by the insulating layer 18. For this reason, the fall of the photoelectric conversion efficiency resulting from a short circuit current flowing between the p side electrode 14 and the n side electrode 15 is suppressed.
　以下、本発明を実施した好ましい形態の他の例について説明する。但し、以下の説明において、上記第１の実施形態と実質的に共通の機能を有する部材を共通の符号で参照し、説明を省略する。 Hereinafter, other examples of preferred embodiments in which the present invention is implemented will be described. However, in the following description, members having substantially the same functions as those of the first embodiment are referred to by common reference numerals, and description thereof is omitted.
　《第２及び第３の実施形態》
図１３は、第２の実施形態における太陽電池の略図的断面図である。図１４は、第３の実施形態にける太陽電池の略図的断面図である。 << Second and Third Embodiments >>
FIG. 13 is a schematic cross-sectional view of a solar cell in the second embodiment. FIG. 14 is a schematic cross-sectional view of a solar cell according to the third embodiment.
　上記第１の実施形態では、ｐ型非晶質半導体層１２ｐの直上に反射層４０が配されている例について説明した。但し、本発明において、反射層４０の位置は、領域Ｒの少なくとも一部を覆うような位置である限りにおいて特に限定されない。 In the first embodiment, the example in which the reflective layer 40 is disposed directly on the p-type amorphous semiconductor layer 12p has been described. However, in the present invention, the position of the reflective layer 40 is not particularly limited as long as it is a position that covers at least a part of the region R.
　例えば図１３に示す太陽電池では、反射層４０は、ｐ側電極１４及びｎ側電極１５よりも上方に配置されている。具体的には、ｐ側電極１４及びｎ側電極１５の上に、領域Ｒ並びにｐ側電極１４及びｎ側電極１５の全体を覆うように絶縁層４１が設けられている。反射層４０は、この絶縁層４１の上に設けられている。絶縁層４１は、領域Ｒ並びにｐ側電極１４及びｎ側電極１５の全体を覆っている。この実施形態のように、本実施形態では、領域Ｒに加えて、ｐ側電極１４及びｎ側電極１５の全体を覆うように反射層４０が設けられていてもよい。 For example, in the solar cell shown in FIG. 13, the reflective layer 40 is disposed above the p-side electrode 14 and the n-side electrode 15. Specifically, an insulating layer 41 is provided on the p-side electrode 14 and the n-side electrode 15 so as to cover the entire region R and the p-side electrode 14 and the n-side electrode 15. The reflective layer 40 is provided on the insulating layer 41. The insulating layer 41 covers the region R and the entire p-side electrode 14 and n-side electrode 15. As in this embodiment, in this embodiment, in addition to the region R, the reflective layer 40 may be provided so as to cover the entire p-side electrode 14 and n-side electrode 15.
　絶縁層４１は、特に限定されないが、例えば、酸化ケイ素、窒化ケイ素、酸窒化ケイ素などにより形成することができる。 The insulating layer 41 is not particularly limited, but can be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like.
　また、例えば図１４に示す太陽電池では、反射層４０が絶縁層１８の内部に設けられている。この実施形態では、反射層４０の端部が絶縁層１８の端面に露出しているが、反射層４０の全体が絶縁層１８に完全に包囲されるように設けられていてもよい。 For example, in the solar cell shown in FIG. 14, the reflective layer 40 is provided inside the insulating layer 18. In this embodiment, the end of the reflective layer 40 is exposed at the end face of the insulating layer 18, but the entire reflective layer 40 may be provided so as to be completely surrounded by the insulating layer 18.
　なお、反射層４０を絶縁層１８の内部に形成する方法としては、絶縁層１８のうち、反射層４０よりも下方に位置する部分を形成した後に、反射層４０を形成し、さらにその後に、絶縁層１８の残りの部分を形成する方法が挙げられる。 In addition, as a method of forming the reflective layer 40 inside the insulating layer 18, after forming a portion of the insulating layer 18 positioned below the reflective layer 40, the reflective layer 40 is formed, and then, A method of forming the remaining part of the insulating layer 18 is exemplified.
　《第４～第９の実施形態》
　図１５は、第４の実施形態における太陽電池の略図的断面図である。図１６は、第５の実施形態にける太陽電池の略図的断面図である。図１７は、第６の実施形態にける太陽電池の略図的断面図である。図１８は、第７の実施形態における太陽電池の略図的断面図である。図１９は、第８の実施形態にける太陽電池の略図的断面図である。図２０は、第９の実施形態にける太陽電池の略図的断面図である。 << Fourth to ninth embodiments >>
FIG. 15 is a schematic cross-sectional view of a solar cell in the fourth embodiment. FIG. 16 is a schematic cross-sectional view of the solar cell in the fifth embodiment. FIG. 17 is a schematic cross-sectional view of the solar cell in the sixth embodiment. FIG. 18 is a schematic cross-sectional view of a solar cell in the seventh embodiment. FIG. 19 is a schematic cross-sectional view of the solar cell in the eighth embodiment. FIG. 20 is a schematic cross-sectional view of the solar cell in the ninth embodiment.
　上記第１の実施形態では、ｎ型の半導体基板１０の上に配されたｐ型非晶質半導体層１２ｐの表面によりｐ型表面１２ｐ１が構成されており、ｎ型非晶質半導体層１３ｎの表面によりｎ型表面１３ｎ１が構成されている例について説明した。但し、本発明は、この構成に限定されない。 In the first embodiment, the p-type surface 12p1 is constituted by the surface of the p-type amorphous semiconductor layer 12p disposed on the n-type semiconductor substrate 10, and the n-type amorphous semiconductor layer 13n The example in which the n-type surface 13n1 is configured by the surface has been described. However, the present invention is not limited to this configuration.
　例えば、図１５～図１７に示す第４～第６の実施形態のように、ｎ型の結晶性半導体基板３０の裏面３０ｂ側の部分の一部分にｐ型のドーパントを熱拡散させることにより、結晶性半導体基板３０の裏面３０ｂの一部分にｐ型の熱拡散領域からなり、ｐ型表面１２ｐ１を構成する半導体領域３１ｐを形成するようにしてもよい。なお、第４～第６の実施形態では、ｎ型表面１３ｎ１は、半導体基板１０の裏面１０ｂの上に設けられたｎ型非晶質半導体層１３ｎにより構成されている。 For example, as in the fourth to sixth embodiments shown in FIGS. 15 to 17, the p-type dopant is thermally diffused into a part of the portion on the back surface 30b side of the n-type crystalline semiconductor substrate 30 to obtain a crystal. Alternatively, a semiconductor region 31p that includes a p-type heat diffusion region and forms the p-type surface 12p1 may be formed on a part of the back surface 30b of the conductive semiconductor substrate 30. In the fourth to sixth embodiments, the n-type surface 13n1 is composed of the n-type amorphous semiconductor layer 13n provided on the back surface 10b of the semiconductor substrate 10.
　さらに、図１８～図２０に示すように、半導体領域３１ｐに加えて、結晶性半導体基板３０の裏面３０ｂの一部分にｎ型の熱拡散領域からなり、ｎ型表面１３ｎ１を構成する半導体領域３１ｎをさらに形成するようにしてもよい。すなわち、ｐ型表面１２ｐ１及びｎ型表面１３ｎ１の両方を熱拡散領域により構成するようにしてもよい。 Further, as shown in FIGS. 18 to 20, in addition to the semiconductor region 31p, a semiconductor region 31n, which is formed of an n-type thermal diffusion region on a part of the back surface 30b of the crystalline semiconductor substrate 30 and constitutes the n-type surface 13n1, is formed. Further, it may be formed. That is, both the p-type surface 12p1 and the n-type surface 13n1 may be configured by a thermal diffusion region.
　なお、図１５に示す第４の実施形態及び図１８に示す第７の実施形態のそれぞれでは、上記第１の実施形態と同様に、ｐ型半導体領域の直上に反射層４０が配置されている。 In each of the fourth embodiment shown in FIG. 15 and the seventh embodiment shown in FIG. 18, the reflective layer 40 is disposed immediately above the p-type semiconductor region, as in the first embodiment. .
　図１６に示す第５の実施形態及び図１９に示す第８の実施形態のそれぞれでは、上記第２の実施形態と同様に、ｐ側電極１４及びｎ側電極１５を覆うように設けられた絶縁層４１の上に反射層４０が配されている。反射層４０は、領域Ｒ並びにｐ側電極１４及びｎ側電極１５の全体を覆っている。 In each of the fifth embodiment shown in FIG. 16 and the eighth embodiment shown in FIG. 19, the insulation provided to cover the p-side electrode 14 and the n-side electrode 15, as in the second embodiment. A reflective layer 40 is disposed on the layer 41. The reflective layer 40 covers the region R and the entire p-side electrode 14 and n-side electrode 15.
　図１７に示す第６の実施形態及び図２０に示す第９の実施形態のそれぞれでは、上記第３の実施形態と同様に、絶縁層１８の内部に反射層４０が形成されている。 In each of the sixth embodiment shown in FIG. 17 and the ninth embodiment shown in FIG. 20, the reflective layer 40 is formed inside the insulating layer 18 as in the third embodiment.
　《第１０の実施形態》
　図２１は、第１０の実施形態における太陽電池の略図的断面図である。 << Tenth Embodiment >>
FIG. 21 is a schematic cross-sectional view of a solar cell according to the tenth embodiment.
　上記第２の実施形態では、反射層４０の下に絶縁層４１が設けられている例について説明した。但し、反射層４０が絶縁性を有する場合は、図２１に示すように、絶縁層４１を設けずに、太陽電池基板９、ｐ側電極１４及びｎ側電極１５を覆うように反射層４０を設けてもよい。この場合は、絶縁層４１を形成する工程が必要とならず、かつ、例えば塗布等により反射層４０を容易に形成することができる。従って、太陽電池１の製造が容易となる。 In the second embodiment, the example in which the insulating layer 41 is provided under the reflective layer 40 has been described. However, when the reflective layer 40 has an insulating property, as shown in FIG. It may be provided. In this case, the step of forming the insulating layer 41 is not necessary, and the reflective layer 40 can be easily formed by, for example, coating. Therefore, manufacture of the solar cell 1 becomes easy.
　なお、絶縁性を有する反射層４０は、特に限定されないが、例えば、白色系の樹脂組成物により構成することができる。白色系の樹脂組成物の具体例としては、例えば、酸化チタン微粒子を含むエチレン・酢酸ビニル共重合体（ＥＶＡ）等が挙げられる。 In addition, the reflective layer 40 having insulating properties is not particularly limited, but can be formed of, for example, a white resin composition. Specific examples of the white resin composition include an ethylene / vinyl acetate copolymer (EVA) containing titanium oxide fine particles.
１…太陽電池
９…太陽電池基板
１０…半導体基板
１０ａ…受光面
１０ｂ…裏面
１２ｐ…ｐ型非晶質半導体層
１２ｐ１…ｐ型表面
１３ｎ…ｎ型非晶質半導体層
１３ｎ１…ｎ型表面
１４…ｐ側電極
１５…ｎ側電極
３０…結晶性半導体基板
３１…絶縁層
３１ｎ…半導体領域
３１ｐ…半導体領域
４０…反射層
４１…絶縁層 DESCRIPTION OF SYMBOLS 1 ... Solar cell 9 ... Solar cell substrate 10 ... Semiconductor substrate 10a ... Light-receiving surface 10b ... Back surface 12p ... P-type amorphous semiconductor layer 12p1 ... P-type surface 13n ... N-type amorphous semiconductor layer 13n1 ... N-type surface 14 ... p-side electrode 15 ... n-side electrode 30 ... crystalline semiconductor substrate 31 ... insulating layer 31n ... semiconductor region 31p ... semiconductor region 40 ... reflective layer 41 ... insulating layer

Claims (10)

  1. 　半導体基板を有し、一主面にｐ型表面及びｎ型表面が露出している太陽電池基板と、
    　前記ｐ型表面の上に設けられているｐ側電極と、
    　前記ｎ型表面の上に設けられているｎ側電極と、
    　前記太陽電池基板の一主面の前記ｐ側及びｎ側電極のいずれもが設けられていない領域の少なくとも一部を少なくとも覆うように設けられた反射層と、
    を備える、太陽電池。     A solar cell substrate having a semiconductor substrate and having a p-type surface and an n-type surface exposed on one main surface;
    A p-side electrode provided on the p-type surface;
    An n-side electrode provided on the n-type surface;
    A reflective layer provided so as to cover at least a part of a region where neither the p-side electrode nor the n-side electrode of one main surface of the solar cell substrate is provided;
    A solar cell comprising:
  2. 　前記反射層は、前記太陽電池基板の一主面の前記ｐ側電極及び前記ｎ側電極のいずれもが設けられていない領域を含み、前記ｐ側電極が配された領域の上から前記ｎ側電極が配された領域の上にわたって設けられており、
    　前記反射層と、前記ｐ側電極及び前記ｎ側電極の少なくとも一方との間に配された絶縁層をさらに備える、請求項１に記載の太陽電池。     The reflective layer includes a region where neither the p-side electrode nor the n-side electrode is provided on one main surface of the solar cell substrate, and the n-side from above the region where the p-side electrode is disposed. It is provided over the area where the electrodes are arranged,
    The solar cell according to claim 1, further comprising: an insulating layer disposed between the reflective layer and at least one of the p-side electrode and the n-side electrode.
  3. 　前記反射層は、前記ｐ側電極及び前記ｎ側電極よりも上方に配されている、請求項２に記載の太陽電池。 The solar cell according to claim 2, wherein the reflective layer is disposed above the p-side electrode and the n-side electrode.
  4. 　前記反射層が内部に設けられた絶縁層をさらに備える、請求項１に記載の太陽電池。 The solar cell according to claim 1, further comprising an insulating layer in which the reflective layer is provided.
  5. 　前記反射層は、Ａｇ，Ａｌ，Ｃｕ，Ｐｔ，Ａｕ及びＴｉからなる群から選ばれた金属、またはＡｇ，Ａｌ，Ｃｕ，Ｐｔ，Ａｕ及びＴｉからなる群から選ばれた１種以上の金属を含む合金からなる、請求項１～４のいずれか一項に記載の太陽電池。 The reflective layer is made of a metal selected from the group consisting of Ag, Al, Cu, Pt, Au, and Ti, or one or more metals selected from the group consisting of Ag, Al, Cu, Pt, Au, and Ti. The solar cell according to any one of claims 1 to 4, comprising an alloy containing the same.
  6. 　前記反射層は絶縁性を有する、請求項１～４のいずれか一項に記載の太陽電池。 The solar cell according to any one of claims 1 to 4, wherein the reflective layer has an insulating property.
  7. 　前記反射層は樹脂からなる、請求項６に記載の太陽電池。 The solar cell according to claim 6, wherein the reflective layer is made of a resin.
  8. 　前記反射層は白色樹脂からなる、請求項７に記載の太陽電池。 The solar cell according to claim 7, wherein the reflective layer is made of a white resin.
  9. 　前記太陽電池基板は、前記半導体基板の一主面の上に設けられており、前記ｐ型表面を構成しているｐ型半導体層と、前記半導体基板の一主面の上に設けられており、前記ｎ型表面を構成しているｎ型半導体層とのうちの少なくとも一方をさらに有する、請求項１～８のいずれか一項に記載の太陽電池。 The solar cell substrate is provided on one main surface of the semiconductor substrate, and is provided on a p-type semiconductor layer constituting the p-type surface and one main surface of the semiconductor substrate. The solar cell according to any one of claims 1 to 8, further comprising at least one of an n-type semiconductor layer constituting the n-type surface.
  10. 　前記半導体基板は、ｐ型ドーパントが拡散しており、前記ｐ型表面を構成しているｐ型半導体領域と、ｎ型ドーパントが拡散しており、前記ｎ型表面を構成しているｎ型半導体領域とのうちの少なくとも一方を有する、請求項１～９のいずれか一項に記載の太陽電池。 The semiconductor substrate has a p-type dopant diffused therein, a p-type semiconductor region constituting the p-type surface, and an n-type semiconductor comprising the n-type dopant diffused and the n-type surface. The solar cell according to any one of claims 1 to 9, having at least one of a region.
PCT/JP2011/078070 2010-12-29 2011-12-05 Solar cell WO2012090650A1 (en)

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