JPWO2014163042A1 - Photoelectric conversion element - Google Patents

Abstract

A first conductivity type layer containing hydrogenated amorphous silicon of the first conductivity type, a second conductivity type layer containing hydrogenated amorphous silicon of the second conductivity type, and an insulating layer provided on the intrinsic layer; A first electrode provided on the first conductivity type layer; and a second electrode provided on the second conductivity type layer, wherein the end of the first conductivity type layer is second from the end of the insulating layer. It is a photoelectric conversion element protruding in the direction of the electrode.

Description

  The present invention relates to a photoelectric conversion element.

  In recent years, a solar cell that directly converts solar energy into electric energy has been rapidly expected as a next-generation energy source particularly from the viewpoint of global environmental problems. There are various types of solar cells, such as those using compound semiconductors or organic materials, but the mainstream is currently using silicon crystals.

  Currently, the most manufactured and sold solar cells have a structure in which electrodes are respectively formed on a light receiving surface that is a surface on which sunlight is incident and a back surface that is opposite to the light receiving surface.

  However, when an electrode is formed on the light receiving surface, sunlight is reflected and absorbed by the electrode, so that the amount of incident sunlight is reduced by the area of the electrode. For this reason, development of solar cells in which electrodes are formed on the back surface is also being promoted (see, for example, JP 2009-524916 A (Patent Document 1)).

  FIG. 38 is a schematic cross-sectional view of the amorphous / crystalline silicon heterojunction device described in Patent Document 1. As shown in FIG. 38, in the amorphous / crystalline silicon heterojunction device described in Patent Document 1, an intrinsic hydrogenated amorphous silicon transition layer 102 is formed on the back surface of the crystalline silicon wafer 101, and an intrinsic hydrogenated amorphous silicon transition layer is formed. An n-doped region 103 and a p-doped region 104 of hydrogenated amorphous silicon are formed in 102, and an aluminum electrode 105 is provided on the n-doped region 103 and the p-doped region 104.

  In the amorphous / crystalline silicon heterojunction device described in Patent Document 1 shown in FIG. 38, the n-doped region 103 and the p-doped region 104 are formed using lithography and / or shadow masking processes (for example, Patent Document 1). Paragraph [0020] etc.).

  The aluminum electrode 105 is formed by evaporating aluminum on the n-doped region 103 and the p-doped region 104 using a mask along the center line where the inner sides of the n-doped region 103 and the p-doped region 104 overlap. (See, for example, paragraphs [0024] and [0025] of Patent Document 1).

Special table 2009-524916

  However, when the n-doped region 103 and the p-doped region 104 are formed using lithography, the n-doped region 103 and the p-doped region 104 have a high etching selectivity with respect to the intrinsic hydrogenated amorphous silicon transition layer 102. Although it is necessary to etch the n-doped region 103 and the p-doped region 104, Patent Document 1 does not describe such an etching method having a large etching selectivity.

  The thickness of the stacked body of the intrinsic hydrogenated amorphous silicon transition layer 102 and the n-doped region 103 and the thickness of the stacked body of the intrinsic hydrogenated amorphous silicon transition layer 102 and the p-doped region 104 are several to several tens. Since it is nm (paragraph [0018] of Patent Document 1), the intrinsic hydrogenated amorphous silicon transition layer 102 is very thin. Thus, it is very difficult to etch the n-doped region 103 and the p-doped region 104 leaving the very thin intrinsic hydrogenated amorphous silicon transition layer 102.

  When the n-doped region 103 and the p-doped region 104 are formed using a shadow masking process, a mask is used when forming the n-doped region 103 and the p-doped region 104 by plasma CVD (Chemical Vapor Deposition). Since the separation between the n-doped region 103 and the p-doped region 104 becomes difficult due to the wraparound of the gas to the back surface, the patterning accuracy becomes very poor. The interval needs to be increased. However, when the interval between the n-doped region 103 and the p-doped region 104 is increased, the region in which neither the n-doped region 103 nor the p-doped region 104 is formed becomes larger. The conversion efficiency of the heterojunction device is lowered.

  In view of the above circumstances, an object of the present invention is to provide a photoelectric conversion element that can be manufactured with high yield and has high characteristics.

  The present invention relates to a semiconductor, an intrinsic layer containing hydrogenated amorphous silicon provided on the semiconductor, a first conductivity type layer containing hydrogenated amorphous silicon of the first conductivity type provided on the intrinsic layer, , A second conductivity type layer containing hydrogenated amorphous silicon of the second conductivity type, an insulating layer, a first electrode provided on the first conductivity type layer, and a first electrode provided on the second conductivity type layer. The photoelectric conversion element is provided with two electrodes, and the end portion of the first conductivity type layer protrudes from the end of the insulating layer in the direction of the second electrode. With such a structure, a photoelectric conversion element that can be manufactured with high yield and has high characteristics can be obtained.

  ADVANTAGE OF THE INVENTION According to this invention, it can manufacture with a high yield and can provide a photoelectric conversion element with a high characteristic.

FIG. 3 is a schematic cross-sectional view of the heterojunction back contact cell according to the first embodiment. FIG. 3 is a schematic cross-sectional view illustrating an example of the method for manufacturing the heterojunction back contact cell of the first embodiment. FIG. 3 is a schematic cross-sectional view illustrating an example of the method for manufacturing the heterojunction back contact cell of the first embodiment. FIG. 3 is a schematic cross-sectional view illustrating an example of the method for manufacturing the heterojunction back contact cell of the first embodiment. FIG. 3 is a schematic cross-sectional view illustrating an example of the method for manufacturing the heterojunction back contact cell of the first embodiment. FIG. 3 is a schematic cross-sectional view illustrating an example of the method for manufacturing the heterojunction back contact cell of the first embodiment. FIG. 3 is a schematic cross-sectional view illustrating an example of the method for manufacturing the heterojunction back contact cell of the first embodiment. FIG. 3 is a schematic cross-sectional view illustrating an example of the method for manufacturing the heterojunction back contact cell of the first embodiment. FIG. 3 is a schematic cross-sectional view illustrating an example of the method for manufacturing the heterojunction back contact cell of the first embodiment. FIG. 3 is a schematic cross-sectional view illustrating an example of the method for manufacturing the heterojunction back contact cell of the first embodiment. FIG. 3 is a schematic cross-sectional view illustrating an example of the method for manufacturing the heterojunction back contact cell of the first embodiment. FIG. 3 is a schematic cross-sectional view illustrating an example of the method for manufacturing the heterojunction back contact cell of the first embodiment. FIG. 3 is a schematic cross-sectional view illustrating an example of the method for manufacturing the heterojunction back contact cell of the first embodiment. FIG. 3 is a schematic cross-sectional view illustrating an example of the method for manufacturing the heterojunction back contact cell of the first embodiment. FIG. 6 is a schematic cross-sectional view of a heterojunction back contact cell according to a second embodiment. FIG. 6 is a schematic cross-sectional view illustrating an example of a method for manufacturing a heterojunction back contact cell according to a second embodiment. FIG. 6 is a schematic cross-sectional view illustrating an example of a method for manufacturing a heterojunction back contact cell according to a second embodiment. FIG. 6 is a schematic cross-sectional view illustrating an example of a method for manufacturing a heterojunction back contact cell according to a second embodiment. FIG. 6 is a schematic cross-sectional view illustrating an example of a method for manufacturing a heterojunction back contact cell according to a second embodiment. FIG. 6 is a schematic cross-sectional view illustrating an example of a method for manufacturing a heterojunction back contact cell according to a second embodiment. FIG. 6 is a schematic cross-sectional view illustrating an example of a method for manufacturing a heterojunction back contact cell according to a second embodiment. FIG. 6 is a schematic cross-sectional view illustrating an example of a method for manufacturing a heterojunction back contact cell according to a second embodiment. FIG. 6 is a schematic cross-sectional view illustrating an example of a method for manufacturing a heterojunction back contact cell according to a second embodiment. FIG. 6 is a schematic cross-sectional view illustrating an example of a method for manufacturing a heterojunction back contact cell according to a second embodiment. FIG. 6 is a schematic cross-sectional view illustrating an example of a method for manufacturing a heterojunction back contact cell according to a second embodiment. FIG. 6 is a schematic cross-sectional view illustrating an example of a method for manufacturing a heterojunction back contact cell according to a second embodiment. FIG. 6 is a schematic cross-sectional view illustrating an example of a method for manufacturing a heterojunction back contact cell according to a second embodiment. 6 is a schematic cross-sectional view of a heterojunction back contact cell according to Embodiment 3. FIG. 10 is a schematic cross-sectional view illustrating an example of a method for manufacturing a heterojunction back contact cell of Embodiment 3. FIG. 10 is a schematic cross-sectional view illustrating an example of a method for manufacturing a heterojunction back contact cell of Embodiment 3. FIG. 10 is a schematic cross-sectional view illustrating an example of a method for manufacturing a heterojunction back contact cell of Embodiment 3. FIG. 10 is a schematic cross-sectional view illustrating an example of a method for manufacturing a heterojunction back contact cell of Embodiment 3. FIG. 10 is a schematic cross-sectional view illustrating an example of a method for manufacturing a heterojunction back contact cell of Embodiment 3. FIG. 10 is a schematic cross-sectional view illustrating an example of a method for manufacturing a heterojunction back contact cell of Embodiment 3. FIG. 10 is a schematic cross-sectional view illustrating an example of a method for manufacturing a heterojunction back contact cell of Embodiment 3. FIG. 10 is a schematic cross-sectional view illustrating an example of a method for manufacturing a heterojunction back contact cell of Embodiment 3. FIG. 10 is a schematic cross-sectional view illustrating an example of a method for manufacturing a heterojunction back contact cell of Embodiment 3. FIG. 1 is a schematic cross-sectional view of an amorphous / crystalline silicon heterojunction device described in Patent Document 1. FIG. 6 is a schematic diagram of a configuration of a photoelectric conversion module according to Embodiment 4. FIG. It is the schematic of the structure of the solar energy power generation system of Embodiment 5. FIG. It is the schematic of an example of a structure of the photoelectric conversion module array shown in FIG. It is the schematic of the structure of the solar energy power generation system of Embodiment 6. FIG. It is the schematic of another example of the structure of the solar energy power generation system of Embodiment 5. FIG. It is the schematic of another example of the structure of the solar energy power generation system of Embodiment 6. FIG.

  Embodiments of the present invention will be described below. In the drawings of the present invention, the same reference numerals represent the same or corresponding parts.

<Embodiment 1>
FIG. 1 is a schematic cross-sectional view of a heterojunction back contact cell according to Embodiment 1, which is an example of the photoelectric conversion element of the present invention. The heterojunction back contact cell of Embodiment 1 includes a semiconductor 1 made of n-type single crystal silicon, an intrinsic layer 4 containing i-type hydrogenated amorphous silicon covering the entire back surface of the semiconductor 1, and an intrinsic layer. N-type layer 6 containing n-type hydrogenated amorphous silicon covering a part of the back surface of 4 and p-type layer 8 containing p-type hydrogenated amorphous silicon covering a part of the back surface of intrinsic layer 4 And a first insulating layer 5 covering a part of the back surface of the intrinsic layer 4. Here, the n-type layer 6, the p-type layer 8, and the first insulating layer 5 cover different regions on the back surface of the semiconductor 1.

  A first electrode 9 is provided on the n-type layer 6, and a second electrode 10 is provided on the p-type layer 8.

  The first insulating layer 5 is formed in a band shape, and the n-type layer 6 covers a part of the back surface of the intrinsic layer 4 and the first insulating layer 5 provided on the back surface of the intrinsic layer 4. One electrode side surface and back surface are covered. Furthermore, the n-type layer 6 has an end 6 a that protrudes from the end of the first insulating layer 5 toward the second electrode 10 on the first insulating layer 5.

  The second insulating layer 3 is provided on the back surface of the n-type layer 6, and the p-type layer 8 covers a part of the back surface of the intrinsic layer 4 and is provided on the back surface of the intrinsic layer 4. The side surface of the first insulating layer 5 on the second electrode side, the end portion 6a of the n-type layer 6, and the side surface of the second insulating layer 3 on the second electrode side and the back surface are covered.

  The first electrode 9 covers the back surface of the n-type layer 6 and covers the side surface of the second insulating layer 3 and the back surface of the p-type layer 8.

  Further, the region 8 b of the p-type layer 8 below the end portion 6 a of the n-type layer 6 includes a region where the second electrode 10 is not provided.

  The structure on the back surface side of the semiconductor 1 is the above structure, but a texture structure (not shown) is formed on the light receiving surface opposite to the back surface of the semiconductor 1, and a passivation film is formed on the texture structure. An antireflection film (not shown) may also be formed. The antireflection film may be a laminated film in which an antireflection layer is laminated on the passivation layer.

  Hereinafter, an example of a method for manufacturing the heterojunction back contact cell of the first embodiment will be described with reference to schematic cross-sectional views of FIGS. First, as shown in FIG. 2, an intrinsic layer 4 made of i-type hydrogenated amorphous silicon is laminated on the entire back surface of the semiconductor 1 that has been subjected to RCA cleaning, and then the first insulation is formed on the entire back surface of the intrinsic layer 4. Layer 5 is laminated. Here, the intrinsic layer 4 and the first insulating layer 5 can be laminated by, for example, a plasma CVD method. In this specification, “i-type” means an intrinsic semiconductor.

  The semiconductor 1 is not limited to n-type single crystal silicon, and a conventionally known semiconductor may be used, for example. The thickness of the semiconductor 1 is not particularly limited, but can be, for example, 50 μm or more and 300 μm or less, and preferably 70 μm or more and 150 μm or less. Further, the specific resistance of the semiconductor 1 is not particularly limited, but may be, for example, 0.5 Ω · cm or more and 10 Ω · cm or less.

  The texture structure of the light receiving surface of the semiconductor 1 can be formed by, for example, texture etching the entire surface of the light receiving surface of the semiconductor 1.

  For example, a silicon nitride film, a silicon oxide film, or a stacked body of a silicon nitride film and a silicon oxide film can be used as the antireflection film serving also as a passivation film on the light receiving surface of the semiconductor 1. Further, the thickness of the antireflection film can be set to, for example, about 100 nm. The antireflection film can be laminated by, for example, a sputtering method or a plasma CVD method.

  The thickness of the intrinsic layer 4 laminated on the entire back surface of the semiconductor 1 is not particularly limited, but may be, for example, 1 nm or more and 10 nm or less, and more specifically about 3 nm.

  The first insulating layer 5 laminated on the entire back surface of the intrinsic layer 4 is not particularly limited as long as it is a layer made of an insulating material, but is preferably made of a material that can be etched without substantially damaging the intrinsic layer 4. As the insulating layer 5, for example, a silicon nitride layer, a silicon oxide layer, or a stacked body of a silicon nitride layer and a silicon oxide layer formed using a plasma CVD method or the like can be used. In this case, for example, by using hydrofluoric acid, it is possible to etch the first insulating layer 5 without damaging the intrinsic layer 4. Although the thickness of the 1st insulating layer 5 is not specifically limited, For example, they are 0.1 micrometer or more and 10 micrometers or less.

  Next, as shown in FIG. 3, a resist 21 having an opening 22 is formed on the back surface of the first insulating layer 5. The resist 21 having the opening 22 can be formed by, for example, a photolithography method or a printing method.

  Next, as shown in FIG. 4, the back surface of the intrinsic layer 4 is exposed from the opening 22 of the resist 21 by removing the portion of the first insulating layer 5 exposed from the opening 22 of the resist 21.

  The removal of the first insulating layer 5 can be performed, for example, by wet etching using hydrofluoric acid or the like. Here, when the first insulating layer 5 is removed by wet etching using hydrofluoric acid, the intrinsic layer 4 made of i-type hydrogenated amorphous silicon can function as an etching stop layer, and the wet etching is performed. It can be stopped by the intrinsic layer 4.

  Next, as shown in FIG. 5, after removing all the resist 21 from the back surface of the first insulating layer 5, the exposed back surface of the intrinsic layer 4 and the first insulating layer 5 are covered as shown in FIG. Then, an n-type layer 6 made of n-type hydrogenated amorphous silicon is laminated by, for example, a plasma CVD method.

  The thickness of the n-type layer 6 is not particularly limited, but is preferably 0.1 to 3 times the thickness of the first insulating layer 5, for example. In this case, since the end portion 6a of the n-type layer 6 is easily formed, the yield is increased.

As the n-type impurity contained in the n-type layer 6, for example, phosphorus can be used, and the n-type impurity concentration of the n-type layer 6 can be set to about 5 × 10 ²⁰ / cm ³ , for example.

  Next, as shown in FIG. 7, the second insulating layer 3 is laminated on the back surface of the n-type layer 6 by, for example, a plasma CVD method.

  The second insulating layer 3 is not particularly limited as long as it is a layer made of an insulating material, but it is preferable that the second insulating layer 3 be made of a material that can be etched without substantially damaging the n-type layer 6. As the second insulating layer 3, for example, a silicon nitride layer, a silicon oxide layer, or a stacked body of a silicon nitride layer and a silicon oxide layer formed using a plasma CVD method or the like can be used. In this case, for example, by using hydrofluoric acid, the second insulating layer 3 can be etched without damaging the n-type layer 6.

  Next, as shown in FIG. 8, a resist 31 having an opening 32 is formed on the back surface of the second insulating layer 3. The resist 31 having the opening 32 can be formed by, for example, a photolithography method or a printing method.

  Next, as shown in FIG. 9, the openings of the resist 31 are removed by removing the respective portions of the second insulating layer 3, the n-type layer 6, and the first insulating layer 5 exposed from the opening 32 of the resist 31. The back surface of the intrinsic layer 4 is exposed from the portion 32.

  The removal of the second insulating layer 3 can be performed, for example, by wet etching using hydrofluoric acid or the like. At this time, the end portion 6a of the n-type layer 6 can be formed by performing side etching beyond the thickness of the second insulating layer 3 and removing the second insulating layer 3. Here, when the second insulating layer 3 is removed by wet etching using hydrofluoric acid, the n-type layer 6 made of n-type hydrogenated amorphous silicon can function as an etching stop layer. Can be stopped by the n-type layer 6.

  The n-type layer 6 can be removed, for example, by wet etching using an alkaline aqueous solution such as an aqueous tetramethylammonium hydroxide solution, an aqueous potassium hydroxide solution, or an aqueous sodium hydroxide solution. At this time, the first insulating layer 5 can function as an etching stop layer, and the wet etching can be stopped by the first insulating layer 5.

  The removal of the first insulating layer 5 can be performed by, for example, wet etching using hydrofluoric acid or the like. At this time, the first insulating layer 5 can be removed by performing side etching beyond the thickness of the first insulating layer 5. In addition, when the first insulating layer 5 is removed by wet etching using hydrofluoric acid, the intrinsic layer 4 made of i-type hydrogenated amorphous silicon can function as an etching stop layer. It can be stopped at layer 4.

  Next, as shown in FIG. 10, after removing all the resist 31 from the back surface of the second insulating layer 3, as shown in FIG. 11, the exposed back surface of the intrinsic layer 4, the end 6a of the n-type layer 6, and A p-type layer 8 made of p-type hydrogenated amorphous silicon is laminated by, for example, a plasma CVD method so as to cover the second insulating layer 3.

  Although the thickness of the p-type layer 8 is not specifically limited, For example, it is 5 nm or more and 50 nm or less.

As the p-type impurity contained in the p-type layer 8, for example, boron can be used, and the p-type impurity concentration of the p-type layer 8 can be set to about 5 × 10 ²⁰ / cm ³ , for example.

  Next, as shown in FIG. 12, an opening 42 is provided on the back surface of the p-type layer 8 so as to fill the opening of the p-type layer 8 including the notch below the end 6a of the n-type layer 6. A resist 41 is formed. The resist 41 having the opening 42 can be formed by, for example, a photolithography method or a printing method.

  Next, as shown in FIG. 13, the back surface of the n-type layer 6 is exposed by removing the p-type layer 8 and the second insulating layer 3 exposed from the opening 42 of the resist 41.

  The p-type layer 8 can be removed, for example, by wet etching using a mixed solution of hydrofluoric acid and nitric acid (for example, hydrofluoric acid: nitric acid = 1: 100 in volume ratio). Further, reactive ion etching may be used instead of wet etching. At this time, as long as the n-type layer 6 is not exposed, a part of the second insulating layer 3 may be removed.

  The second insulating layer 3 can be removed by, for example, wet etching using hydrofluoric acid or the like. Here, when the second insulating layer 3 is removed by wet etching using hydrofluoric acid, the n-type layer 6 made of n-type hydrogenated amorphous silicon can function as an etching stop layer. Can be stopped by the n-type layer 6.

  Thereafter, as shown in FIG. 14, after all the resist 41 is removed from the back surface of the p-type layer 8, a conductive film is laminated by, for example, sputtering or vapor deposition from the opening 42 and the opening 43 on the back surface of the semiconductor 1. As a result, as shown in FIG. 1, the first electrode 9 is formed on the n-type layer 6, and the second electrode 10 is formed on the p-type layer 8.

  As the conductive film used for forming the first electrode 9 and the second electrode 10, for example, a metal film containing at least one of silver and aluminum, or a transparent conductive film such as ITO and a metal film containing at least one of silver and aluminum A deposited film or the like can be used.

  As described above, the heterojunction back contact cell of the first embodiment can be manufactured.

  In the method of manufacturing the heterojunction back contact cell according to the first embodiment, a notch is formed in the region below the end 6 a of the n-type layer 6 in the opening 43 on the back surface side of the p-type layer 8. Therefore, the conductive film is separated by this notch, and the second electrode 10 is formed in a self-aligned manner. Therefore, since a process such as lithography and / or shadow masking is not required for patterning the second electrode 10, a heterojunction back contact cell can be easily manufactured.

  Further, in the heterojunction back contact cell of the first embodiment, the end 6a of the n-type layer 6 has a notch formed only in the opening 43 on the back surface side of the p-type layer 8, so that the first electrode The electrode area of the first electrode 9 can be increased, and the parasitic resistance of the first electrode 9 can be suppressed.

  When the semiconductor 1 is n-type, the width of the n-type layer 6 is often narrower than the width of the p-type layer 8 and the first electrode 9 tends to have high resistance. It is preferable to increase the electrode area of the first electrode 9 by forming a notch in the opening 43 on the back surface side. On the other hand, when the semiconductor 1 is p-type, it is preferable to increase the electrode area of the second electrode 10 for the same reason as described above.

  Further, as described above, in the first embodiment, patterning of n-type layer 6 and p-type layer 8 can be performed on first insulating layer 5 and second insulating layer 3, respectively. Thereby, since the damage which the semiconductor 1 and the intrinsic layer 4 receive at the time of patterning of the n-type layer 6 and the p-type layer 8 can be reduced, a heterojunction type back contact cell can be manufactured with a high yield, The characteristics can be enhanced.

  Further, in the first embodiment, since there is no gap in the projected images of the first electrode 9 and the second electrode 10 on the back surface of the semiconductor 1, the light incident from the light receiving surface of the semiconductor 1 and transmitted through the semiconductor 1 is transmitted. Since the first electrode 9 and the second electrode 10 can reflect the semiconductor 1 side, the characteristics of the heterojunction back contact cell can be enhanced also from this viewpoint.

  In the first embodiment, it is not necessary to form the n-type layer 6 and the p-type layer 8 using a shadow masking process. Thereby, since the n-type layer 6 and the p-type layer 8 can be formed with high precision, the heterojunction back contact cell can be manufactured with a high yield and the characteristics can be enhanced.

  As described above, the heterojunction back contact cell of Embodiment 1 can be manufactured with high yield and can be a photoelectric conversion element with high characteristics.

  In particular, in the heterojunction back contact cell of the first embodiment, the region 8b of the p-type layer 8 below the end 6a of the n-type layer 6 includes a region where the second electrode 10 is not formed. A notch is formed in the opening on the back side of the p-type layer 8 by the end 6 a of the n-type layer 6. This notch allows the second electrode 10 to be formed in a self-aligned manner, so that a heterojunction back contact cell can be manufactured with a high yield.

  In the heterojunction back contact cell of the first embodiment, since the end 6a of the n-type layer 6 is covered with the p-type layer 8, the p-type layer below the end 6a of the n-type layer 6 is used. The notch can be stably formed by the eight regions. Since the second electrode 10 can be formed in a self-aligned manner by this notch, a heterojunction back contact cell can be manufactured with a higher yield.

  In the heterojunction back contact cell of the first embodiment, when the first insulating layer 5 contains silicon nitride, the first insulating layer 5 is etched from i-type hydrogenated amorphous silicon in the wet etching. Since the intrinsic layer 4 can be made to function as an etching stop layer, side etching more than the thickness of the first insulating layer 5 can be easily performed.

  In the heterojunction back contact cell of the first embodiment, since the second insulating layer 3 is provided on the n-type layer 6, the n-type layer 6 and the p-type layer 8 are formed by the second insulating layer 3. Can be insulated in the thickness direction.

  In the heterojunction back contact cell of the first embodiment, when the second insulating layer 3 contains silicon nitride, the n-type hydrogenated amorphous silicon is used in the wet etching of the second insulating layer 3. Since the n-type layer 6 can be made to function as an etching stop layer, side etching more than the thickness of the second insulating layer 3 can be easily performed.

  In the first embodiment, since the p-type layer 8 is formed after the n-type layer 6 is formed, a good passivation effect on the back surface of the semiconductor 1 by the intrinsic layer 4 can be obtained. That is, when the p-type layer 8 is formed before the n-type layer 6 is formed, the minority carrier lifetime of the intrinsic layer 4 covered with the p-type layer 8 is reduced by the annealing effect when the n-type layer 6 is stacked. However, when the p-type layer 8 is formed after the n-type layer 6 is formed, such a decrease in minority carrier lifetime can be suppressed.

  In the above description, the first conductivity type is n-type and the second conductivity type is p-type. However, it goes without saying that the first conductivity type may be p-type and the second conductivity type may be n-type. .

<Embodiment 2>
FIG. 15 is a schematic cross-sectional view of a heterojunction back contact cell according to Embodiment 2, which is another example of the photoelectric conversion element of the present invention. The heterojunction back contact cell according to the second embodiment is characterized in that the second intrinsic layer 61 containing i-type hydrogenated amorphous silicon is located immediately below the n-type layer 6.

  Hereinafter, an example of a method for manufacturing the heterojunction back contact cell according to the second embodiment will be described with reference to the schematic cross-sectional views of FIGS. First, intrinsic layer 4 and first insulating layer 5 are stacked in this order on the back surface of semiconductor 1, and the same as in Embodiment 1 until a resist having an opening is provided on the back surface of first insulating layer 5. It is.

  Next, as shown in FIG. 16, the first insulating layer 5 and the intrinsic layer 4 exposed from the opening 52 of the resist 51 provided on the back surface of the first insulating layer 5 are removed, and the back surface of the semiconductor 1 is removed. Expose.

  The removal of the first insulating layer 5 can be performed, for example, by wet etching using hydrofluoric acid or the like. Here, when the second insulating layer 3 is removed by wet etching using hydrofluoric acid, the intrinsic layer 4 made of i-type hydrogenated amorphous silicon can function as an etching stop layer, and the wet etching is performed. It can be stopped by the intrinsic layer 4.

  The intrinsic layer 4 can be removed by, for example, wet etching using an alkaline aqueous solution such as an aqueous tetramethylammonium hydroxide solution, an aqueous potassium hydroxide solution, or an aqueous sodium hydroxide solution. At this time, a part of the semiconductor 1 may be removed.

  Next, as shown in FIG. 17, after removing the resist 51 from the back surface of the first insulating layer 5, the exposed back surface of the semiconductor 1 and the first insulating layer 5 are covered as shown in FIG. The second intrinsic layer 61 made of i-type hydrogenated amorphous silicon is laminated by, for example, a plasma CVD method.

  Although the thickness of the 2nd intrinsic layer 61 is not specifically limited, For example, they are 1 nm or more and 5 nm or less.

  Next, as shown in FIG. 19, the n-type layer 6 is laminated on the back surface of the second intrinsic layer 61 by, for example, a plasma CVD method.

  The thickness of the n-type layer 6 is not particularly limited, but is preferably 0.1 to 3 times the thickness of the first insulating layer 5, for example. In this case, since the end portion 6a of the n-type layer 6 is easily formed, the yield is increased.

  Next, as shown in FIG. 20, the second insulating layer 3 is laminated on the back surface of the n-type layer 6 by, for example, a plasma CVD method.

  Next, as shown in FIG. 21, a resist 71 having an opening 72 is formed on the back surface of the second insulating layer 3. The resist 71 having the opening 72 can be formed by, for example, a photolithography method or a printing method.

  Next, as shown in FIG. 22, the respective portions of the second insulating layer 3, the n-type layer 6, the second intrinsic layer 61, and the first insulating layer 5 exposed from the opening 72 of the resist 71 are removed. Then, the back surface of the intrinsic layer 4 is exposed from the opening 72 of the resist 71.

  The removal of the second insulating layer 3 can be performed, for example, by wet etching using hydrofluoric acid or the like. At this time, the second insulating layer 3 can be removed by performing side etching beyond the thickness of the second insulating layer 3. Here, when the second insulating layer 3 is removed by wet etching using hydrofluoric acid, the n-type layer 6 made of n-type hydrogenated amorphous silicon can function as an etching stop layer. Can be stopped by the n-type layer 6.

  The removal of the n-type layer 6 and the second intrinsic layer 61 can be performed, for example, by wet etching using an alkaline aqueous solution such as a tetramethylammonium hydroxide aqueous solution, a potassium hydroxide aqueous solution, or a sodium hydroxide aqueous solution. At this time, the first insulating layer 5 can function as an etching stop layer, and the wet etching can be stopped by the first insulating layer 5.

  The removal of the first insulating layer 5 can be performed by, for example, wet etching using hydrofluoric acid or the like. At this time, the first insulating layer 5 can be removed by performing side etching beyond the thickness of the first insulating layer 5. In addition, when the first insulating layer 5 is removed by wet etching using hydrofluoric acid, the intrinsic layer 4 made of i-type hydrogenated amorphous silicon can function as an etching stop layer. It can be stopped at layer 4.

  Next, as shown in FIG. 23, after all the resist 71 is removed from the back surface of the second insulating layer 3, as shown in FIG. 24, the exposed back surface of the intrinsic layer 4, the end 6a of the n-type layer 6, A p-type layer 8 made of p-type hydrogenated amorphous silicon is laminated by, for example, a plasma CVD method so as to cover the second intrinsic layer 61 and the second insulating layer 3 immediately below the end 6a of the n-type layer 6.

  Although the thickness of the p-type layer 8 is not specifically limited, For example, it is 5 nm or more and 50 nm or less.

  Next, as shown in FIG. 25, a resist 81 having an opening 82 is formed on the back surface of the p-type layer 8 so as to fill the opening on the back surface side of the p-type layer 8. The resist 81 having the opening 82 can be formed by, for example, a photolithography method or a printing method.

  Next, as shown in FIG. 26, the back surface of the n-type layer 6 is exposed by removing the p-type layer 8 and the second insulating layer 3 exposed from the opening 82 of the resist 81.

  The p-type layer 8 can be removed, for example, by wet etching using a mixed solution of hydrofluoric acid and nitric acid (for example, hydrofluoric acid: nitric acid = 1: 100 in volume ratio). At this time, as long as the n-type layer 6 is not exposed, a part of the second insulating layer 3 may be removed.

  The second insulating layer 3 can be removed by, for example, wet etching using hydrofluoric acid or the like. Here, when the second insulating layer 3 is removed by wet etching using hydrofluoric acid, the n-type layer 6 made of n-type hydrogenated amorphous silicon can function as an etching stop layer. Can be stopped by the n-type layer 6.

  Next, as shown in FIG. 27, after all the resist 81 is removed from the back surface of the p-type layer 8, the conductive film is formed from the opening 82 and the opening 83 on the back surface side of the semiconductor 1 by, for example, sputtering or vapor deposition. By stacking, the first electrode 9 is formed on the n-type layer 6 and the second electrode 10 is formed on the p-type layer 8 as shown in FIG.

  As the conductive film used for forming the first electrode 9 and the second electrode 10, for example, a metal film containing at least one of silver and aluminum, or a transparent conductive film such as ITO and a metal film containing at least one of silver and aluminum A deposited film or the like can be used.

  As described above, the heterojunction back contact cell of the second embodiment can be manufactured.

  Also in the method of manufacturing the heterojunction back contact cell of the second embodiment, a notch is formed in the region below the end 6a of the n-type layer 6 in the opening 43 on the back surface side of the p-type layer 8. Therefore, the conductive film is separated by this notch, and the second electrode 10 is formed in a self-aligned manner. Therefore, since a process such as lithography and / or shadow masking is not required for patterning the second electrode 10, a heterojunction back contact cell can be easily manufactured.

  Also in the heterojunction back contact cell of the second embodiment, the end 6a of the n-type layer 6 has a notch formed only in the opening 83 on the back surface side of the p-type layer 8, so that the first electrode The electrode area of the first electrode 9 can be increased, and the parasitic resistance of the first electrode 9 can be suppressed.

  As described above, also in the second embodiment, the patterning of the n-type layer 6 and the p-type layer 8 can be performed on the first insulating layer 5 and the second insulating layer 3, respectively. Thereby, since the damage which the semiconductor 1 and the intrinsic layer 4 receive at the time of patterning of the n-type layer 6 and the p-type layer 8 can be reduced, a heterojunction type back contact cell can be manufactured with a high yield, The characteristics can be enhanced.

  Also in the second embodiment, the light incident from the light-receiving surface of the semiconductor 1 and transmitted through the semiconductor 1 can be reflected by the first electrode 9 and the second electrode 10 toward the semiconductor 1 side. Therefore, the characteristics of the heterojunction back contact cell can be improved.

  Also in the second embodiment, it is not necessary to form the n-type layer 6 and the p-type layer 8 using a shadow masking process. Thereby, since the n-type layer 6 and the p-type layer 8 can be formed with high precision, the heterojunction back contact cell can be manufactured with a high yield and the characteristics can be enhanced.

  As described above, the heterojunction back contact cell of Embodiment 2 can also be manufactured with high yield and can be a photoelectric conversion element with high characteristics.

  Further, also in the second embodiment, since the second intrinsic layer 61 containing intrinsic hydrogenated amorphous silicon is located directly under the p-type layer 8, the back surface of the semiconductor 1 by the intrinsic layer 4 is further improved. Since a good passivation effect can be obtained, it is possible to further suppress a decrease in minority carrier lifetime.

  Since the description other than the above in Embodiment 2 is the same as that in Embodiment 1, the description thereof is omitted here.

<Embodiment 3>
FIG. 28 is a schematic cross-sectional view of a heterojunction back contact cell according to Embodiment 3, which is another example of the photoelectric conversion element of the present invention. In the heterojunction back contact cell of the third embodiment, the first electrode 9 is provided on the p-type layer 8 and the second electrode 10 is provided on the n-type layer 6. 8 is characterized in that an end 8 a of 8 protrudes in the direction of the second electrode 10 from the end of the first insulating layer 5. In the heterojunction back contact cell of the third embodiment, the region 6b of the n-type layer 6 below the end portion 8a of the p-type layer 8 includes a region where the second electrode 10 is not formed.

  Hereinafter, an example of a method for manufacturing the heterojunction back contact cell according to the third embodiment will be described with reference to schematic cross-sectional views of FIGS. First, as shown in FIG. 29, the intrinsic layer 4, the n-type layer 6, and the first insulating layer 5 are stacked in this order on the back surface of the semiconductor 1. Here, intrinsic layer 4, n-type layer 6 and first insulating layer 5 can be laminated by, for example, a plasma CVD method.

  The thickness of the intrinsic layer 4 is not particularly limited, but can be, for example, 1 nm or more and 10 nm or less, and more specifically about 3 nm.

  Although the thickness of the n-type layer 6 is not specifically limited, For example, it can be 5 nm or more and 50 nm or less.

  Although the thickness of the 1st insulating layer 5 is not specifically limited, For example, they are 0.1 micrometer or more and 10 micrometers or less.

  Next, as shown in FIG. 30, a resist 91 having an opening 92 is formed on the back surface of the first insulating layer 5. The resist 91 having the opening 92 can be formed by, for example, a photolithography method or a printing method.

  Next, as shown in FIG. 31, the first insulating layer 5, the n-type layer 6 and the intrinsic layer 4 exposed from the opening 52 of the resist 51 provided on the back surface of the first insulating layer 5 are removed, The back surface of the semiconductor 1 is exposed.

  The removal of the first insulating layer 5 can be performed, for example, by wet etching using hydrofluoric acid or the like. Here, when the first insulating layer 5 is removed by wet etching using hydrofluoric acid, the intrinsic layer 4 made of n-type hydrogenated amorphous silicon can function as an etching stop layer. It can be stopped by the intrinsic layer 4.

  The n-type layer 6 and the intrinsic layer 4 can be removed, for example, by wet etching using an alkaline aqueous solution such as a tetramethylammonium hydroxide aqueous solution, a potassium hydroxide aqueous solution, or a sodium hydroxide aqueous solution. At this time, a part of the semiconductor 1 may be removed.

  Next, as shown in FIG. 32, after removing the resist 91 from the back surface of the first insulating layer 5, as shown in FIG. 33, the exposed back surface of the semiconductor 1, the side surface of the n-type layer 6, and the first insulating layer 5, a second intrinsic layer 61 made of i-type hydrogenated amorphous silicon is stacked by, for example, a plasma CVD method.

  Although the thickness of the 2nd intrinsic layer 61 is not specifically limited, For example, they are 3 nm or more and 10 nm or less.

  Next, as shown in FIG. 34, the p-type layer 8 is laminated on the back surface of the second intrinsic layer 61 by, for example, a plasma CVD method.

  The thickness of the p-type layer 8 is not particularly limited, but is preferably 0.1 to 3 times the thickness of the first insulating layer 5. In this case, since the end portion 8a of the p-type layer 8 is easily formed, the yield is increased.

  Next, as shown in FIG. 35, a resist 201 having an opening 202 is formed on the back surface of the p-type layer 8. The resist 201 having the opening 202 can be formed by, for example, a photolithography method or a printing method.

  Next, as shown in FIG. 36, the openings of the resist 201 are removed by removing the respective portions of the p-type layer 8, the second intrinsic layer 61, and the first insulating layer 5 exposed from the opening 202 of the resist 201. The back surface of the n-type layer 6 is exposed from the portion 202.

  The p-type layer 8 can be removed, for example, by wet etching using a mixed solution of hydrofluoric acid, nitric acid and acetic acid. By adjusting the volume ratio of hydrofluoric acid, nitric acid and acetic acid in the mixed solution, the etching rate of the mixed solution with respect to the p-type layer 8 is made larger than the etching rate with respect to the second intrinsic layer 61, so that the second intrinsic The layer 61 can function as an etching stop layer. The volume ratio of hydrofluoric acid, nitric acid, and acetic acid in such a mixed solution can be, for example, hydrofluoric acid: nitric acid: acetic acid = 1: 3: 8. At this time, as long as the n-type layer 6 is not exposed, a part of the first insulating layer 5 may be removed.

  The removal of the second intrinsic layer 61 can be performed, for example, by wet etching using an alkaline aqueous solution such as a tetramethylammonium hydroxide aqueous solution, a potassium hydroxide aqueous solution, or a sodium hydroxide aqueous solution. At this time, since the first insulating layer 5 can function as an etching stop layer, the wet etching can be stopped by the first insulating layer 5.

  The first insulating layer 5 can be removed by, for example, wet etching using hydrofluoric acid or the like. At this time, the end portion 8a of the p-type layer 8 can be formed by performing side etching beyond the thickness of the first insulating layer 5 and removing the first insulating layer 5. When the first insulating layer 5 is removed by wet etching using hydrofluoric acid, the n-type layer 6 made of n-type hydrogenated amorphous silicon can function as an etching stop layer. It can be stopped by the n-type layer 6.

  Next, as shown in FIG. 37, after all the resist 81 is removed from the back surface of the p-type layer 8, the conductive film is formed from the opening 202 and the opening 203 on the back surface side of the semiconductor 1 by, for example, sputtering or vapor deposition. By stacking, the second electrode 10 is formed on the n-type layer 6 and the first electrode 9 is formed on the p-type layer 8 as shown in FIG.

  As the conductive film used for forming the first electrode 9 and the second electrode 10, for example, a metal film containing at least one of silver and aluminum, or a transparent conductive film such as ITO and a metal film containing at least one of silver and aluminum A deposited film or the like can be used.

  As described above, the heterojunction back contact cell of the third embodiment can be manufactured.

  In the method of manufacturing the heterojunction back contact cell according to the third embodiment, the notch is formed in the region 6b of the n-type layer 6 below the end 8a of the p-type layer 8. Are separated, and the second electrode 10 is formed in a self-aligned manner. Therefore, since a process such as lithography and / or shadow masking is not required for patterning the second electrode 10, a heterojunction back contact cell can be easily manufactured.

  Also in the heterojunction back contact cell of the third embodiment, the end 8a of the p-type layer 8 has a notch formed only in the opening on the back surface side of the n-type layer 6, so that the first electrode 9 The electrode area of the first electrode 9 can be increased, and the parasitic resistance of the first electrode 9 can be suppressed.

  Further, as described above, in the third embodiment, the p-type layer 8 can be patterned on the first insulating layer 5. As a result, the damage to the semiconductor 1 and the intrinsic layer 4 during the patterning of the p-type layer 8 can be reduced, so that the heterojunction back contact cell can be manufactured with a high yield and its characteristics are enhanced. be able to.

  Also in the third embodiment, the light incident from the light-receiving surface of the semiconductor 1 and transmitted through the semiconductor 1 can be reflected by the first electrode 9 and the second electrode 10 toward the semiconductor 1 side. Therefore, the characteristics of the heterojunction back contact cell can be improved.

  Also in the third embodiment, it is not necessary to form the n-type layer 6 and the p-type layer 8 using a shadow masking process. Thereby, since the n-type layer 6 and the p-type layer 8 can be formed with high precision, the heterojunction back contact cell can be manufactured with a high yield and the characteristics can be enhanced.

  Also in the third embodiment, since the second intrinsic layer 61 containing intrinsic hydrogenated amorphous silicon is located immediately below the p-type layer 8, the back surface of the semiconductor 1 by the intrinsic layer 4 is further improved. Since a good passivation effect can be obtained, it is possible to further suppress a decrease in minority carrier lifetime.

  As described above, the heterojunction back contact cell of Embodiment 3 can also be manufactured with high yield and can be a photoelectric conversion element with high characteristics.

  Since the description other than the above in the third embodiment is the same as that in the first and second embodiments, the description thereof is omitted here.

  Hereinafter, as another aspect of the present invention, a photoelectric conversion module (Embodiment 4) and a photovoltaic power generation system (Embodiment 5 and Embodiment 6) each including the heterojunction back contact cell according to Embodiments 1 to 3 will be described. explain.

  Since the heterojunction back contact cell of Embodiments 1 to 3 has high characteristics, the photoelectric conversion module and the photovoltaic power generation system including the same also have high characteristics.

<Embodiment 4>
The fourth embodiment is a photoelectric conversion module using the heterojunction back contact cell of the first to third embodiments as a photoelectric conversion element.

<Photoelectric conversion module>
FIG. 39 shows an outline of the configuration of the photoelectric conversion module of the fourth embodiment which is an example of the photoelectric conversion module of the present invention using the heterojunction back contact cell of the first to third embodiments as a photoelectric conversion element. Referring to FIG. 39, the photoelectric conversion module 1000 according to Embodiment 4 includes a plurality of photoelectric conversion elements 1001, a cover 1002, and output terminals 1013 and 1014.

  The plurality of photoelectric conversion elements 1001 are arranged in an array and connected in series. FIG. 39 illustrates an arrangement in which the photoelectric conversion elements 1001 are connected in series. However, the arrangement and the connection method are not limited to this, and the photoelectric conversion elements 1001 may be connected in parallel. The series and the parallel may be combined. It may be an array. For each of the plurality of photoelectric conversion elements 1001, the heterojunction back contact cell according to any of Embodiments 1 to 3 is used. The photoelectric conversion module 1000 is not limited to the above description as long as at least one of the plurality of photoelectric conversion elements 1001 includes any one of the photoelectric conversion elements of Embodiments 1 to 3. The photoelectric conversion module 1000 may have any configuration. . Further, the number of photoelectric conversion elements 1001 included in the photoelectric conversion module 1000 can be any integer of 2 or more.

  The cover 1002 is composed of a weather resistant cover and covers the plurality of photoelectric conversion elements 1001. The cover 1002 is, for example, a transparent base material (for example, glass) provided on the light receiving surface side of the photoelectric conversion element 1001 and a back surface base material provided on the back surface side opposite to the light receiving surface side of the photoelectric conversion element 1001. (For example, glass, resin sheet or the like) and a sealing material (for example, EVA (ethylene vinyl acetate) or the like) that fills the space between the transparent substrate and the back substrate.

  The output terminal 1013 is connected to the photoelectric conversion element 1001 arranged at one end of the plurality of photoelectric conversion elements 1001 connected in series.

  The output terminal 1014 is connected to the photoelectric conversion element 1001 arranged at the other end of the plurality of photoelectric conversion elements 1001 connected in series.

<Embodiment 5>
Embodiment 5 is a photovoltaic power generation system using the heterojunction back contact cell of Embodiments 1 to 3 as a photoelectric conversion element. Since the photoelectric conversion element of the present invention has high characteristics (such as conversion efficiency), the photovoltaic power generation system of the present invention including the photoelectric conversion element can also have high characteristics. Note that the photovoltaic power generation system is a device that appropriately converts the power output from the photoelectric conversion module and supplies it to a commercial power system or an electric device.

<Solar power generation system>
A solar power generation system is a device that converts power output from a photoelectric conversion module as appropriate and supplies it to a commercial power system or an electrical device.

  In FIG. 40, the outline of the structure of the solar power generation system of Embodiment 5 which is an example of the solar power generation system of this invention which used the heterojunction type | mold back contact cell of Embodiment 1-3 as a photoelectric conversion element is shown. . Referring to FIG. 40, the photovoltaic power generation system 2000 of the fifth embodiment includes a photoelectric conversion module array 2001, a connection box 2002, a power conditioner 2003, a distribution board 2004, and a power meter 2005. As described later, the photoelectric conversion module array 2001 includes a plurality of photoelectric conversion modules 1000 (Embodiment 4).

  The solar power generation system 2000 is generally added with functions such as “Home Energy Management System (HEMS)” and “Building Energy Management System (BEMS)”. be able to. Thereby, it is possible to reduce energy consumption by monitoring the power generation amount of the solar power generation system 2000, monitoring / controlling the power consumption amount of each electrical device connected to the solar power generation system 2000, and the like. .

  The connection box 2002 is connected to the photoelectric conversion module array 2001. The power conditioner 2003 is connected to the connection box 2002. Distribution board 2004 is connected to power conditioner 2003 and electrical equipment 2011. The power meter 2005 is connected to the distribution board 2004 and the commercial power system. As shown in FIG. 43, a storage battery 2100 may be connected to the power conditioner 2003. In this case, output fluctuations due to fluctuations in the amount of sunshine can be suppressed, and power stored in the storage battery 2100 can be supplied to the electrical equipment 2011 or the commercial power system even in a time zone without sunshine. Further, the storage battery 2100 may be built in the power conditioner 2003.

<Operation>
The photovoltaic power generation system 2000 of the fifth embodiment operates as follows, for example.

  The photoelectric conversion module array 2001 converts sunlight into electricity to generate DC power, and supplies the DC power to the connection box 2002.

  The connection box 2002 receives DC power generated by the photoelectric conversion module array 2001 and supplies the DC power to the power conditioner 2003.

  The power conditioner 2003 converts the DC power received from the connection box 2002 into AC power and supplies it to the distribution board 2004. Note that a part of the DC power received from the connection box 2002 may be supplied to the distribution board 2004 as it is without being converted to AC power. 43, when the storage battery 2100 is connected to the power conditioner 2003 (or when the storage battery 2100 is built in the power conditioner 2003), the power conditioner 2003 is received from the connection box 2002. A part or all of the DC power can be appropriately converted to be stored in the storage battery 2100. The power stored in the storage battery 2100 is appropriately supplied to the power conditioner 2003 according to the amount of power generated by the photoelectric conversion module and the power consumption of the electrical equipment 2011, and is appropriately converted to the distribution board 2004. Supplied.

  The distribution board 2004 supplies at least one of the power received from the power conditioner 2003 and the commercial power received via the power meter 2005 to the electrical equipment 2011. The distribution board 2004 supplies the AC power received from the power conditioner 2003 to the electrical equipment 2011 when the AC power received from the power conditioner 2003 is larger than the power consumption of the electrical equipment 2011. The surplus AC power is supplied to the commercial power system via the power meter 2005.

  Further, the distribution board 2004 electrically converts the AC power received from the commercial power system and the AC power received from the power conditioner 2003 when the AC power received from the power conditioner 2003 is less than the power consumption of the electrical equipment 2011. Supplied to the equipment 2011.

  The power meter 2005 measures the power in the direction from the commercial power system to the distribution board 2004, and measures the power in the direction from the distribution board 2004 to the commercial power system.

<Photoelectric conversion module array>
The photoelectric conversion module array 2001 will be described.

  FIG. 41 shows an outline of an example of the configuration of the photoelectric conversion module array 2001 shown in FIG. Referring to FIG. 41, a photoelectric conversion module array 2001 includes a plurality of photoelectric conversion modules 1000 and output terminals 2013 and 2014.

  The plurality of photoelectric conversion modules 1000 are arranged in an array and connected in series. FIG. 41 illustrates an arrangement in which the photoelectric conversion modules 1000 are connected in series. However, the arrangement and connection method are not limited to this, and the photoelectric conversion modules 1000 may be arranged in parallel or may be combined in series and parallel. It is good also as an arrangement. Note that the number of photoelectric conversion modules 1000 included in the photoelectric conversion module array 2001 can be any integer of 2 or more.

  The output terminal 2013 is connected to the photoelectric conversion module 1000 located at one end of the plurality of photoelectric conversion modules 1000 connected in series.

  The output terminal 2014 is connected to the photoelectric conversion module 1000 located at the other end of the plurality of photoelectric conversion modules 1000 connected in series.

  In addition, the above description is an example to the last, and the solar power generation system of Embodiment 5 is the above description as long as it includes at least one of the heterojunction back contact cells of Embodiments 1 to 3 as a photoelectric conversion element. It is not limited to this, and any configuration can be taken.

<Embodiment 6>
The sixth embodiment is a photovoltaic power generation system that is larger than the photovoltaic power generation system described as the fifth embodiment. The solar power generation system of the sixth embodiment also includes at least one of the heterojunction back contact cells of the first to third embodiments as a photoelectric conversion element. Since the photoelectric conversion element of the present invention has high characteristics (such as conversion efficiency), the photovoltaic power generation system of the present invention including the photoelectric conversion element can also have high characteristics.

<Large-scale solar power generation system>
FIG. 42 shows an outline of the configuration of the photovoltaic power generation system according to Embodiment 6, which is an example of the large-scale photovoltaic power generation system of the present invention. Referring to FIG. 42, solar power generation system 4000 of the sixth embodiment includes a plurality of subsystems 4001, a plurality of power conditioners 4003, and a transformer 4004. The photovoltaic power generation system 4000 is a larger scale photovoltaic power generation system than the photovoltaic power generation system 2000 of the fifth embodiment shown in FIG.

  The plurality of power conditioners 4003 are each connected to the subsystem 4001. In the photovoltaic power generation system 4000, the number of the power conditioners 4003 and the subsystems 4001 connected thereto can be any integer of 2 or more. As shown in FIG. 44, a storage battery 4100 may be connected to the power conditioner 4003. In this case, output fluctuation due to fluctuations in the amount of sunshine can be suppressed, and power stored in the storage battery 4100 can be supplied even in a time zone without sunshine. Further, the storage battery 4100 may be built in the power conditioner 4003.

  The transformer 4004 is connected to a plurality of power conditioners 4003 and a commercial power system.

  Each of the plurality of subsystems 4001 includes a plurality of module systems 3000. The number of module systems 3000 in the subsystem 4001 can be any integer greater than or equal to two.

  Each of the plurality of module systems 3000 includes a plurality of photoelectric conversion module arrays 2001, a plurality of connection boxes 3002, and a current collection box 3004. The number of the junction box 3002 in the module system 3000 and the photoelectric conversion module array 2001 connected to the junction box 3002 can be any integer of 2 or more.

  The current collection box 3004 is connected to a plurality of connection boxes 3002. The power conditioner 4003 is connected to a plurality of current collection boxes 3004 in the subsystem 4001.

<Operation>
Solar power generation system 4000 of the sixth embodiment operates as follows, for example.

  The plurality of photoelectric conversion module arrays 2001 of the module system 3000 convert sunlight into electricity to generate DC power, and supply the DC power to the current collection box 3004 via the connection box 3002. A plurality of current collection boxes 3004 in the subsystem 4001 supplies DC power to the power conditioner 4003. Further, the plurality of power conditioners 4003 convert DC power into AC power and supply the AC power to the transformer 4004. 44, when the storage battery 4100 is connected to the power conditioner 4003 (or when the storage battery 4100 is built in the power conditioner 4003), the power conditioner 4003 is received from the current collection box 3004. In addition, a part or all of the direct current power can be appropriately converted to be stored in the storage battery 4100. The electric power stored in the storage battery 4100 is appropriately supplied to the power conditioner 4003 side according to the power generation amount of the subsystem 4001, appropriately converted into electric power, and supplied to the transformer 4004.

  The transformer 4004 converts the voltage level of the AC power received from the plurality of power conditioners 4003 and supplies it to the commercial power system.

  Note that the photovoltaic power generation system 4000 only needs to include at least one of the heterojunction back contact cells of Embodiments 1 to 3 as a photoelectric conversion element, and all the photoelectric generation systems included in the photovoltaic power generation system 4000 can be used. The conversion element may not be the heterojunction back contact cell of the first to third embodiments. For example, all of the photoelectric conversion elements included in one subsystem 4001 are the heterojunction back contact cells of Embodiments 1 to 3, and some or all of the photoelectric conversion elements included in another subsystem 4001 are implemented. In some cases, the heterojunction back contact cell of the first to third embodiments may not be used.

<Summary>
The present invention relates to a semiconductor, an intrinsic layer containing hydrogenated amorphous silicon provided on the semiconductor, a first conductivity type layer containing hydrogenated amorphous silicon of the first conductivity type provided on the intrinsic layer, , A second conductivity type layer containing hydrogenated amorphous silicon of the second conductivity type, an insulating layer, a first electrode provided on the first conductivity type layer, and a first electrode provided on the second conductivity type layer. The photoelectric conversion element is provided with two electrodes, and the end portion of the first conductivity type layer protrudes from the end of the insulating layer in the direction of the second electrode. With such a structure, a photoelectric conversion element that can be manufactured with high yield and has high characteristics can be obtained.

  In the photoelectric conversion element of the present invention, it is preferable that the region of the second conductivity type layer below the end of the first conductivity type layer includes a region where the second electrode is not formed. With this configuration, the second electrode can be formed in a self-aligned manner by forming a notch in the opening on the back surface side of the second conductivity type layer by the end portion of the first conductivity type layer. Therefore, the heterojunction back contact cell can be manufactured with a high yield.

  Moreover, in the photoelectric conversion element of this invention, it is preferable that the edge part of a 1st conductivity type layer is covered with the 2nd conductivity type layer. With this configuration, the second electrode can be formed in a self-aligned manner by stably forming a notch in the region of the second conductivity type layer below the end of the first conductivity type layer. Therefore, the heterojunction back contact cell can be manufactured with a higher yield.

  Moreover, in the photoelectric conversion element of this invention, it is preferable that an insulating layer contains a silicon nitride or a silicon oxide. With such a configuration, the intrinsic layer can function as an etching stop layer in the wet etching of the insulating layer, so that the side etching more than the thickness of the first insulating layer can be easily performed.

  Moreover, in the photoelectric conversion element of this invention, it is preferable that the 2nd insulating layer is provided on the 1st conductivity type layer. With such a configuration, the first conductive type layer and the second conductive type layer can be insulated in the thickness direction by the second insulating layer.

  In the photoelectric conversion element of the present invention, the second insulating layer preferably contains silicon nitride or silicon oxide. By adopting such a configuration, the first conductivity type layer can function as an etching stop layer in the wet etching of the second insulating layer, so that the side etching more than the thickness of the second insulating layer can be easily performed. Can do.

  In the photoelectric conversion element of the present invention, it is preferable that the semiconductor is the first conductivity type, the first conductivity type is n-type, and the second conductivity type is p-type. By adopting such a configuration, it is possible to increase the electrode area of the first electrode on the first conductivity type layer, which is likely to be narrower than the width of the second conductivity type layer, and to suppress the parasitic resistance of the first electrode. it can.

  In the photoelectric conversion element of the present invention, it is preferable that a second intrinsic layer containing intrinsic hydrogenated amorphous silicon is located immediately below the first conductivity type layer or directly below the second conductivity type layer. With such a configuration, it is possible to obtain a further favorable passivation effect on the back surface of the semiconductor by the intrinsic layer, and thus it is possible to further suppress a decrease in minority carrier lifetime.

  As described above, the embodiments of the present invention have been described, but it is also planned from the beginning to appropriately combine the configurations of the above-described embodiments.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  INDUSTRIAL APPLICATION This invention can be utilized for the manufacturing method of a photoelectric conversion element and a photoelectric conversion element, and can be suitably used especially for the manufacturing method of a heterojunction type back contact cell and a heterojunction type back contact cell.

  1 semiconductor, 3 second insulating layer, 4 intrinsic layer, 5 first insulating layer, 6 n-type layer, 6a end, 6b region, 8 p-type layer, 8a end, 8b region, 9 first electrode, 10 first 2 electrodes, 21 resists, 22 openings, 31 resists, 32 openings, 41 resists, 42 openings, 43 openings, 51 resists, 52 openings, 61 second intrinsic layer, 71 resists, 72 openings, 81 resists , 82 opening, 83 opening, 91 resist, 92 opening, 101 crystalline silicon wafer, 102 intrinsic hydrogenated amorphous silicon transition layer, 103 n doped region, 104 p doped region, 105 aluminum electrode, 201 resist, 202 opening , 203 opening, 1000 photoelectric conversion module, 1001 photoelectric conversion element, 1002 cover, 1013, 1 14 output terminal, 2000 photovoltaic power generation system, 2001 photoelectric conversion module array, 2002 connection box, 2003 power conditioner, 2004 distribution board, 2005 power meter, 2011 electrical equipment, 2013, 2014 output terminal, 2100 storage battery, 3000 module System, 3002 Junction box, 3004 Current collection box, 4000 Solar power generation system, 4001 Subsystem, 4003 Power conditioner, 4004 Transformer, 4100 Storage battery.

Claims (5)

Semiconductors,
An intrinsic layer containing hydrogenated amorphous silicon provided on the semiconductor;
A first conductivity type layer containing hydrogenated amorphous silicon of the first conductivity type, a second conductivity type layer containing hydrogenated amorphous silicon of the second conductivity type, and an insulating layer provided on the intrinsic layer; ,
A first electrode provided on the first conductivity type layer;
A second electrode provided on the second conductivity type layer,
The photoelectric conversion element, wherein an end portion of the first conductivity type layer protrudes from an end of the insulating layer toward the second electrode.   2. The photoelectric conversion element according to claim 1, wherein a region of the second conductivity type layer below the end portion of the first conductivity type layer includes a region where the second electrode is not formed.   The photoelectric conversion element according to claim 1 or 2, wherein the end portion of the first conductivity type layer is covered with the second conductivity type layer.   The photoelectric conversion element according to claim 1, wherein the insulating layer contains silicon nitride or silicon oxide. The semiconductor is of a first conductivity type;
5. The photoelectric conversion element according to claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.

Images