WO2016163168A1 - Photoelectric conversion element - Google Patents

Abstract

This photoelectric conversion element is provided with: a semiconductor substrate (1); an n-type amorphous semiconductor layer (4), which is formed on the semiconductor substrate (1), and which has a first conductivity type; a p-type amorphous semiconductor layer (5), which is formed adjacent to the n-type amorphous semiconductor layer (4) in the in-plane direction of the semiconductor substrate (1), and which has a second conductivity type that is the opposite conductivity type to the first conductivity type; an electrode (6) formed on the n-type amorphous semiconductor layer (4); an electrode (7) formed on the p-type amorphous semiconductor layer (5) by having a gap region between the electrode (6) and the electrode (7); and a reflecting layer (9) formed at least on the gap region. The electrode (6) and/or the electrode (7) is a translucent electrode that passes light.

Description

Photoelectric conversion element

The present invention relates to a photoelectric conversion element.

Conventionally, intrinsic (i-type) amorphous silicon is interposed between an n-type crystalline silicon substrate and a p-type amorphous silicon layer to reduce defects at the interface, and characteristics at the heterojunction interface. There is known a photoelectric conversion device with improved characteristics. This photoelectric conversion device is called a heterojunction solar cell.

A heterojunction solar cell described in International Publication No. 2013/133005 is shown in FIG. An n-electrode 1506 and a p-electrode 1507 are formed on the n-type amorphous semiconductor layer 1503 and the p-type amorphous semiconductor layer 1505, respectively. In the heterojunction solar cell, electrons which are majority carriers generated in the silicon substrate are diffused into the n-type amorphous semiconductor layer 1503 and collected by the n-electrode 1506. Further, holes that are minority carriers diffuse into the p-type amorphous semiconductor layer 1505 and are collected by the p-electrode 1507.

In the solar cell shown in FIG. 34, an n-type amorphous semiconductor layer 1503 and a p-type amorphous semiconductor layer 1505 are formed on the back surface opposite to the light receiving surface. A heterojunction solar cell in which an n-type amorphous semiconductor layer and a p-type amorphous semiconductor layer are thus formed on the back surface is referred to as a back surface heterojunction solar cell.

However, in the backside heterojunction solar cell described in International Publication No. 2013/133005, light can be received only from the light-receiving surface, and the region between the n-electrode 1506 and the p-electrode 1507 There is a problem that light that is incident on the light and transmitted to the back surface does not contribute to power generation.

In an embodiment of the present invention, a photoelectric conversion element that can receive light on both sides and increase power generation efficiency is provided.
The photoelectric conversion element in one embodiment of the present invention includes a semiconductor substrate, a first amorphous semiconductor layer formed on the semiconductor substrate and having a first conductivity type, and the in-plane direction of the semiconductor substrate. A second amorphous semiconductor layer formed adjacent to the first amorphous semiconductor layer and having a second conductivity type opposite to the first conductivity type; and the first amorphous semiconductor layer A first electrode formed thereon and a second electrode formed on the second amorphous semiconductor layer with a gap region between the first electrode and at least the gap region; And at least one of the first electrode and the second electrode is a translucent electrode that transmits light.

According to the embodiment of the present invention, by using at least one of the first electrode and the second electrode as a translucent electrode, it is possible to receive light on both sides, so that power generation efficiency can be improved. In addition, by providing a reflective layer on at least the gap region, the light incident on the gap region is reflected by the reflective layer and returns to the semiconductor substrate, increasing the proportion of light absorbed by the semiconductor substrate and improving power generation efficiency. it can.

1 is a cross-sectional view showing a configuration of a photoelectric conversion element according to Embodiment 1 of the present invention. FIG. 2 is an enlarged view of the translucent electrode, the protective film, and the conductive reflective layer shown in FIG. FIG. 3 is a diagram showing a texture structure in which a plurality of pyramidal irregularities having various sizes and shapes are formed. FIG. 4 is a diagram illustrating the relationship between the texture size of the back surface of the semiconductor substrate and the reverse saturation current density. FIG. 5 is a cross-sectional view showing a detailed structure of the n-type amorphous semiconductor layer shown in FIG. FIG. 6 is a cross-sectional view showing another detailed structure of the n-type amorphous semiconductor layer shown in FIG. FIG. 7 is a first process diagram showing a method for manufacturing the photoelectric conversion element shown in FIG. 1. FIG. 8 is a second process diagram illustrating a method for manufacturing the photoelectric conversion element illustrated in FIG. 1. FIG. 9 is a third process diagram illustrating a method for manufacturing the photoelectric conversion element illustrated in FIG. 1. FIG. 10 is a fourth process diagram illustrating the method of manufacturing the photoelectric conversion element shown in FIG. FIG. 11 is a fifth process diagram illustrating the method for manufacturing the photoelectric conversion element illustrated in FIG. 1. FIG. 12 is a view showing an SEM photograph of a semiconductor substrate on which texture structures having different sizes are formed. FIG. 13 is a plan view seen from the back side of the photoelectric conversion element shown in FIG. FIG. 14 is a plan view of the wiring sheet. FIG. 15 is a diagram showing the results of a moisture-proof resistance test. FIG. 16 is a diagram for explaining the inclination angle of the texture. FIG. 17 is a diagram for explaining that a semiconductor layer and a dopant wrap around under a shadow mask when an n-type amorphous semiconductor layer and a p-type amorphous semiconductor layer are patterned. FIG. 18 is a diagram for explaining a void region between a semiconductor substrate on which a texture is formed and a shadow mask. FIG. 19 is a diagram for explaining that boron, which is a p-type dopant, wraps around inward from the edge of the shadow mask. FIG. 20 is a diagram for explaining that the wraparound width of boron varies depending on the texture size. FIG. 21 is a cross-sectional view showing the configuration of the photoelectric conversion element according to Embodiment 2 of the present invention. 22 is a diagram showing a manufacturing process different from the manufacturing method of the photoelectric conversion element shown in FIG. 1 among the manufacturing methods of the photoelectric conversion element shown in FIG. FIG. 23 is a diagram illustrating a manufacturing process subsequent to the manufacturing process illustrated in FIG. 22. FIG. 24 is a cross-sectional view showing the configuration of the photoelectric conversion element according to Embodiment 3 of the present invention. FIG. 25 is a schematic diagram illustrating a configuration of a cluster-type CVD apparatus. FIG. 26 is a cross-sectional view showing a configuration of a photoelectric conversion element according to Embodiment 5 of the present invention. 27 is a diagram showing a manufacturing process different from the manufacturing method of the photoelectric conversion element shown in FIG. 1 among the manufacturing methods of the photoelectric conversion element shown in FIG. FIG. 28 is a schematic diagram illustrating a configuration of a photoelectric conversion module including the photoelectric conversion element according to the fifth embodiment. FIG. 29 is a schematic diagram illustrating a configuration of a photovoltaic power generation system including the photoelectric conversion element according to the sixth embodiment. 30 is a schematic diagram showing the configuration of the photoelectric conversion module array shown in FIG. FIG. 31 is a schematic diagram illustrating a configuration of another photovoltaic power generation system including the photoelectric conversion element according to the sixth embodiment. FIG. 32 is a schematic diagram illustrating a configuration of a photovoltaic power generation system including the photoelectric conversion element according to the seventh embodiment. FIG. 33 is a schematic diagram illustrating a configuration of another photovoltaic power generation system including the photoelectric conversion element according to the seventh embodiment. FIG. 34 is a cross-sectional view showing a heterojunction solar cell described in International Publication No. 2013/133005.

The photoelectric conversion element in one embodiment of the present invention includes a semiconductor substrate, a first amorphous semiconductor layer formed on the semiconductor substrate and having a first conductivity type, and the in-plane direction of the semiconductor substrate. A second amorphous semiconductor layer formed adjacent to the first amorphous semiconductor layer and having a second conductivity type opposite to the first conductivity type; and the first amorphous semiconductor layer A first electrode formed thereon and a second electrode formed on the second amorphous semiconductor layer with a gap region between the first electrode and at least the gap region; And at least one of the first electrode and the second electrode is a translucent electrode that transmits light (first configuration).

According to the first configuration, since at least one of the first electrode and the second electrode is a translucent electrode, it is possible to receive light on both sides, and thus power generation efficiency is improved. In addition, by providing a reflective layer on the gap region, light incident on the gap region is reflected by the reflective layer and returns to the semiconductor substrate, so that the proportion of light absorbed by the semiconductor substrate increases and power generation efficiency is improved. .

In the first configuration, the reflective layer may have conductivity and may be in contact with the first electrode or the second electrode (second configuration).

According to the second configuration, the reflection layer formed on the gap region is used as the first electrode or the electrode electrically connected to the second electrode, and the current obtained by power generation is extracted from the reflection layer. be able to.

In the first or second configuration, a texture is formed on at least one surface of the semiconductor substrate, and the first amorphous semiconductor layer and the first surface are formed on the surface of the semiconductor substrate on which the texture is formed. Two amorphous semiconductor layers may be formed (third configuration).

According to the third configuration, incident light from the surface on which the texture is formed is not easily reflected, and the proportion of light absorbed by the semiconductor substrate is increased, so that power generation efficiency is improved.

In the first to third configurations, the reflective layer is also formed on a part of the first electrode and a part of the second electrode, and the part of the first electrode and the part of the second electrode You may make it further provide the protective film formed between a part of 2nd electrode and the said reflection layer (4th structure).

According to the fourth configuration, since the first electrode and the second electrode can be structurally and electrically protected by the protective film, the reliability is improved.

In the fourth configuration, each of the first electrode and the second electrode may be covered with the protective film and the reflective layer (fifth configuration).

According to the fifth configuration, since the first electrode and the second electrode can be structurally and electrically protected by the protective film and the reflective layer, the reliability is further improved.

[Embodiment]
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated. In addition, in order to make the explanation easy to understand, in the drawings referred to below, the configuration is shown in a simplified or schematic manner, or some components are omitted. Further, the dimensional ratio between the constituent members shown in each drawing does not necessarily indicate an actual dimensional ratio.

In this specification, the amorphous semiconductor layer may contain a microcrystalline phase. The microcrystalline phase includes crystals having an average particle size of 1 to 50 nm.

[Embodiment 1]
1 is a cross-sectional view showing a configuration of a photoelectric conversion element according to Embodiment 1 of the present invention. Referring to FIG. 1, a photoelectric conversion element 10 according to Embodiment 1 of the present invention includes a semiconductor substrate 1, an antireflection film 2, a passivation film 3, an n-type amorphous semiconductor layer 4, and a p-type non-layer. A crystalline semiconductor layer 5, translucent electrodes 6, 7, a protective film 8, and a conductive reflective layer 9 are provided.

The semiconductor substrate 1 is made of, for example, an n-type single crystal silicon substrate. The semiconductor substrate 1 has a thickness of 100 to 150 μm, for example. The semiconductor substrate 1 has a texture structure formed on both sides.

The antireflection film 2 is disposed in contact with one surface (light receiving surface) of the semiconductor substrate 1. Of the two surfaces of the semiconductor substrate 1, since sunlight is mainly incident from the surface on the side where the antireflection film 2 is disposed, the surface on which the antireflection film 2 is disposed is referred to as a light receiving surface. Of the two surfaces of the semiconductor substrate 1, the surface opposite to the light receiving surface is referred to as the back surface. However, the photoelectric conversion element 10 according to the present embodiment is a double-sided light receiving type in which sunlight can enter from the back side.

Note that an intrinsic amorphous semiconductor layer or an n-type or p-type amorphous semiconductor layer may be provided between the antireflection film 2 and the light-receiving surface of the semiconductor substrate 1. This configuration is preferable because the passivation property of the light receiving surface can be improved.

The passivation film 3 is disposed in contact with the back surface of the semiconductor substrate 1.

The n-type amorphous semiconductor layer 4 is disposed in contact with the passivation film 3.

The p-type amorphous semiconductor layer 5 is disposed adjacent to the n-type amorphous semiconductor layer 4 in the in-plane direction of the semiconductor substrate 1. More specifically, the p-type amorphous semiconductor layer 5 is arranged at a desired distance from the n-type amorphous semiconductor layer 4 in the in-plane direction of the semiconductor substrate 1.

The n-type amorphous semiconductor layers 4 and the p-type amorphous semiconductor layers 5 are alternately arranged in the in-plane direction of the semiconductor substrate 1.

The translucent electrode 6 is disposed on the n-type amorphous semiconductor layer 4 in contact with the n-type amorphous semiconductor layer 4.

The translucent electrode 7 is disposed on the p-type amorphous semiconductor layer 5 in contact with the p-type amorphous semiconductor layer 5.

The protective film 8 is disposed in contact with the passivation film 3, the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5, and the translucent electrodes 6 and 7. More specifically, the protective film 8 is provided between the adjacent n-type amorphous semiconductor layer 4 and p-type amorphous semiconductor layer 5 and between the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5, and the transparent layer. In contact with part of the photoelectrodes 6 and 7, and in contact with part of the passivation film 3 disposed between the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5. Be placed. The protective film 8 has an opening 8A on the translucent electrodes 6 and 7, and is formed in an area of 5 μm or more from the end of the translucent electrodes 6 and 7 toward the inside of the translucent electrodes 6 and 7. It is formed.

The conductive reflective layer 9 includes a conductive reflective layer 9a and a conductive reflective layer 9b.

The conductive reflective layer 9a is disposed at least on the gap region G described later. More specifically, the conductive reflective layer 9a is disposed in contact with a part of the protective film 8, and is disposed in contact with a part of the translucent electrode 6 that is not covered with the protective film 8. Is done.

The conductive reflective layer 9b is disposed on at least a gap region G described later. More specifically, the conductive reflective layer 9b is disposed in contact with a part of the protective film 8, and is disposed in contact with a part of the translucent electrode 7 that is not covered with the protective film 8. Is done.

The antireflection film 2 is made of, for example, a silicon nitride film and has a film thickness of, for example, 60 nm.

The passivation film 3 is made of, for example, amorphous silicon, amorphous silicon oxide, amorphous silicon nitride, amorphous silicon oxynitride, or polycrystalline silicon.

In the case where the passivation film 3 is made of an oxide of amorphous silicon, the passivation film 3 may be made of a thermal oxide film of silicon or formed by a vapor phase growth method such as a plasma CVD (Chemical Vapor Deposition) method. It may be made of a silicon oxide.

The passivation film 3 has a thickness of 1 to 20 nm, for example, and preferably has a thickness of 1 to 3 nm. When the passivation film 3 is made of a silicon insulating film, the passivation film 3 has a film thickness that allows carriers (electrons and holes) to tunnel. In the first embodiment, the passivation film 3 is made of a thermal oxide film of silicon, and the thickness of the passivation film 3 is set to 2 nm.

The n-type amorphous semiconductor layer 4 is an amorphous semiconductor layer having n-type conductivity and containing hydrogen. The n-type amorphous semiconductor layer 4 includes, for example, n-type amorphous silicon, n-type amorphous silicon germanium, n-type amorphous germanium, n-type amorphous silicon carbide, and n-type amorphous silicon nitride. N-type amorphous silicon oxide, n-type amorphous silicon oxynitride, n-type amorphous silicon carbon oxide, and the like.

The n-type amorphous semiconductor layer 4 includes, for example, phosphorus (P) as an n-type dopant. The n-type amorphous semiconductor layer 4 has a thickness of 3 to 50 nm, for example.

The p-type amorphous semiconductor layer 5 is an amorphous semiconductor layer having p-type conductivity and containing hydrogen. The p-type amorphous semiconductor layer 5 includes, for example, p-type amorphous silicon, p-type amorphous silicon germanium, p-type amorphous germanium, p-type amorphous silicon carbide, and p-type amorphous silicon nitride. , P-type amorphous silicon oxide, p-type amorphous silicon oxynitride, p-type amorphous silicon carbon oxide, and the like.

The p-type amorphous semiconductor layer 5 includes, for example, boron (B) as a p-type dopant. The p-type amorphous semiconductor layer 5 has a thickness of 5 to 50 nm, for example.

FIG. 2 is an enlarged view of the translucent electrodes 6, 7, the protective film 8, and the conductive reflective layer 9 shown in FIG. 1. 2A is an enlarged view of a portion where the translucent electrode 6 is formed, and FIG. 2B is an enlarged view of a portion where the translucent electrode 7 is formed. However, in FIG. 2, for easy understanding of the structure, the back surface of the semiconductor substrate 1 is flat, and the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are formed on the flat passivation film 3. The structure in which is formed is shown. However, in actuality, as shown in FIG. 1, a texture structure is formed on the back surface of the substrate 1, a passivation film 3 is formed on the surface on which the texture structure is formed, and the passivation film 3 having an uneven shape. An n-type amorphous semiconductor layer 4 and a p-type amorphous semiconductor layer 5 are formed thereon.

The translucent electrode 6 is made of a translucent material that transmits light, for example, ITO (Indium Tin Oxide), ZnO, and IWO (Indium Tungsten Oxide), in order to allow light from the back surface to enter.

Referring to FIG. 2, translucent electrode 6 includes translucent conductive layers 6a and 6b.

The conductive layer 6 a is disposed in contact with the n-type amorphous semiconductor layer 4. The conductive layer 6b is disposed in contact with the conductive layer 6a. When the width of the opening 8A of the protective film 8 is L and the distance from the end of the translucent electrodes 6 and 7 to the opening 8A is H, the conductive layers 6a and 6b are formed of the n-type amorphous semiconductor layer 4 In the in-plane direction, the n-type amorphous semiconductor layer 4 is formed in a range of H + L / 2 on both sides from the center. The width L is, for example, 20 μm or more, and preferably 100 μm or more. By setting the width L to such a value, it is possible to secure incident light from the back surface and to transmit the translucent electrodes 6, 7, the n-type amorphous semiconductor layer 4, and the p-type amorphous semiconductor layer 5. It is preferable because adhesion can be secured and contact resistance can be reduced. The distance H is, for example, 5 μm or more in consideration of the adhesion between the translucent electrodes 6 and 7 and the protective film 8.

The translucent electrode 7 includes translucent conductive layers 7a and 7b. Conductive layer 7 a is disposed in contact with p-type amorphous semiconductor layer 5. The conductive layer 7b is disposed in contact with the conductive layer 7a. The conductive layers 7 a and 7 b are formed in a range of H + L / 2 on both sides from the center of the p-type amorphous semiconductor layer 5 in the in-plane direction of the p-type amorphous semiconductor layer 5.

As a result, each of the translucent electrodes 6 and 7 has a length of 2H + L in the in-plane direction of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5.

The protective film 8 has a two-layer structure of protective layers 8a and 8b, for example. When the protective film 8 is formed on the n-type amorphous semiconductor layer 4, the protective layer 8 a is disposed in contact with the passivation film 3, the n-type amorphous semiconductor layer 4, and the translucent electrode 6. The protective layer 8b is disposed in contact with the protective layer 8a. When the protective film 8 is formed on the p-type amorphous semiconductor layer 5, the protective layer 8 a is disposed in contact with the passivation film 3, the p-type amorphous semiconductor layer 5, and the translucent electrode 7. The protective layer 8b is disposed in contact with the protective layer 8a.

In the in-plane direction of the n-type amorphous semiconductor layer 4, a region outside the n-type amorphous semiconductor layer 4 with respect to the end of the translucent electrode 6 is referred to as a gap region G <b> 1. A region outside the p-type amorphous semiconductor layer 5 with respect to the end of the translucent electrode 7 in the in-plane direction of the layer 5 is referred to as a gap region G2. As a result, the gap region G1 exists on both sides of the n-type amorphous semiconductor layer 4 in the in-plane direction of the n-type amorphous semiconductor layer 4. In addition, a gap region G <b> 2 exists on both sides of the p-type amorphous semiconductor layer 5 in the in-plane direction of the p-type amorphous semiconductor layer 5.

A protective film 8 is disposed in contact with the passivation film 3, the n-type amorphous semiconductor layer 4, and the translucent electrode 6, and is in contact with the passivation film 3, the p-type amorphous semiconductor layer 5, and the translucent electrode 7. As a result of the arrangement, a gap region G (= G1 + G2) exists in the regions of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 adjacent in the in-plane direction of the semiconductor substrate 1. As shown in FIG. 1, the protective film 8 is formed on part of the translucent electrodes 6 and 7 and the gap region G.

The gap region G is a region where the passivation film 3, the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are exposed, and has a width of 20 μm to 500 μm, for example.

When the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are formed on the texture formed on the back surface of the semiconductor substrate 1 using a shadow mask, the gap region G is 50 μm or more and 300 μm or less. Preferably there is. If the gap region G is too narrow, the alignment accuracy of the shadow mask is lowered when forming the translucent electrodes 6, 7, and the translucent electrode 6 comes into contact with the p-type amorphous semiconductor layer 5, There is a possibility that the photoelectrode 7 contacts the n-type amorphous semiconductor layer 4. In this case, the leak current becomes large and the characteristics of the solar cell deteriorate. On the other hand, if the gap region G is too large, the carrier collection efficiency decreases in the gap region G, which is not preferable. For the above reasons, the gap region G is preferably 50 μm or more and 300 μm or less.

As the conductive layers 6a and 7a, it is preferable to use transparent conductive films having good adhesion to the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, respectively. Further, as the conductive layers 6b and 7b, it is preferable to use a transparent conductive film with high conductivity or a transparent conductive film with high light transmittance. For the transparent conductive film, for example, ITO, ZnO, IWO or the like can be used. ZnO can be formed by performing sputtering treatment under the same conditions using a ZnO target doped with 0.5 to 4 wt% of Al instead of the ITO target.

The translucent electrodes 6 and 7 may be a single film of the above-described transparent conductive film, or may have a two-layer structure such as ITO / IWO. Further, the conductive reflective layer 9 is made of silver and the adhesiveness between silver and ZnO is utilized, so that the translucent electrodes 6 and 7 have a two-layer structure of ITO / ZnO and the translucent electrodes 6 and 7 are used. The conductive reflective layer 9 may be effectively prevented from peeling off.

The film thickness of each of the conductive layers 6a, 6b, 7a and 7b is, for example, 3 to 100 nm, and in this embodiment, for example, 60 nm.

Since the conductive layers 6b and 7b are also in contact with the insulating film 8 and the conductive reflective layer 9, it is preferable to select a film type having high adhesion to the insulating film 8 and the conductive reflective layer 9.

Each of the protective layers 8a and 8b described above is made of an inorganic insulating film. The inorganic insulating film is made of an oxide film, a nitride film, an oxynitride film, or the like.

The oxide film is made of an oxide film such as silicon, aluminum, titanium, zirconia, hafnium, zinc, tantalum and yttrium.

The nitride film is made of a nitride film such as silicon and aluminum.

The oxynitride film is made of an oxynitride film such as silicon and aluminum.

The protective layer 8b is made of an inorganic insulating film different from the protective layer 8a. That is, two types of films are selected from the inorganic insulating films described above to form the protective layers 8a and 8b.

Further, the protective layer 8a may be made of a semiconductor layer, and the protective layer 8b may be made of the above-described inorganic insulating film.

In this case, the semiconductor layer is an amorphous semiconductor layer. The amorphous semiconductor layer is made of amorphous silicon, amorphous silicon germanium, amorphous germanium, amorphous silicon carbide, amorphous silicon nitride, amorphous silicon oxide, amorphous silicon oxynite. It consists of a ride and amorphous silicon carbon oxide. Since the higher insulation can suppress the leakage between the translucent electrodes 6 and 7, the protective layer 8a is preferably made of an intrinsic amorphous semiconductor layer. For example, the protective layer 8a is made of intrinsic amorphous silicon, and the protective layer 8b is made of a silicon nitride film.

However, when the protective layer 8b is made of an insulating film, the protective layer 8a may be made of an n-type amorphous semiconductor layer or a p-type amorphous semiconductor layer.

The protective layer 8b is preferably made of a dielectric film having a positive fixed charge. The dielectric film having a positive fixed charge is, for example, a silicon nitride film and a silicon oxynitride film.

Since the semiconductor substrate 1 is made of n-type single crystal silicon, when the protective layer 8b is made of a dielectric film having a positive fixed charge, the protective layer 8b applies an electric field to holes that are minority carriers, and the gap The lifetime of minority carriers (holes) in the region G can be maintained long.

The protective film 8 is not limited to a two-layer structure, and may be a single layer or a multilayer structure of two or more layers.

When the protective film 8 is composed of a single layer, the protective film 8 is composed of one kind of film selected from the inorganic insulating films described above.

When the protective film 8 has a multilayer structure, the protective film 8 includes the protective layers 8a and 8b described above in the multilayer structure.

As described above, when the protective film 8 has a two-layer structure, the protective layer 8a is formed of an amorphous semiconductor layer, and the protective layer 8b is formed of an insulating film, whereby the n-type amorphous semiconductor layer 4 and This is preferable because the passivation property to the p-type amorphous semiconductor layer 5 and the insulation between the translucent electrodes 6 and 7 can be compatible.

When the semiconductor substrate 1 is made of an n-type silicon substrate, the protective layer 8b is formed of a dielectric film having a positive fixed charge, so that an electric field is applied to the gap region, and minority carriers (holes) in the gap region are formed. Since lifetime can be lengthened, it is further preferable.

Further, when the above-described inorganic insulating film is included in the multilayer structure of the protective film 8, it diffuses into the amorphous semiconductor layers (n-type amorphous semiconductor layer 4 and p-type amorphous semiconductor layer 5). Since the moisture-proof effect which prevents a water | moisture content etc. can be acquired, it is preferable. Among the inorganic insulating films described above, a silicon nitride film and a silicon oxynitride film are particularly preferable because they have a particularly high moisture resistance as compared with other inorganic insulating films. When an n-type silicon substrate is used, moisture resistance and the electric field effect due to positive fixed charges can be obtained together, so that both long-term reliability and high efficiency of the photoelectric conversion element 10 are achieved. can do.

For example, when the protective film 8 is a multilayer film having a two-layer structure or more, for example, a three-layer structure, one protective layer (a protective layer in contact with the n-type amorphous semiconductor layer 4 or the p-type amorphous semiconductor layer 5). Is made of an amorphous semiconductor layer, and the remaining two protective layers are made of two types of films selected from inorganic insulating films.

Further, when the protective film 8 is composed of a single layer or multiple layers, the protective film 8 may have a structure in which an organic insulating film or the like is formed on the above-described inorganic insulating film.

The organic substance is composed of, for example, an imide resin, an epoxy resin, a fluororesin, a polycarbonate, and a liquid crystal polymer.

The imide resin is, for example, polyimide. The fluororesin is, for example, polytetrafluoroethylene (PTFE). The organic substance may be a resist formed by screen printing.

The conductive reflective layer 9 functions as a light reflective layer that reflects light incident from the light receiving surface, and a conductive layer (electrode for taking out current obtained by power generation in contact with the translucent electrode 6 or 7. ).

The conductive reflective layer 9 is made of metal. Examples of metals include Ag, Al, nickel (Ni), copper (Cu), tin (Sn), platinum (Pt), gold (Au), chromium (Cr), tungsten (W), cobalt (Co), and titanium. It is made of any one of (Ti), an alloy thereof, or a laminated film of two or more layers of these metals. Further, as the conductive reflective layer 9, a paste-like electrode such as a silver paste or a copper paste, or a SMARTWIRE type electrode manufactured by MEYER-BURGER may be used.

The film thickness of the conductive reflective layer 9 can be freely designed, but is preferably 50 μm to 200 μm, for example. More preferably, it is about 20 μm to 100 μm.

When the conductive reflective layer 9 is made of a metal containing a high light reflective film such as silver (Ag), aluminum (Al), or copper (Cu) as a main component, the reflectance of the conductive reflective layer 9 is 90%. That's it. The light that can reach the back surface of the semiconductor substrate 1 is light in a long wavelength region of about 800 to 1200 nm. In the gap region G, in order to effectively use the reflection of incident light from the light receiving surface, the reflectance of the conductive reflective layer 9 in the above wavelength region is preferably 60% or more, and 70% or more. Is more preferable.

If the light incident from the light receiving surface of the semiconductor substrate 1 enters the region where the conductive reflective layer 9 is provided, mainly the gap region G, the light is reflected by the conductive reflective layer 9 and returns into the semiconductor substrate 1. The probability that the semiconductor substrate 1 is effectively absorbed increases. In the case of the backside heterojunction solar cell in this embodiment, the conductive reflective layer 9 is formed on the gap region G, thereby improving efficiency by playing two roles of an electrically conductive layer and a light reflective layer. This is preferable. In the conventional backside heterojunction solar cell, when light enters the gap region between the p-type semiconductor layer and the n-type semiconductor layer, the efficiency loss is large because the light reflectance in the gap region is low. However, according to the backside heterojunction solar cell in the present embodiment, the light loss in the gap region G is increased to suppress the efficiency loss, and further, the gap region G is used as a conductive layer. Current can be transmitted with resistance loss suppressed.

Usually, the width of the gap region G is often formed wider than several tens of μm due to the accuracy and variation of the manufacturing process, leading to efficiency loss. However, according to the present embodiment, even when the gap region G is wide, the conductive reflective layer 9 can prevent light from being transmitted to the back surface, and the conductive reflective layer 9 is formed with a wide width. This is preferable because the resistance of the conductive reflective layer 9 can be lowered.

In the solar cell according to the present embodiment, as described above, by effectively using the gap region G, the width of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, the width of the gap region G, etc. Since the design value can be designed relatively freely, the degree of freedom in design is increased, which is preferable.

In the photoelectric conversion element 10 in the present embodiment, the size of the texture formed on the back surface of the semiconductor substrate 1 is less than 30 μm.

[Definition of texture size]
In this specification, the size of the texture means a size in a state in which the main surface of the semiconductor substrate is viewed in plan, that is, in a state viewed from vertically above the main surface. As a specific example of the texture, there is a pyramidal (quadrangular pyramid or quadrangular frustum-shaped) uneven structure obtained by performing anisotropic etching on an n-type single crystal silicon substrate having a (100) principal surface. is there. As shown in FIG. 3, the actual texture has a plurality of pyramidal irregularities of various sizes and shapes. This unevenness includes overlapping and deformed ones.

Therefore, in the present embodiment, when the texture is viewed in plan, the average value of the diameter of the circumscribed circle of the convex portion of the texture is defined as the size of the texture. Here, the size of the texture was obtained by the following method.

An area having a size of 100 μm × 100 μm is extracted from the semiconductor substrate 1, and 20 pieces (r 1, r 1, r 1) from the extracted area in order from the longest one of the oblique line lengths (the oblique line lengths in plan view) r r2,..., r20) are detected. Then, twice the average length of the detected 20 diagonal lengths r (r1, r2,..., R20) is set as the size of the texture structure. This is because, in a 100 μm × 100 μm region of the semiconductor substrate 1, when the texture is viewed in plan, the diameters R of the circumscribed circles of the pyramid-shaped convex portions are 20 in order from the longest one (R 1, R 2 ,..., R20) is detected, and is equal to the average length of the diameters R of the 20 circumscribed circles detected.

Note that the size of the texture structure may be defined based on the length of one side of the bottom surface of the pyramidal unevenness, or the size of the texture structure may be defined based on the height of the pyramidal unevenness. . For example, when the shape of the pyramid-shaped unevenness is a quadrangular pyramid whose bottom surface is a square, the length a of one side of the bottom surface has a relationship of a diagonal line length r of the side surface in a plan view and a = 2 × r / √2. is there. When the angle formed between the bottom surface and the oblique side of the side surface is θ, the height b has a relationship of b = r × tan θ.

For the reasons described later, the texture size should be less than 30 μm. The texture size is preferably 25 μm or less. The texture size can be easily measured by observation with an SEM or the like.

[Reason why the size of the texture formed on the back surface of the semiconductor substrate 1 is less than 30 μm]
In the backside heterojunction solar cell in this embodiment, the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are adjacent to each other on the backside of the semiconductor substrate 1. As will be described later, when the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are formed using the shadow mask, the source gas or the dopant gas wraps around the inner side in the in-plane direction below the shadow mask. Will occur. It has been found that the reverse saturation current density of the IV characteristics of the manufactured solar battery cell increases as this wraparound increases. It was also found that when the wraparound of the source gas and the dopant gas is increased, the insulation between the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 is impaired and current leakage occurs.

FIG. 4 is a diagram showing the relationship between the texture size of the back surface of the semiconductor substrate 1 and the reverse saturation current density. When the texture size is 30 μm or more, the reverse saturation current density is 5 × 10 ⁻³ mA / cm ² or more, and the reverse saturation current density shows a saturation tendency regardless of the texture size. From this, it is considered that current leakage is large.

On the other hand, when the texture size is less than 30 μm, the reverse saturation current density is about 6 × 10 ⁻⁴ mA / cm ² or less, and the reverse saturation current density can be reduced by about one digit. The reverse saturation current density determines the quality of the pn junction of the photoelectric conversion element. A smaller value can improve the static characteristics of the solar cell such as an open circuit voltage.

As shown in FIG. 4, when the texture size is 30 μm or more, the reverse saturation current density has a substantially constant characteristic (k2), but when the texture size is less than 30 μm, the smaller the texture size, The reverse saturation current density is reduced (k1). That is, it was found that the characteristics differ greatly between the case where the texture size is 30 μm or more and the case where the texture size is less than 30 μm. As described above, the smaller the reverse saturation current density can improve the static characteristics of the solar cell.

That is, since it is critical to make the texture size less than 30 μm, in the photoelectric conversion element in the present embodiment, the size of the texture formed on the back surface of the semiconductor substrate 1 is made less than 30 μm.

As shown in FIG. 4, when the texture size is 25 μm or less, there is a large step in the characteristics and the reverse saturation current density is one digit or more smaller than when the texture size is 30 μm or more. Therefore, since it is also critical to make the texture size 25 μm or less, the texture size is more preferably 25 μm or less.

Further, when the texture size is 10 μm or less, the reverse saturation current density is 3 × 10 ⁻⁵ mA / cm ² or less, which is more preferable.

FIG. 5 is a sectional view showing a detailed structure of the n-type amorphous semiconductor layer 4 shown in FIG. However, FIG. 5 shows a structure in which the back surface of the semiconductor substrate 1 is flat and the n-type amorphous semiconductor layer 4 is formed on the flat passivation film 3 as in FIG. Actually, a texture structure is formed on the back surface of the semiconductor substrate 1.

Referring to FIG. 5, n-type amorphous semiconductor layer 4 has a flat region FT and a thickness reduction region TD in the in-plane direction of n-type amorphous semiconductor layer 4. The flat region FT is a portion of the n-type amorphous semiconductor layer 4 that has the thickest film thickness and is substantially constant.

When the point at both ends of the flat region FT is A, and the point at which the film thickness decrease rate changes from the first decrease rate to the second decrease rate larger than the first decrease rate is B point, the film thickness The decrease region TD is a region from point A to point B in the in-plane direction of the n-type amorphous semiconductor layer 4.

The film thickness reduction regions TD are arranged on both sides of the flat region FT in the in-plane direction of the n-type amorphous semiconductor layer 4.

The reason why the n-type amorphous semiconductor layer 4 has the film thickness reduction region TD is that, as will be described later, the n-type amorphous semiconductor layer 4 is formed by plasma CVD using a shadow mask. Since the film thickness reduction region TD has a thinner film thickness than the flat region FT, the dopant concentration of the film thickness reduction region TD is higher than the dopant concentration of the flat region FT.

The translucent electrode 6 is disposed in contact with the entire flat region FT of the n-type amorphous semiconductor layer 4 and a part of the film thickness reduction region TD.

The p-type amorphous semiconductor layer 5 also has the same structure as the n-type amorphous semiconductor layer 4 shown in FIG. The translucent electrode 7 is disposed in contact with the entire flat region FT of the p-type amorphous semiconductor layer 5 and a part of the film thickness reduction region TD.

As a result, the resistance when carriers (electrons) reach the translucent electrode 6 via the n-type amorphous semiconductor layer 4 is n-type amorphous having a constant film thickness in the in-plane direction of the passivation film 3. The resistance becomes lower than that in the case where a high quality semiconductor layer is formed. The resistance when carriers (holes) reach the translucent electrode 7 via the p-type amorphous semiconductor layer 5 is p-type amorphous having a constant film thickness in the in-plane direction of the passivation film 3. The resistance becomes lower than that in the case where a high quality semiconductor layer is formed. Therefore, the conversion efficiency of the photoelectric conversion element 10 can be improved.

The translucent electrode 6 may be in contact with the entire thickness decreasing region TD of the n-type amorphous semiconductor layer 4, and the translucent electrode 7 is formed of the film thickness of the p-type amorphous semiconductor layer 5. It may be in contact with the entire reduction region TD.

FIG. 6 is a cross-sectional view showing another detailed structure of the n-type amorphous semiconductor layer 4 shown in FIG. Referring to FIG. 6A, the photoelectric conversion element 10 includes an n-type amorphous semiconductor layer 41 instead of the n-type amorphous semiconductor layer 4, and a light-transmitting property instead of the light-transmitting electrode 6. The electrode 61 may be provided.

In the n-type amorphous semiconductor layer 41, the point at which the film thickness is maximum is C point, and the film thickness decrease rate changes from the first decrease rate to the second decrease rate larger than the first decrease rate. Let the point be point D. As a result, the film thickness reduction region TD is a region from the point C to the point D in the in-plane direction of the n-type amorphous semiconductor layer 41.

The n-type amorphous semiconductor layer 41 has two thickness reduction regions TD in the in-plane direction of the n-type amorphous semiconductor layer 41. The two film thickness reduction regions TD are arranged in contact with each other in the in-plane direction of the n-type amorphous semiconductor layer 41.

The translucent electrode 61 is disposed in contact with a part of one film thickness reduction area TD and a part of the other film thickness reduction area TD among the two film thickness reduction areas TD.

The photoelectric conversion element 10 includes a p-type amorphous semiconductor layer having the same structure as the n-type amorphous semiconductor layer 41 shown in FIG. 6A instead of the p-type amorphous semiconductor layer 5. Also good.

As a result, the resistance when carriers (electrons) reach the translucent electrode 61 via the n-type amorphous semiconductor layer 41 is n-type amorphous having a constant film thickness in the in-plane direction of the passivation film 3. The resistance becomes lower than that in the case where a high quality semiconductor layer is formed. Further, the resistance when carriers (holes) reach the translucent electrode through the p-type amorphous semiconductor layer having the same structure as that of the n-type amorphous semiconductor layer 41 is the in-plane direction of the passivation film 3. As compared with the case where a p-type amorphous semiconductor layer having a constant film thickness is formed, the resistance becomes lower. Therefore, the conversion efficiency of the photoelectric conversion element 10 can be improved.

Note that the translucent electrode is composed of the n-type amorphous semiconductor layer 41 and the p-type amorphous semiconductor layer having the same structure as the n-type amorphous semiconductor layer 41 in the entire two film thickness reduction regions TD. It may be arranged in contact with.

Referring to FIG. 6B, the photoelectric conversion element 10 includes an n-type amorphous semiconductor layer 42 instead of the n-type amorphous semiconductor layer 4, and translucent instead of the translucent electrode 6. An electrode 62 may be provided.

In the n-type amorphous semiconductor layer 42, the point at which the film thickness is maximum is taken as point E, and the film thickness decrease rate changes from the first rate of decrease to a second rate of decrease that is greater than the first rate of decrease. Let the point be the F point, and let the point where the sign of the rate of change of the film thickness changes from negative to positive.

As a result, the film thickness reduction region TD1 is a region from the point E to the point F in the in-plane direction of the n-type amorphous semiconductor layer 42, and the film thickness reduction region TD2 is the region of the n-type amorphous semiconductor layer 42. This is the region from point E to point G in the in-plane direction.

The n-type amorphous semiconductor layer 42 has two film thickness reduction regions TD1 and two film thickness reduction regions TD2 in the in-plane direction of the n-type amorphous semiconductor layer 42.

The two film thickness reduction regions TD2 are arranged so that the film thickness distribution in the in-plane direction of the n-type amorphous semiconductor layer 42 is symmetric with respect to a line passing through the G point. The two film thickness reduction regions TD1 are arranged on both sides of the two film thickness reduction regions TD2 in the in-plane direction of the n-type amorphous semiconductor layer 42.

The translucent electrode 62 is disposed in contact with the entire two film thickness reduction regions TD2, a part of one film thickness reduction region TD1, and a part of the other film thickness reduction region TD1.

The photoelectric conversion element 10 includes a p-type amorphous semiconductor layer having the same structure as the n-type amorphous semiconductor layer 42 shown in FIG. 6B instead of the p-type amorphous semiconductor layer 5. Also good.

As a result, the resistance when carriers (electrons) reach the translucent electrode 62 via the n-type amorphous semiconductor layer 42 is n-type amorphous having a constant film thickness in the in-plane direction of the passivation film 3. The resistance becomes lower than that in the case where a high quality semiconductor layer is formed. Further, the resistance when carriers (holes) reach the translucent electrode through the p-type amorphous semiconductor layer having the same structure as that of the n-type amorphous semiconductor layer 42 is the in-plane direction of the passivation film 3. As compared with the case where a p-type amorphous semiconductor layer having a constant film thickness is formed, the resistance becomes lower. Therefore, the conversion efficiency of the photoelectric conversion element 10 can be improved.

Note that the translucent electrode is composed of the entire n-type amorphous semiconductor layer 42 and the p-type amorphous semiconductor layer having the same structure as the n-type amorphous semiconductor layer 42 in the entire two thickness reduction regions TD1. In addition, the two film thickness reduction regions TD2 may be disposed in contact with each other.

As described above, the photoelectric conversion element 10 includes the n-type amorphous semiconductor layer and the p-type amorphous semiconductor layer having the film thickness reduction region TD (TD1, TD2). In the embodiment of the present invention, the film thickness reduction region is one of the film thickness reduction regions TD, TD1, and TD2.

Accordingly, the first point is the point where the film thickness of the n-type amorphous semiconductor layer or the p-type amorphous semiconductor layer is the maximum, and the in-plane of the n-type amorphous semiconductor layer or the p-type amorphous semiconductor layer In the direction, a point at which the film thickness decrease rate changes from the first decrease rate to a second decrease rate larger than the first decrease rate, or a point at which the sign of the film thickness change rate changes from negative to positive. When the second point is taken, the film thickness reduction region is a region from the first point to the second point in the in-plane direction of the n-type amorphous semiconductor layer or the p-type amorphous semiconductor layer.

In the embodiment of the present invention, it is sufficient that at least one of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 has a film thickness reduction region.

7 to 11 are first to fifth process diagrams showing a method for manufacturing the photoelectric conversion element 10 shown in FIG. 1, respectively.

Referring to FIG. 7, when manufacturing of photoelectric conversion element 10 is started, a wafer having a thickness of 100 to 300 μm is cut out from bulk silicon by a wire saw. Then, etching for removing the damaged layer on the surface of the wafer and etching for adjusting the thickness are performed to prepare the semiconductor substrate 1 '(see step (a) in FIG. 7).

Generally, a semiconductor substrate having a texture structure is manufactured by etching a semiconductor substrate obtained by slicing a silicon ingot with a wire saw or the like. The semiconductor substrate that forms the texture structure is mainly the sliced substrate by the free abrasive grain method, but there is also a cost reduction and the improvement of the slicing technique, and the same texture structure can be formed also by the sliced substrate by the fixed abrasive grain method. .

Etching of the semiconductor substrate 1 ′ can be performed by wet etching using an alkaline etchant. This etching proceeds by a reaction such as the following reaction formulas (1), (2), and (3) in a sodium hydroxide solution.
Si + 2NaOH + H ₂ O → Na ₂ SiO ₃ + 2H ₂ (1)
2Si + 2NaOH + 3H ₂ O → Na ₂ Si ₂ O ₅ + 4H ₂ (2)
3Si + 4NaOH + 4H ₂ O → Na ₄ Si ₃ O ₈ + 6H ₂ (3)

In order to form a texture structure on the surface of the semiconductor substrate 1 ′, anisotropic etching is performed by using, for example, an etching solution with a controlled etching rate. Formation of the texture structure on the surface of the semiconductor substrate 1 'is based on the following mechanism. The etching rate of the semiconductor substrate 1 ′ with the alkaline aqueous solution is the fastest on the (100) plane of silicon and the slowest on the (111) plane. Therefore, if the etching rate is suppressed by adding a specific additive (hereinafter also referred to as “etching inhibitor”) that can reduce the etching rate to the alkaline aqueous solution, etching of the (100) surface of silicon and the like A crystal plane that is easily etched is preferentially etched, and a (111) plane having a slow etching rate remains on the surface. Since the (111) plane has an inclination of about 54 degrees with respect to the (100) plane, a pyramidal uneven structure composed of the (111) plane and its equivalent plane is formed at the final stage of the process. Is done.

However, depending on the etching conditions, a texture having an inclination of about 40-54 degrees may be formed, and the inclined surface of the texture is not necessarily formed by the (111) plane. That is, the texture inclined surface does not have to be the (111) surface, and for example, the texture may have a gentle structure.

As the texture forming etching solution, an etching solution obtained by adding isopropyl alcohol as an etching inhibitor to an aqueous solution of sodium hydroxide (NaOH) can be used. Etching is performed by heating the etching solution to about 60 to 80 ° C. and immersing the (100) plane semiconductor substrate for 10 to 30 minutes.

In addition, by using an etching solution containing sodium hydroxide or potassium hydroxide, a specific additive such as lignin, and sodium hydrogen carbonate or potassium hydrogen carbonate, the texture structure of the micro pyramid structure (the bottom of the uneven recess) To 1 μm or less). Thus, the texture size can be controlled by changing various conditions such as the temperature of the etching solution, the processing time, the type of etching inhibitor, the etching rate, and the type of substrate.

As described above, irregularities having different texture sizes were formed on the surface of the semiconductor substrate by changing the etching conditions.

FIG. 12 is a view showing an SEM (Scanning Electron Microscopy) photograph of a semiconductor substrate on which texture structures having different sizes are formed. FIG. 12A shows an SEM photograph in the case where the length of the bottom side of the pyramid constituting the texture structure is 2 μm or less, and FIG. 12B shows the length of the bottom side of the pyramid is 10 μm or less. FIG. 12 (c) shows an SEM photograph in the case where the bottom side length of the pyramid is about 15 μm.

After step (a) in FIG. 7, the semiconductor substrate 1 'is etched using an alkaline solution such as NaOH and KOH (for example, an aqueous solution of KOH: 1 to 5 wt%, isopropyl alcohol: 1 to 10 wt%). As a result, both sides of the semiconductor substrate 1 ′ are anisotropically etched, and the semiconductor substrate 1 in which the pyramid-shaped texture structure is formed on both sides is obtained (see step (b) in FIG. 7).

Subsequently, the surface of the semiconductor substrate 1 is thermally oxidized to form an oxide film 11 on the light receiving surface of the semiconductor substrate 1, and a passivation film 3 is formed on the back surface of the semiconductor substrate 1 (see step (c) in FIG. 7). .

The oxidation of the semiconductor substrate 1 may be either wet treatment or thermal oxidation. In the case of wet oxidation, for example, the semiconductor substrate 1 is immersed in hydrogen peroxide, nitric acid, ozone water or the like, and then the semiconductor substrate 1 is heated at 800 to 1000 ° C. in a dry atmosphere. In the case of thermal oxidation, for example, the semiconductor substrate 1 is heated to 900 to 1000 ° C. in an atmosphere of oxygen or water vapor.

After the step (c) of FIG. 7, a silicon nitride film 12 is formed in contact with the oxide film 11 using a sputtering method, EB (Electron Beam) deposition, a CVD method, or the like. Thereby, the antireflection film 2 is formed on the light receiving surface of the semiconductor substrate 1 (see step (d) in FIG. 8).

After the step (d) of FIG. 8, the semiconductor substrate 1 is put into the reaction chamber of the plasma apparatus, and the shadow mask 30 is disposed on the passivation film 3 of the semiconductor substrate 1 (see step (e) of FIG. 8).

The shadow mask 30 is made of, for example, a metal mask. The metal mask is made of, for example, stainless steel, has a thickness of 200 μm, an opening width of 850 μm, a masked width of 1050 μm, and a period of 1900 μm. However, the opening width can be changed as appropriate.

Then, the temperature of the semiconductor substrate 1 is set to 130 to 180 ° C., and hydrogen (H ₂ ) gas of 0 to 100 sccm, SiH ₄ gas of 40 sccm, and phosphine (PH ₃ ) gas of 40 sccm are flowed into the reaction chamber. Is set to 40 to 120 Pa. Thereafter, high frequency power (13.56 MHz) having an RF power density of 5 to 15 mW / cm ² is applied to the parallel plate electrodes. Note that the PH ₃ gas is diluted with hydrogen, and the concentration of the PH ₃ gas is, for example, 1%.

As a result, n-type amorphous silicon is deposited in the region of the passivation film 3 that is not covered by the shadow mask 30, and the n-type amorphous semiconductor layer 4 is formed on the passivation film 3 (step of FIG. f)).

When the shadow mask 30 is disposed on the passivation film 3, there is a gap between the shadow mask 30 and the passivation film 3. As a result, active species such as SiH and SiH ₂ decomposed by the plasma enter the gap between the shadow mask 30 and the passivation film 3, and an n-type amorphous material is also formed in a part of the region covered by the shadow mask 30. A semiconductor layer 4 is formed. Compared to the case where the film is formed on the semiconductor substrate on which the texture structure is not formed, when the film is formed on the semiconductor substrate 1 on which the texture structure is formed, the gap between the shadow mask 30 and the passivation film 3 is reduced. More wraparound. As a result, the n-type amorphous semiconductor layer 4 having the thickness reduction region TD is formed on the passivation film 3. An n-type amorphous silicon 31 is also deposited on the shadow mask 30.

The width of the film thickness reduction region TD and the film thickness reduction rate in the n-type amorphous semiconductor layer 4 are the film formation pressure when the n-type amorphous semiconductor layer 4 is formed, the thickness of the shadow mask 30 and It is controlled by changing the opening width of the shadow mask 30. For example, when the thickness of the shadow mask 30 is increased, the width of the film thickness reduction region TD is increased.

After the step (f) in FIG. 8, a shadow mask 40 is disposed on the passivation film 3 and the n-type amorphous semiconductor layer 4 instead of the shadow mask 30 (see step (g) in FIG. 9). The shadow mask 40 has the same material, thickness, and opening width as the shadow mask 30.

In the step (g) of FIG. 9, the shadow mask 40 is illustrated as being separated from the passivation film 3, but the thickness of the n-type amorphous semiconductor layer 4 is 3 as described above. Since it is very thin as ˜50 nm, the shadow mask 40 is actually arranged close to the passivation film 3.

Then, the temperature of the semiconductor substrate 1 is set to 130 to 180 ° C., and 0 to 100 sccm of H ₂ gas, 40 sccm of SiH ₄ gas, and 40 sccm of diborane (B ₂ H ₆ ) gas are allowed to flow into the reaction chamber. The pressure is set to 40-200 Pa. Thereafter, high frequency power (13.56 MHz) having an RF power density of 5 to 15 mW / cm ² is applied to the parallel plate electrodes. Note that B ₂ H ₆ gas is diluted with hydrogen, and the concentration of B ₂ H ₆ gas is, for example, 2%.

As a result, p-type amorphous silicon is deposited in the region of the passivation film 3 not covered by the shadow mask 40, and the p-type amorphous semiconductor layer 5 is formed on the passivation film 3 (step of FIG. 9). h)).

When the shadow mask 40 is disposed on the passivation film 3 and the n-type amorphous semiconductor layer 4, there is a gap between the shadow mask 40 and the passivation film 3. As a result, active species such as SiH and SiH ₂ decomposed by the plasma wrap around the gap between the shadow mask 40 and the passivation film 3, and p-type amorphous is also formed in a part of the region covered by the shadow mask 40. A semiconductor layer 5 is formed. Compared to the case where the film is formed on the semiconductor substrate on which the texture structure is not formed, when the film is formed on the semiconductor substrate 1 on which the texture structure is formed, the gap between the shadow mask 40 and the passivation film 3 is reduced. More wraparound. Thereby, the p-type amorphous semiconductor layer 5 having the film thickness reduction region TD is formed on the passivation film 3. Also, the p-type amorphous silicon 32 is deposited on the shadow mask 40.

The width of the film thickness reduction region TD and the film thickness reduction rate in the p-type amorphous semiconductor layer 5 are the film formation pressure when the p-type amorphous semiconductor layer 5 is formed, the thickness of the shadow mask 40, and It is controlled by changing the opening width of the shadow mask 40. For example, when the thickness of the shadow mask 40 is increased, the width of the film thickness reduction region TD is increased.

When the n-type amorphous semiconductor layer 4 is not provided with the film thickness reduction region TD, for example, the n-type amorphous semiconductor layer 4 is not formed on the entire upper surface of the passivation film 3 without the shadow mask 30 being disposed. The semiconductor layer 4 is formed, and the n-type amorphous semiconductor layer 4 is formed in a predetermined region by etching. Even when the p-type amorphous semiconductor layer 5 is not provided with the film thickness reduction region TD, it can be formed by the same method.

When the shadow mask 40 is removed after the p-type amorphous semiconductor layer 5 is deposited, the n-type amorphous semiconductor layers 4 and the p-type amorphous semiconductor layers 5 arranged alternately in the in-plane direction of the semiconductor substrate 1. Is formed on the passivation film 3 (see step (i) in FIG. 9).

After the step (i) in FIG. 9, the shadow mask 50 is arranged so that the opening is located on the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 (step (j) in FIG. 10). reference). The shadow mask 50 has the same material and thickness as the shadow mask 30. The opening width is set to the sum of the width of the flat region FT of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 and the width of the two film thickness reduction regions TD. The opening width may be slightly different from the above width.

After the step (j) in FIG. 10, conductive layers 6a and 7a and conductive layers 6b and 7b are sequentially deposited through the shadow mask 50. Thereby, the translucent electrodes 6 and 7 are deposited on the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, respectively (see step (k) in FIG. 10).

The conductive layers 6a and 7a and the conductive layers 6b and 7b are formed by sputtering, vapor deposition, ion plating, thermal CVD, MOCVD (Metal-Organic-Chemical-Vapour-Deposition), sol-gel method, or a method of spraying and heating a liquid material. , And an inkjet method or the like.

As described above, the translucent electrodes 6 and 7 may have a single layer structure. Therefore, the translucent electrodes 6 and 7 are, for example, translucent conductive films such as ITO, IWO, ZnO, or a multilayer film thereof. For example, the translucent electrode on the n-type amorphous semiconductor layer 4 is used. The electrode 7 is made of ITO, and the translucent electrode 6 on the p-type amorphous semiconductor layer 5 is made of IWO, so that each contact resistance is lowered. The conductive electrode may be formed in two steps. In particular, ITO and IWO are preferable for lowering the contact resistance on the p-type amorphous semiconductor layer 5 from the work function value of these materials, and a film such as ZnO is provided on the n-type amorphous semiconductor layer 4. Species are preferred.

ITO is, for example, an ITO target doped with 0.5 to 4 wt% of SnO ₂ , flowing argon gas or a mixed gas of argon gas and oxygen gas, substrate temperature of 25 to 250 ° C., 0.1 to 1.5 Pa. It is formed by performing a sputtering process at a pressure of 0.01 to 2 kW.

ZnO is formed by performing a sputtering process under the same conditions using a ZnO target doped with 0.5 to 4 wt% of Al instead of the ITO target.

After the step (k) in FIG. 10, the shadow mask 60 is disposed on the translucent electrodes 6 and 7 (see step (l) in FIG. 10). The shadow mask 60 has the same material and thickness as the shadow mask 30.

Then, the protective film 8 is formed on the passivation film 3, the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5, and the translucent electrodes 6 and 7.

More specifically, an intrinsic amorphous semiconductor film and a silicon nitride film are formed by using a plasma CVD method to form a passivation film 3, an n-type amorphous semiconductor layer 4, a p-type amorphous semiconductor layer 5, and a translucent electrode. 6 and 7 are sequentially deposited. In this case, for example, an intrinsic amorphous semiconductor film is formed using SiH ₄ gas as a material gas, and the thickness of the intrinsic amorphous semiconductor film is, for example, 10 nm. Further, for example, a silicon nitride film is formed using SiH ₄ gas and NH ₃ gas as material gases, and the thickness of the silicon nitride film is, for example, 120 nm. Thus, the protective film 8 is formed (see step (m) in FIG. 11). The protective film 8 does not have an intrinsic amorphous semiconductor film, and may be formed of a single film such as a silicon nitride film, a silicon oxynitride film, an aluminum or titanium oxide film, a nitride film, or an oxynitride film. .

After the step (m) of FIG. 11, the shadow mask 70 is disposed on the translucent electrodes 6 and 7. Here, as shown in FIG. 1, the shadow mask 70 is arranged at a position shifted in the in-plane direction from the center in the in-plane direction of the translucent electrodes 6 and 7 so that the conductive reflective layer 9 is formed ( Step (n) in FIG. 11). The shadow mask 70 has the same material and thickness as the shadow mask 30.

Then, the conductive reflective layer 9 is formed on the gap region G (see step (o) in FIG. 11). Here, the conductive reflective layer 9a in contact with the translucent electrode 6 and the conductive reflective layer 9b in contact with the translucent electrode 7 are formed. The conductive reflective layer 9 a is electrically connected to the translucent electrode 6, but is electrically insulated from the conductive reflective layer 9 b and the translucent electrode 7. The conductive reflective layer 9b is electrically connected to the translucent electrode 7, but is electrically insulated from the conductive reflective layer 9a and the translucent electrode 6.

With the above configuration, a back-side heterojunction solar cell can be manufactured by bifacial (double-sided light reception). At this time, when the conductive reflective layers 9a and 9b are made of, for example, silver (Ag) or aluminum (Al), the reflectivity of the conductive reflective layers 9a and 9b is preferably 90% or more. It is preferably made of a metal such as (In), Ti, Ni, Cu, Cr, W, Co, palladium (Pd) and Sn.

In the above description, stainless steel has been given as an example of the material of the shadow masks 30, 40, 50, 60, 70, but is not limited to stainless steel, for example, copper, nickel, nickel alloys (42 alloy, Invar material or the like) or molybdenum.

Further, the shadow masks 30, 40, 50, 60, 70 do not have to be metal masks, and may be glass masks, ceramic masks, organic film masks, or the like.

Further, a semiconductor substrate made of the same material as the semiconductor substrate 1 may be processed by etching to form a shadow mask. In this case, since both the semiconductor substrate 1 and the shadow mask are made of the same material, the thermal expansion coefficients are the same, and no misalignment occurs due to the difference in thermal expansion coefficients.

Considering the relationship with the thermal expansion coefficient of the semiconductor substrate 1 and the raw material cost, the material of the shadow masks 30, 40, 50, 60, 70 is preferably 42 alloy. Focusing on the relationship with the coefficient of thermal expansion of the semiconductor substrate 1, when the shadow mask 30, 40, 50, 60, 70 is made of a material having a nickel composition of about 36% and an iron composition of about 64%, the semiconductor substrate It is closest to the thermal expansion coefficient of 1, and the alignment error due to the difference in thermal expansion coefficient can be minimized.

Moreover, it is preferable that the thickness of the shadow mask 30, 40, 50, 60, 70 can be regenerated and used many times from the viewpoint of suppressing the running cost of production. In this case, the film deposited on the shadow masks 30, 40, 50, 60, and 70 can be removed using hydrofluoric acid or NaOH. Considering the number of times of reproduction, the thickness of the shadow masks 30, 40, 50, 60, 70 is preferably 30 μm to 300 μm.

Further, in the manufacturing method described above, it has been described that the intrinsic amorphous semiconductor film / silicon nitride film constituting the protective film 8 is continuously formed in one reaction chamber, but in the embodiment of the present invention, However, the present invention is not limited thereto, and after the intrinsic amorphous semiconductor layer is formed, the sample may be exposed to the atmosphere once so that a silicon nitride film is formed by a sputtering apparatus or another CVD apparatus.

When the intrinsic amorphous semiconductor film / silicon nitride film constituting the protective film 8 is formed without being exposed to the atmosphere, it is preferable because contamination of organic substances or moisture in the atmosphere can be suppressed.

Furthermore, the protective film 8 may be formed using EB vapor deposition, sputtering, laser ablation, CVD, and ion plating.

Furthermore, in the embodiment of the present invention, after the passivation film 3 is formed, the passivation film 3 may be nitrided by a plasma CVD method using nitrogen (N ₂ ) gas to form a passivation film made of SiON. . As a result, it is possible to suppress the diffusion of the dopant (B) in the p-type amorphous semiconductor layer 5 formed on the passivation film 3 into the semiconductor substrate 1. And even if it is a case where the passivation film 3 which has the film thickness which can flow a tunnel current is formed, since the spreading | diffusion of boron (B) can be suppressed effectively, it is preferable.

As described above, since the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are deposited on the semiconductor substrate 1 using the shadow masks 30 and 40, adjacent n-type amorphous semiconductors are deposited. A gap region G is formed between the layer 4 and the p-type amorphous semiconductor layer 5. Then, between the adjacent translucent electrodes 6, 7, the protective film 8 is formed of the translucent electrodes 6, 7 and the gap region G (passivation film 3, n-type amorphous semiconductor layer 4 and p-type amorphous semiconductor layer). 5) Formed on top.

As a result, even when conductive dust adheres to the gap region G, a short circuit is prevented.

Therefore, the reliability of the photoelectric conversion element 10 can be improved.

The translucent electrodes 6 and 7 do not necessarily have an overlapping region with the protective film 8, but preferably have an overlapping region for the following reason, and also have an overlapping region in this embodiment.

The translucent electrodes 6 and 7 are covered with a protective film 8 in a region of 5 μm or more from the end toward the inside. As a result, it is possible to effectively prevent moisture from entering from the opening end of the protective film 8, and to prevent the protective film 8 from peeling off, thereby preventing a decrease in yield due to misalignment during production.

Even when an electric material having poor adhesion with the amorphous semiconductor layers 4 and 5 in contact with the translucent electrodes 6 and 7 is used as the translucent electrodes 6 and 7, the protective film 8 is formed. By forming, adhesion improves. For this reason, the range of the electrode material selection is widened, and the characteristics can be easily improved, which is preferable.

Furthermore, since part of the translucent electrodes 6 and 7 that are not covered with the protective film 8 is covered with the conductive reflective film 9, the protective properties of the translucent electrodes 6 and 7 are enhanced.

In a conventional heterojunction solar cell in which an n-type amorphous semiconductor layer or a p-type amorphous semiconductor layer and a TCO (transparent conductive film) are formed on almost the entire surface of a substrate surface, the amorphous semiconductor layer, the TCO, There is no break between. However, when a plurality of layers such as an n-type amorphous semiconductor layer or a p-type amorphous semiconductor layer, a TCO, and an electrode are alternately formed as in the backside heterojunction solar cell in this embodiment, FIG. As shown, a large number of end portions of each layer are generated. When a peel test or the like is performed with such a configuration, there is a possibility of peeling from the end. However, it is preferable to form a texture structure on the surface of the semiconductor substrate 1 because an anchor effect is generated and peeling and the like are easily suppressed. Further, it is more preferable that the electrode end portion that is most easily peeled off is covered with a protective film, whereby peeling can be more effectively suppressed.

Further, in the gap region G, the passivation film 3, the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are covered with a protective film 8. As a result, an effect of long-term stability of the photoelectric conversion element 10 can be obtained.

FIG. 13 is a plan view seen from the back side of the photoelectric conversion element 10 shown in FIG. Referring to (a) of FIG. 13, n-type amorphous semiconductor layer 4 and p-type amorphous semiconductor layer 5 are alternately arranged at desired intervals in the in-plane direction of semiconductor substrate 1. The translucent electrodes 6 and 7 are disposed on the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, respectively. As a result, a gap region G is formed between the adjacent translucent electrodes 6 and 7.

Referring to FIG. 13B, the protective film 8 is disposed on the gap region G and the peripheral region of the semiconductor substrate 1.

The translucent electrodes 6 and 7 are formed by being electrically connected to the conductive reflective layers 9a and 9b with a part of the opening 8A and a contact width Z shown in FIG. The contact width Z at this time is preferably 5 μm or more, and more preferably 10 μm or more. However, the contact width Z is preferably about 70% or less of the width of the translucent electrodes 6 and 7. If the width is larger than this, the amount of light taken from the back surface is greatly reduced. Therefore, the contact width Z is preferably about 70% or less of the width of the translucent electrodes 6 and 7.

Carriers taken out from the silicon wafer pass through the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, pass through the translucent electrodes 6 and 7, pass through the region of the contact width Z, and become conductive. It flows in the reflective layer 9. By connecting the conductive reflective layer 9 to the finger portion of the wiring material, it is possible to take out the electric power generated in the wafer on the wiring sheet side.

In the present embodiment, the conductive reflective layer 9 is formed on the protective film 8 above the gap region, thereby suppressing an electrical short circuit between the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5. can do. The electrode end on the opposite side of the contact width Z region where the conductive reflective layer 9 is in contact with the n-type amorphous semiconductor layer 4 or the p-type amorphous semiconductor layer 5 is at least 3 μm inside from the end of the protective film 8 It is preferable to form. More preferably, it is 5 μm or more inside from the end of the protective film 8. The interval W shown in FIG. 11 (o) is the interval between the end of the conductive reflective layer 9 opposite to the region of the contact width Z and the end of the protective film 8.

The end of the protective film 8 is often thin and may have low insulation. Further, due to misalignment or the like, the conductive reflective layer 9 may come into contact with the adjacent amorphous semiconductor layer and a leak current may be generated. Therefore, the conductive reflective layer 9 may be the n-type amorphous semiconductor layer 4 or p. It is preferable that the electrode end on the opposite side of the contact width Z region in contact with the type amorphous semiconductor layer 5 is provided with the distance W from the end of the protective film 8 by the distance described above.

In FIG. 13B, a region that is not covered with the protective film 8 exists in the peripheral portion of the semiconductor substrate 1, but in the photoelectric conversion element 10, the entire back surface of the semiconductor substrate 1 is protected. Most preferably, the film is covered with a film and a part of the translucent electrodes 6 and 7 is exposed.

FIG. 14 is a plan view of the wiring sheet. Referring to FIG. 14, wiring sheet 70 includes an insulating base 710 and wiring members 71-87.

The insulating base material 710 may be an electrically insulating material and can be used without any particular limitation. The insulating base 710 may be made of, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyphenylene sulfide (PPS), polyvinyl fluoride (PVF), polyimide, and the like. In addition, the insulating base 710 is preferably transparent so that it can transmit sunlight, and it is preferable that the insulating base 710 has as high a translucency as possible.

The film thickness of the insulating substrate 710 is not particularly limited, but is preferably 25 μm or more and 150 μm or less. The insulating base 710 may have a single layer structure or a multilayer structure of two or more layers.

The wiring member 71 has a bus bar portion 711 and finger portions 712. One end of the finger portion 712 is connected to the bus bar portion 711.

The wiring member 72 has a bus bar portion 721 and finger portions 722 and 723. One end of the finger portion 722 is connected to the bus bar portion 721. One end of the finger portion 723 is connected to the bus bar portion 721 on the opposite side of the connection portion between the bus bar portion 721 and the finger portion 722 with respect to the bus bar portion 721.

The wiring member 73 includes a bus bar portion 731 and finger portions 732 and 733. One end of the finger portion 732 is connected to the bus bar portion 731. One end of the finger portion 733 is connected to the bus bar portion 731 on the opposite side of the connection portion between the bus bar portion 731 and the finger portion 732 with respect to the bus bar portion 731.

The wiring member 74 has a bus bar portion 741 and finger portions 742 and 743. One end of the finger portion 742 is connected to the bus bar portion 741. One end of the finger portion 743 is connected to the bus bar portion 741 on the opposite side of the connection portion between the bus bar portion 741 and the finger portion 742 with respect to the bus bar portion 741.

The wiring member 75 has a bus bar portion 751 and finger portions 752 and 753. The finger portions 752 and 753 are arranged adjacent to each other in the length direction of the bus bar portion 751, and one end thereof is connected to the bus bar portion 751 on the same side of the bus bar portion 751.

The wiring member 76 includes a bus bar portion 761 and finger portions 762 and 763. One end of the finger portion 762 is connected to the bus bar portion 761. One end of the finger part 763 is connected to the bus bar part 761 on the opposite side of the connection part between the bus bar part 761 and the finger part 762 with respect to the bus bar part 761.

The wiring member 77 has a bus bar portion 771 and finger portions 772 and 773. One end of finger portion 772 is connected to bus bar portion 771. One end of the finger portion 773 is connected to the bus bar portion 771 on the opposite side of the connection portion between the bus bar portion 771 and the finger portion 772 with respect to the bus bar portion 771.

The wiring member 78 includes a bus bar portion 781 and finger portions 782 and 783. One end of the finger portion 782 is connected to the bus bar portion 781. One end of the finger portion 783 is connected to the bus bar portion 781 on the opposite side of the connection portion between the bus bar portion 781 and the finger portion 782 with respect to the bus bar portion 781.

The wiring member 79 has a bus bar portion 791 and finger portions 792 and 793. Finger portions 792 and 793 are arranged adjacent to each other in the length direction of bus bar portion 791, and one end thereof is connected to bus bar portion 791 on the same side of bus bar portion 791.

The wiring member 80 has a bus bar portion 801 and finger portions 802 and 803. One end of the finger portion 802 is connected to the bus bar portion 801. One end of the finger part 803 is connected to the bus bar part 801 on the opposite side of the connection part between the bus bar part 801 and the finger part 802 with respect to the bus bar part 801.

The wiring member 81 has a bus bar portion 811 and finger portions 812 and 813. One end of the finger portion 812 is connected to the bus bar portion 811. One end of the finger portion 813 is connected to the bus bar portion 811 on the opposite side of the connection portion between the bus bar portion 811 and the finger portion 812 with respect to the bus bar portion 811.

The wiring member 82 has a bus bar portion 821 and finger portions 822 and 823. One end of the finger portion 822 is connected to the bus bar portion 821. One end of the finger part 823 is connected to the bus bar part 821 on the opposite side of the connection part between the bus bar part 821 and the finger part 822 with respect to the bus bar part 821.

The wiring member 83 includes a bus bar portion 831 and finger portions 832 and 833. Finger portions 832 and 833 are arranged adjacent to each other in the length direction of bus bar portion 831, and one end thereof is connected to bus bar portion 831 on the same side of bus bar portion 831.

The wiring member 84 includes a bus bar portion 841 and finger portions 842 and 843. One end of the finger portion 842 is connected to the bus bar portion 841. One end of the finger portion 843 is connected to the bus bar portion 841 on the opposite side of the connection portion between the bus bar portion 841 and the finger portion 842 with respect to the bus bar portion 841.

The wiring member 85 includes a bus bar portion 851 and finger portions 852 and 853. One end of the finger portion 852 is connected to the bus bar portion 851. One end of the finger portion 853 is connected to the bus bar portion 851 on the opposite side of the connection portion between the bus bar portion 851 and the finger portion 852 with respect to the bus bar portion 851.

The wiring member 86 has a bus bar portion 861 and finger portions 862 and 863. One end of the finger portion 862 is connected to the bus bar portion 861. One end of the finger portion 863 is connected to the bus bar portion 861 on the opposite side of the connection portion between the bus bar portion 861 and the finger portion 862 with respect to the bus bar portion 861.

The wiring member 87 has a bus bar portion 871 and finger portions 872. One end of the finger portion 872 is connected to the bus bar portion 871.

The wiring member 71 is disposed on the insulating base 710 so that the finger portion 712 meshes with the finger portion 722 of the wiring member 72.

The wiring member 72 is disposed on the insulating substrate 710 so that the finger portion 722 is engaged with the finger portion 712 of the wiring member 71 and the finger portion 723 is engaged with the finger portion 732 of the wiring member 73.

The wiring member 73 is disposed on the insulating base 710 so that the finger portion 732 is engaged with the finger portion 723 of the wiring member 72 and the finger portion 733 is engaged with the finger portion 742 of the wiring member 74.

The wiring member 74 is disposed on the insulating base 710 so that the finger portion 742 is engaged with the finger portion 733 of the wiring member 73 and the finger portion 743 is engaged with the finger portion 752 of the wiring member 75.

The wiring member 75 is disposed on the insulating base 710 so that the finger portions 752 are engaged with the finger portions 743 of the wiring member 74 and the finger portions 753 are engaged with the finger portions 762 of the wiring member 76.

The wiring member 76 is disposed on the insulating base 710 so that the finger portion 762 is engaged with the finger portion 753 of the wiring member 75 and the finger portion 763 is engaged with the finger portion 772 of the wiring member 77.

The wiring member 77 is disposed on the insulating substrate 710 so that the finger portion 772 meshes with the finger portion 763 of the wiring material 76 and the finger portion 773 meshes with the finger portion 782 of the wiring material 78.

The wiring member 78 is disposed on the insulating base 710 so that the finger portions 782 mesh with the finger portions 773 of the wiring material 77 and the finger portions 783 mesh with the finger portions 792 of the wiring material 79.

The wiring member 79 is disposed on the insulating base 710 so that the finger portion 792 is engaged with the finger portion 783 of the wiring member 78 and the finger portion 793 is engaged with the finger portion 802 of the wiring member 80.

The wiring member 80 is disposed on the insulating base 710 so that the finger portion 802 is engaged with the finger portion 793 of the wiring member 79 and the finger portion 803 is engaged with the finger portion 812 of the wiring member 81.

The wiring member 81 is disposed on the insulating base 710 so that the finger portion 812 is engaged with the finger portion 803 of the wiring member 80 and the finger portion 813 is engaged with the finger portion 822 of the wiring member 82.

The wiring member 82 is disposed on the insulating base 710 so that the finger portion 822 is engaged with the finger portion 813 of the wiring member 81 and the finger portion 823 is engaged with the finger portion 832 of the wiring member 83.

The wiring member 83 is disposed on the insulating base 710 so that the finger portion 832 is engaged with the finger portion 823 of the wiring member 82 and the finger portion 833 is engaged with the finger portion 842 of the wiring member 84.

The wiring member 84 is disposed on the insulating base 710 so that the finger portion 842 is engaged with the finger portion 833 of the wiring member 83 and the finger portion 843 is engaged with the finger portion 852 of the wiring member 85.

The wiring member 85 is disposed on the insulating base 710 such that the finger portion 852 is engaged with the finger portion 843 of the wiring member 84 and the finger portion 853 is engaged with the finger portion 862 of the wiring member 86.

The wiring member 86 is arranged on the insulating base 710 so that the finger portion 862 is engaged with the finger portion 853 of the wiring member 85 and the finger portion 863 is engaged with the finger portion 872 of the wiring member 87.

The wiring member 87 is disposed on the insulating base 710 so that the finger portion 872 meshes with the finger portion 863 of the wiring member 86.

Each of the wiring members 71 to 87 is not particularly limited as long as it is electrically conductive. Each of the wiring members 71 to 87 is made of, for example, Cu, Al, Ag, and an alloy containing these as main components.

The thickness of the wiring members 71 to 87 is not particularly limited, but is preferably 10 μm or more and 80 μm or less. If it is less than 10 μm, the wiring resistance becomes high, and if it exceeds 80 μm, the silicon substrate is warped due to the difference in thermal expansion coefficient between the wiring material and the silicon substrate due to the heat applied when the photoelectric conversion element 10 is bonded. appear.

Further, in order to effectively capture sunlight from the back surface, the width of the wiring material is preferably as narrow as possible, and the width does not cover the area where the translucent electrodes 6 and 7 are not covered with the protective film 8. Is preferred. The width of the wiring members 71 to 87 is more preferably equal to or less than the width of the gap region G of the photoelectric conversion element 10 +300 μm. Therefore, when the width of the gap region G is 100 μm, the width of the wiring members 71 to 87 is preferably 400 μm or less. In such a case, the light from the back surface can be taken in efficiently. More preferably, the width of the wiring members 71 to 87 is equal to or less than the width of the gap region G of the photoelectric conversion element 10 +150 μm.

The shape of the insulating substrate 710 is not limited to the shape shown in FIG. 14 and can be changed as appropriate. Further, a conductive material such as Ni, Au, Pt, Pd, Sn, In, and ITO may be formed on a part of the surface of the wiring members 71 to 87. As described above, the conductive material such as Ni is formed on a part of the surface of the wiring materials 71 to 87 because the electrical connection between the wiring materials 71 to 87 and the conductive reflective layer 9 of the photoelectric conversion element 10 is performed. This is to improve the weather resistance of the wiring members 71 to 87. Further, the wiring members 71 to 87 may have a single layer structure or a multilayer structure.

The photoelectric conversion element 10 is arranged on the region REG1 so that the conductive reflective layer 9a is connected to the finger part 712 of the wiring member 71 and the conductive reflective layer 9b is connected to the finger part 722 of the wiring member 72, so The photoelectric conversion element 10 is arranged on the region REG2 so that the reflective layer 9a is connected to the finger part 723 of the wiring material 72 and the conductive reflective layer 9b is connected to the finger part 732 of the wiring material 73. Thereafter, the photoelectric conversion element 10 is similarly disposed on the wiring members 73 to 87. Thereby, the 16 photoelectric conversion elements 10 are connected in series. Light from the back surface enters through the insulating base 710 and the translucent electrodes 6 and 7.

The conductive reflective layers 9a and 9b of the photoelectric conversion element 10 are connected to the wiring members 71 to 87 by an adhesive. Examples of the adhesive include solder resin, solder, conductive adhesive, thermosetting Ag paste, low-temperature curing copper paste, anisotropic conductive film (ACF), anisotropic conductive paste (ACP: Anisotropic paste). It consists of one or more types of adhesives selected from the group consisting of Conductive Paste) and insulating adhesives (NCP: NonＣＰConductive Paste).

For example, TCAP-5401-27 manufactured by Tamura Kaken Co., Ltd. can be used as the solder resin.

As the insulating adhesive, an epoxy resin, an acrylic resin, a urethane resin, or the like can be used, and a thermosetting resin or a photocurable resin can be used.

As the conductive adhesive, solder particles containing at least one of tin and bismuth can be used. More preferably, the conductive adhesive is an alloy of tin and bismuth, indium, silver or the like. As a result, the melting point of the solder can be suppressed, and an adhesion process at a low temperature becomes possible.

When the photoelectric conversion element 10 in which the protective film 8 and the conductive reflective layer 9 are formed on the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5 and the translucent electrodes 6 and 7 is used, An inorganic insulating film on the photoelectrodes 6 and 7 and an inorganic insulating film on the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 exist. Different. And in the photoelectric conversion element 10, the inorganic insulating film from which a foundation | substrate differs is formed continuously. In such a situation, when a thermal history is applied to an inorganic insulating film having a different base, peeling of the inorganic insulating film may occur due to a difference in thermal expansion coefficient of the base.

Therefore, a low temperature, particularly a heat process of 200 ° C. or lower is preferable, and as a result, a thermosetting Ag paste, a low temperature curable copper paste, an anisotropic conductive film and an anisotropic conductive film that can be cured and electrically bonded at a low temperature. A paste is particularly preferred.

As described above, the photoelectric conversion element 10 disposed on the wiring sheet 70 is disposed between the ethylene vinyl acetate resin (EVA resin) disposed on the glass substrate and the EVA resin disposed on the PET film. . Then, the EVA resin on the glass substrate side is pressure-bonded to the photoelectric conversion element 10 by vacuum pressure bonding using a laminator device, and the EVA resin on the PET film side is pressure-bonded to the photoelectric conversion element 10 and heated to 125 ° C. to be cured. I let you. Thereby, a solar cell module can be produced by sealing the photoelectric conversion element 10 with the wiring sheet 70 in the EVA resin cured between the glass substrate and the PET film.

In consideration of ensuring insulation, the thickness of the inorganic insulating film constituting the protective film 8 is preferably 20 nm or more, and more preferably 40 nm or more. When the film thickness is 1 μm or more, the inorganic insulating film may be peeled off due to the internal stress of the inorganic insulating film on the electrode. Therefore, the film thickness is preferably less than 1 μm.

Also, if the width of the conductive reflective layers 9a and 9b is narrow, the series resistance increases, so that the width needs to be 20 μm or more, more preferably 40 μm or more.

[Moisture resistance]
FIG. 15 is a diagram showing the results of a moisture-proof resistance test. Referring to FIG. 15, i represents intrinsic amorphous silicon, i / n represents a laminated film of intrinsic amorphous silicon and n-type amorphous silicon, and i / SiN represents intrinsic amorphous silicon. It represents a laminated film of silicon and silicon nitride.

I / n / SiN represents a laminated film of intrinsic amorphous silicon, n-type amorphous silicon and silicon nitride, and i / SiON represents a laminated film of intrinsic amorphous silicon and silicon oxynitride. I / SiO ₂ represents a laminated film of intrinsic amorphous silicon and silicon dioxide, and i / TiO ₂ represents a laminated film of intrinsic amorphous silicon and titanium dioxide.

In addition, an i layer such as n / SiN, n / SiON, n / SiO ₂ , or n / TiO ₂ may be replaced with an n layer.

Note that the concentration of P in the n-type amorphous silicon is 1 × 10 ²⁰ cm ⁻³ .

The amorphous semiconductor film shown in FIG. 15 was formed on a silicon substrate, and immediately after the film formation, the lifetime of minority carriers of the sample was measured using a μPCD (microwave Photo Conductivity Decay) method. In the μPCD method, a state in which carriers are induced in the semiconductor layer by irradiating the surface of the semiconductor layer with laser light and a state in which the induced carriers disappear by irradiating the laser light are created. Measure time. In order to measure the amount of carriers, the surface of the semiconductor layer is irradiated with microwaves, and the reflectance of the microwaves is measured.

Then, after 3 days and 8 days, the minority carrier lifetime was measured under the same conditions as above.

In FIG. 15, the lifetime normalized by the lifetime immediately after film formation is shown.

As shown in FIG. 15, in an amorphous semiconductor film such as amorphous silicon, moisture (H ₂ O, OH group, etc.) from the atmosphere is diffused, so that the lifetime after 3 days and after 8 days is as follows. It is greatly reduced by about 30 to 50% compared to immediately after the film (see Sample 1 to Sample 4).

This is due to the following reason. An amorphous film has a lower film density than a single crystal film having the same composition, and includes many voids in the film. The reason why the refractive index of the amorphous film is lower than that of the crystal is that there are many voids, and the existence of voids is related to moisture resistance, and it is difficult to obtain an effect when the film thickness is thin. it is conceivable that. When the film thickness is about several nanometers to 30 nm, it is considered that moisture from the outside is absorbed by the amorphous semiconductor layer and the passivation property of the crystalline silicon interface is lowered.

On the other hand, when any one of SiN, SiON, and SiO ₂ is formed on the amorphous semiconductor layer, the lifetime after 3 days and after 8 days is maintained as the lifetime immediately after the film formation. When TiO ₂ is formed thereon, the lifetime after 3 days and after 8 days is only about 10% lower than the lifetime immediately after film formation (see Sample 5 to Sample 9).

Thus, it was found that by forming an inorganic insulating film (SiN or the like) on the amorphous semiconductor layer, the above moisture absorption can be suppressed and the lifetime can be suppressed.

When a thermal oxide film (2 nm) is formed on a silicon substrate, the lifetime is about 40% lower than that immediately after film formation after 8 days. Accordingly, it has been found that covering the surface of the silicon substrate with intrinsic amorphous silicon is important for suppressing the decrease in lifetime (see Sample 5 to Sample 10).

As described above, it has been found that by forming an inorganic insulating film on the amorphous semiconductor layer, it is possible to ensure moisture proofness and suppress the change in passivation properties over time.

From such knowledge, electrical insulation and moisture resistance can be realized by adopting a structure in which an inorganic insulating film is formed on an amorphous semiconductor layer.

Therefore, by adopting an inorganic insulating film as the protective film 8, the formation of the protective film 8 in the combination with the passivation film 3, the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 is performed on the electrode 6. , 7 can be prevented, the moisture resistance in the gap region G can be improved, and the passivation can be improved at the same time.

Further, it is preferable to form the protective film 8 with a two-layer structure in which an inorganic insulating film is formed on the amorphous semiconductor layer, since electrical insulation and moisture resistance can be realized.

The film thickness of the inorganic insulating film is preferably 20 nm or more in consideration of moisture resistance, and is preferably 10 nm or more for a silicon nitride film or silicon oxynitride film having high moisture resistance.

Since the metal electrodes and / or the TCO electrodes are formed in the regions where the translucent electrodes 6 and 7 are formed, they ensure moisture resistance, so that the protective film 8 on the metal electrodes or the TCO electrodes is provided. The moisture-proof property can be secured with respect to the opening 8A.

Further, since the protective film 8 is formed so as to cover a part of the translucent electrodes 6 and 7 similarly to the gap region G, the surface of the translucent electrodes 6 and 7 below the protective film 8 is formed. Is protected by the protective film 8 and can prevent surface oxidation and discoloration. As a result, the long-term reliability of the translucent electrodes 6 and 7 can be secured, which is preferable.

Thus, it is preferable that the protective film 8 is formed on the translucent electrodes 6 and 7 and the gap region G in order to improve insulation and moisture resistance. The protective film on the translucent electrodes 6 and 7 and the protective film on the gap region G do not necessarily need to be continuous films, but by forming them as continuous films, the number of process steps can be reduced. The film quality is more preferable because it is uniform and uniform.

It has been found that the above moisture-proof effect can be obtained even on the surface of the semiconductor substrate 1 on which the texture is formed.

[Heat-resistant]
As described above, when the photoelectric conversion element 10 is modularized, there is a step of bonding the photoelectric conversion element 10 and the wiring sheet 70 using a conductive adhesive or an insulating adhesive, which is about 180 ° C. for about 20 minutes. There is a heating process.

When the thermal history at 180 ° C. for 20 minutes is entered, the gap region G and the gap region G when the protective film 8 is present on the amorphous semiconductor layer around the wafer and when the protective film 8 is not present. , And the lifetime of minority carriers in the periphery of the wafer.

When the protective film 8 does not exist on the amorphous semiconductor layer, the lifetime of minority carriers, which is usually about 2400 μs, decreased to 700 μs.

On the other hand, in the case where the protective film 8 is present on the amorphous semiconductor layer, the lifetime of the minority carriers remained at a decrease of 2000 μs.

Thus, it has been found that the presence of the protective film 8 also in the gap region G and the peripheral portion of the wafer can suppress a decrease in the lifetime of minority carriers in the entire wafer.

Further, since the inorganic insulating film (protective film 8) is also present on the translucent electrodes 6 and 7, and the translucent electrodes 6 and 7 assist the heat dissipation of the inorganic insulating film, the heat resistance is more preferable. The effect is obtained.

It has been found that the heat resistance effect described above can be obtained even on the surface of the semiconductor substrate 1 on which the texture is formed.

[Adhesion of protective film]
When the protective film 8 was formed on the surface of the semiconductor substrate 1 on which the texture was formed, the effect of improving the adhesion of the protective film 8 was confirmed. The protective film 8 includes a portion formed on the translucent electrodes 6 and 7 and a portion formed in the gap region G. Depending on the selection and combination of the underlying material, peeling may occur. . However, when the protective film 8 is formed on the surface on which the texture is formed, the effect of significantly improving the adhesion is seen even with a combination with a base that peels off. In a simple peel test, even if the surface is peeled off on a flat surface on which no texture is formed, the protective film 8 is formed on the surface on which the texture is formed. These contribute to the long-term reliability of the photoelectric conversion element 10.

[Electrode floating]
Compared to the photoelectric conversion element 10 of the present embodiment in which the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are patterned on the textured surface, the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are formed on the semiconductor substrate on which no texture is formed. A comparative photoelectric conversion element in which the amorphous semiconductor layer and the p-type amorphous semiconductor layer were patterned was produced. About these two photoelectric conversion elements, the temperature was raised to 150 ° C., 170 ° C., 190 ° C., and 210 ° C. and heated at the respective temperatures for 10 minutes in each atmosphere, and the lifting of the electrodes was observed.

In this observation of the lifting of the electrode, a photoelectric conversion element in which ITO is directly formed on the translucent electrodes 6 and 7 and silver is formed on the amorphous semiconductor layer in the conductive reflective layer 9 was used. Here, electrode floating in the width of the contact region Z will be described.

In the photoelectric conversion element of the comparative example patterned on the flat surface where the texture is not formed, when heated at 190 ° C., the contact region Z of the electrode 9 was lifted. In the photoelectric conversion element 10 of the present embodiment provided, no lifting of the electrode was observed. The film formation conditions of the amorphous semiconductor layer are the same in any of the photoelectric conversion elements, but the (111) plane or a surface with a plane orientation close thereto is formed on the textured surface of the semiconductor substrate 1. It is thought that the results are different due to the change in the film quality.

In the (100) plane of the semiconductor substrate, two dangling bonds of silicon appear on the outermost surface, whereas in the (111) plane where the texture is formed, there is one dangling bond. Due to the difference in the number of dangling bonds, the passivation property of the semiconductor substrate surface and the film quality of the formed amorphous semiconductor layer, such as the amount of hydrogen, oxygen and nitrogen in the film, also change. It is thought that the state of changes.

The electrode floating is considered to be not a problem even in the configuration of the photoelectric conversion element of the comparative example. However, according to the configuration of the photoelectric conversion element 10 in the present embodiment, the electrode floating can be suppressed even when heated at a high temperature. Therefore, in consideration of the yield and the like, the configuration in which the texture is formed on the semiconductor substrate is more preferable.

This electrode floating was found to correlate with the texture inclination angle for the above reasons. As shown in FIG. 16, the texture inclination angle is, for example, an angle θ formed between the (100) plane surface and the texture inclination plane (111) plane in the case of a (100) plane semiconductor substrate. It becomes.

The angle θ may deviate from the theoretical value of 54.7 degrees to a smaller angle depending on etching conditions and the like. It has been found that the yield of electrode floating is improved when the angle θ is 30 degrees or more. The angle θ is preferably 40 degrees or more. When the electrode floats, the contact resistance increases, leading to peeling of the electrode and lowering the reliability. According to the configuration in which the texture is formed on the semiconductor substrate like the photoelectric conversion element 10 of the present embodiment, since the electrode floating can be suppressed even when heated at a high temperature, the degree of freedom of the process in the modularization process is increased. More preferred.

In addition, when the conductive reflective layer 9 on the protective film 8 was formed on the textured surface, an effect of suppressing electrode floating and electrode peeling was observed. In the gap region G on the textured surface, the structure in which the amorphous semiconductor layer (passivation film 3), the protective film 8, and the conductive reflective layer 9 are laminated in this order effectively suppresses electrode floating and electrode peeling. I understood that I could do it.

[Influence of wraparound]
FIG. 17 is a diagram for explaining that when the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are patterned, the semiconductor layer and the dopant wrap around under the shadow mask. FIG. 17A is a view when the amorphous semiconductor layer 161 is patterned on the semiconductor substrate 1 on which the texture is formed, and FIG. 17B is a flat semiconductor substrate on which the texture is not formed. It is a figure at the time of patterning the amorphous semiconductor layer 161a.

In both cases where the texture is formed on the semiconductor substrate and when the texture is not formed, the amorphous semiconductor is formed by Δd inward in the in-plane direction from the end Z of the shadow mask 160 below the shadow mask 160. It was found that the layer 161 and the dopant wrap around.

When the semiconductor substrate 1a shown in FIG. 17B is a flat surface, the flatness of the surface is high and there are only 1 nm irregularities, so that the gap between the shadow mask 160a and the semiconductor substrate 1a can be very narrow. This makes it difficult for the source gas and the dopant gas to flow between the shadow mask 160a and the semiconductor substrate 1a, so that the wraparound width Δd is greatly suppressed.

On the other hand, in the semiconductor substrate 1 on which the texture shown in FIG. 17A is formed, since the surface is uneven, the gap between the shadow mask 160 and the surface of the semiconductor substrate 1 is larger than the flat surface. . In particular, as described above, when a pyramid-like texture is formed by anisotropic etching using an alkali solution on a semiconductor substrate, there are many voids near the top of the pyramid, and it is difficult to suppress the wraparound of the source gas and the dopant gas. It has a shape. Since the source gas and the dopant gas flow into the increased gap, the wraparound width Δd increases.

FIG. 18A is a diagram showing a texture formed on the semiconductor substrate 1, and FIG. 18B is a diagram illustrating a void area between the semiconductor substrate 1 on which the texture is formed and the shadow mask 170. FIG. It is a figure for doing. As shown in FIG. 18A, when the texture size increases, the difference in size of one pyramid increases. For example, in the region B, a large pyramid having a texture size of about 40 μm exists, whereas in the region A, a plurality of small pyramids having a texture size of about 15 μm exist. Therefore, the difference in texture size between the pyramids in the region A and the region B is as large as 25 μm.

When irregularities having a large texture size are formed, as described above, due to the large difference in texture size and the presence of a region where a plurality of small textures are gathered, as shown schematically in FIG. And a large void region 171 is formed between the surface of the semiconductor substrate. Since the source gas and the dopant gas wrap around the void region 171, the wraparound width Δd increases.

FIG. 19 is a diagram for explaining that boron, which is a p-type dopant, wraps around from the end of the shadow mask 160 in the in-plane direction. FIG. 19A shows the boron concentration characteristics of the surface measured by TOF-SIMS (time-of-flight secondary ion mass spectrometry). FIG. 19B shows the positional relationship between the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5. An intrinsic (i-type) amorphous semiconductor layer is formed on the entire surface of the semiconductor substrate 1, and then an n-type amorphous semiconductor layer 4 is formed using a shadow mask, and then a p-type amorphous semiconductor layer 5 is formed. Once formed, the boron concentration characteristics were measured. As shown by the arrow in FIG. 19B, the boron concentration characteristic in the X-axis direction was measured from the p-type amorphous semiconductor layer 5 toward the i-type amorphous semiconductor layer. FIG. 19C shows the magnitude of the wraparound width of boron in the Y-axis direction shown in FIG.

In FIG. 19A, the shadow mask 150 of the photoelectric conversion element 10 of the present embodiment in which the texture is formed on the semiconductor substrate 1 and the photoelectric conversion element of the comparative example in which the texture is not formed on the semiconductor substrate are shown. The relationship between the inward in-plane distance and the boron concentration is shown. However, the region from 0 to 180 μm is a region where the p-type amorphous semiconductor layer 5 is formed. The size of the texture formed on the semiconductor substrate was 1.5 μm.

When the texture size is increased, a region having a large gap and a region having a small gap are formed in the plane. Therefore, when the shadow mask is arranged, as shown in FIG. In the Y-axis direction, it was found that the wraparound width of boron differs depending on the location. The variation in the wraparound width of boron is preferably smaller in consideration of the stability of the characteristics of the photoelectric conversion element and the yield. In a place where the gap is large, the wraparound width increases as Δd1 and Δd3 in FIG. 19C, and in a region where the texture size is relatively the same, the wraparound width decreases as Δd2. Therefore, it is necessary to suppress the region where the wraparound width of boron is as large as possible, such as Δd1 and Δd3.

When the texture size is reduced, the generation of a large void area as shown in FIG. Thereby, the wraparound width Δd of boron is relatively uniform in the Y-axis direction and can be reduced.

FIG. 20 is a diagram for explaining that the wraparound width of boron varies depending on the texture size. (A) of FIG. 20 shows the area | region which analyzed the density | concentration of boron. However, the upper view of FIG. 20A is a top view, and the lower view is a side view. 20B shows the boron density characteristics when the texture size is 35 μm, and FIG. 20C shows the boron density characteristics when the texture size is 3 μm.

Here, an 8 nm i-type intrinsic amorphous semiconductor layer was first formed on the surface of the semiconductor substrate, and a p-type amorphous semiconductor layer 5 was formed thereon using a shadow mask. Then, the in-plane distribution of the boron concentration on the outermost surface was measured using TOF-SIMS. When the texture size is 35 μm, boron wraps around at a very high concentration in the region of about 300 μm in the i-layer region. On the other hand, when the texture size is 3 μm, the boron concentration in the region of about 300 μm is lower than the boron concentration when the texture size is 35 μm.

[Difference in wraparound by dopant type]
It has been found that the wraparound of the dopant gas has different characteristics depending on the dopant gas type. It has been found that when a dopant gas containing boron is used as the dopant gas of the p-type amorphous semiconductor layer 5, a very special wraparound occurs. Here, although the result when diborane (B ₂ H ₆ ) is used will be described, other dopant gas containing boron may be used.

In FIG. 19A, the region from 0 to 180 μm is a region where the p-type amorphous semiconductor layer 5 is formed. When the texture is formed on the semiconductor substrate 1, as shown in FIG. 19A, the vicinity of the boundary between the region where the p-type amorphous semiconductor layer 5 is formed and the region where the p-type amorphous semiconductor layer 5 is not formed (about 180 μm). In the region), the boron concentration has a peak, which is about four times the region where the p-type amorphous semiconductor layer 5 is formed. A boron diffusion region is seen from about 180 μm to 300 μm from the vicinity of this boundary toward the region where the p-type amorphous semiconductor layer 5 is not formed. The width of the boron diffusion region is a wraparound width Δd (Δd = 300 μm−180 μm = 120 μm). Here, a region having a higher boron concentration than the boron concentration in the region where the p-type amorphous semiconductor layer 5 is formed is referred to as a “high boron concentration region”.

Even on a flat surface where no texture is formed on the semiconductor substrate, there is a region where the boron concentration is at a peak. The boron concentration in this region is boron in the region where the p-type amorphous semiconductor layer 5 is formed. The density is about twice or less. For this reason, there is a correlation between the uneven surface of the semiconductor substrate 1 and the boron concentration in the high-concentration region of boron. It can be seen that the boron concentration increases as the unevenness of the texture formed on the semiconductor substrate 1 increases.

Therefore, when forming the p-type amorphous semiconductor layer 5 using boron as a dopant, it is preferable to form the n-type amorphous semiconductor layer 4 so as not to overlap the high concentration region of boron. This is because when the n-type amorphous semiconductor layer 4 is formed later, the i-type amorphous semiconductor layer 4 and the n-type amorphous semiconductor layer 4 are formed. A high-concentration region of boron is formed at the interface, and a phenomenon in which the lifetime of minority carriers decreases is observed in this region, which is not preferable. For example, of the formation region of the n-type amorphous semiconductor layer 4 shown in FIG. 2A, a region having a width of (L + 2H) may be formed out of the high concentration region of boron. Further, in FIG. 5, it is sufficient that the region sandwiched between the two B points is formed away from the high-concentration region of boron. In FIG. In (b) of 6, it is only necessary that the region sandwiched between the two F points is formed away from the high concentration region of boron.

For the same reason, the translucent electrode 6 may be formed out of the high concentration region of boron. The region of (L + 2H) width in FIG. 2A is preferably formed away from the high concentration region of boron.

As a dopant of the n-type amorphous semiconductor layer 4, film formation was performed using a dopant gas containing phosphorus. In the present embodiment, phosphine (PH ₂ ) is used as a dopant gas containing phosphorus. When a dopant gas containing phosphorus was used, no special wraparound such as boron was caused. In boron, the wraparound width Δd was about 120 μm, but the wraparound width of phosphorus was about 20-30 μm even when using the texture size and shadow mask under the same conditions. Thus, it turned out that the amount of wraparound by a dopant seed | species differs.

When p-type amorphous semiconductor layer 5 or n-type amorphous semiconductor layer 4 is patterned using a shadow mask, it is preferable to first form an amorphous semiconductor layer containing a dopant having a small wraparound width. The interface between the passivation film 3 and the p-type amorphous semiconductor layer 5 or the n-type amorphous semiconductor layer 4 is particularly important, and it is not preferable that a dopant of a different conductive layer enters here. When an amorphous semiconductor layer containing a dopant having a large wraparound width is formed first after the passivation film 3 is formed, the wraparound width is large in a region on the passivation film of the amorphous semiconductor layer having a small wraparound width to be formed later. It is highly possible that the dopant diffuses and the characteristics are deteriorated.

That is, in the case of the above boron and phosphorus, the n-type amorphous semiconductor layer 4 containing phosphorus with a small wraparound width is formed first, and then the p-type amorphous semiconductor layer containing boron with a large wraparound width. 5 is preferably formed.

According to the photoelectric conversion element 10 according to the present embodiment, since the electrodes 6 and 7 are translucent electrodes, light can be incident not only from the light receiving surface but also from the back surface. Will improve. Further, by providing the conductive reflective layer 9 on the gap region G, light incident on the gap region G from the light receiving surface is reflected by the conductive reflective layer 9 and returns to the semiconductor substrate 1, so that it is absorbed by the semiconductor substrate 1. The ratio of light to be increased will increase the power generation efficiency.

[Embodiment 2]
FIG. 21 is a cross-sectional view showing the configuration of the photoelectric conversion element according to Embodiment 2 of the present invention. Referring to FIG. 21, in photoelectric conversion element 200 according to Embodiment 2, translucent electrodes 6 and 7 are covered with protective film 208 and conductive reflective layer 209. Other configurations are the same as those of the photoelectric conversion element 10.

Compared with the configuration shown in FIG. 1, the protective film 208 of the photoelectric conversion element according to Embodiment 2 has a larger area covering the translucent electrodes 6 and 7. However, the translucent electrodes 6 and 7 are not completely covered with the protective film 208, and the protective film 208 has an opening 208A. A conductive reflective layer 209 is provided so as to cover the opening 208 </ b> A of the protective film 208. That is, the translucent electrodes 6 and 7 are electrically connected to the conductive reflective layer 209 in the opening 208A of the protective film 208, and carriers can be taken out through this electrically connected contact region. it can.

Thus, since the translucent electrodes 6 and 7 can be structurally and electrically protected by covering the translucent electrodes 6 and 7 with the protective film 208 and the conductive reflective layer 209, reliability is improved. Can be improved. Furthermore, it is more preferable to form a protective film on the conductive reflective layers 209a and 209b because the electrical insulation of the conductive reflective layers 209a and 209b can be improved.

A method for manufacturing the photoelectric conversion element 200 according to this embodiment will be described. The manufacturing method of the photoelectric conversion element 200 according to the present embodiment differs from the manufacturing method of the photoelectric conversion element 10 according to the first embodiment (see FIGS. 7 to 11) after the step (k) in FIG. It is a manufacturing process. That is, step (a) in FIG. 7 to step (k) in FIG. 10 are the same as the manufacturing steps of the photoelectric conversion element 10 according to the first embodiment. Therefore, hereinafter, the manufacturing process after the process (k) in FIG. 10 will be described.

After the step (k) in FIG. 10, the shadow mask 80 is disposed on the translucent electrodes 6 and 7 (see step (l2) in FIG. 22). The shadow mask 80 has the same material and thickness as the shadow mask 60, but is narrower than the shadow mask 60.

Then, the protective film 208 is formed on the passivation film 3, the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5, and the translucent electrodes 6 and 7 (see step (m2) in FIG. 22).

In consideration of ensuring insulation, the thickness of the inorganic insulating film constituting the protective film 208 is preferably 20 nm or more, and more preferably 40 nm or more. When the film thickness is 1 μm or more, the inorganic insulating film may be peeled off due to the internal stress of the inorganic insulating film on the electrode. Therefore, the film thickness is preferably less than 1 μm.

Subsequently, the shadow mask 90 is disposed so that the opening is positioned on the opening 208A of the protective film 208 (see step (n2) in FIG. 22). The shadow mask 90 has the same material and thickness as the shadow mask 70, but is narrower than the shadow mask 70.

Then, the conductive reflective layer 209 is formed on the gap region G (see step (o2) in FIG. 23). Here, the conductive reflective layer 209a in contact with the translucent electrode 6 and the conductive reflective layer 209b in contact with the translucent electrode 7 are formed. The conductive reflective layer 209a is electrically connected to the translucent electrode 6, but the conductive reflective layer 209b and the translucent electrode 7 are electrically insulated. In addition, the conductive reflective layer 209b is electrically connected to the translucent electrode 7, but is electrically insulated from the conductive reflective layer 209a and the translucent electrode 6. The conductive reflective layers 209a and 209b have high series resistance when the width is narrow, and therefore the width needs to be 20 μm or more, and more preferably 40 μm or more.

Other explanations in the second embodiment are the same as those in the first embodiment.

[Embodiment 3]
FIG. 24 is a cross-sectional view showing the configuration of the photoelectric conversion element according to Embodiment 3 of the present invention. Referring to FIG. 24, photoelectric conversion element 300 according to Embodiment 3 is obtained by replacing antireflection film 2 of photoelectric conversion element 10 shown in FIG. 1 with antireflection film 301 and replacing passivation film 3 with passivation film 302. Other configurations are the same as those of the photoelectric conversion element 10.

The antireflection film 301 is disposed in contact with the light receiving surface of the semiconductor substrate 1.

The antireflection film 301 has a three-layer structure of i-type amorphous silicon / n-type amorphous silicon / silicon nitride film. In this case, the film thickness of i-type amorphous silicon is, for example, 5 nm, the film thickness of n-type amorphous silicon is, for example, 8 nm, and the film thickness of the silicon nitride film is, for example, 60 nm.

The passivation film 302 is formed between the semiconductor substrate 1, the n-type amorphous semiconductor layer 4, and the p-type amorphous semiconductor layer 5, the semiconductor substrate 1, the n-type amorphous semiconductor layer 4, and the p-type amorphous semiconductor. The semiconductor layer 5 and the protective film 8 are disposed in contact with each other.

The passivation film 302 is made of an i-type amorphous semiconductor layer. The i-type amorphous semiconductor layer is an amorphous semiconductor layer that is substantially intrinsic and contains hydrogen. The i-type amorphous semiconductor layer includes, for example, i-type amorphous silicon, i-type amorphous silicon germanium, i-type amorphous germanium, i-type amorphous silicon carbide, i-type amorphous silicon carbide, i-type It consists of amorphous silicon nitride, i-type amorphous silicon oxynitride, i-type amorphous silicon oxide, i-type amorphous silicon carbon oxide, and the like.

The thickness of the passivation film 302 is, for example, 1 nm to 15 nm, and preferably 3 nm to 12 nm.

In this way, the passivation film 302 is formed of i-type amorphous silicon oxynitride or i-type amorphous silicon nitride, so that it is included in the p-type amorphous semiconductor layer 5 formed on the passivation film 302. It is possible to suppress diffusion of a dopant such as boron into the semiconductor substrate 1.

The i-type amorphous semiconductor layer constituting the passivation film 302 has defects at the interface between the semiconductor substrate 1 and the n-type amorphous semiconductor layer 4 and at the interface between the semiconductor substrate 1 and the p-type amorphous semiconductor layer 5. To reduce.

In the photoelectric conversion element 300, the step of forming the antireflection film 2 (FIG. 8D) in the manufacturing steps shown in FIGS. 7 to 11 is replaced with the step of forming the antireflection film 301. Manufacture is performed according to a manufacturing process in which the process of forming (FIG. 7C) is replaced with the process of forming the passivation film 302.

The antireflection film 301 is formed by sequentially depositing i-type amorphous silicon, n-type amorphous silicon, and a silicon nitride film on the light receiving surface of the semiconductor substrate 1 by plasma CVD. More specifically, the plasma CVD method is performed under the conditions of the substrate temperature: 130 to 180 ° C., the hydrogen gas flow rate: 0 to 100 sccm, the silane gas flow rate: 40 sccm, the pressure: 40 to 120 Pa, and the RF power density: 5 to 15 mW / cm ^2. To deposit i-type amorphous silicon.

Further, the n-type amorphous silicon is formed by plasma CVD with further flowing PH ₃ gas under the above conditions, and the silicon nitride film is formed by plasma CVD with further flowing NH ₃ gas under the above conditions. The

After forming the antireflection film 301, a passivation film 302 is formed on the back surface of the semiconductor substrate 1. More specifically, the passivation film 302 is formed by depositing i-type amorphous silicon on the back surface of the semiconductor substrate 1 by plasma CVD using the same conditions as the i-type amorphous silicon of the antireflection film 301. Form.

Then, after forming the passivation film 302, the photoelectric conversion element 300 is completed by sequentially executing the process (e) to the process (o) of FIG.

In the step (m) of FIG. 11, a protective film 8 having a three-layer structure made of 4 nm i-type amorphous silicon, 8 nm n-type amorphous silicon, and 60 nm silicon nitride film (SiN) was formed.

As described above, in the third embodiment, the i-type amorphous silicon as the passivation film 302 is formed on the entire surface of the semiconductor substrate 1 by a single film formation. For this reason, the semiconductor substrate 1 can be passivated by covering the surface of the semiconductor substrate 1 with a substantially uniform film thickness. In this embodiment, the film thickness is 9 nm.

Then, on the uniform passivation film 302, the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 having a film thickness reduction region were formed 100 μm apart using a shadow mask. Therefore, both passivation properties and low resistance can be achieved.

Also, as described above, the n-type amorphous semiconductor layer 4 containing phosphorus with a small wraparound width was formed first, and then the p-type amorphous semiconductor layer 5 containing boron with a large wraparound width was formed.

The silicon nitride film is formed by a plasma CVD method by additionally flowing NH ₃ gas in the same plasma apparatus as the plasma apparatus in which i-type amorphous silicon is formed. Further, the n-type amorphous silicon is formed by plasma CVD by additionally flowing PH ₃ gas in the same plasma apparatus as the plasma apparatus in which i-type amorphous silicon is formed. Therefore, a three-layer structure of i-type amorphous silicon / n-type amorphous silicon / silicon nitride film constituting the antireflection film 301 can be continuously formed in a vacuum atmosphere.

Further, after forming the antireflection film 301, the semiconductor substrate 1 is inverted by a manipulator in the plasma apparatus, and i-type amorphous silicon is deposited on the back surface of the semiconductor substrate 1 by the plasma CVD method to form a passivation film 302. .

Further, the shadow mask is aligned at an appropriate position, and then the conductive layers of the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5, and the translucent electrodes 6 and 7 are described in the first embodiment. By forming the film under conditions, the structures of the light receiving surface and the back surface of the photoelectric conversion element 300 can be manufactured in a vacuum atmosphere without being exposed to the air, and the photoelectric conversion element 300 can be manufactured.

In Embodiment 3, as described above, the antireflection film 301 is formed by successively forming a three-layer structure of i-type amorphous silicon / n-type amorphous silicon / silicon nitride film, and then The semiconductor substrate 1 is inverted to form a passivation film 302 on the back surface, and the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are formed using a shadow mask (a metal mask in this embodiment). It is preferable to form a film. In particular, before forming the i-type amorphous silicon (passivation film 302) on the back surface, if a silicon nitride film is formed on the amorphous silicon layer on the light receiving surface, the i-type amorphous material is formed on the back surface. The thermal history when forming silicon (passivation film 302) may cause the light-receiving surface to have a lower passivation property, but a silicon nitride film is preferable because it suppresses the deterioration of the passivation property.

Further, as described above, the protective film 8 has a three-layer structure. However, even when the protective film 8 having a three-layer structure is formed, the protective film 8 is formed on the translucent electrodes 6 and 7 and the gap region G. It is preferable that 8 is formed in order to improve insulation and moisture resistance. The protective film on the translucent electrodes 6 and 7 and the protective film on the gap region G do not necessarily have to be continuous, but by forming them continuously, the process man-hours can be reduced and the film quality is uniform. Therefore, it is more preferable.

Furthermore, in the photoelectric conversion element 300, it turned out that the effect similar to the effect in Embodiment 1 is acquired regarding heat resistance and an electrode floating suppression effect.

In addition, in the photoelectric conversion element 300, it was found that the same effect can be obtained by suppressing the wraparound width by making the texture size less than 30 μm, and suppressing the reverse saturation current associated therewith. Further, in this embodiment, since the passivation film is different, the same effect can be obtained as the effect relating to the conductive layer and the insulating film described in Embodiment 1.

Since the passivation film 3 of the photoelectric conversion element 10 is made of a thermal oxide film, it is difficult to form all of the amorphous silicon on the light receiving surface and the back surface in a vacuum atmosphere in the first embodiment.

However, in this embodiment, the photoelectric conversion element 300 is manufactured using a cluster-type CVD apparatus as shown in FIG. All the chambers 222 to 228 and the transfer chamber 220 shown in FIG. 25 are in a vacuum, and the photoelectric conversion element to be manufactured can be moved between the respective chambers using the arm 220a of the transfer chamber 220 without being exposed to the atmosphere. . Hereinafter, a manufacturing procedure of the photoelectric conversion element 300 will be described.

The semiconductor substrate 1 with texture formed on both sides after the RCA cleaning was set on the load lock unit 221 and the inside of the chamber was evacuated.

Thereafter, the semiconductor substrate 1 is sent to the i layer forming chamber 225 via the transfer chamber 220, and an i-type amorphous semiconductor layer is formed on the light receiving surface side of the semiconductor substrate 1. Thereafter, the semiconductor substrate 1 is sent to the n-layer formation chamber 222, and an n-type amorphous semiconductor layer is formed in contact with the i-type amorphous semiconductor layer. Thereafter, the semiconductor substrate 1 is sent to the SiN formation chamber 226, and a silicon nitride film is formed in contact with the n-type amorphous semiconductor layer. Thereby, the antireflection film 301 is formed on the light receiving surface of the semiconductor substrate 1 without exposure to the atmosphere.

Next, the semiconductor substrate 1 is sent to the vacuum alignment & wafer inversion chamber 224 to invert the semiconductor substrate 1. Then, the semiconductor substrate 1 is sent to the i layer forming chamber 225, and an i-type amorphous semiconductor layer is formed on the entire textured surface on the back surface of the semiconductor substrate 1.

Next, the semiconductor substrate 1 is sent to the vacuum alignment & wafer inversion chamber 224, and a shadow mask (metal mask) for forming the n-type amorphous semiconductor layer is aligned with a predetermined position of the semiconductor substrate 1, and then the n layer Then, the n-type amorphous semiconductor layer 4 is deposited on the i-layer amorphous semiconductor layer.

Subsequently, in the vacuum alignment & wafer inversion chamber 224, a shadow mask (metal mask) for forming the p-type amorphous semiconductor layer is placed at a predetermined position (position for forming the p-type amorphous semiconductor layer). The p-type amorphous semiconductor layer 5 is formed in the p-layer formation chamber 223 again.

Next, in the vacuum alignment & wafer inversion chamber 224, the shadow mask (metal mask) for forming the p-type amorphous semiconductor layer is replaced with a shadow mask (metal mask) for electrode formation, and a predetermined mask on the semiconductor substrate 1 is formed. Align to position. Thereafter, in the electrode formation chamber 227, the translucent electrodes 6 and 7 are formed on the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 by a single film formation.

Thereafter, in the vacuum alignment & wafer inversion chamber 224, the shadow mask for electrode formation is removed and replaced with a shadow mask for the electrode protective film SiN, and alignment is performed at a predetermined position. Then, the protective film 8 is formed in the SiN formation chamber 226.

Subsequently, in the vacuum alignment & wafer inversion chamber 224, the shadow mask for the electrode protective film SiN is removed and replaced with a shadow mask for the reflective layer, and aligned at a predetermined position. Finally, by forming the conductive reflective layer 9 in the reflective layer forming chamber 228, a back junction solar cell can be fabricated by bifacial (double-sided light reception) without being exposed to the atmosphere. By performing such a process, a back junction type solar cell can be manufactured by bifacial (double-sided light reception) in a very short process time.

Also, i-type (intrinsic), p-type, and n-type amorphous semiconductor layers are easily oxidized when exposed to the atmosphere, and when oxidized, the series resistance component may increase. However, it is preferable to fabricate through the above process because oxidation at the interface and the like can be suppressed and a low-resistance solar cell can be fabricated.

In the process described above, the amorphous semiconductor layer on the light receiving surface, the amorphous semiconductor layer on the back surface, the electrode on the back surface, and the protective film on the back surface are all formed without exposure to the atmosphere. However, after film formation on the light-receiving surface side, or before the formation of the back surface electrode or before the formation of the back surface protective film, exposure to the atmosphere may be performed to perform the process in another apparatus. Preferably, the film formation of the amorphous semiconductor layer on the back surface (film formation of the intrinsic amorphous semiconductor layer, film formation of the n-type amorphous semiconductor layer, film formation of the p-type amorphous semiconductor layer) is exposed to the atmosphere. Without performing alignment of the shadow mask in a vacuum, it is preferable because the interface oxidation can be suppressed and a low-resistance solar cell can be manufactured.

From the viewpoint described above, the third embodiment is preferable to the first embodiment. It is preferable to deposit all the amorphous silicon on the light-receiving surface and the back surface in a vacuum atmosphere, because production variations can be suppressed and the yield can be improved.

In the above, the manufacturing process in the cluster type PECVD apparatus has been described. However, there is no problem even if the process apparatuses are arranged in an inline type in a line in a line.

Furthermore, it is more preferable to form the translucent electrodes 6, 7, the protective film 8, and the conductive reflective layer 9 without exposing to the atmosphere. The effect of can be obtained.

Other explanations in the third embodiment are the same as those in the first embodiment.

Further, in the above description, the amorphous semiconductor layer has been described as being formed by the plasma CVD method. May be. When the CatCVD method is used, the film formation conditions are, for example, substrate temperature: 100 to 300 ° C., pressure: 10 to 500 Pa, catalyst medium temperature (when tungsten is used as the thermal catalyst): 1500 to 2000 ° C., RF power Density: 0.01-1 W / cm ² . Thereby, an amorphous semiconductor layer with high quality can be formed at a relatively low temperature and in a short time.

[Embodiment 4]
FIG. 26 is a cross-sectional view showing the configuration of the photoelectric conversion element according to Embodiment 4 of the present invention. Referring to FIG. 26, the photoelectric conversion element 400 according to the fourth embodiment does not include the protective film 8 included in the above-described photoelectric conversion elements 10, 200, and 300. Other configurations are the same as those of the photoelectric conversion element 10.

The conductive reflective layer 9 a is disposed in contact with a part of the passivation film 3, the n-type amorphous semiconductor layer 4, and the translucent electrode 6. The conductive reflective layer 9 a is not in contact with the p-type amorphous semiconductor layer 5 and the translucent electrode 7.

The conductive reflective layer 9 b is disposed in contact with the passivation film 3, the p-type amorphous semiconductor layer 5, and a part of the translucent electrode 7. The conductive reflective layer 9 b is not in contact with the n-type amorphous semiconductor layer 4 and the translucent electrode 6.

A method for manufacturing the photoelectric conversion element 400 according to this embodiment will be described. The manufacturing method of the photoelectric conversion element 400 according to the present embodiment differs from the manufacturing method of the photoelectric conversion element 10 according to the first embodiment (see FIGS. 7 to 11) after the step (k) in FIG. It is a manufacturing process. That is, step (a) in FIG. 7 to step (k) in FIG. 10 are the same as the manufacturing steps of the photoelectric conversion element 10 according to the first embodiment. Therefore, hereinafter, the manufacturing process after the process (k) in FIG. 10 will be described.

After step (k) in FIG. 10, the shadow mask 100 is disposed (see step (l3) in FIG. 27). The shadow mask 100 has the same material and thickness as the shadow mask 30.

Then, the conductive reflective layer 9 is formed on the gap region G (see step (m3) in FIG. 27). Here, the conductive reflective layer 9a in contact with the translucent electrode 6 and the conductive reflective layer 9b in contact with the translucent electrode 7 are formed. The conductive reflective layer 9 a is electrically connected to the translucent electrode 6, but is electrically insulated from the conductive reflective layer 9 b and the translucent electrode 7. The conductive reflective layer 9b is electrically connected to the translucent electrode 7, but is electrically insulated from the conductive reflective layer 9a and the translucent electrode 6. When the width of the conductive reflective layers 9a and 9b is narrow, the series resistance becomes high. Therefore, the width needs to be 20 μm or more, and more preferably 40 μm or more.

Other explanations in the fourth embodiment are the same as those in the first embodiment.

[Embodiment 5]
FIG. 28 is a schematic diagram illustrating a configuration of a photoelectric conversion module including the photoelectric conversion element according to the fifth embodiment. Referring to FIG. 28, photoelectric conversion module 1000 includes a plurality of photoelectric conversion elements 1001, a cover 1002, and output terminals 1003 and 1004.

The plurality of photoelectric conversion elements 1001 are arranged in an array and connected in series. Note that the plurality of photoelectric conversion elements 1001 may be connected in parallel instead of being connected in series, or may be connected in combination of series and parallel.

Each of the plurality of photoelectric conversion elements 1001 includes any one of the photoelectric conversion elements 10, 200, 300, and 400.

The cover 1002 is made of a weather resistant cover and covers the plurality of photoelectric conversion elements 1001. The cover 1002 includes, for example, a transparent base material (for example, glass) provided on the light receiving surface side of the photoelectric conversion element 1001 and a back surface base material (on the reverse side opposite to the light receiving surface side of the photoelectric conversion element 1001). For example, glass, a resin sheet etc.) and the sealing material (for example, EVA etc.) which fills the clearance gap between a transparent base material and a back surface base material are included.

The output terminal 1003 is connected to a photoelectric conversion element 1001 arranged at one end of a plurality of photoelectric conversion elements 1001 connected in series.

The output terminal 1004 is connected to the photoelectric conversion element 1001 disposed at the other end of the plurality of photoelectric conversion elements 1001 connected in series.

As described above, the photoelectric conversion elements 10, 200, 300, and 400 are excellent in insulation, moisture resistance, and heat resistance.

Therefore, the insulation, moisture resistance and heat resistance of the photoelectric conversion module 1000 can be improved.

Note that the number of photoelectric conversion elements 1001 included in the photoelectric conversion module 1000 is an arbitrary integer of 2 or more.

Also, the photoelectric conversion module according to Embodiment 5 is not limited to the configuration shown in FIG. 28, and may have any configuration as long as any one of the photoelectric conversion elements 10, 200, 300, and 400 is used.

[Embodiment 6]
FIG. 29 is a schematic diagram showing a configuration of a photovoltaic power generation system including a photoelectric conversion element according to this embodiment.

Referring to FIG. 29, the photovoltaic power generation system 1100 includes a photoelectric conversion module array 1101, a connection box 1102, a power conditioner 1103, a distribution board 1104, and a power meter 1105.

The connection box 1102 is connected to the photoelectric conversion module array 1101. The power conditioner 1103 is connected to the connection box 1102. Distribution board 1104 is connected to power conditioner 1103 and electrical equipment 1110. The power meter 1105 is connected to the distribution board 1104 and the grid connection.

The photoelectric conversion module array 1101 converts sunlight into electricity to generate DC power, and supplies the generated DC power to the connection box 1102.

The connection box 1102 receives the DC power generated by the photoelectric conversion module array 1101 and supplies the received DC power to the power conditioner 1103.

The power conditioner 1103 converts the DC power received from the connection box 1102 into AC power, and supplies the converted AC power to the distribution board 1104.

Distribution board 1104 supplies AC power received from power conditioner 1103 and / or commercial power received via power meter 1105 to electrical equipment 1110. Further, when the AC power received from the power conditioner 1103 is larger than the power consumption of the electric equipment 1110, the distribution board 1104 supplies the surplus AC power to the grid interconnection via the power meter 1105.

The power meter 1105 measures power in the direction from the grid connection to the distribution board 1104 and measures power in the direction from the distribution board 1104 to the grid connection.

FIG. 30 is a schematic diagram showing the configuration of the photoelectric conversion module array 1101 shown in FIG.

Referring to FIG. 30, the photoelectric conversion module array 1101 includes a plurality of photoelectric conversion modules 1120 and output terminals 1121 and 1122.

The plurality of photoelectric conversion modules 1120 are arranged in an array and connected in series. Note that the plurality of photoelectric conversion modules 1120 may be connected in parallel instead of being connected in series, or may be connected in combination of series and parallel. Each of the plurality of photoelectric conversion modules 1120 includes a photoelectric conversion module 1000 shown in FIG.

The output terminal 1121 is connected to a photoelectric conversion module 1120 located at one end of a plurality of photoelectric conversion modules 1120 connected in series.

The output terminal 1122 is connected to the photoelectric conversion module 1120 located at the other end of the plurality of photoelectric conversion modules 1120 connected in series.

Note that the number of photoelectric conversion modules 1120 included in the photoelectric conversion module array 1101 is an arbitrary integer of 2 or more.

Operation in the solar power generation system 1100 will be described. The photoelectric conversion module array 1101 generates sunlight by converting sunlight into electricity, and supplies the generated DC power to the power conditioner 1103 via the connection box 1102.

The power conditioner 1103 converts the DC power received from the photoelectric conversion module array 1101 into AC power, and supplies the converted AC power to the distribution board 1104.

The distribution board 1104 supplies the AC power received from the power conditioner 1103 to the electrical device 1110 when the AC power received from the power conditioner 1103 is greater than or equal to the power consumption of the electrical device 1110. Then, the distribution board 1104 supplies surplus AC power to the grid connection via the power meter 1105.

Further, when the AC power received from the power conditioner 1103 is less than the power consumption of the electric device 1110, the distribution board 1104 receives the AC power received from the grid connection and the AC power received from the power conditioner 1103 to the electric device 1110. Supply.

As described above, the photovoltaic power generation system 1100 includes any one of the photoelectric conversion elements 10, 200, 300, and 400 that are excellent in insulation, moisture resistance, and heat resistance.

Therefore, the insulation, moisture resistance and heat resistance of the solar power generation system 1100 can be improved.

FIG. 31 is a schematic diagram showing the configuration of another photovoltaic power generation system including the photoelectric conversion element according to this embodiment.

The photovoltaic power generation system including the photoelectric conversion element according to this embodiment may be a photovoltaic power generation system 1100A shown in FIG.

Referring to FIG. 31, solar power generation system 1100A is the same as solar power generation system 1100 except that storage battery 1106 is added to solar power generation system 1100 shown in FIG.

The storage battery 1106 is connected to the power conditioner 1103.

In the solar power generation system 1100A, the power conditioner 1103 appropriately converts part or all of the DC power received from the connection box 1102 and stores it in the storage battery 1106.

The power conditioner 1103 performs the same operation as that in the photovoltaic power generation system 1100.

The storage battery 1106 stores the DC power received from the power conditioner 1103. The storage battery 1106 supplies the stored power to the power conditioner 1103 as appropriate according to the amount of power generated by the photoelectric conversion module array 1101 and / or the power consumption of the electric device 1110.

Thus, since the solar power generation system 1100A includes the storage battery 1106, it can suppress output fluctuations due to fluctuations in the amount of sunshine, and can use the electric power stored in the storage battery 1106 even in a time zone without sunlight. The device 1110 can be supplied.

Note that the storage battery 1106 may be built in the power conditioner 1103.

In addition, the photovoltaic power generation system according to Embodiment 6 is not limited to the configuration shown in FIGS. 29 and 30 or the configuration shown in FIGS. 30 and 31, but as long as any one of photoelectric conversion elements 10, 200, 300, and 400 is used. It may be a simple configuration.

[Embodiment 7]
FIG. 32 is a schematic diagram showing a configuration of a photovoltaic power generation system including the photoelectric conversion element according to this embodiment.

32, the photovoltaic power generation system 1200 includes subsystems 1201 to 120n (n is an integer of 2 or more), power conditioners 1211 to 121n, and a transformer 1221. The photovoltaic power generation system 1200 is a photovoltaic power generation system having a larger scale than the photovoltaic power generation systems 1100 and 1100A shown in FIGS.

The power conditioners 1211 to 121n are connected to the subsystems 1201 to 120n, respectively.

The transformer 1221 is connected to the power conditioners 1211 to 121n and the grid connection.

Each of the subsystems 1201 to 120n includes module systems 1231 to 123j (j is an integer of 2 or more).

Each of the module systems 1231 to 123j includes photoelectric conversion module arrays 1301 to 130i (i is an integer of 2 or more), connection boxes 1311 to 131i, and a current collection box 1321.

Each of the photoelectric conversion module arrays 1301 to 130i has the same configuration as the photoelectric conversion module array 1101 shown in FIG.

The connection boxes 1311 to 131i are connected to the photoelectric conversion module arrays 1301 to 130i, respectively.

The current collection box 1321 is connected to the connection boxes 1311 to 131i. Also, j current collection boxes 1321 of the subsystem 1201 are connected to the power conditioner 1211. The j current collection boxes 1321 of the subsystem 1202 are connected to the power conditioner 1212. Hereinafter, similarly, j current collection boxes 1321 of the subsystem 120n are connected to the power conditioner 121n.

The i photoelectric conversion module arrays 1301 to 130i of the module system 1231 convert sunlight into electricity to generate DC power, and the generated DC power is supplied to the current collecting box 1321 through the connection boxes 1311 to 131i, respectively. Supply. The i photoelectric conversion module arrays 1301 to 130i of the module system 1232 convert sunlight into electricity to generate DC power, and the generated DC power is supplied to the current collecting box 1321 through the connection boxes 1311 to 131i, respectively. Supply. Similarly, the i photoelectric conversion module arrays 1301 to 130i of the module system 123j convert sunlight into electricity to generate DC power, and the generated DC power is connected to the connection boxes 1311 to 131i, respectively. To supply box 1321.

And the j current collection boxes 1321 of the subsystem 1201 supply DC power to the power conditioner 1211.

The j current collection boxes 1321 of the subsystem 1202 supply DC power to the power conditioner 1212 in the same manner.

Hereinafter, similarly, the j current collecting boxes 1321 of the subsystem 120n supply DC power to the power conditioner 121n.

The power conditioners 1211 to 121n convert the DC power received from the subsystems 1201 to 120n into AC power, and supply the converted AC power to the transformer 1221.

The transformer 1221 receives AC power from the power conditioners 1211 to 121n, converts the voltage level of the received AC power, and supplies it to the grid interconnection.

As described above, the photovoltaic power generation system 1200 includes any one of the photoelectric conversion elements 10, 200, 300, and 400 that are excellent in insulation, moisture resistance, and heat resistance.

Therefore, the insulation, moisture resistance and heat resistance of the photovoltaic power generation system 1200 can be improved.

FIG. 33 is a schematic diagram showing a configuration of another photovoltaic power generation system including the photoelectric conversion element according to this embodiment.

The photovoltaic power generation system including the photoelectric conversion element according to this embodiment may be a photovoltaic power generation system 1200A shown in FIG.

33, a photovoltaic power generation system 1200A is obtained by adding storage batteries 1241 to 124n to the photovoltaic power generation system 1200 shown in FIG. 32, and is otherwise the same as the photovoltaic power generation system 1200.

Storage batteries 1241 to 124n are connected to power conditioners 1211 to 121n, respectively.

In the photovoltaic power generation system 1200A, the power conditioners 1211 to 121n convert the DC power received from the subsystems 1201 to 120n into AC power, and supply the converted AC power to the transformer 1221. The power conditioners 1211 to 121n appropriately convert the DC power received from the subsystems 1201 to 120n, and store the converted DC power in the storage batteries 1241 to 124n, respectively.

The storage batteries 1241 to 124n supply the stored power to the power conditioners 1211 to 121n according to the amount of DC power from the subsystems 1201 to 120n, respectively.

Thus, since the photovoltaic power generation system 1200A includes the storage batteries 1241 to 124n, it is possible to suppress output fluctuations due to fluctuations in the amount of sunshine, and power is stored in the storage batteries 1241 to 124n even in a time zone without sunlight. Power can be supplied to the transformer 1221.

The storage batteries 1241 to 124n may be incorporated in the power conditioners 1211 to 121n, respectively.

Moreover, the solar power generation system according to Embodiment 7 is not limited to the configuration shown in FIGS. 32 and 33, and any configuration may be used as long as any one of photoelectric conversion elements 10, 200, 300, and 400 is used. .

Further, in the seventh embodiment, it is not necessary that all the photoelectric conversion elements included in the photovoltaic power generation systems 1200 and 1200A are the photoelectric conversion elements 10, 200, 300, and 400 according to the first to fourth embodiments. .

For example, all of the photoelectric conversion elements included in a certain subsystem (any one of the subsystems 1201 to 120n) are any one of the photoelectric conversion elements 10, 200, 300, and 400 according to the first to fourth embodiments. It is possible that some or all of the photoelectric conversion elements included in another subsystem (any one of the subsystems 1201 to 120n) are photoelectric conversion elements other than the photoelectric conversion elements 10, 200, 300, and 400.

The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and is intended to include meanings equivalent to the scope of claims for patent and all modifications within the scope.

In each of the above-described embodiments, the configuration in which the texture structure is formed on both surfaces of the semiconductor substrate 1 has been described. However, the light receiving surface may be configured not to have the texture structure, or the back surface may not be provided with the texture structure. It can also be configured. Moreover, it can also be set as the structure which does not provide a texture structure in both surfaces of a light-receiving surface and a back surface.

Further, although the configuration in which the passivation film 3 (or the passivation film 202) is disposed in contact with the back surface of the semiconductor substrate 1 has been described, a configuration in which the passivation film 3 (or the passivation film 202) is not disposed may be employed.

One of the translucent electrode 6 and the translucent electrode 7 may be a translucent electrode. However, in order to increase the incident light from the back surface, it is preferable that both the translucent electrode 6 and the translucent electrode 7 are translucent.

The conductive reflective layer 9 is used as an electrode in contact with the translucent electrode 6 or the translucent electrode 7, but may be a simple reflective layer that is not in contact with the translucent electrode 6 or 7. When the conductive reflective layer 9 is a simple reflective layer, this reflective layer can be an insulating layer. In this case, the photoelectric conversion element 10 is connected to the region REG1 so that the translucent electrode 6 is connected to the finger part 712 of the wiring member 71 shown in FIG. 14 and the translucent electrode 7 is connected to the finger part 722 of the wiring member 72. The photoelectric conversion element 10 is placed on the region REG2 so that the translucent electrode 6 is connected to the finger part 723 of the wiring member 72 and the translucent electrode 7 is connected to the finger part 732 of the wiring member 73. Deploy. Thereafter, the photoelectric conversion element 10 is similarly disposed on the wiring members 73 to 87. In this case, the wiring members 71 to 87 are preferably made of a transparent conductive material such as ITO, ZnO and IWO. Thereby, light can be made incident from the back side. When the conductive reflective layer 9 is an insulating layer instead of a conductive layer, the insulation between the adjacent translucent electrodes 6 and 7 is improved, and a short circuit between the adjacent translucent electrodes 6 and 7 is further suppressed. can do.

Therefore, the photoelectric conversion element according to the embodiment of the present invention includes a semiconductor substrate, a first amorphous semiconductor layer formed on the semiconductor substrate and having the first conductivity type, and in the in-plane direction of the semiconductor substrate. A second amorphous semiconductor layer formed adjacent to the first amorphous semiconductor layer and having a second conductivity type opposite to the first conductivity type, and formed on the first amorphous semiconductor layer A first electrode formed on the second amorphous semiconductor layer with a gap region between the first electrode and a reflective layer formed on the gap region; If at least one of the first electrode and the second electrode is a translucent electrode that transmits light, it is possible to receive light on both sides and to obtain a photoelectric conversion element with improved power generation efficiency. It becomes possible.

The present invention is applied to a photoelectric conversion element, a solar cell module including the photoelectric conversion element, and a solar power generation system.

Claims (5)

1. A semiconductor substrate;
   A first amorphous semiconductor layer formed on the semiconductor substrate and having a first conductivity type;
   A second amorphous semiconductor layer formed adjacent to the first amorphous semiconductor layer in an in-plane direction of the semiconductor substrate and having a second conductivity type opposite to the first conductivity type;
   A first electrode formed on the first amorphous semiconductor layer;
   A second electrode formed on the second amorphous semiconductor layer with a gap region between the first electrode and the first electrode;
   A reflective layer formed on at least the gap region;
   With
   At least one of the first electrode and the second electrode is a photoelectric conversion element that is a translucent electrode that transmits light.
2. The photoelectric conversion element according to claim 1, wherein the reflective layer has conductivity and is in contact with the first electrode or the second electrode.
3. A texture is formed on at least one surface of the semiconductor substrate,
   The photoelectric conversion according to claim 1, wherein the first amorphous semiconductor layer and the second amorphous semiconductor layer are formed on a surface of the semiconductor substrate on which the texture is formed. element.
4. The reflective layer is also formed on a part of the first electrode and a part of the second electrode,
   4. The protective film according to claim 1, further comprising a protective film formed between a part of the first electrode and a part of the second electrode, and the reflective layer. 5. Photoelectric conversion element.
5. The photoelectric conversion element according to claim 4, wherein each of the first electrode and the second electrode is covered with the protective film and the reflective layer.

Images