WO2012083710A1 - 分块功率管电路及其实现方法 - Google Patents

分块功率管电路及其实现方法 Download PDF

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Publication number
WO2012083710A1
WO2012083710A1 PCT/CN2011/078656 CN2011078656W WO2012083710A1 WO 2012083710 A1 WO2012083710 A1 WO 2012083710A1 CN 2011078656 W CN2011078656 W CN 2011078656W WO 2012083710 A1 WO2012083710 A1 WO 2012083710A1
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Prior art keywords
signal
power tube
control
circuit
power supply
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PCT/CN2011/078656
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English (en)
French (fr)
Inventor
余凯
谢强
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201180001480.8A priority Critical patent/CN102439832B/zh
Priority to PCT/CN2011/078656 priority patent/WO2012083710A1/zh
Publication of WO2012083710A1 publication Critical patent/WO2012083710A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017581—Coupling arrangements; Interface arrangements programmable

Definitions

  • the present invention relates to the field of switching power supplies, and in particular, to a block power tube circuit and an implementation method thereof. Background technique
  • the switching power supply is an important module in the power management unit that efficiently supplies battery energy to the processor core, I/O (Input/Output), memory, and other components.
  • Efficiency is an important indicator of switching power supply. The main factor affecting it is the conduction loss, dynamic loss and switching loss of the power tube in the switching power supply.
  • the conduction loss has a great influence on the efficiency
  • the load connected to the switching power supply is a light load
  • the dynamic loss has a great influence on the efficiency
  • the operating frequency of the switching power supply is at a high frequency
  • the switching loss has a great influence on the efficiency
  • the operating frequency of the switching power supply has a great influence on the efficiency of the conduction loss at low frequencies. Reducing the loss of the power tube over the full load range is key to improving the efficiency of the switching power supply.
  • the industry's way to improve the efficiency of the switching power supply in the full load range is: Use a fixed-size high-power tube to reduce the conduction loss and improve the heavy load efficiency.
  • its peripheral circuit uses Pul se Skipping. Mode or Burs t mode to reduce power tube switching frequency to reduce dynamic losses and switching losses, improve light load efficiency; and ultimately achieve high efficiency over the full load range.
  • Embodiments of the present invention provide a method and apparatus for implementing a block power tube circuit that can achieve high efficiency in a full load range with a simple circuit.
  • the technical solution adopted by the embodiment of the present invention is:
  • a block power tube circuit for logicly controlling a voltage regulation signal of a switching power supply to implement a power supply voltage required by a processor and a memory connected to the switching power supply, and managing a power tube switch in the current switching power supply a state, comprising: a control circuit, a driving circuit, and a block power tube group, wherein
  • the control circuit is configured to adjust a square wave duty ratio of the P-signal according to the voltage adjustment signal, generate a PWMP signal and a PWMN signal, and a control signal m, where the control signal m is used to manage the number of ways that the power tube pair is turned on,
  • the PWMP signal and the P medical signal are used to provide a power tube state control signal to the driving circuit, wherein the P-P signal and the P-N signal are respectively sent to the P-P signal end and the PWMN signal end of the driving circuit;
  • the driving circuit is configured to generate a driving signal PG and a driving signal NG according to the P-P signal and the P-medical N signal, wherein the PG signal is used to control a switching state of the PM0S power tube of the power tube pair, the NG The signal is used to control a switching state of the power tube to the Zhongli OS power tube, where the P-P signal end and the P-N signal end of the driving circuit are respectively used to receive the P-P signal and the P
  • the N-signal includes: at least one power tube pair, each power tube pair includes a PM0S power tube and a Li OS power tube, and the PM0S power tube and the Le OS power tube are connected to a drain end thereof.
  • the input end of the PMOS power tube receives the PG signal sent by the driving circuit, and the input end of the MN OS power tube receives the NG signal sent by the driving circuit.
  • a method for implementing a block power tube circuit wherein the block power tube circuit comprises a control circuit, a driving circuit and a block power tube group, wherein the block power tube group includes at least one power tube pair, each The road power tube pair includes a PM0S power tube and a MN OS power tube, and the method includes:
  • a voltage adjustment signal generated according to a magnitude of a supply voltage required by the processor and the memory to which the switching power supply is connected, and a P-N signal, a PWMP signal, and a control signal m are generated by the control circuit by using the P-signal and the voltage adjustment signal, Controlling, by the control signal m, the number of ways that the power tube pair is turned on; the PWMP signal and the PWMN signal generate driving signals PG and NG through the driving circuit, and pass the PG letter. No. Controls the switching state of the PMOS power tube in the power tube, and controls the switching state of the power tube to the Zhongli OS power tube through the NG signal.
  • the block power tube circuit and the implementation method thereof according to the embodiments of the present invention use the voltage adjustment signal to control the number of open channels of the power tube through the driving circuit .
  • the embodiment of the present invention can dynamically adjust the number of power tube opening, so that the number of power tube switches can be controlled according to different requirements, the loss in various situations can be reduced, and the efficiency of the switching power supply can be improved. Specifically, when the power supply voltage required by the processor and the memory connected to the switching power supply is large, and the supply current exceeds 1 amp, the load connected to the switching power supply is determined as a heavy load, and the conduction loss is applied to the switching power supply at this time.
  • the efficiency has the greatest impact, most of the power tubes are turned on, the conduction loss is reduced, and the efficiency is improved.
  • the power supply voltage required for the processor and the memory to which the switching power supply is connected is small, and the supply current is less than 100 milliamps, the switching power supply is connected.
  • the incoming load is judged to be a light load.
  • the dynamic loss has the greatest influence on the efficiency of the switching power supply, and a small portion of the power tube is turned on, the dynamic loss is reduced, and the efficiency is improved, thereby achieving high efficiency in a full load range with a simple circuit.
  • FIG. 1 is a circuit diagram of a block power tube according to Embodiment 1 of the present invention.
  • FIG. 2 is a circuit diagram of a block power tube according to Embodiment 2 of the present invention.
  • Embodiment 3 is a driving circuit diagram of Embodiment 2 of the present invention.
  • FIG. 4 is a circuit diagram of a dynamic dead zone control circuit according to Embodiment 2 of the present invention.
  • FIG. 5 is a block diagram of a block power tube according to Embodiment 2 of the present invention.
  • FIG. 6 is a flowchart of a method for implementing a block power tube circuit according to Embodiment 3 of the present invention.
  • the embodiment provides a block power tube circuit for performing logic control on a voltage adjustment signal of a switching power supply to implement a power supply voltage required by a processor and a memory connected to the switching power supply, and managing the current switching power supply.
  • the switching state of the power tube as shown in FIG. 1, the circuit includes a control circuit 1 1 , a driving circuit 12 and a block power tube group 13 , wherein:
  • the control circuit 1 1 is configured to adjust a square wave duty ratio of the PWM signal according to the voltage adjustment signal, generate a PWMP signal and a PWMN signal, and a control signal m, where the control signal m is used to manage the number of ways that the power tube is turned on. Further adjusting the efficiency of the switching power supply, the P medical P signal and the P N signal are used to provide a power tube state control signal to the driving circuit 12, wherein the P medical P signal and the P N signal are respectively sent to the The P medical signal terminal and the PWMN signal terminal of the driving circuit 12.
  • the driving circuit 12 is configured to generate a driving signal PG and a driving signal NG according to the P medical P signal and the P medical N signal, wherein the PG signal is used to control a switching state of the PM0S power tube of the power tube pair, The NG signal is used to control the switching state of the power tube to the Zhongli OS power tube, wherein the PWMP signal end and the P medical N signal end of the driving circuit 12 are respectively used to receive the PWMP signal and the PWMN signal.
  • the block power tube group 13 includes at least one power tube pair, each power tube pair includes a PMOS power tube and an NMOS power tube, and the PMOS power tube and the drain end of the NMOS power tube are connected, wherein The input end of the PMOS power tube receives the PG signal sent by the driving circuit 12, and the input end of the MN power tube receives the NG signal sent by the driving circuit 12.
  • the block power transistor circuit provided by the embodiment of the present invention is based on a processor connected to the switching power supply
  • the embodiment of the present invention can dynamically adjust the number of power tube opening, so that the number of power tube switches can be controlled according to different requirements, the loss in various situations can be reduced, and the efficiency of the switching power supply can be improved. Specifically, when the power supply voltage required by the processor and the memory connected to the switching power supply is large, and the supply current exceeds 1 amp, the load connected to the switching power supply is determined as a heavy load, and the conduction loss is applied to the switching power supply at this time.
  • the efficiency has the greatest impact, most of the power tubes are turned on, the conduction loss is reduced, and the efficiency is improved.
  • the power supply voltage required for the processor and the memory to which the switching power supply is connected is small, and the supply current is less than 100 mA, the switching power supply The load of the access is judged as light load.
  • the dynamic loss has the greatest influence on the efficiency of the switching power supply, and a small part of the power tube is turned on, the dynamic loss is reduced, and the efficiency is improved, thereby achieving high efficiency in a full load range with a simple circuit.
  • the embodiment provides a block power tube circuit for performing logic control on a voltage adjustment signal of a switching power supply to implement a power supply voltage required by a processor and a memory connected to the switching power supply, and managing the current switching power supply.
  • the switching state of the power tube as shown in FIG. 2, the circuit includes a control circuit 1 1 , a driving circuit 12 , and a block power tube group 13 , wherein:
  • the control circuit 1 1 is configured to adjust a square wave duty ratio of the PWM signal according to the voltage adjustment signal, generate a PWMP signal and a PWMN signal, and a control signal m, where the control signal m is used to manage the number of ways that the power tube is turned on. Further adjusting the efficiency of the switching power supply, the P medical P signal and the P N signal are used to provide a power tube state control signal to the driving circuit 12, wherein the P medical P signal and the P N signal are respectively sent to the The P medical signal terminal and the PWMN signal terminal of the driving circuit 12.
  • the driving circuit 12 is configured to generate a driving signal PG and a driving signal NG according to the P medical P signal and the P medical N signal, wherein the PG signal is used to control a switching state of the PM0S power tube of the power tube pair, The NG signal is used to control the switching state of the power tube to the Zhongli OS power tube, wherein the PWMP signal end and the P medical N signal end of the driving circuit 12 are respectively used to receive the PWMP signal and the PWMN signal.
  • the block power tube group 13 includes at least one power tube pair, each power tube pair includes a PMOS power tube and an NMOS power tube, and the PMOS power tube and the drain end of the NMOS power tube are connected, wherein The input end of the PMOS power tube receives the PG signal sent by the driving circuit 12, and the input end of the MN power tube receives the NG signal sent by the driving circuit 12.
  • the P-signal is generated by the P-signal module 14 and is an ordinary pulse-width modulated signal.
  • the voltage-regulating signal is generated by the voltage-adjusting signal module 15, and the voltage regulating module 15 is processed according to the switching power supply.
  • the supply voltage required by the device and the memory generates a corresponding voltage regulation signal.
  • control circuit 11 further includes:
  • the dynamic dead zone control circuit 11 1 is configured to change the dead time by changing the number of the delay unit to be turned on or off, so that the PM0S power tube and the MN OS power tube are in different states.
  • the dead time is a protection period set to prevent the PM0S power tube and the LV power tube in the power tube pair from being simultaneously turned on due to the switching speed problem.
  • control circuit 11 controls the dead time of the output of the dynamic dead zone control circuit 111 by controlling the closed state of the switch of the delay unit in the dynamic dead zone control circuit 111.
  • the input end of the dynamic dead zone control circuit 111 receives the block power tube drive signals PG and NG, and the PG signal and the NG signal are feedback signals, and the PG1-PGn signals output by the drive circuit 12 in FIG. NGl-NGn is fed back, and the PG signal and the NG signal are used to provide a control signal for the dynamic dead zone control circuit 11; the output end of the dynamic dead zone control circuit 111 and the DTF signal end of the drive circuit 11
  • the DTR signal terminal is connected to output a DTF signal and a DTR signal, wherein the DTF signal is a falling dead time control signal for controlling the falling edge of the P-P signal of the PM0S power tube, thereby controlling the falling dead time, the DTR signal
  • the rising dead time control signal is used to control the rising edge of the P-N signal of the MN OS power tube, thereby controlling the rising dead time.
  • the DTF signal terminal of the dynamic dead zone control circuit 111 of FIG. 4 is connected to the DTF signal terminal of the driving circuit 12 of FIG. 3, and the DTR signal terminal of the dynamic dead zone control circuit 111 of FIG. 4 and the driving circuit 12 of FIG. The DTR signal is connected.
  • each delay unit is connected to the dead zone circuit through two control switches. When both control switches are closed, the delay unit is connected to the circuit to delay the signal transmission, thereby delaying the conduction of the power tube.
  • each power tube pair shares the same dynamic dead zone control circuit.
  • the load connected to the switching power supply is determined as a heavy load, and the control signal m is generated according to the voltage adjustment signal.
  • the control signal m determines the number of power tube pairs to be turned on, and increases the number of power tube turns; when the power supply voltage required by the processor and the memory to which the switching power supply is connected is small, and the power supply current is less than 100 mA, The load connected to the switching power supply is determined as a light load, and the control signal m is generated according to the voltage adjustment signal.
  • the control signal m determines the number of power tube pairs to be closed, and reduces the number of power tube opening.
  • the driving signal is sequentially turned on according to the voltage adjustment signal for each 5 mv of the supply voltage required by the processor and the memory connected to the power supply. For each pair of power tube pairs, the power supply voltage required by the processor and the memory connected to the switching power supply is reduced by 5 mv, and the driving signal sequentially turns off one power tube pair according to the voltage adjustment signal.
  • the block power tubes need to be symmetrically distributed, and each driving circuit is placed near the corresponding block power tube.
  • the 1-way block power tube (PM0S power tube 1 and MN OS power tube 1) is first turned on.
  • 2, 3, and 4 channels are sequentially turned on. Block the power tube until the n-way block power tube is turned on; conversely, as the load connected to the switching power supply decreases, turn off the n-way, n-1-way, and n-2-way block power tubes until the power tube
  • the number is in line with the requirements of the switching power supply to load.
  • the P-signal is a synchronizing signal, and includes a P-P signal and a P-medical N signal.
  • the PWMP signal is used to control a switching state of the PM0S power tube
  • the PWMN signal is used to control a switching state of the MN OS power tube.
  • the PR/PF and PRa/PRb inputs are connected to a logic control chip for controlling the PM0S power tube Rising time and falling time;
  • the NR/NF and NRa/NRb inputs are connected to the logic control chip to control the rise and fall times of the MN OS power tube.
  • the block power tube circuit provided by the embodiment of the present invention controls the number of ways that the power tube is turned on by using a control signal generated by the voltage adjustment signal and the PWM signal according to the size of the power supply voltage required by the processor and the memory connected to the switching power supply. .
  • the embodiment of the present invention can dynamically adjust the number of power tube activations, so that the number of power tube switches can be controlled according to different requirements, the loss in various situations can be reduced, and the efficiency of the switching power supply can be improved.
  • the load connected to the switching power supply is determined as a heavy load, and the conduction loss is applied to the switching power supply at this time.
  • the efficiency has the greatest impact, most of the power tubes are turned on, the conduction loss is reduced, and the efficiency is improved.
  • the power supply voltage required for the processor and the memory to which the switching power supply is connected is small, and the supply current is less than 100 mA, the switching power supply The load of the access is judged as light load.
  • the dynamic loss has the greatest influence on the efficiency of the switching power supply, and a small part of the power tube is turned on, the dynamic loss is reduced, and the efficiency is improved, thereby achieving high efficiency in a full load range with a simple circuit.
  • the number of driving circuits of the power stage pre-stage changing the driving capability, controlling the rise and fall times of the PM0S power tube and the MN OS power tube; changing the dead time by changing the number of delay units in the dynamic dead-time circuit Time, control of the dead time of the PM0S power tube and the MN OS power tube.
  • This embodiment provides a method for implementing a block power tube circuit. As shown in FIG. 6, the method includes:
  • the voltage adjustment signal generated according to the size of the power supply voltage required by the processor and the memory connected to the switching power supply, and the P-N signal and the P-P signal are generated by the control circuit by using the P-signal and the voltage adjustment signal.
  • the control signal m is used to manage the number of ways that the power tube pair is turned on by the control signal m.
  • the PWMP signal and the PWMN signal generate driving signals PG and NG through a driving circuit, and control a switching state of a PM0S power tube in a power tube pair by a PG signal, and control a power tube alignment by using the NG signal.
  • the block power tube circuit further includes a dynamic dead zone control circuit, and the method further includes: the MN OS power tube is in a state of being not turned on at the same time.
  • the input end of the dynamic dead zone control circuit receives the block power tube driving signals PG and NG, and the PG signal and the NG signal are feedback signals, and the PG1-PGn signal and the NGl- output by the driving circuit in FIG.
  • the NGn feedback is obtained, and the PG signal and the NG signal are used to provide a control signal for the dynamic dead zone control circuit; the output end of the dynamic dead zone control circuit is connected to the DTF signal end and the DTR signal end of the drive circuit, and the output is DTF signal and DTR signal, wherein the DTF signal is a falling dead time control signal, used to control the falling edge of the P P P signal of the PM0S power tube, thereby controlling the falling dead time, and the DTR signal is the rising dead time control The signal is used to control the rising edge of the P-N signal of the MN OS power tube, thereby controlling the magnitude of the rising dead time.
  • the voltage adjustment signal is generated according to the size of the power supply voltage required by the processor and the memory to which the switching power supply is connected, and the P-signal and the voltage adjustment signal generate a PWMN signal, a P-P signal, and a control through the control circuit.
  • the signal m, the number of ways that the power tube pair is turned on by the control signal m includes:
  • the load connected to the switching power supply is determined as a heavy load, and the control signal m is generated according to the voltage adjustment signal.
  • the control signal m determines the number of power tube pairs to be turned on, and increases the number of power tube turns; when the power supply voltage required by the processor and the memory to which the switching power supply is connected is small, and the power supply current is less than 100 mA, The load connected to the switching power supply is determined as a light load, and the control signal m is generated according to the voltage adjustment signal.
  • the control signal m determines the number of power tube pairs to be closed, and reduces the number of power tube opening.
  • the drive signal sequentially turns on one power tube pair according to the voltage adjustment signal, and the required supply voltage of the processor and the memory connected to the switching power supply is reduced by 5mv.
  • the drive signal sequentially turns off one power tube pair according to the voltage adjustment signal.
  • the implementation method of the block power tube circuit provided by the embodiment of the present invention controls the power tube pair by using the voltage adjustment signal and the control signal generated by the P signal according to the size of the power supply voltage required by the processor and the memory connected to the switching power supply.
  • the number of ways to open Compared with the prior art, the embodiment of the present invention can dynamically adjust the number of power tube opening, so that the number of switches of the power tube can be controlled according to different requirements, the loss in various situations can be reduced, and the efficiency of the switching power supply can be improved.
  • the load connected to the switching power supply is determined as a heavy load, and the conduction loss is applied to the switching power supply at this time.
  • the efficiency has the greatest impact, most of the power tubes are turned on, the conduction loss is reduced, and the efficiency is improved.
  • the power supply voltage required for the processor and the memory to which the switching power supply is connected is small, and the supply current is less than 100 mA, the switching power supply The load of the access is judged as light load.
  • the dynamic loss has the greatest influence on the efficiency of the switching power supply, and a small part of the power tube is turned on, the dynamic loss is reduced, and the efficiency is improved, thereby achieving high efficiency in a full load range with a simple circuit.
  • the method for providing the above-mentioned method can be implemented in the method of the method of the present invention.
  • the embodiments of the present invention can be understood by those skilled in the art to implement all or part of the processes in the foregoing embodiments, which can be completed by a computer program to instruct related hardware, and the program can be stored in a computer readable storage.
  • the program when executed, may include the flow of an embodiment of the methods as described above.
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

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Abstract

本发明实施例公开了一种分块功率管电路及其实现方法，所述分块功率管电路包括：控制电路，所述控制电路用于根据电压调节信号调节PWM信号的方波占空比，生成PWMP信号和PWMN信号以及控制信号m；驱动电路，所述驱动电路的PWMP信号端和PWMN信号端接收控制电路发送的PWMP信号和PWMN信号，用于根据所述PWMP信号和PWMN信号生成驱动信号PG和驱动信号NG，通过PG信号和NG信号控制功率管对中PMOS功率管和NMOS功率管的开关状态；分块功率管组，所述分块功率管组包括至少一路功率管对，每路功率管对包括一个PMOS功率管和一个NMOS功率管，所述PMOS功率管和NMOS功率管的输入端分别接收所述驱动电路发送的PG信号和NG信号。本发明适用于开关电源中。

Description

分块功率管电路及其实现方法 技术领域
本发明涉及开关电源技术领域， 特别涉及一种分块功率管电路及其实现 方法。 背景技术
开关电源是电源管理单元中的重要模块， 能够实现将电池能量高效供给 处理器内核、 I/O ( Input/Output , 输入 /输出）、 存储器及其他部件。 效率是 开关电源的重要指标， 影响它的主要因素是开关电源中功率管的导通损耗、 动态损耗和开关损耗。 一般而言， 开关电源接入的负载为重负载时导通损耗 对效率的影响大； 开关电源接入的负载为轻负载时动态损耗对效率的影响大； 开关电源的工作频率在高频时开关损耗对效率的影响大； 开关电源的工作频 率在低频时导通损耗对效率的影响大。 减小功率管在全负载范围内的损耗是 提高开关电源效率的关键。
目前， 业界提高开关电源在全负载范围内效率的方法是： 釆用固定尺寸 的大功率管， 减小导通损耗， 提高重负载效率； 同时， 其外围电路釆用 Pul se Skipping (脉冲跳跃）模式或 Burs t (突变）模式， 降低功率管开关频数， 以 减小动态损耗和开关损耗， 提高轻负载效率； 最终实现全负载范围内的高效 率。
在实现本发明的过程中， 发明人发现现有技术中至少存在如下问题： Pul se Skipping模式和 Burs t模式虽然能通过降低功率管开关频数提高轻 负载时开关电源的效率， 但是固定大尺寸的功率管使得效率的改善相当有限； 同时， 这种降功率管开关频数的方法， 会显著恶化输出波纹。 发明内容
本发明的实施例提供一种分块功率管电路实现方法及装置， 能够以简单 的电路实现全负载范围内的高效率。 本发明实施例釆用的技术方案为：
一种分块功率管电路， 用于对开关电源的电压调节信号进行逻辑控制， 以实现根据开关电源所接入的处理器和存储器所需的供电电压， 管理当前开 关电源中的功率管的开关状态， 其特征在于， 包括控制电路、 驱动电路及分 块功率管组， 其中，
所述控制电路用于根据电压调节信号调节 P丽信号的方波占空比， 生成 PWMP信号和 PWMN信号以及控制信号 m , 所述控制信号 m用于管理功率管对开启 的路数， 所述 PWMP信号和 P醫 N信号用于为驱动电路提供功率管状态控制信号， 其中， 所述 P丽 P信号和 P丽 N信号分别输送至所述驱动电路的 P丽 P信号端和 PWMN信号端；
所述驱动电路用于根据所述 P丽 P信号和 P醫 N信号生成驱动信号 PG和驱动 信号 NG , 所述 PG信号用于控制所述功率管对中 PM0S功率管的开关状态， 所述 NG信号用于控制所述功率管对中丽 OS功率管的开关状态， 其中， 所述驱动电 路的 P丽 P信号端和 P丽 N信号端分别用于接收所述 P丽 P信号和所述 P丽 N信号； 所述分块功率管组包括至少一路功率管对， 每路功率管对包括一个 PM0S 功率管和一个丽 OS功率管， 所述 PM0S功率管和丽 OS功率管的漏端相连接， 其 中， 所述 PM0S功率管的输入端接收所述驱动电路发送的 PG信号， 所述丽 OS功 率管的输入端接收所述驱动电路发送的 NG信号。
一种分块功率管电路的实现方法， 其特征在于， 所述分块功率管电路包 括控制电路、 驱动电路及分块功率管组， 所述分块功率管组包括至少一路功 率管对， 每路功率管对包括一个 PM0S功率管和一个丽 OS功率管， 所述方法包 括：
根据开关电源所接入的处理器和存储器所需的供电电压的大小产生的电 压调节信号， 利用 P丽信号和所述电压调节信号通过控制电路产生 P丽 N信号、 PWMP信号以及控制信号 m, 通过所述控制信号 m管理功率管对开启的路数； 所述 PWMP信号和 PWMN信号通过驱动电路产生驱动信号 PG和 NG , 通过 PG信 号控制功率管对中 PMOS功率管的开关状态， 通过 NG信号控制功率管对中丽 OS 功率管的开关状态。
本发明实施例提供的分块功率管电路及其实现方法， 根据开关电源所接 入的处理器和存储器所需的供电电压的大小， 利用电压调节信号通过驱动电 路控制功率管对开启的路数。 与现有技术相比， 本发明实施例能够对功率管 开启的数目进行动态调整， 从而可以根据不同的需求控制功率管得开关数目， 减低各种情况下的损耗， 提高开关电源的效率。 具体的， 当开关电源所接入 的处理器和存储器所需的供电电压较大， 供电电流超过 1安培时， 将开关电源 接入的负载判定为重负载， 此时导通损耗对开关电源的效率影响最大， 开启 大部分功率管， 减小导通损耗， 提高效率； 当开关电源所接入的处理器和存 储器所需的供电电压较小， 供电电流小于 100毫安培时， 将开关电源接入的负 载判定为轻负载， 此时动态损耗对开关电源的效率影响最大， 开启小部分功 率管， 减小动态损耗， 提高效率， 从而以简单的电路实现了全负载范围内的 高效率。 附图说明
为了更清楚地说明本发明实施例中的技术方案， 下面将对实施例或现有 技术描述中所需要使用的附图作简单地介绍， 显而易见地， 下面描述中的附 图仅仅是本发明的一些实施例， 对于本领域普通技术人员来讲， 在不付出创 造性劳动的前提下， 还可以根据这些附图获得其它的附图。
图 1为本发明实施例一提供的分块功率管电路图；
图 2为本发明实施例二提供的分块功率管电路图；
图 3为本发明实施例二提供的驱动电路图；
图 4为本发明实施例二提供的动态死区控制电路图；
图 5为本发明实施例二提供的分块功率管组图；
图 6为本发明实施例三提供的分块功率管电路的实现方法流程图。
具体实施方式 下面将结合本发明实施例中的附图， 对本发明实施例中的技术方案进行 清楚、 完整地描述， 显然， 所描述的实施例仅仅是本发明一部分实施例， 而 不是全部的实施例。 基于本发明中的实施例， 本领域普通技术人员在没有做 出创造性劳动前提下所获得的所有其它实施例， 都属于本发明保护的范围。
为使本发明技术方案的优点更加清楚， 下面结合附图和实施例对本发明 作详细说明。
实施例一
本实施例提供一种分块功率管电路， 用于对开关电源的电压调节信号进 行逻辑控制， 以实现根据开关电源所接入的处理器和存储器所需的供电电压， 管理当前开关电源中的功率管的开关状态， 如图 1所示， 所述电路包括控制电 路 1 1、 驱动电路 12及分块功率管组 1 3 , 其中：
所述控制电路 1 1用于才艮据电压调节信号调节 PWM信号的方波占空比， 生成 PWMP信号和 PWMN信号以及控制信号 m , 所述控制信号 m用于管理功率管对开启 的路数进而调整开关电源的效率， 所述 P醫 P信号和 P丽 N信号用于为驱动电路 1 2提供功率管状态控制信号， 其中， 所述 P醫 P信号和 P丽 N信号分别输送至所 述驱动电路 12的 P醫 P信号端和 PWMN信号端。
所述驱动电路 12用于根据所述 P醫 P信号和 P醫 N信号生成驱动信号 PG和驱 动信号 NG , 所述 PG信号用于控制所述功率管对中 PM0S功率管的开关状态， 所 述 NG信号用于控制所述功率管对中丽 OS功率管的开关状态， 其中， 所述驱动 电路 12的 PWMP信号端和 P醫 N信号端分别用于接收所述 PWMP信号和所述 PWMN信 号。
所述分块功率管组 1 3包括至少一路功率管对， 每路功率管对包括一个 PM0S功率管和一个 NM0S功率管， 所述 PM0S功率管和 NM0S功率管的漏端相连接， 其中，所述 PM0S功率管的输入端接收所述驱动电路 12发送的 PG信号，所述丽 OS 功率管的输入端接收所述驱动电路 12发送的 NG信号。
本发明实施例提供的分块功率管电路， 根据开关电源所接入的处理器和 存储器所需的供电电压的大小， 利用电压调节信号和 PWM信号产生的控制信号 控制功率管对开启的路数。 与现有技术相比， 本发明实施例能够对功率管开 启的数目进行动态调整， 从而可以根据不同的需求控制功率管得开关数目， 减低各种情况下的损耗， 提高开关电源的效率。 具体的， 当开关电源所接入 的处理器和存储器所需的供电电压较大， 供电电流超过 1安培时， 将开关电源 接入的负载判定为重负载， 此时导通损耗对开关电源的效率影响最大， 开启 大部分功率管， 减小导通损耗， 提高效率； 当开关电源所接入的处理器和存 储器所需的供电电压较小， 供电电流小于 1 00毫安培时， 将开关电源接入的负 载判定为轻负载， 此时动态损耗对开关电源的效率影响最大， 开启小部分功 率管， 减小动态损耗， 提高效率， 从而以简单的电路实现了全负载范围内的 高效率。
实施例二
本实施例提供一种分块功率管电路， 用于对开关电源的电压调节信号进 行逻辑控制， 以实现根据开关电源所接入的处理器和存储器所需的供电电压， 管理当前开关电源中的功率管的开关状态， 如图 2所示， 所述电路包括控制电 路 1 1、 驱动电路 12及分块功率管组 1 3 , 其中：
所述控制电路 1 1用于才艮据电压调节信号调节 PWM信号的方波占空比， 生成 PWMP信号和 PWMN信号以及控制信号 m , 所述控制信号 m用于管理功率管对开启 的路数进而调整开关电源的效率， 所述 P醫 P信号和 P丽 N信号用于为驱动电路 1 2提供功率管状态控制信号， 其中， 所述 P醫 P信号和 P丽 N信号分别输送至所 述驱动电路 12的 P醫 P信号端和 PWMN信号端。
所述驱动电路 12用于根据所述 P醫 P信号和 P醫 N信号生成驱动信号 PG和驱 动信号 NG , 所述 PG信号用于控制所述功率管对中 PM0S功率管的开关状态， 所 述 NG信号用于控制所述功率管对中丽 OS功率管的开关状态， 其中， 所述驱动 电路 12的 PWMP信号端和 P醫 N信号端分别用于接收所述 PWMP信号和所述 PWMN信 号。 所述分块功率管组 1 3包括至少一路功率管对， 每路功率管对包括一个 PM0S功率管和一个 NM0S功率管， 所述 PM0S功率管和 NM0S功率管的漏端相连接， 其中，所述 PM0S功率管的输入端接收所述驱动电路 12发送的 PG信号，所述丽 OS 功率管的输入端接收所述驱动电路 12发送的 NG信号。
其中， 所述 P丽信号由 P丽信号模块 14产生， 为普通的脉宽调制信号； 所 述电压调节信号由电压调节信号模块 15产生， 所述电压调节模块 15根据开关 电源所接入的处理器和存储器所需的供电电压生成相应的电压调节信号。
进一步的， 如图 2所示， 所述控制电路 11还包括：
动态死区控制电路 11 1 , 所述动态死区控制电路 111用于通过改变延时单 元开启或关闭的数目以改变死区时间， 使 PM0S功率管和丽 OS功率管处于不同 时导通的状态， 其中， 所述死区时间是为了防止一路功率管对中的 PM0S功率 管和丽 OS功率管因为开关速度问题发生同时导通而设置的一个保护时段。
进一步的， 所述控制电路 11通过控制动态死区控制电路 111中延时单元的 开关的闭合状态， 来控制动态死区控制电路 111输出的死区时间的大小。
具体的， 所述动态死区控制电路 111的输入端接收分块功率管驱动信号 PG 和 NG , 所述 PG信号和 NG信号为反馈信号， 由图 2中驱动电路 12输出的 PGl-PGn 信号和 NGl-NGn反馈回来得到， 所述 PG信号和 NG信号用于为动态死区控制电路 1 11提供控制信号； 所述动态死区控制电路 111的输出端与所述驱动电路 11的 DTF信号端和 DTR信号端连接， 输出 DTF信号和 DTR信号， 其中， DTF信号为下降 死区时间控制信号， 用于控制 PM0S功率管的 P丽 P信号的下降沿， 进而控制下 降死区时间的大小， DTR信号为上升死区时间控制信号， 用于控制丽 OS功率管 的 P丽 N信号的上升沿， 进而控制上升死区时间的大小。
进一步的， 图 4中动态死区控制电路 111的 DTF信号端与图 3中驱动电路 12 的 DTF信号端连接， 图 4中动态死区控制电路 111的 DTR信号端与图 3中驱动电路 12的 DTR信号端连接。
具体的， 如图 4所示， 每个延时单元通过两个控制开关与死区电路连接， 当两个控制开关均闭合时， 延时单元被接入电路中， 起到延迟信号传递作用， 从而延迟功率管的导通。
进一步的， 每一路功率管对公用同一个动态死区控制电路。
进一步的， 当开关电源所接入的处理器和存储器所需的供电电压较大， 供电电流超过 1安培时， 将开关电源接入的负载判定为重负载， 根据电压调节 信号生成控制信号 m , 由控制信号 m决定所需要开启的功率管对路数， 增加功 率管开启的数目； 当开关电源所接入的处理器和存储器所需的供电电压较小， 供电电流小于 1 00毫安培时， 将开关电源接入的负载判定为轻负载， 根据电压 调节信号生成控制信号 m , 由控制信号 m决定所需要关闭的功率管对路数， 减 少功率管开启的数目。
其中， 当判定开关电源接入的负载处于轻负载或重负载范围内时， 所述 电源所接入的处理器和存储器所需的供电电压每增加 5mv , 驱动信号就根据电 压调节信号依次开启一路功率管对， 开关电源所接入的处理器和存储器所需 的供电电压每降低 5mv , 驱动信号就根据电压调节信号依次关闭一路功率管 对。
具体的， 如图 5所示， 所述分块功率管需要对称分布， 每一个驱动电路就 近放置于对应分块功率管附近。当开关电源开始工作时， 1路分块功率管（PM0S 功率管 1和丽 OS功率管 1 ) 首先开启工作， 随着开关电源接入的负载的增加， 依次开启 2路、 3路、 4路分块功率管， 直到开启 n路分块功率管； 相反的， 随 着开关电源接入的负载的减少， 依次关闭 n路、 n-1路、 n-2路分块功率管， 直 到功率管的数目符合开关电源接入负载的要求。
进一步的， 如图 3所示， 所述驱动电路 12中：
P丽信号为同步信号， 包括 P丽 P信号和 P醫 N信号， 所述 PWMP信号用于控制 PM0S功率管的开关状态， 所述 PWMN信号用于控制丽 OS功率管的开关状态。
PR/PF和 PRa/PRb输入端与逻辑控制芯片连接， 用于控制 PM0S功率管的上 升时间和下降时间大小；
NR/NF和 NRa/NRb输入端与逻辑控制芯片连接， 用于控制丽 OS功率管的上 升时间和下降时间大小。
本发明实施例提供的分块功率管电路， 根据开关电源所接入的处理器和 存储器所需的供电电压的大小， 利用电压调节信号和 PWM信号产生的控制信号 控制功率管对开启的路数。 与现有技术相比， 本发明实施例能够对功率管开 启的数目进行动态调整， 从而可以根据不同的需求控制功率管得开关数目， 减低各种情况下的损耗， 提高开关电源的效率。 具体的， 当开关电源所接入 的处理器和存储器所需的供电电压较大， 供电电流超过 1安培时， 将开关电源 接入的负载判定为重负载， 此时导通损耗对开关电源的效率影响最大， 开启 大部分功率管， 减小导通损耗， 提高效率； 当开关电源所接入的处理器和存 储器所需的供电电压较小， 供电电流小于 1 00毫安培时， 将开关电源接入的负 载判定为轻负载， 此时动态损耗对开关电源的效率影响最大， 开启小部分功 率管， 减小动态损耗， 提高效率， 从而以简单的电路实现了全负载范围内的 高效率。 此外， 通过调整功率管前级驱动电路的数目， 改变驱动能力， 实现 PM0S功率管和丽 OS功率管的上升和下降时间的控制； 通过改变动态死区电路 中延时单元的数目， 改变死区时间， 实现对 PM0S功率管和丽 OS功率管的死区 时间的控制。
实施例三
本实施例提供一种分块功率管电路的实现方法， 如图 6所示， 所述方法包 括：
601、 根据开关电源所接入的处理器和存储器所需的供电电压的大小产生 的电压调节信号， 利用 P丽信号和所述电压调节信号通过控制电路产生 P丽 N信 号、 P丽 P信号以及控制信号 m, 通过所述控制信号 m管理功率管对开启的路数。
602、 所述 PWMP信号和 PWMN信号通过驱动电路产生驱动信号 PG和 NG , 通过 PG信号控制功率管对中 PM0S功率管的开关状态， 通过 NG信号控制功率管对中 丽 OS功率管的开关状态。
进一步的， 所述分块功率管电路还包括动态死区控制电路， 所述方法还 包括： 丽 OS功率管处于不同时导通的状态。
具体的， 所述动态死区控制电路的输入端接收分块功率管驱动信号 PG和 NG , 所述 PG信号和 NG信号为反馈信号， 由图 2中驱动电路输出的 PGl-PGn信号 和 NGl-NGn反馈回来得到， 所述 PG信号和 NG信号用于为动态死区控制电路提供 控制信号； 所述动态死区控制电路的输出端与所述驱动电路的 DTF信号端和 DTR信号端连接， 输出 DTF信号和 DTR信号， 其中， DTF信号为下降死区时间控 制信号， 用于控制 PM0S功率管的 P丽 P信号的下降沿， 进而控制下降死区时间 的大小， DTR信号为上升死区时间控制信号， 用于控制丽 OS功率管的 P丽 N信号 的上升沿， 进而控制上升死区时间的大小。
进一步的， 所述根据开关电源所接入的处理器和存储器所需的供电电压 的大小产生电压调节信号， P丽信号和所述电压调节信号通过控制电路产生 PWMN信号、 P丽 P信号以及控制信号 m , 通过所述控制信号 m管理功率管对开启 的路数包括：
进一步的， 当开关电源所接入的处理器和存储器所需的供电电压较大， 供电电流超过 1安培时， 将开关电源接入的负载判定为重负载， 根据电压调节 信号生成控制信号 m , 由控制信号 m决定所需要开启的功率管对路数， 增加功 率管开启的数目； 当开关电源所接入的处理器和存储器所需的供电电压较小， 供电电流小于 1 00毫安培时， 将开关电源接入的负载判定为轻负载， 根据电压 调节信号生成控制信号 m , 由控制信号 m决定所需要关闭的功率管对路数， 减 少功率管开启的数目。
其中， 当判定开关电源接入的负载处于轻负载或重负载范围内时， 所述 电源所接入的处理器和存储器所需的供电电压每增加 5mv , 驱动信号就根据电 压调节信号依次开启一路功率管对， 开关电源所接入的处理器和存储器所需 的供电电压每降低 5mv , 驱动信号就根据电压调节信号依次关闭一路功率管 对。
本发明实施例提供的分块功率管电路的实现方法， 根据开关电源所接入 的处理器和存储器所需的供电电压的大小， 利用电压调节信号和 P丽信号产生 的控制信号控制功率管对开启的路数。 与现有技术相比， 本发明实施例能够 对功率管开启的数目进行动态调整， 从而可以根据不同的需求控制功率管得 开关数目， 减低各种情况下的损耗， 提高开关电源的效率。 具体的， 当开关 电源所接入的处理器和存储器所需的供电电压较大， 供电电流超过 1安培时， 将开关电源接入的负载判定为重负载， 此时导通损耗对开关电源的效率影响 最大， 开启大部分功率管， 减小导通损耗， 提高效率； 当开关电源所接入的 处理器和存储器所需的供电电压较小， 供电电流小于 1 00毫安培时， 将开关电 源接入的负载判定为轻负载， 此时动态损耗对开关电源的效率影响最大， 开 启小部分功率管， 减小动态损耗， 提高效率， 从而以简单的电路实现了全负 载范围内的高效率。
本发明实施例提供的分块功率管电路可以实现上述提供的方法实施例， 具体功能实现请参见方法实施例中的说明， 在此不再赘述。 本发明实施例提 本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流 程， 是可以通过计算机程序来指令相关的硬件来完成， 所述的程序可存储于 一计算机可读取存储介质中， 该程序在执行时， 可包括如上述各方法的实施 例的流程。其中，所述的存储介质可为磁碟、光盘、只读存储记忆体（ Read-Only Memory, ROM )或随机存^ ^己忆体 ( Random Access Memory, RAM )等。
以上所述， 仅为本发明的具体实施方式， 但本发明的保护范围并不局限 于此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可轻易 想到的变化或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发明的保 护范围应该以权利要求的保护范围为准。

Claims

权利要求 书
1、 一种分块功率管电路， 用于对开关电源的电压调节信号进行逻辑控制， 以实现根据开关电源所接入的处理器和存储器所需的供电电压， 管理当前开关 电源中的功率管的开关状态， 其特征在于， 包括控制电路、 驱动电路及分块功 率管组， 其中，
所述控制电路用于根据电压调节信号调节 P醫信号的方波占空比， 生成 PWMP 信号和 P醫 N信号以及控制信号 m, 所述控制信号 m用于管理功率管对开启的路数， 所述 P丽 P信号和 P丽 N信号用于为驱动电路提供功率管状态控制信号， 其中， 所 述 PWMP信号和 P丽 N信号分别输送至所述驱动电路的 PWMP信号端和 P醫 N信号端； 所述驱动电路用于根据所述 P丽 P信号和 P丽 N信号生成驱动信号 PG和驱动信 号 NG , 所述 PG信号用于控制所述功率管对中 PM0S功率管的开关状态， 所述 NG信 号用于控制所述功率管对中丽 OS功率管的开关状态，其中，所述驱动电路的 P丽 P 信号端和 P丽 N信号端分别用于接收所述 P丽 P信号和所述 P丽 N信号；
所述分块功率管组包括至少一路功率管对， 每路功率管对包括一个 PM0S功 率管和一个丽 OS功率管， 所述 PM0S功率管和丽 OS功率管的漏端相连接， 其中， 所述 PM0S功率管的输入端接收所述驱动电路发送的 PG信号， 所述丽 OS功率管的 输入端接收所述驱动电路发送的 NG信号。
1、 根据权利要求 1所述的分块功率管电路， 其特征在于， 所述控制电路还 包括：
动态死区控制电路， 所述动态死区控制电路用于通过改变延时单元开启或 关闭的数目以改变死区时间， 使 PM0S功率管和丽 OS功率管处于不同时导通的状 态； 所述动态死区控制电路的输入端接收分块功率管驱动信号， 所述 PG信号和 NG信号用于为动态死区控制电路提供控制信号， 所述动态死区控制电路的输出 端与所述驱动电路的 DTF信号端和 DTR信号端连接。
3、 根据权利要求 1或 2所述的分块功率管电路， 其特征在于， 所述控制电路 通过控制动态死区控制电路中延时单元的开关的闭合状态， 来控制动态死区控 制电路输出的死区时间的大小。
4、 根据权利要求 2所述的分块功率管电路， 其特征在于， 所述分块功率管 驱动信号包括 PM0S功率管驱动信号 PG和丽 OS功率管驱动信号 NG , 所述 PG信号和 NG信号为反馈信号， 由驱动电路输出的 PGl -PGn信号和 NGl-NGn反馈回来得到。
5、 根据权利要求 3所述的分块功率管电路， 其特征在于， 所述动态死区控 制电路的输出端输出 DTF信号和 DTR信号， 其中， DTF信号为下降死区时间控制信 号， 用于控制 PM0S功率管的 P丽 P信号的下降沿， 进而控制下降死区时间的大小， DTR信号为上升死区时间控制信号， 用于控制丽 OS功率管的 P丽 N信号的上升沿， 进而控制上升死区时间的大小。
6、 一种分块功率管电路的实现方法， 其特征在于， 所述分块功率管电路包 括控制电路、 驱动电路及分块功率管组， 所述分块功率管组包括至少一路功率 管对， 每路功率管对包括一个 PM0S功率管和一个丽 OS功率管， 所述方法包括： 根据开关电源所接入的处理器和存储器所需的供电电压的大小产生的电压 调节信号， 利用 P丽信号和所述电压调节信号通过控制电路产生 P丽 N信号、 P醫 P 信号以及控制信号 m, 通过所述控制信号 m管理功率管对开启的路数；
所述 P丽 P信号和 P丽 N信号通过驱动电路产生驱动信号 PG和 NG , 通过 PG信号 控制功率管对中 PM0S功率管的开关状态， 通过 NG信号控制功率管对中丽 OS功率 管的开关状态。
7、 根据权利要求 6所述的方法， 其特征在于， 所述分块功率管电路还包括 动态死区控制电路， 所述方法还包括：
通过改变延时单元开启或关闭的数目以改变死区时间， 使 PM0S功率管和 丽 OS功率管处于不同时导通的状态。
8、 根据权利要求 7所述的方法， 其特征在于， 所述利用分块功率管驱动信 号通过所述动态死区控制电路控制各功率管对的死区时间包括：
所述动态死区控制电路输出 DTF信号和 DTR信号， 其中， DTF信号为下降死区 时间控制信号， 用于控制 PM0S功率管的 P丽 P信号的下降沿， 进而控制下降死区 时间的大小， DTR信号为上升死区时间控制信号， 用于控制丽 OS功率管的 P丽 N信 号的上升沿， 进而控制上升死区时间的大小。
9、 根据权利要求 6所述的方法， 其特征在于， 所述根据开关电源所接入的 处理器和存储器所需的供电电压的大小产生的电压调节信号， 利用 P丽信号和所 述电压调节信号通过控制电路产生 P丽 N信号、 P丽 P信号以及控制信号 m, 通过所 述控制信号 m管理功率管对开启的路数包括：
当开关电源所接入的处理器和存储器所需的供电电压较大， 供电电流超过 1 安培时， 将开关电源接入的负载判定为重负载， 根据电压调节信号生成控制信 号 m, 由控制信号 m决定所需要开启的功率管对路数， 增加功率管开启的数目； 当开关电源所接入的处理器和存储器所需的供电电压较小， 供电电流小于 1 00毫安培时， 将开关电源接入的负载判定为轻负载， 根据电压调节信号生成控 制信号 m , 由控制信号 m决定所需要关闭的功率管对路数， 减少功率管开启的数 目。
1 0、 根据权利要求 6所述的方法， 其特征在于， 所述通过所述控制信号 m管 理功率管对开启的路数包括：
开关电源所接入的处理器和存储器所需的供电电压每增加一定的值， 驱动 信号就根据电压调节信号依次开启一路功率管对， 开关电源所接入的处理器和 存储器所需的供电电压每降低一定的值， 驱动信号就根据电压调节信号依次关 闭一路功率管对。
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