WO2012077647A1 - Ecran à cristaux liquides, dispositif d'affichage et procédé ce commande de l'écran à cristaux liquides - Google Patents

Ecran à cristaux liquides, dispositif d'affichage et procédé ce commande de l'écran à cristaux liquides Download PDF

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Publication number
WO2012077647A1
WO2012077647A1 PCT/JP2011/078105 JP2011078105W WO2012077647A1 WO 2012077647 A1 WO2012077647 A1 WO 2012077647A1 JP 2011078105 W JP2011078105 W JP 2011078105W WO 2012077647 A1 WO2012077647 A1 WO 2012077647A1
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Prior art keywords
bus line
pixel
liquid crystal
reference voltage
sub
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PCT/JP2011/078105
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English (en)
Japanese (ja)
Inventor
誠二 大橋
豪 鎌田
昇平 勝田
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シャープ株式会社
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
    • G09G2300/0447—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations for multi-domain technique to improve the viewing angle in a liquid crystal display, such as multi-vertical alignment [MVA]

Definitions

  • the present invention relates to a counter matrix type liquid crystal panel, a display device including the counter matrix type liquid crystal panel, and a driving method thereof.
  • liquid crystal display devices are required to have high image quality.
  • a driving method that divides one pixel into a plurality of subpixels is used to improve viewing angle characteristics. Commonly used.
  • the multi-pixel driving bright subpixels and dark subpixels are formed in one pixel and halftones are displayed. As a result, whitening or the like during halftone display can be suppressed.
  • the luminance of each sub-pixel is controlled by varying the potential of each auxiliary capacitor Cs connected to the two sub-pixels and causing a potential difference in each sub-pixel.
  • Patent Document 1 in a multi-pixel driving type liquid crystal display device, it is desirable to set the area ratio of two sub-pixels to 1/2 or more and 4 or less in order to obtain high visual characteristics. Are listed.
  • a counter matrix type has been proposed as a configuration method of the liquid crystal display device.
  • a gate bus line, a reference voltage bus line, a switching element, and a display electrode are provided on a first substrate, and a counter electrode that is also used as a data bus line is provided on a second substrate.
  • a counter electrode that is also used as a data bus line is provided on a second substrate.
  • Patent Document 2 listed below, by dividing one pixel of a counter-matrix liquid crystal display device into two sub-pixels, even if one of the sub-pixels is defective, a pixel defect occurs. However, a technique for maintaining good display quality is disclosed.
  • Japanese Patent Publication Japanese Patent Laid-Open No. 2006-133577 (published May 25, 2006)” Japanese Patent Publication “Japanese Patent Laid-Open No. 2000-75318 (published on March 4, 2000)”
  • FIG. 15 shows a top view of a liquid crystal panel that is an experimental experiment for the case.
  • the aperture ratio of the pixel is increased. It turns out that the dead space 90 which does not contribute arises.
  • the present invention has been made to solve the above-mentioned problems, and its main object is to dead even when the area ratio of a plurality of sub-pixels constituting a multi-pixel is changed in a counter matrix type liquid crystal panel.
  • the object is to provide a liquid crystal panel in which no space is generated.
  • a liquid crystal panel includes a first substrate, a second substrate disposed so as to face the first substrate, the first substrate, and the first substrate.
  • a liquid crystal panel provided between the two substrates and a plurality of pixel regions arranged two-dimensionally along the row direction and the column direction, each of the pixel regions including at least the above-described pixel region
  • the first substrate includes two sub-pixel regions arranged in the row direction, and the first substrate intersects with the gate bus line provided corresponding to the pixel region arranged in the row direction, and the gate bus line through an insulating film.
  • the above-mentioned base corresponding to the pixel electrode A switching element for turning on and off the electrical connection with the voltage bus line, and the second substrate is a data bus line provided for each of the sub-pixel regions corresponding to the pixel regions arranged in the column direction. It is characterized by having.
  • each pixel region includes at least two subpixel regions arranged in the row direction, and the reference voltage bus line intersecting with the gate bus line is provided for each subpixel region.
  • a pixel electrode having a large area and a pixel electrode having a small area can be arranged in the row direction and formed in one pixel region without causing a dead space.
  • a voltage having an arbitrary value can be applied to two sub-pixel areas provided in one pixel area.
  • the counter matrix type liquid crystal panel having a configuration in which two sub-pixel regions are arranged side by side in one pixel region, a multi-pixel structure that does not cause useless space can be obtained, and viewing angle characteristics can be improved.
  • a voltage of an arbitrary value can be applied to at least two subpixel regions arranged in the row direction of each pixel region, a potential difference between the subpixel regions can be freely set after the liquid crystal panel is completed.
  • the voltage between the sub-pixel regions can be adjusted appropriately, and the yield can be improved.
  • each pixel region includes at least two subpixel regions arranged in the row direction includes, for example, two sets of two subpixel regions arranged in the row direction, and four subpixels in one pixel region. This means that it is allowed to provide a region.
  • a liquid crystal panel includes a first substrate, a second substrate disposed so as to face the first substrate, the first substrate, and the first substrate.
  • a plurality of pixel regions are two-dimensionally arranged along the row direction and the column direction, and each of the pixel regions is arranged at least in the column direction.
  • the second substrate includes a data bus line provided corresponding to the pixel region arranged in the column direction, and the gate bus line is formed in a meandering shape. It is characterized in that the areas of the two sub-pixel regions are different.
  • the first substrate When a pixel electrode is provided for each sub-pixel region, two pixel electrodes having different areas can be provided side by side in the column direction without creating a dead space in one pixel region.
  • the meandering center line is a bisector that divides the pixel region into two regions of equal area arranged in the column direction.
  • the gate bus line is displaced from the center line in the column direction, the two regions having the same area aligned in the column direction naturally have different areas.
  • a pixel electrode having a small area is formed by simply reducing one pixel electrode of the two regions having the same area without meandering the gate bus line, the sub-electrode on which the pixel electrode having a small area is formed. Dead space occurs in the pixel area.
  • the area of the sub-pixel region itself is made different by meandering the gate bus line, so that a pixel electrode having a large area can be obtained without causing a dead space in one pixel region. And a pixel electrode having a small area can be formed in one pixel region.
  • each pixel area includes at least two subpixel areas arranged in the column direction includes, for example, two sets of two subpixel areas arranged in the column direction, and four subpixels in one pixel area. This means that it is allowed to provide a region.
  • a liquid crystal panel includes a first substrate, a second substrate disposed so as to face the first substrate, the first substrate, and the first substrate.
  • a liquid crystal panel provided between the two substrates and a plurality of pixel regions arranged two-dimensionally along the row direction and the column direction, each of the pixel regions including at least the above-described pixel region
  • the first substrate includes two sub-pixel regions arranged in the row direction, and the first substrate intersects with the gate bus lines provided corresponding to the pixel regions arranged in the row direction, and the gate bus lines via an insulating film.
  • the reference voltage bus line provided for each sub-pixel region, the pixel electrode provided for each sub-pixel region, the gate electrode supplied to the gate bus line, the pixel electrode, Reference voltage corresponding to the pixel electrode
  • a data bus provided in common in the two sub-pixel regions corresponding to the pixel regions arranged in the column direction. It is characterized by having a line.
  • each pixel region includes at least two subpixel regions arranged in the row direction, and the reference voltage bus line intersecting with the gate bus line is provided for each subpixel region.
  • a pixel electrode having a large area and a pixel electrode having a small area can be arranged in the row direction and formed in one pixel region without causing a dead space.
  • the data bus line and the reference voltage can be changed by changing the voltage applied to the reference voltage bus line provided for each subpixel region according to the subpixel region.
  • the potential difference from the bus line can be changed for each sub-pixel region.
  • the counter matrix type liquid crystal panel having a configuration in which two sub-pixel regions are arranged side by side in one pixel region, a multi-pixel structure that does not cause useless space can be obtained, and viewing angle characteristics can be improved.
  • each pixel region includes at least two subpixel regions arranged in the row direction includes, for example, two sets of two subpixel regions arranged in the row direction, and four subpixels in one pixel region. This means that it is allowed to provide a region.
  • the areas of the two subpixel regions arranged in the row direction are made different, and of the two subpixel regions, the smaller subpixel region or the larger one of the two subpixel regions
  • the subpixel regions may be arranged so as to be aligned in the column direction.
  • a column of sub-pixel regions having a small area and a column of sub-pixel regions having a large area can be formed.
  • the color of the low gradation area to the halftone area is displayed on the column of the subpixel area having a small area
  • the color of the high gradation area from the halftone area is displayed on the column of the subpixel area having a large area.
  • a driving method of a liquid crystal panel according to the present invention is a driving method in the above-described liquid crystal panel, and at least the two subpixel regions arranged in the row direction are defined as a first subpixel region and a second subpixel region.
  • the reference voltage bus line corresponding to the first sub-pixel region is a first reference voltage bus line
  • the reference voltage bus line corresponding to the second sub-pixel region is a second reference voltage bus line
  • the voltages applied to the bus line and the second reference voltage bus line are made the same, and the voltages applied to the first data bus line and the second data bus line are made different.
  • the potential difference between the first data bus line and the first reference voltage bus line is made different from the potential difference between the second data bus line and the second reference voltage bus line. It is said.
  • the switching element when a gate signal is output to the gate bus line provided corresponding to the pixel region, the switching element is turned on, and at least the first sub-pixel region aligned in the row direction and The second subpixel region is selected at the same time, and the voltage applied to the reference voltage bus line corresponding to each subpixel region is written into the pixel electrode of each subpixel region.
  • each data bus line is opposed to the pixel electrode in each sub-pixel region, the liquid crystal layer in the first sub-pixel region has a potential difference between the first data bus line and the first reference voltage bus line.
  • a potential difference between the second data bus line and the second reference voltage bus line is applied to the liquid crystal layer in the second subpixel region.
  • the voltage applied to the first reference voltage bus line is the same as the voltage applied to the second reference voltage bus line, and is applied to the first data bus line and the second data bus line. Therefore, the voltage applied to the liquid crystal layer in the first subpixel region can be made different from the voltage applied to the liquid crystal layer in the second subpixel region.
  • the voltages applied to the first data bus line and the second data bus line based on the alignment state of the liquid crystal molecules in the first sub-pixel region and the alignment state of the liquid crystal molecules in the second sub-pixel region.
  • the viewing angle characteristics in the counter matrix type liquid crystal panel can be improved.
  • a driving method of a liquid crystal panel according to the present invention is a driving method in the above-described liquid crystal panel, and a reference voltage bus line corresponding to at least one of the two sub-pixel regions arranged in the column direction is connected to the first voltage line.
  • the reference voltage bus line corresponding to the other sub-pixel region is the second reference voltage bus line
  • the first reference voltage bus line is applied to the first reference voltage bus line and the second reference voltage bus line.
  • the potential difference between the data bus line and the first reference voltage bus line is made different from the potential difference between the data bus line and the second reference voltage bus line by making each voltage different. It is said.
  • the switching element when a gate signal is output to the gate bus line provided corresponding to the pixel region, the switching element is turned on, and at least two sub-pixel regions arranged in the column direction are simultaneously selected. Then, the voltage applied to the reference voltage bus line corresponding to each subpixel region is written into the pixel electrode of each subpixel region.
  • the voltage applied to the liquid crystal layer in the one sub-pixel region can be made different from the voltage applied to the liquid crystal layer in the other sub-pixel region.
  • the alignment state of the liquid crystal molecules in the one subpixel region can be made different from the alignment state of the liquid crystal molecules in the other subpixel region with respect to the voltage written to the data bus line. Viewing angle characteristics in a matrix type liquid crystal panel can be improved.
  • the areas of the two sub-pixel regions are different by making the gate bus line meandering.
  • the area of one subpixel area of two subpixel areas corresponding to a certain data bus line is smaller than the area of the other subpixel area, it corresponds to the data bus line adjacent to the data bus line.
  • the area of one of the two subpixel areas is larger than the area of the other subpixel area.
  • a driving method of a liquid crystal panel according to the present invention is a driving method in the above-described liquid crystal panel, and at least the two subpixel regions arranged in the row direction are defined as a first subpixel region and a second subpixel region.
  • the reference voltage bus line corresponding to the first sub-pixel region is a first reference voltage bus line
  • the reference voltage bus line corresponding to the second sub-pixel region is a second reference voltage bus line.
  • the switching element when a gate signal is output to the gate bus line provided corresponding to the pixel region, the switching element is turned on, and at least the first sub-pixel region aligned in the row direction and The second subpixel region is selected at the same time, and the voltage applied to the reference voltage bus line corresponding to each subpixel region is written into the pixel electrode of each subpixel region.
  • the voltage applied to the liquid crystal layer in the first subpixel region can be made different from the voltage applied to the liquid crystal layer in the second subpixel region.
  • the alignment state of the liquid crystal molecules in the first subpixel region can be made different from the alignment state of the liquid crystal molecules in the second subpixel region with respect to the voltage written to the data bus line. Viewing angle characteristics in a matrix type liquid crystal panel can be improved.
  • the liquid crystal panel according to the present invention includes the first substrate, the second substrate disposed so as to face the first substrate, the first substrate, and the second substrate.
  • the first substrate includes a gate bus line provided corresponding to the pixel region aligned in the row direction, and the pixel substrate aligned in the row direction, A reference voltage bus line provided for each sub-pixel region, a pixel electrode provided for each sub-pixel region, and a gate signal supplied to the gate bus line, between each pixel electrode and the reference voltage bus line.
  • the second substrate includes a data bus line provided corresponding to the pixel region arranged in the column direction, and the gate bus line has a meandering shape, whereby the two sub-pixels are provided. It is characterized by different areas.
  • FIG. 2 is a diagram showing an equivalent circuit of the TFT substrate shown in FIG. 1 and a voltage applied to a liquid crystal capacitor during x-frame display.
  • FIG. 2 is a diagram showing an equivalent circuit of the TFT substrate shown in FIG. 1 and a voltage applied to a liquid crystal capacitor during x + 1 frame display.
  • FIG. 5 is a diagram showing an equivalent circuit of a TFT substrate when the liquid crystal capacitance shown in FIGS. 4A and 4B is expressed as a capacitor.
  • FIG. 3 is a timing chart illustrating an operation of the liquid crystal panel illustrated in FIG. 1. It is a top view which shows the outline of a structure of the TFT substrate of the liquid crystal panel shown in FIG. It is a top view which shows the outline of a structure of the TFT substrate of the liquid crystal panel shown in FIG. It is a top view which shows the layout of the TFT substrate of the liquid crystal panel which concerns on other embodiment of this invention.
  • FIG. 10 is a diagram showing an equivalent circuit of the TFT substrate shown in FIG. 9 and a voltage applied to a liquid crystal capacitor during x-frame display.
  • FIG. 10 is a diagram showing an equivalent circuit of the TFT substrate shown in FIG. 9 and an applied voltage of a liquid crystal capacitor at the time of x + 1 frame display.
  • FIG. 10 is a timing chart showing the operation of the liquid crystal panel shown in FIG. 9. It is a top view which shows the layout of the TFT substrate of the liquid crystal panel which concerns on further another embodiment of this invention.
  • FIG. 13 is a diagram showing an equivalent circuit of the TFT substrate shown in FIG. 12 and a voltage applied to a liquid crystal capacitor during x frame display. 13 is a timing chart showing the operation of the liquid crystal panel shown in FIG. In the prior art, it is a top view of a liquid crystal panel when the area ratio of two sub-pixels constituting a multi-pixel is changed.
  • FIG. 16 is a diagram schematically showing the brightness of each sub-pixel in the liquid crystal panel shown in FIG. 15.
  • FIG. 16 is a diagram showing an example of display on the liquid crystal panel shown in FIG. 15.
  • a liquid crystal panel according to an embodiment of the present invention, a display device including the liquid crystal panel, and a driving method thereof will be described with reference to FIGS.
  • the dimensions, materials, shapes, relative arrangements, and the like of the components described in this embodiment are not intended to limit the scope of the present invention only, unless otherwise specified. It is just an example.
  • FIG. 2 is a perspective view of the liquid crystal panel 1 according to the present embodiment.
  • FIG. 3 is a diagram showing details of the liquid crystal panel 1 according to the present embodiment.
  • the liquid crystal panel 1 includes a TFT substrate (first substrate) 10 and a counter substrate (second substrate) 20 disposed to face the first substrate. ing. A liquid crystal layer (not shown) is formed between the TFT substrate 10 and the counter substrate 20.
  • the TFT substrate 10 includes a plurality of TFTs (switching elements) 12 and a plurality of pixels on one surface (hereinafter also referred to as a mounting surface of the TFT substrate 10).
  • the electrode 14 includes a plurality of gate bus lines 16 formed in parallel to each other, and a reference voltage bus line 18 formed in parallel to the gate bus lines 16.
  • the TFT 12 has a gate terminal connected to the gate bus line 16, a source terminal connected to the reference voltage bus line 18, and a drain terminal connected to the pixel electrode 14.
  • a terminal connected to the reference voltage bus line 18 is called a source terminal, and a terminal connected to the pixel electrode 14 is a drain. Called a terminal.
  • the gate bus line 16 supplies a scanning signal (gate signal) to the connected TFT 12.
  • the reference voltage bus line 18 supplies a reference voltage to the pixel electrode 14 via the TFT 12. Further, as shown in FIG. 3A, the gate bus line 16 includes a gate input terminal 16a, and the reference voltage bus line 18 includes a reference voltage input terminal 18c.
  • the counter substrate 20 includes data bus lines 22 formed in parallel with each other on one surface (hereinafter also referred to as a mounting surface of the counter substrate 20). .
  • the portion of the data bus line 22 that faces the pixel electrode 14 also serves as the counter electrode 24 of the pixel electrode 14.
  • a liquid crystal layer is formed by sandwiching a liquid crystal layer between the pixel electrode 14 and the counter electrode 24.
  • the data bus line 22 supplies a data (video) signal to the counter electrode 24.
  • the data bus line 22 includes a data input terminal 22a.
  • the TFT substrate 10 and the counter substrate 20 are arranged so that the mounting surface of the TFT substrate 10 and the mounting surface of the counter substrate 20 face each other, as shown in FIG.
  • the gate bus line 16 formed on the mounting surface of the TFT substrate 10 and the data bus line 22 formed on the mounting surface of the counter substrate 20 intersect via the liquid crystal layer.
  • FIG. 7 is a top view schematically showing the configuration of the TFT substrate 10 of the liquid crystal panel 1 according to this embodiment.
  • the gate input terminal 16a of the gate bus line 16 and the reference voltage input terminal 18c of the reference voltage bus line 18 supply a scanning signal to each gate bus line 16 at the end portion of the TFT substrate 10, and each reference voltage.
  • a gate drive circuit 32 that supplies a reference voltage to the bus line 18 is connected.
  • the data input terminal 22 a of the data bus line 22 is connected to a data driving circuit 34 that supplies a data signal to each data bus line 22 in the flexible printed circuit board 30.
  • FIG. 1 is a top view showing a layout of the TFT substrate 10 of the liquid crystal panel 1 according to the present embodiment.
  • M and m are natural numbers, M ⁇ m).
  • Lines 22 (m ⁇ 1) to 22 (m + 2) are indicated by broken lines.
  • the liquid crystal panel 1 includes pixels (pixel regions) 110 defined by the gate bus lines 16 and the data bus lines 22.
  • the pixels 110 are two-dimensionally arranged along the row direction and the column direction.
  • Each pixel includes Sub-pix1 which is the first sub-pixel 111 (first sub-pixel region) and Sub-pix2 which is the second sub-pixel 112 (second sub-pixel region).
  • the pixel electrode 14 includes a first pixel electrode 141 constituting the first subpixel 111 and a second pixel electrode 142 constituting the second subpixel 112.
  • the TFT 12 includes a first TFT 121 constituting the first subpixel 111 and a second TFT 122 constituting the second subpixel 112.
  • pixels defined by an nth gate bus line 16n are natural numbers, N ⁇ n
  • an mth data bus line 22m 110 is a pixel 110mn
  • a first subpixel 111 of the pixel 110mn is a first subpixel 111mn
  • a second subpixel 112 is a second subpixel 112mn.
  • the first pixel electrode 141 constituting the first subpixel 111mn is referred to as a first pixel electrode 141mn
  • the second pixel electrode 142 constituting the second subpixel 112mn is referred to as a second pixel electrode 142mn.
  • first TFT 121 constituting the first sub pixel 111mn is referred to as a first TFT 121mn
  • second TFT 122 constituting the second sub pixel 112 is referred to as a second TFT 122mn.
  • the first sub-pixel 111 and the second sub-pixel 112 are arranged in the column direction.
  • the gate terminal of the first TFT 121mn included in the first subpixel 111mn is connected to the gate bus line 16n
  • the source terminal is connected to the reference voltage bus line 18a (first reference voltage bus line)
  • the drain terminal is connected to the first pixel. It is connected to the electrode 141mn.
  • the gate terminal of the second TFT 122mn included in the second subpixel 112 is connected to the gate bus line 16n
  • the source terminal is connected to the reference voltage bus line 18b (second reference voltage bus line)
  • the drain terminal is connected to the second pixel. It is connected to the electrode 142mn.
  • the TFT substrate 10 of the liquid crystal panel 1 in this embodiment is configured such that the area ratio of the second subpixel 112 to the first subpixel 111 is greater than 1 and 4 or less. Preferably it is.
  • the potential difference between the data bus line 22 and the reference voltage bus line 18 in the first sub-pixel 111 (small sub-pixel region) having a small area is made larger than the potential difference in the second sub-pixel 112 (large sub-pixel region) having a large area. Since the voltage is increased, the voltage applied to the liquid crystal layer of the first subpixel 111 exceeds the liquid crystal threshold earlier than the liquid crystal layer of the second subpixel 112. That is, when the voltage applied to the liquid crystal layer of the first subpixel 111 exceeds the threshold value of the liquid crystal, the voltage applied to the liquid crystal layer of the second subpixel 112 does not exceed the threshold value of the liquid crystal.
  • the first sub-pixel 111 starts to display first from the color of the low gradation region, reaches a higher luminance than the second sub-pixel 112,
  • the second sub-pixel 112 emits light so as to supplement the light emission amount from the halftone area to the high gradation area. That is, the first sub-pixel 111 having a small area mainly contributes to display from a low gradation to a halftone, while the second sub-pixel 112 having a large area mainly contributes to display from a half-tone to a high gradation. This makes it easy to control the viewing angle characteristic to a desired characteristic.
  • the low gradation region is more reduced when the low gradation region is the first sub-pixel 111 having a smaller area.
  • the viewing angle characteristic can be further improved as compared with the second sub-pixel 112 having a large area.
  • the gate bus line 16 is formed in a meandering shape as shown in FIG. Accordingly, two first pixel electrodes 141 and second pixel electrodes 142 having different areas can be provided side by side in the column direction without creating a dead space in one pixel 110.
  • the meandering center line is a bisector that divides the pixel 110 into two equal-area regions arranged in the column direction.
  • the gate bus line 16 is displaced from the center line with respect to the column direction, the two areas having the same area arranged in the column direction naturally have different areas.
  • a pixel electrode having a small area is formed by simply reducing one of the pixel electrodes in two regions having the same area without causing the gate bus line 16 to meander. There was a dead space in the pixel.
  • the area of the sub-pixel itself is made different by meandering the gate bus line 16, so that the first area 110 has a small area without causing unnecessary dead space.
  • One pixel electrode 141 and a second pixel electrode 142 having a large area can be formed in one pixel 110.
  • the counter matrix type liquid crystal panel 1 having a configuration in which two sub-pixels are vertically arranged in one pixel region, a multi-pixel structure that does not cause useless space can be obtained, and viewing angle characteristics can be improved.
  • each pixel 110 is not limited to a configuration including two sub-pixels arranged in the column direction.
  • two sets of two sub-pixels arranged in the column direction are provided, and four sub-pixels are provided in one pixel region. Also good.
  • the meandering center line is more preferably a bisector that divides each pixel 110mn into two regions arranged with the same width in the column direction. Accordingly, it is possible to select a configuration in which the width of the meander from the bisector when the gate bus line 16 meanders along the row direction can be selected, and thereby the second pixel electrode 142 having a large area, the area The small first pixel electrodes 141 can be arranged along the row direction at a constant area ratio.
  • first TFT 121 and the second TFT 122 are alternately provided for each bent portion of the gate bus line 16 formed in a meandering shape. Thereby, the layout of the arrangement of the first TFT 121 and the second TFT 122 can be simplified.
  • FIG. 4A is a diagram showing an equivalent circuit of the TFT substrate 10 of the liquid crystal panel 1 according to the present embodiment and a voltage applied to the liquid crystal capacitor during x-frame display.
  • FIG. 4B is a diagram showing an equivalent circuit of the TFT substrate 10 of the liquid crystal panel 1 according to the present embodiment, and a voltage applied to the liquid crystal capacitor during x + 1 frame display.
  • FIG. 5 is a diagram showing an equivalent circuit of the TFT substrate 10 when the first liquid crystal capacitor 131 and the second liquid crystal capacitor 132 shown in FIGS. 4A and 4B are represented as the first capacitor 151 and the second capacitor 152.
  • the liquid crystal panel 1 includes a pixel 110mn (first pixel region) defined by the data bus line 22m and the gate bus line 16n, a data bus line 22 (m + 1), and the like.
  • the pixels 110mn to 110 (m + 2) n and the pixels 110m (n + 1) to 110 (m + 2) (n + 1) are arranged adjacent to each other in the row direction, and the pixel 110mn, the pixel 110m (n + 1), and the pixel 110 (m + 1) n
  • the pixels 110 (m + 1) (n + 1) and the like are arranged adjacent to each other in the column direction.
  • the pixel 110mn includes two subpixels in the order of the second subpixel 112mn (first subpixel area) and the first subpixel 111mn (second subpixel area) in the column direction from the reference voltage bus line 18a.
  • the pixel 110 (m + 1) n includes two subpixels in the column direction from the reference voltage bus line 18a in the order of the first subpixel 111 (m + 1) n and the second subpixel 112 (m + 1) n. Yes.
  • the pixel 110m (n + 1) includes two subpixels in the column direction from the reference voltage bus line 18b, the first subpixel 111m (n + 1) (third subpixel region) and the second subpixel 112m (n + 1).
  • the pixel 110 (m + 1) (n + 1) includes two subpixels in the column direction from the reference voltage bus line 18b in the order of (fourth subpixel region), and the second subpixel 112 (m + 1) (n + 1) , First sub-pixels 111 (m + 1) (n + 1) in this order. That is, the pixel 110m (n + 1) and the pixel 110 (m + 1) (n + 1) are arranged to be line-symmetric with the pixel 110mn and the pixel 110 (m + 1) n with respect to the reference voltage bus line 18b.
  • the second subpixel 112mn as the first subpixel region in which the pixels 110mn are arranged in the column direction
  • the second subpixel region The first sub-pixel 111m and the second sub-pixel 112m as the fourth sub-pixel region and the first sub-pixel 111m (n + 1) as the third sub-pixel region in which the pixels 110m (n + 1) are arranged in the column direction.
  • N + 1) and the reference voltage bus line 18b is shared by the first sub-pixel 111mn and the first sub-pixel 111m (n + 1) that are adjacent to each other in the column direction.
  • the pixel 110 (m + 2) n has the same configuration as the pixel 110mn
  • the pixel 110 (m + 2) (n + 1) has the same configuration as the pixel 110m (n + 1).
  • each subpixel includes a TFT 12 and a liquid crystal capacitor.
  • the liquid crystal capacitor includes a pixel electrode 14, a counter electrode 24 formed by the data bus line 22, and a liquid crystal layer sandwiched between the pixel electrode 14 and the counter electrode 24.
  • the liquid crystal capacitors include a first liquid crystal capacitor 131mn and a second liquid crystal capacitor 132mn. As shown in FIG. 5, the first liquid crystal capacitor 131mn and the second liquid crystal capacitor 132mn can be expressed as a first capacitor 151mn and a second capacitor 152mn in an equivalent circuit.
  • the gate terminal of the first TFT 121mn included in the first sub-pixel 111mn of the pixel 110mn is connected to the gate bus line 16n, the source terminal is connected to the reference voltage bus line 18b, and the drain terminal is connected to the first terminal.
  • One liquid crystal capacitor 131mn is connected to the data bus line 22m.
  • the gate terminal of the second TFT 122mn included in the second subpixel 112mn is connected to the gate bus line 16n, the source terminal is connected to the reference voltage bus line 18a, and the drain terminal is connected to the data bus line 22m via the second liquid crystal capacitor 132mn. It is connected to the.
  • the gate terminal of the first TFT 121 (m + 1) n included in the first sub-pixel 111 (m + 1) n of the pixel 110 (m + 1) n is connected to the gate bus line 16n, the source terminal is connected to the reference voltage bus line 18a, and the drain terminal. Is connected to the data bus line 22 (m + 1) through the first liquid crystal capacitor 131 (m + 1) n.
  • the second TFT 122 (m + 1) n included in the second subpixel 112 (m + 1) n has a gate terminal connected to the gate bus line 16n, a source terminal connected to the reference voltage bus line 18b, and a drain terminal connected to the second liquid crystal capacitor. It is connected to the data bus line 22 (m + 1) through 132 (m + 1) n.
  • the first sub-pixel 111 (m + 2) n and the second sub-pixel 112 (m + 2) n of the pixel 110 (m + 2) n have the drain terminals of the first TFT 121 (m + 2) n and the second TFT 122 (m + 2) n as the first. Except for being connected to the data bus line 22 (m + 2) via the liquid crystal capacitor 131 (m + 2) n and the second liquid crystal capacitor 132 (m + 2) n, it has the same configuration as the first sub-pixel 111mn and the second sub-pixel 112mn. is there.
  • the pixel 110mn corresponds to red
  • the pixel 110 (m + 1) n corresponds to green
  • the pixel 110 (m + 2) n becomes blue.
  • the present invention is not limited to this.
  • FIG. FIG. 6 is a timing chart showing the operation of the liquid crystal panel 1 according to the present embodiment.
  • the operation of the first sub pixel 111mn shown in FIG. 4A when displaying the xth frame (x frame) will be described as an example.
  • the reference voltage of the reference voltage bus line 18a that was controlled to the L level when the x-1 frame was displayed is controlled to the H level.
  • the reference voltage of the reference voltage bus line 18b that has been controlled to the H level when the x-1 frame is displayed is controlled to the L level.
  • the first gate bus line 16 is scanned.
  • the H level reference voltage is set to +1 V and the L level reference voltage is set to 0 V.
  • the present invention is not limited to this.
  • a scanning signal is supplied to the gate terminals of the first TFT 121mn and the second TFT 122mn, and the first TFT 121mn and the second TFT 122mn. Turns on. Similarly, a scanning signal is also supplied to the gate terminals of the first TFT 121 (m + 1) n, the second TFT 122 (m + 1) n, the first TFT 121 (m + 2) n, and the second TFT 122 (m + 2) n, and is turned on.
  • the first liquid crystal capacitor 131mn is applied with a potential difference nodeX ⁇ nodeY between nodeX and nodeY of the first liquid crystal capacitor 131mn, that is, + 5V that is a potential difference between the counter electrode and the pixel electrode. Will be.
  • + 5V is applied to nodeX of the second liquid crystal capacitor 132mn of the pixel 110mn, and + 1V of the same voltage as that of the reference voltage bus line 18a is applied to nodeY.
  • +4 V which is the potential difference between nodeX and nodeY of the second liquid crystal capacitor 132mn, is applied to the second liquid crystal capacitor 132mn.
  • + 4V which is the same voltage as the data bus line 22m
  • 0V of the same voltage as that of the reference voltage bus line 18b is applied to nodeY of the first liquid crystal capacitor 131m (n + 1).
  • + 4V which is a potential difference nodeX ⁇ nodeY between nodeX and nodeY is applied to the first liquid crystal capacitor 131m (n + 1).
  • + 4V is applied to nodeX of the second liquid crystal capacitor 132m (n + 1), and + 1V of the same voltage as the reference voltage bus line 18a is applied to nodeY. Is done.
  • +3 V which is a potential difference between nodeX and nodeY, is applied to the second liquid crystal capacitor 132m (n + 1).
  • the voltage of the first liquid crystal capacitor 131mn does not change, and the voltage applied at time txn is maintained. That is, the voltage applied to the first liquid crystal capacitor 131mn when the gate bus line 16n is scanned to display the x frame until the gate bus line 16n is scanned again to display the x + 1 frame. Will be maintained.
  • the second liquid crystal capacitor 132mn the first liquid crystal capacitor 131 (m + 1) n, the second liquid crystal capacitor 132 (m + 1) n, the first liquid crystal capacitor 131 (m + 2) n, and the second liquid crystal capacitor 132 (m + 2) n.
  • the voltage applied at time txn is maintained.
  • a scanning signal is supplied to the gate terminals of the first TFT 121mn and the second TFT 122mn, The first TFT 121mn and the second TFT 122mn are turned on. Similarly, a scanning signal is also supplied to the gate terminals of the first TFT 121 (m + 1) n, the second TFT 122 (m + 1) n, the first TFT 121 (m + 2) n, and the second TFT 122 (m + 2) n, and is turned on.
  • ⁇ 4V is applied to the node X of the second liquid crystal capacitor 132mn of the pixel 110mn, and 0V of the same voltage as the reference voltage bus line 18a is applied to the node Y. Applied. As a result, ⁇ 4V that is a potential difference between nodeX and nodeY of the second liquid crystal capacitor 132mn is applied to the second liquid crystal capacitor 132mn.
  • the first liquid crystal capacitor 131 (m + 1) (n + 1) of the pixel 110 (m + 1) (n + 1) has + 4V.
  • the second liquid crystal capacitance 132 (m + 1) (n + 1) becomes + 3V.
  • the data bus line 22 (m + 2) is controlled to ⁇ 3V
  • the first liquid crystal capacitor 131 (m + 2) (n + 1) of the pixel 110 (m + 2) (n + 1) becomes ⁇ 4V
  • the second liquid crystal capacitor 132 ( m + 2) (n + 1) becomes ⁇ 3V.
  • the voltage of the first liquid crystal capacitor 131mn does not change, and the voltage applied at time t (x + 1) n is maintained. That is, the voltage applied to the first liquid crystal capacitor 131mn when the gate bus line 16n is scanned to display the x + 1 frame until the gate bus line 16n is scanned again to display the x + 1 frame. Will be maintained.
  • the driving method of the liquid crystal panel 1 is the driving method in the liquid crystal panel 1 having the configuration described based on FIGS. 4A, 4B, and 6, and is the first that is arranged in the column direction.
  • the data bus The potential difference between the line 22m and the reference voltage bus line 18a is different from the potential difference between the data bus line 22m and the reference voltage bus line 18b.
  • a potential difference between the data bus line 22m and the reference voltage bus line 18a is applied to the liquid crystal layer of one pixel, while the data bus line 22m and the reference voltage bus line are applied to the liquid crystal layer of the other sub-pixel.
  • a potential difference from 18b is applied.
  • the voltage applied to the liquid crystal layer of the first sub-pixel 111 mn can be made different from the voltage applied to the liquid crystal layer of the second sub-pixel 112 mn.
  • the alignment state of the liquid crystal molecules in the first sub pixel 111mn and the alignment state of the liquid crystal molecules in the second sub pixel 112mn can be made different from each other with respect to the voltage written to the data bus line 22m.
  • the viewing angle characteristics of the liquid crystal panel 1 can be improved.
  • the areas of the two sub-pixel regions are different by making the gate bus line meandering.
  • the area of one subpixel area of two subpixel areas corresponding to a certain data bus line is smaller than the area of the other subpixel area, it corresponds to the data bus line adjacent to the data bus line.
  • the area of one of the two subpixel areas is larger than the area of the other subpixel area.
  • FIG. 8 is a top view schematically showing the configuration of the TFT substrate 10 of the liquid crystal panel 2 according to this embodiment. As shown in FIG. 8, the interval between the gate bus lines 16 ′ is narrow, the width of the data bus line 22 ′ is different, and the reference voltage bus line 18 ′ (not shown) is arranged to intersect the gate bus line 16 ′. Except for this, the configuration is the same as that of the liquid crystal panel 1 of the first embodiment.
  • FIG. 9 is a top view showing a layout of the TFT substrate 10 of the liquid crystal panel 2 according to the present embodiment.
  • FIG. 9 of the total number M of data bus lines 22 ′ formed on the counter substrate 20, data bus lines 22m ′ to 22 (m + 4) ′ arranged near the m-th data bus line 22m ′. Is indicated by a broken line.
  • the liquid crystal panel 2 includes an nth gate bus line 16n ′, an mth data bus line 22m ′, and an m + 1th data bus line 22 out of a total of N gate bus lines 16 ′.
  • the pixel 210mn defined by (m + 1) ′.
  • the pixel 210mn includes a first sub-pixel 211mn and a second sub-pixel 212 (m + 1) n.
  • the first subpixel 211mn includes a first pixel electrode 241mn and a first TFT 221mn.
  • the second sub pixel 212 (m + 1) n includes a second pixel electrode 242 (m + 1) n and a second TFT 222 (m + 1) n. Further, as shown in FIG. 9, in the area of one pixel 210, the first sub-pixel 211 and the second sub-pixel 212 are arranged in the row direction.
  • the TFT substrate 10 of the liquid crystal panel 1 in this embodiment is configured such that the area ratio of the second subpixel 212 to the first subpixel 211 is greater than 1 and 4 or less. Preferably it is.
  • the potential difference between the data bus line 22 ′ and the reference voltage bus line 18 ′ in the first sub-pixel 211 having a small area is made larger than the potential difference in the second sub-pixel 212 having a large area.
  • the voltage applied to the liquid crystal layer exceeds the threshold value of the liquid crystal earlier than the liquid crystal layer of the second subpixel 212. In other words, when the voltage applied to the liquid crystal layer of the first sub-pixel 211 exceeds the threshold value of the liquid crystal, the voltage applied to the liquid crystal layer of the second sub-pixel 212 does not exceed the threshold value of the liquid crystal.
  • the first sub-pixel 211 starts to display the color of the low gradation region first, reaches a higher luminance than the second sub-pixel 212,
  • the second sub-pixel 212 emits light so as to compensate for the amount of light emission from the halftone area to the high gradation area. That is, the first sub-pixel 211 having a small area mainly contributes to display from a low gradation to a halftone, while the second sub-pixel 212 having a large area mainly contributes to display from a halftone to a high gradation. This makes it easy to control the viewing angle characteristic to a desired characteristic.
  • the low gradation region is less affected when the low gradation region is the first sub-pixel 211 having a smaller area.
  • the viewing angle characteristics can be further improved as compared with the second sub-pixel 212 having a large area.
  • the data bus line 22 ′ is provided in each of the first sub-pixel 211 and the second sub-pixel 212, the two sub-pixels 211 and 212 included in one pixel 210 have an arbitrary polarity and an arbitrary value. Can be applied.
  • the counter matrix type liquid crystal panel 2 having a configuration in which two sub-pixels 211 and 212 are arranged side by side in one pixel 210, a multi-pixel structure that does not cause useless space is obtained, and viewing angle characteristics are improved. Can do.
  • each pixel 210 is not limited to the configuration including the two sub-pixels 211 and 212 arranged in the row direction, and for example, four sub-pixels may be provided in one pixel region.
  • FIG. 10A is a diagram showing an equivalent circuit of the TFT substrate 10 of the liquid crystal panel 2 according to the present embodiment and a voltage applied to the liquid crystal capacitor during x-frame display.
  • FIG. 10B is a diagram showing an equivalent circuit of the TFT substrate 10 of the liquid crystal panel 2 according to the present embodiment and a voltage applied to the liquid crystal capacitor during x + 1 frame display.
  • the liquid crystal panel 2 in this embodiment is defined by a data bus line 22 (m + i) ′, a data bus line 22 (m + i + 1) ′, and a gate bus line 16 (n + j) ′.
  • Pixel 210 (m + i) (n + j) is provided.
  • i is 0 and a natural number that satisfies m ⁇ i
  • j is 0 and a natural number that satisfies n ⁇ j.
  • Each pixel includes two sub-pixels.
  • the pixel 210 (m + i) (n + j) and the pixel 210 (m + i + 1) (n + j) are arranged adjacent to each other in the row direction, and the pixel 210 (m + i) (n + j) and the pixel 210 (m + i) (n + j + 1) are adjacent to each other in the column direction. Are arranged.
  • the pixel 210 (m + i) (n + j) includes two sub-pixels in the order of the first sub-pixel and the second sub-pixel in the row direction.
  • each subpixel includes a TFT 12 and a liquid crystal capacitor.
  • the liquid crystal capacitance is constituted by the pixel electrode 14, the counter electrode 24 formed by the data bus line 22 ′, and a liquid crystal layer sandwiched between the pixel electrode 14 and the counter electrode 24.
  • the liquid crystal capacitance of the pixel 210 (m + i) (n + j) illustrated in FIGS. 10A and 10B includes a first liquid crystal capacitance 231mn and a second liquid crystal capacitance 232 (m + 1) n.
  • the gate terminal of the first TFT 221mn included in the first sub-pixel 211mn of the pixel 210mn is connected to the gate bus line 16n ′, the source terminal is connected to the reference voltage bus line 18a ′, and the drain terminal is It is connected to the data bus line 22m ′ via the first liquid crystal capacitor 231mn.
  • the gate terminal of the second TFT 222 (m + 1) n included in the second subpixel 212 (m + 1) n is connected to the gate bus line 16n ′, the source terminal is connected to the reference voltage bus line 18b ′, and the drain terminal is the second terminal.
  • the liquid crystal capacitor 232 (m + 1) n is connected to the data bus line 22 (m + 1) ′.
  • the gate terminal of the first TFT 221 (m + 2) n included in the first sub-pixel 211 (m + 2) n of the pixel 210 (m + 2) n is connected to the gate bus line 16n ′, the source terminal is connected to the reference voltage bus line 18a ′, The drain terminal is connected to the data bus line 22 (m + 2) ′ via the first liquid crystal capacitor 231 (m + 2) n.
  • the gate terminal of the second TFT 222 (m + 3) n included in the second subpixel 212 (m + 3) n is connected to the gate bus line 16n ′, the source terminal is connected to the reference voltage bus line 18b ′, and the drain terminal is the second.
  • the liquid crystal capacitor 232 (m + 3) n is connected to the data bus line 22 (m + 3) ′.
  • the first TFT 221 (m + i) (n + j) included in the first subpixel 211 (m + i) (n + j) of the pixel 210 (m + i) (n + j) has a gate terminal connected to the gate bus line 16 (n + j) ′ and a drain. The terminal is connected to the data bus line 22 (m + i) ′ via the first liquid crystal capacitor 231 (m + i) (n + j).
  • the gate terminal of the second TFT 222 (m + i + 1) (n + j) is connected to the gate bus line 16 (n + j) ′, and the drain terminal is the second liquid crystal capacitor 232 (m + i + 1). It is connected to the data bus line 22 (m + i + 1) ′ via (n + j).
  • the reference voltage bus line 18b ′ is shared by, for example, the second sub-pixel 212 (m + 1) n of the pixel 210mn and the first sub-pixel 211 (m + 2) n of the pixel 210 (m + 2) n. .
  • the wiring layout can be simplified.
  • the pixel 210mn corresponds to red
  • the pixel 210m (n + 1) corresponds to green
  • the pixel 210m (n + 2) corresponds to blue.
  • the present invention is not limited to this.
  • FIG. 11 is a timing chart showing the operation of the liquid crystal panel 2 according to the present embodiment.
  • the operation of the first sub-pixel 211mn shown in FIG. 10 when displaying the x frame will be described as an example.
  • the voltages of the reference voltage bus lines 18a ′ and 18b ′ are always constant, and are constant at 0V when displaying either the x frame or the x + 1 frame.
  • a scanning signal is supplied to the gate terminals of the first TFT 221mn and the second TFT 222 (m + 1) n.
  • the first TFT 221mn and the second TFT 222 (m + 1) n are turned on.
  • a scanning signal is also supplied to the gate terminals of the first TFT 221 (m + 2) n and the second TFT 222 (m + 3) n, and is turned on.
  • + 5V of the same voltage as the data bus line 22m' is applied to the nodeX of the first liquid crystal capacitor 231mn of the pixel 210mn.
  • 0V of the same voltage as that of the reference voltage bus line 18a ' is applied to nodeY of the first liquid crystal capacitor 231mn.
  • + 5V that is a potential difference nodeX ⁇ nodeY between nodeX and nodeY of the first liquid crystal capacitor 231mn is applied to the first liquid crystal capacitor 231mn.
  • + 4V is applied to nodeX of the second liquid crystal capacitor 232 (m + 1) n of the pixel 210mn, and nodeY is the same as the reference voltage bus line 18b ′.
  • a voltage of 0V is applied.
  • + 4V which is the potential difference between nodeX and nodeY of the second liquid crystal capacitor 232 (m + 1) n, is applied to the second liquid crystal capacitor 232 (m + 1) n.
  • the voltage of the first liquid crystal capacitor 231mn does not change, and the voltage applied at time txn is maintained. That is, the voltage applied to the first liquid crystal capacitor 231mn by scanning the gate bus line 16n ′ to display the x frame causes the gate bus line 16n ′ to be scanned again to display the x + 1 frame. Until it will be maintained.
  • the voltage applied to the second liquid crystal capacitor 232 (m + 1) n, the first liquid crystal capacitor 231 (m + 2) n, and the second liquid crystal capacitor 232 (m + 3) n is also applied at time txn at time tx (n + 1). Is maintained.
  • the scanning signal is applied to the gate terminals of the first TFT 221mn, the second TFT 222 (m + 1) n, the first TFT 221 (m + 2) n, and the second TFT 222 (m + 3) n. Is supplied and turned ON.
  • the data bus line 22m ′ is controlled to ⁇ 5V, 22 (m + 2) ′ to + 5V, the data bus line 22 (m + 1) ′ is controlled to ⁇ 4V, and 22 (m + 3) ′ to + 4V, FIG.
  • the applied voltage of the first liquid crystal capacitor 231mn is ⁇ 5V
  • the applied voltage of the first liquid crystal capacitor 231 (m + 2) n is + 5V
  • the applied voltage of the second liquid crystal capacitor 232 (m + 1) n is ⁇ 4V.
  • the applied voltage of the second liquid crystal capacitor 232 (m + 3) n is + 4V.
  • the scanning signal is supplied to the gate terminals of the first TFT 221 (m + 2) (n + 1), and the second TFT 222 (m + 3) (n + 1), and is turned on.
  • the data bus line 22m ′ is controlled to ⁇ 4V, 22 (m + 2) ′ to + 4V, the data bus line 22 (m + 1) ′ is ⁇ 3V, and 22 (m + 3) ′ is + 3V.
  • the applied voltage of the first liquid crystal capacitor 231m (n + 1) becomes ⁇ 4V
  • the applied voltage of the first liquid crystal capacitor 231 (m + 2) (n + 1) becomes + 4V
  • the second The applied voltage of the liquid crystal capacitor 232 (m + 1) (n + 1) is ⁇ 3V
  • the applied voltage of the second liquid crystal capacitor 232 (m + 3) (n + 1) is + 3V.
  • the data bus line 22m ′ is controlled to ⁇ 3V, 22 (m + 2) ′ to + 3V, the data bus line 22 (m + 2) ′ is controlled to ⁇ 2V, and 22 (m + 3) ′ to + 2V, as shown in FIG. 10B.
  • the applied voltage of the first liquid crystal capacitor 231m (n + 2) is ⁇ 3V
  • the applied voltage of the first liquid crystal capacitor 231 (m + 2) (n + 2) is + 3V
  • the second liquid crystal capacitor 232 (m + 1) (n + 2) is applied.
  • the voltage is -2V
  • the voltage applied to the second liquid crystal capacitor 232 (m + 3) (n + 2) is + 2V.
  • the driving method of the liquid crystal panel 2 is a driving method in the liquid crystal panel having the configuration described based on FIG. 9, FIG. 10A, and FIG.
  • a reference voltage bus line 18a ′ corresponding to the first sub-pixel 211mn and a reference voltage bus line 18b ′ corresponding to the second sub-pixel 212 (m + 1) n are applied to the data bus line 22m ′ corresponding to the first sub-pixel 211mn and applied to the data bus line 22 (m + 1) ′ corresponding to the second sub-pixel 212 (m + 1) n.
  • the potential difference between the data bus line 22m ′ and the reference voltage bus line 18a ′ can be reduced. 22 and (m + 1) 'and the reference voltage bus line 18b' is different from the potential difference between.
  • a potential difference between the data bus line 22m ′ and the reference voltage bus line 18a ′ is applied to the liquid crystal layer of the first subpixel 211mn, while the liquid crystal layer of the second subpixel 212 (m + 1) n is applied to the liquid crystal layer of the first subpixel 211mn.
  • a potential difference between the data bus line 22 (m + 1) ′ and the reference voltage bus line 18b ′ is applied.
  • the voltage applied to the reference voltage bus line 18a ′ and the voltage applied to the reference voltage bus line 18b ′ are the same, and are applied to the data bus line 22m ′ and the data bus line 22 (m + 1) ′. Since the voltages are different, the voltage applied to the liquid crystal layer of the first sub-pixel 211mn and the voltage applied to the liquid crystal layer of the second sub-pixel 212 (m + 1) n can be made different.
  • the voltages applied to the data bus lines 22m ′ and 22 (m + 1) ′ are the liquid crystal molecule alignment state in the first sub-pixel 211mn and the liquid crystal molecule alignment state in the second sub-pixel 212 (m + 1) n.
  • the viewing angle characteristics in the counter matrix type liquid crystal panel can be improved.
  • the burn-in of the liquid crystal panel 2 can be reduced by performing the driving with the polarity reversed for each pixel arranged in the column direction.
  • FIG. 12 is a top view showing a layout of the TFT substrate 10 of the liquid crystal panel 3 according to the present embodiment.
  • FIG. 12 of the total number M of data bus lines 22 ′′ formed on the counter substrate 20, data bus lines 22m ′′ to 22 (m + 4) ′′ arranged in the vicinity of the mth data bus line 22m ′′. Is indicated by a broken line.
  • the liquid crystal panel 3 includes a pixel 310mn defined by an nth gate bus line 16n ′′ and an mth data bus line 22m ′′ among a total of N gate bus lines 16 ′′.
  • the pixel 310mn includes a first sub pixel 311mn and a second sub pixel 312mn.
  • the first subpixel 311mn includes a first pixel electrode 341mn and a first TFT 321mn.
  • the second subpixel 312mn includes a second pixel electrode 342mn and a second TFT 322mn. Also, as shown in FIG. 12, in the area of one pixel 310, the first sub-pixel 311 and the second sub-pixel 312 are arranged in the row direction.
  • a pixel electrode having a large area and a pixel electrode having a small area can be arranged in the row direction and formed in one pixel 310 without causing unnecessary dead space in one pixel 310.
  • the data bus line 22 ′′ is provided in common for the first sub-pixel 311 and the second sub-pixel 312, the voltage applied to the reference voltage bus line 18 ′′ provided for each sub-pixel is changed for each sub-pixel.
  • the potential difference between the data bus line 22 ′′ and the reference voltage bus line 18 ′′ can be changed for each sub-pixel.
  • a counter matrix type liquid crystal panel having a configuration in which two sub-pixels 311 and 312 are arranged side by side in one pixel 310, a multi-pixel structure that does not cause useless space can be obtained, and viewing angle characteristics can be improved. it can.
  • each pixel 310 is not limited to the configuration including the two sub-pixels 311 and 312 arranged in the row direction, and for example, a configuration in which four sub-pixels are provided in one pixel region may be employed.
  • the TFT substrate 10 of the liquid crystal panel 3 in this embodiment is configured such that the area ratio of the second subpixel 312 to the first subpixel 311 is greater than 1 and 4 or less. Preferably it is.
  • the potential difference between the data bus line 22 ′′ and the reference voltage bus line 18 ′′ in the first sub-pixel 311 having a small area is made larger than the potential difference in the second sub-pixel 312 having a large area.
  • the voltage applied to the liquid crystal layer exceeds the liquid crystal threshold earlier than the liquid crystal layer of the second subpixel 312. That is, when the voltage applied to the liquid crystal layer of the first sub-pixel 311 exceeds the threshold value of the liquid crystal, the voltage applied to the liquid crystal layer of the second sub-pixel 312 does not exceed the threshold value of the liquid crystal.
  • the first sub-pixel 311 starts to display the color of the low gradation region first, reaches a higher luminance than the second sub-pixel 312,
  • the second sub-pixel 312 emits light so as to compensate for the light emission amount from the halftone area to the high gradation area. That is, the first sub-pixel 311 having a small area mainly contributes to display from a low gradation to a halftone, while the second sub-pixel 312 having a large area mainly contributes to display from a half-tone to a high gradation. This makes it easy to control the viewing angle characteristic to a desired characteristic.
  • the low gradation region is more reduced when the low gradation region is the first sub-pixel 311 having a smaller area.
  • the viewing angle characteristic can be further improved as compared with the second sub-pixel 312 having a large area.
  • FIG. 13 is a diagram showing an equivalent circuit of the TFT substrate 10 of the liquid crystal panel 3 according to the present embodiment, and a voltage applied to the liquid crystal capacitor during x frame display.
  • the liquid crystal panel 3 in this embodiment includes pixels 210 (m + p) (n + q) defined by data bus lines 22 (m + p) ′′ and gate bus lines 16 (n + q) ′′.
  • p is 0 and a natural number satisfying m ⁇ p
  • q is 0 and a natural number satisfying n ⁇ q.
  • Each pixel includes two sub-pixels.
  • the pixel 310 (m + p) (n + q) and the pixel 310 (m + p + 1) (n + q) are arranged adjacent to each other in the row direction, and the pixel 310 (m + p) (n + q) and the pixel 310 (m + p) (n + q + 1) are adjacent to each other in the column direction. Are arranged.
  • the pixel 310 (m + p) (n + q) includes two subpixels in the row direction in the order of the first subpixel and the second subpixel.
  • the pixel 310mn and the pixel 310 (m + 1) n, the pixel 310m (n + 1), the pixel 310 (m + 1) (n + 1), the pixel 310m (n + 2), and the pixel 310 (m + 1) (n + 2) are arranged adjacent to each other in the row direction.
  • the pixels 310mn to 310m (n + 2) and the pixels 310 (m + 1) n to 310 (m + 1) (n + 2) are arranged adjacent to each other in the column direction.
  • Each pixel 310 includes two subpixels in the order of the first subpixel and the second subpixel in the row direction.
  • each subpixel includes a TFT 12 and a liquid crystal capacitor.
  • the liquid crystal capacitance includes a pixel electrode 14, a counter electrode 24 formed by the data bus line 22 ′′, and a liquid crystal layer sandwiched between the pixel electrode 14 and the counter electrode 24.
  • the liquid crystal capacitor provided in the pixel 310mn includes a first liquid crystal capacitor 331mn and a second liquid crystal capacitor 332mn.
  • the gate terminal of the first TFT 321mn included in the first sub-pixel 311mn of the pixel 310mn is connected to the gate bus line 16n ", the source terminal is connected to the reference voltage bus line 18a", and the drain terminal is The first liquid crystal capacitor 331 mn is connected to the data bus line 22 m ′′.
  • the gate terminal of the second TFT 322mn included in the second subpixel 312mn is connected to the gate bus line 16n ", the source terminal is connected to the reference voltage bus line 18b", and the drain terminal is connected to the data bus via the second liquid crystal capacitor 332mn. Connected to line 22m ".
  • the gate terminal of the first TFT 321 (m + 1) n included in the first sub-pixel 311 (m + 1) n of the pixel 310 (m + 1) n is connected to the gate bus line 16n ′′, and the source terminal is connected to the reference voltage bus line 18a ′′.
  • the drain terminal is connected to the data bus line 22m ′′ via the first liquid crystal capacitor 331 (m + 1) n.
  • the gate terminal of the second TFT 322 (m + 1) n included in the second subpixel 312 (m + 1) n is connected to the gate bus line 16n ′′, the source terminal is connected to the reference voltage bus line 18b ′′, and the drain terminal is the second terminal. It is connected to the data bus line 22 (m + 1) ′′ via the liquid crystal capacitor 332 (m + 1) n.
  • the gate terminal is connected to the gate bus line 16 (n + q) ′′ and the source terminal Is connected to the reference voltage bus line 18a ′′, and the drain terminal is connected to the data bus line 22 (m + p) ′′ via the first liquid crystal capacitor 331 (m + p) (n + q).
  • the second sub-pixel 312 In (m + p) (n + q)
  • the gate terminal of the second TFT 322 (m + p) (n + q) is connected to the gate bus line 16 (n + q) ′′
  • the source terminal is connected to the reference voltage bus line 18b ′′
  • the drain terminal is the second liquid crystal.
  • the capacitor is connected to the data bus line 22 (m + p) ′′ via a capacitor 232 (m + p) (n + q).
  • the pixel 310mn corresponds to red
  • the pixel 310m (n + 1) corresponds to green
  • the pixel 310m (n + 2) corresponds to blue.
  • the present invention is not limited to this.
  • FIG. 14 is a timing chart showing the operation of the liquid crystal panel 3 according to the present embodiment.
  • the operation of the first sub-pixel 311mn shown in FIG. 13 when displaying the x frame will be described as an example.
  • a scanning signal is supplied to the gate terminals of the first TFT 321mn and the second TFT 322mn, and the first TFT 321mn and The second TFT 322mn is turned on.
  • a scanning signal is also supplied to the gate terminals of the first TFT 321 (m + 1) n and the second TFT 322 (m + 2) n, which are turned on.
  • the first liquid crystal capacitor 331mn has a first liquid crystal capacitor. A potential difference nodeX ⁇ nodeY of + 5V between nodeX and nodeY of 331 mn is applied.
  • the voltage applied to the first liquid crystal capacitor 331 (m + 1) n of the pixel 310 (m + 1) n is the reference voltage bus line 18b ′′. Is ⁇ 5V, and the voltage applied to the second liquid crystal capacitor 332 (m + 1) n is ⁇ 4V, which is the potential difference from the reference voltage bus line 18a ′′.
  • the voltage of the first liquid crystal capacitor 331mn does not change, and the voltage applied at time txn is maintained. That is, when the gate bus line 16n ′′ is scanned to display the x frame, the voltage applied to the first liquid crystal capacitor 331mn is scanned again to display the x + 1 frame. Until it will be maintained.
  • the second liquid crystal capacitor 332mn, the first liquid crystal capacitor 331 (m + 1) n, and the second liquid crystal capacitor 332 (m + 1) n are also maintained at the time txn at time tx (n + 1). .
  • a scanning signal is supplied to the gate terminal of the first TFT 321mn, and is turned on.
  • the second TFT 322mn, the first TFT 321 (m + 1) n, and The scanning signal is also supplied to the gate terminal of the second TFT 322 (m + 1) n, and the second TFT 322 (m + 1) n is turned on.
  • the voltage of the first liquid crystal capacitor 331mn does not change, and the voltage applied at time txn is maintained. That is, when the gate bus line 16n ′′ is scanned to display the x frame, the voltage applied to the first liquid crystal capacitor 331mn is scanned again to display the x + 1 frame. Until it will be maintained.
  • the second liquid crystal capacitor 332mn, the first liquid crystal capacitor 331 (m + 1) n, and the second liquid crystal capacitor 332 (m + 1) n are also maintained at the time txn at time tx (n + 1). .
  • the driving method of the liquid crystal panel 3 is a driving method in the liquid crystal panel having the configuration described with reference to FIGS. 13 and 14, and at least the first sub-pixels arranged in the row direction.
  • the voltages applied to the reference voltage bus line 18a “corresponding to the first sub pixel 311mn and the reference voltage bus line 18b" corresponding to the second sub pixel 312mn differ between the 311mn and the second sub pixel 312mn.
  • the potential difference between the data bus line 22m ′′ and the reference voltage bus line 18a ′′ is different from the potential difference between the data bus line 22m ′′ and the reference voltage bus line 18b ′′.
  • a potential difference between the data bus line 22m ′′ and the reference voltage bus line 18a ′′ is applied to the liquid crystal layer of the first sub-pixel 311mn, while the data bus line 22m is applied to the liquid crystal layer of the second sub-pixel 312mn.
  • the potential difference between “and the reference voltage bus line 18b” is applied.
  • the voltage applied to the liquid crystal layer of the first sub-pixel 311mn and the voltage applied to the liquid crystal layer of the second sub-pixel 312mn can be made different.
  • the alignment state of the liquid crystal molecules in the first sub-pixel 311 mn can be made different from the alignment state of the liquid crystal molecules in the second sub-pixel 312 mn with respect to the voltage written to the data bus line 22 m ′′. Viewing angle characteristics in a matrix type liquid crystal panel can be improved.
  • the liquid crystal panel shown in FIG. 15 it is possible to prevent a decrease in visibility that occurs when the area ratio of two sub-pixels constituting a multi-pixel is changed.
  • the bright pixels 98 and the dark pixels 99 are alternately arranged in the row direction and the column direction to form a checkered pattern. As shown in the figure, a rough surface occurs in the image.
  • FIG. 16 is a diagram schematically showing the brightness of each sub-pixel when the area ratio of two sub-pixels constituting a multi-pixel is changed in the conventional technique.
  • FIG. 17 is a diagram showing an example of display when the area ratio of two sub-pixels constituting a multi-pixel is changed in the related art.
  • the first sub-pixel 311 and the second sub-pixel 312 are alternately arranged in the row direction, but the first sub-pixel 311 and the second sub-pixel 312 are arranged. Are arranged so as to be aligned in the column direction, so that a column of sub-pixels with a small area and a column of sub-pixels with a large area can be formed.
  • a liquid crystal panel includes a first substrate, a second substrate disposed so as to face the first substrate, the first substrate, and the first substrate.
  • a liquid crystal panel provided between the two substrates and a plurality of pixel regions arranged two-dimensionally along the row direction and the column direction, each of the pixel regions including at least the above-described pixel region
  • the first substrate includes two sub-pixel regions arranged in the row direction, and the first substrate intersects with the gate bus line provided corresponding to the pixel region arranged in the row direction, and the gate bus line through an insulating film.
  • the above standard corresponding to the pixel electrode A data bus line provided for each of the sub-pixel regions corresponding to the pixel regions arranged in the column direction. It is characterized by having.
  • each pixel region includes at least two subpixel regions arranged in the row direction, and the reference voltage bus line intersecting with the gate bus line is provided for each subpixel region.
  • a pixel electrode having a large area and a pixel electrode having a small area can be arranged in the row direction and formed in one pixel region without causing a dead space.
  • a voltage having an arbitrary value can be applied to two sub-pixel areas provided in one pixel area.
  • the counter matrix type liquid crystal panel having a configuration in which two sub-pixel regions are arranged side by side in one pixel region, a multi-pixel structure that does not cause useless space can be obtained, and viewing angle characteristics can be improved.
  • a voltage of an arbitrary value can be applied to at least two subpixel regions arranged in the row direction of each pixel region, a potential difference between the subpixel regions can be freely set after the liquid crystal panel is completed.
  • the voltage between the sub-pixel regions can be adjusted appropriately, and the yield can be improved.
  • each pixel region includes at least two subpixel regions arranged in the row direction includes, for example, two sets of two subpixel regions arranged in the row direction, and four subpixels in one pixel region. This means that it is allowed to provide a region.
  • the potential difference between the data bus line and the reference voltage bus line which are provided for each sub-pixel region and make a pair is different for each sub-pixel region.
  • the data bus line and the reference voltage bus line are provided in pairs for each sub-pixel region, various voltages can be applied to the data bus line and the reference voltage bus line.
  • the potential difference between the data bus line and the reference voltage bus line can be changed in various ways.
  • the counter matrix type liquid crystal panel having a configuration in which two sub-pixel regions are arranged side by side in one pixel region, a multi-pixel structure that does not cause useless space can be obtained, and viewing angle characteristics can be improved.
  • the two sub-pixel regions provided in each of the pixel regions have different areas, and a data bus line and a reference voltage that are provided for each sub-pixel region and make a pair.
  • a data bus line and a reference voltage that are provided for each sub-pixel region and make a pair.
  • the potential difference between the bus lines it is preferable that the potential difference in the sub-pixel region having a small area out of the two sub-pixel regions is larger than the potential difference in the sub-pixel region having a large area.
  • the potential difference in a sub-pixel region having a small area (hereinafter referred to as a small sub-pixel region) is made larger than the potential difference in a sub-pixel region having a large area (hereinafter referred to as a large sub-pixel region). Therefore, the voltage applied to the liquid crystal layer in the small sub-pixel region exceeds the threshold value earlier than the liquid crystal layer in the large sub-pixel region. That is, when the voltage applied to the liquid crystal layer in the small sub-pixel region exceeds the threshold value, the voltage applied to the liquid crystal layer in the large sub-pixel region does not exceed the threshold value.
  • the small sub-pixel area starts to display the color of the low gradation area first, reaches a higher brightness than the large sub-pixel area, Thus, light is emitted so as to compensate the light emission amount from the halftone area to the high gradation area.
  • the small sub-pixel region mainly contributes to the display from low gradation to halftone, while the large sub-pixel region mainly contributes to the display from halftone to high gradation. This makes it easy to control the viewing angle characteristic to a desired characteristic.
  • the low gradation area is the large subpixel area when the low gradation area is the small subpixel area.
  • the viewing angle characteristics can be further improved than the above.
  • a liquid crystal panel includes a first substrate, a second substrate disposed so as to face the first substrate, the first substrate, and the first substrate.
  • a plurality of pixel regions are two-dimensionally arranged along the row direction and the column direction, and each of the pixel regions is arranged at least in the column direction.
  • the second substrate includes a data bus line provided corresponding to the pixel region arranged in the column direction, and the gate bus line is formed in a meandering shape. It is characterized in that the areas of the two sub-pixel regions are different.
  • the first substrate When a pixel electrode is provided for each sub-pixel region, two pixel electrodes having different areas can be provided side by side in the column direction without creating a dead space in one pixel region.
  • the meandering center line is a bisector that divides the pixel region into two regions of equal area arranged in the column direction.
  • the gate bus line is displaced from the center line in the column direction, the two regions having the same area aligned in the column direction naturally have different areas.
  • a pixel electrode having a small area is formed by simply reducing one pixel electrode of the two regions having the same area without meandering the gate bus line, the sub-electrode on which the pixel electrode having a small area is formed. Dead space occurs in the pixel area.
  • the area of the sub-pixel region itself is made different by meandering the gate bus line, so that a pixel electrode having a large area can be obtained without causing a dead space in one pixel region. And a pixel electrode having a small area can be formed in one pixel region.
  • each pixel area includes at least two subpixel areas arranged in the column direction includes, for example, two sets of two subpixel areas arranged in the column direction, and four subpixels in one pixel area. This means that it is allowed to provide a region.
  • the meandering center line is a bisector that divides the pixel region into two regions arranged with the same width in the column direction, and is provided for each pixel electrode.
  • One switching element is preferably provided for each meandering bent portion.
  • the layout of the switching element arrangement can be simplified.
  • the first pixel region is arranged in the column direction.
  • a pixel region and a second sub-pixel region, and the second pixel region includes a third sub-pixel region and a fourth sub-pixel region arranged in the column direction
  • the reference voltage bus line includes the column It is preferable that the second subpixel region and the third subpixel region which are adjacent to each other in the direction are shared.
  • pixel regions adjacent in the column direction can share one reference voltage bus line, so that a simple wiring layout can be achieved.
  • a liquid crystal panel includes a first substrate, a second substrate disposed so as to face the first substrate, the first substrate, and the first substrate.
  • a liquid crystal panel provided between the two substrates and a plurality of pixel regions arranged two-dimensionally along the row direction and the column direction, each of the pixel regions including at least the above-described pixel region
  • the first substrate includes two sub-pixel regions arranged in the row direction, and the first substrate intersects with the gate bus lines provided corresponding to the pixel regions arranged in the row direction, and the gate bus lines via an insulating film.
  • the reference voltage bus line provided for each sub-pixel region, the pixel electrode provided for each sub-pixel region, the gate electrode supplied to the gate bus line, the pixel electrode, Reference voltage corresponding to the pixel electrode
  • a data bus provided in common in the two sub-pixel regions corresponding to the pixel regions arranged in the column direction. It is characterized by having a line.
  • each pixel region includes at least two subpixel regions arranged in the row direction, and the reference voltage bus line intersecting with the gate bus line is provided for each subpixel region.
  • a pixel electrode having a large area and a pixel electrode having a small area can be arranged in the row direction and formed in one pixel region without causing a dead space.
  • the data bus line and the reference voltage can be changed by changing the voltage applied to the reference voltage bus line provided for each subpixel region according to the subpixel region.
  • the potential difference from the bus line can be changed for each sub-pixel region.
  • the counter matrix type liquid crystal panel having a configuration in which two sub-pixel regions are arranged side by side in one pixel region, a multi-pixel structure that does not cause useless space can be obtained, and viewing angle characteristics can be improved.
  • each pixel region includes at least two subpixel regions arranged in the row direction includes, for example, two sets of two subpixel regions arranged in the row direction, and four subpixels in one pixel region. This means that it is allowed to provide a region.
  • the areas of the two subpixel regions arranged in the row direction are made different, and of the two subpixel regions, the smaller subpixel region or the larger one of the two subpixel regions
  • the subpixel regions may be arranged so as to be aligned in the column direction.
  • a column of sub-pixel regions having a small area and a column of sub-pixel regions having a large area can be formed.
  • the color of the low gradation area to the halftone area is displayed on the column of the subpixel area having a small area
  • the color of the high gradation area from the halftone area is displayed on the column of the subpixel area having a large area.
  • the first sub-regions are arranged in the row direction.
  • a pixel region and a second sub-pixel region, and the second pixel region includes a third sub-pixel region and a fourth sub-pixel region arranged in the row direction
  • the reference voltage bus line includes the row It is preferable that the second subpixel region and the third subpixel region which are adjacent to each other in the direction are shared.
  • pixel regions adjacent in the row direction can share one reference voltage bus line, so that a simple wiring layout can be achieved.
  • a display device including the liquid crystal panel according to the present invention is also included in the scope of the present invention.
  • a driving method of a liquid crystal panel according to the present invention is a driving method in the above-described liquid crystal panel, and at least the two subpixel regions arranged in the row direction are defined as a first subpixel region and a second subpixel region.
  • the reference voltage bus line corresponding to the first sub-pixel region is a first reference voltage bus line
  • the reference voltage bus line corresponding to the second sub-pixel region is a second reference voltage bus line
  • the voltages applied to the bus line and the second reference voltage bus line are made the same, and the voltages applied to the first data bus line and the second data bus line are made different.
  • the potential difference between the first data bus line and the first reference voltage bus line is made different from the potential difference between the second data bus line and the second reference voltage bus line. It is said.
  • the switching element when a gate signal is output to the gate bus line provided corresponding to the pixel region, the switching element is turned on, and at least the first sub-pixel region aligned in the row direction and The second subpixel region is selected at the same time, and the voltage applied to the reference voltage bus line corresponding to each subpixel region is written into the pixel electrode of each subpixel region.
  • each data bus line is opposed to the pixel electrode in each sub-pixel region, the liquid crystal layer in the first sub-pixel region has a potential difference between the first data bus line and the first reference voltage bus line.
  • a potential difference between the second data bus line and the second reference voltage bus line is applied to the liquid crystal layer in the second subpixel region.
  • the voltage applied to the first reference voltage bus line is the same as the voltage applied to the second reference voltage bus line, and is applied to the first data bus line and the second data bus line. Therefore, the voltage applied to the liquid crystal layer in the first subpixel region can be made different from the voltage applied to the liquid crystal layer in the second subpixel region.
  • the voltages applied to the first data bus line and the second data bus line based on the alignment state of the liquid crystal molecules in the first sub-pixel region and the alignment state of the liquid crystal molecules in the second sub-pixel region.
  • the viewing angle characteristics in the counter matrix type liquid crystal panel can be improved.
  • a driving method of a liquid crystal panel according to the present invention is a driving method in the above-described liquid crystal panel, and a reference voltage bus line corresponding to at least one of the two sub-pixel regions arranged in the column direction is connected to the first voltage line.
  • the reference voltage bus line corresponding to the other sub-pixel region is the second reference voltage bus line
  • the first reference voltage bus line is applied to the first reference voltage bus line and the second reference voltage bus line.
  • the potential difference between the data bus line and the first reference voltage bus line is made different from the potential difference between the data bus line and the second reference voltage bus line by making each voltage different. It is said.
  • the switching element when a gate signal is output to the gate bus line provided corresponding to the pixel region, the switching element is turned on, and at least two sub-pixel regions arranged in the column direction are simultaneously selected. Then, the voltage applied to the reference voltage bus line corresponding to each subpixel region is written into the pixel electrode of each subpixel region.
  • the voltage applied to the liquid crystal layer in the one sub-pixel region can be made different from the voltage applied to the liquid crystal layer in the other sub-pixel region.
  • the alignment state of the liquid crystal molecules in the one subpixel region can be made different from the alignment state of the liquid crystal molecules in the other subpixel region with respect to the voltage written to the data bus line. Viewing angle characteristics in a matrix type liquid crystal panel can be improved.
  • the areas of the two sub-pixel regions are different by making the gate bus line meandering.
  • the area of one subpixel area of two subpixel areas corresponding to a certain data bus line is smaller than the area of the other subpixel area, it corresponds to the data bus line adjacent to the data bus line.
  • the area of one of the two subpixel areas is larger than the area of the other subpixel area.
  • a driving method of a liquid crystal panel according to the present invention is a driving method in the above-described liquid crystal panel, and at least the two subpixel regions arranged in the row direction are defined as a first subpixel region and a second subpixel region.
  • the reference voltage bus line corresponding to the first sub-pixel region is a first reference voltage bus line
  • the reference voltage bus line corresponding to the second sub-pixel region is a second reference voltage bus line.
  • the switching element when a gate signal is output to the gate bus line provided corresponding to the pixel region, the switching element is turned on, and at least the first sub-pixel region aligned in the row direction and The second subpixel region is selected at the same time, and the voltage applied to the reference voltage bus line corresponding to each subpixel region is written into the pixel electrode of each subpixel region.
  • the voltage applied to the liquid crystal layer in the first subpixel region can be made different from the voltage applied to the liquid crystal layer in the second subpixel region.
  • the alignment state of the liquid crystal molecules in the first subpixel region can be made different from the alignment state of the liquid crystal molecules in the second subpixel region with respect to the voltage written to the data bus line. Viewing angle characteristics in a matrix type liquid crystal panel can be improved.
  • the liquid crystal panel according to the present invention can be suitably applied to TVs, personal computer monitors, mobile phones and the like.

Abstract

La présente invention concerne un écran (1) à cristaux liquides caractérisé en ce qu'un pixel (210) faisant partie de l'écran à cristaux liquides est doté d'au moins deux sous-pixels (211, 212) alignés dans la direction des lignes, en ce qu'un substrat (10) de TFT est muni d'une ligne (16) de bus de grilles, d'une ligne (18) de bus de tension de référence, d'une électrode (14) de pixel et d'un TFT (12) qui établit et coupe la liaison électrique entre l'électrode (14) de pixel et la ligne (18) de bus de tension de référence, et en ce qu'un substrat (20) de façade est muni d'une ligne (22) de bus de données.
PCT/JP2011/078105 2010-12-10 2011-12-05 Ecran à cristaux liquides, dispositif d'affichage et procédé ce commande de l'écran à cristaux liquides WO2012077647A1 (fr)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104020605A (zh) * 2014-04-22 2014-09-03 友达光电股份有限公司 显示面板
WO2017130293A1 (fr) * 2016-01-26 2017-08-03 堺ディスプレイプロダクト株式会社 Dispositif d'affichage à cristaux liquides

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63241524A (ja) * 1987-03-30 1988-10-06 Hitachi Ltd 液晶デイスプレイ
JPH024291A (ja) * 1988-06-23 1990-01-09 Fujitsu Ltd アクティブマトリクス型液晶表示装置
JPH11295758A (ja) * 1998-04-10 1999-10-29 Nec Corp 液晶表示装置及びその駆動方法
JP2005316211A (ja) * 2004-04-30 2005-11-10 Fujitsu Display Technologies Corp 視角特性を改善した液晶表示装置
JP2008309884A (ja) * 2007-06-12 2008-12-25 Sony Corp 液晶表示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63241524A (ja) * 1987-03-30 1988-10-06 Hitachi Ltd 液晶デイスプレイ
JPH024291A (ja) * 1988-06-23 1990-01-09 Fujitsu Ltd アクティブマトリクス型液晶表示装置
JPH11295758A (ja) * 1998-04-10 1999-10-29 Nec Corp 液晶表示装置及びその駆動方法
JP2005316211A (ja) * 2004-04-30 2005-11-10 Fujitsu Display Technologies Corp 視角特性を改善した液晶表示装置
JP2008309884A (ja) * 2007-06-12 2008-12-25 Sony Corp 液晶表示装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104020605A (zh) * 2014-04-22 2014-09-03 友达光电股份有限公司 显示面板
CN104020605B (zh) * 2014-04-22 2017-01-18 友达光电股份有限公司 显示面板
WO2017130293A1 (fr) * 2016-01-26 2017-08-03 堺ディスプレイプロダクト株式会社 Dispositif d'affichage à cristaux liquides

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