WO2012077647A1 - Liquid crystal panel, display device, and method for driving the liquid crystal panel - Google Patents

Liquid crystal panel, display device, and method for driving the liquid crystal panel Download PDF

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Publication number
WO2012077647A1
WO2012077647A1 PCT/JP2011/078105 JP2011078105W WO2012077647A1 WO 2012077647 A1 WO2012077647 A1 WO 2012077647A1 JP 2011078105 W JP2011078105 W JP 2011078105W WO 2012077647 A1 WO2012077647 A1 WO 2012077647A1
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Prior art keywords
bus line
pixel
liquid crystal
reference voltage
sub
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PCT/JP2011/078105
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French (fr)
Japanese (ja)
Inventor
誠二 大橋
豪 鎌田
昇平 勝田
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シャープ株式会社
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Publication of WO2012077647A1 publication Critical patent/WO2012077647A1/en

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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3648Control of matrices with row and column drivers using an active matrix
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1343Electrodes
    • G02F1/134309Electrodes characterised by their geometrical arrangement
    • G02F1/134345Subdivided pixels, e.g. for grey scale or redundancy
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/04Structural and physical details of display devices
    • G09G2300/0421Structural details of the set of electrodes
    • G09G2300/0426Layout of electrodes and connections
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/04Structural and physical details of display devices
    • G09G2300/0439Pixel structures
    • G09G2300/0443Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
    • G09G2300/0447Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations for multi-domain technique to improve the viewing angle in a liquid crystal display, such as multi-vertical alignment [MVA]

Definitions

  • the present invention relates to a counter matrix type liquid crystal panel, a display device including the counter matrix type liquid crystal panel, and a driving method thereof.
  • liquid crystal display devices are required to have high image quality.
  • a driving method that divides one pixel into a plurality of subpixels is used to improve viewing angle characteristics. Commonly used.
  • the multi-pixel driving bright subpixels and dark subpixels are formed in one pixel and halftones are displayed. As a result, whitening or the like during halftone display can be suppressed.
  • the luminance of each sub-pixel is controlled by varying the potential of each auxiliary capacitor Cs connected to the two sub-pixels and causing a potential difference in each sub-pixel.
  • Patent Document 1 in a multi-pixel driving type liquid crystal display device, it is desirable to set the area ratio of two sub-pixels to 1/2 or more and 4 or less in order to obtain high visual characteristics. Are listed.
  • a counter matrix type has been proposed as a configuration method of the liquid crystal display device.
  • a gate bus line, a reference voltage bus line, a switching element, and a display electrode are provided on a first substrate, and a counter electrode that is also used as a data bus line is provided on a second substrate.
  • a counter electrode that is also used as a data bus line is provided on a second substrate.
  • Patent Document 2 listed below, by dividing one pixel of a counter-matrix liquid crystal display device into two sub-pixels, even if one of the sub-pixels is defective, a pixel defect occurs. However, a technique for maintaining good display quality is disclosed.
  • Japanese Patent Publication Japanese Patent Laid-Open No. 2006-133577 (published May 25, 2006)” Japanese Patent Publication “Japanese Patent Laid-Open No. 2000-75318 (published on March 4, 2000)”
  • FIG. 15 shows a top view of a liquid crystal panel that is an experimental experiment for the case.
  • the aperture ratio of the pixel is increased. It turns out that the dead space 90 which does not contribute arises.
  • the present invention has been made to solve the above-mentioned problems, and its main object is to dead even when the area ratio of a plurality of sub-pixels constituting a multi-pixel is changed in a counter matrix type liquid crystal panel.
  • the object is to provide a liquid crystal panel in which no space is generated.
  • a liquid crystal panel includes a first substrate, a second substrate disposed so as to face the first substrate, the first substrate, and the first substrate.
  • a liquid crystal panel provided between the two substrates and a plurality of pixel regions arranged two-dimensionally along the row direction and the column direction, each of the pixel regions including at least the above-described pixel region
  • the first substrate includes two sub-pixel regions arranged in the row direction, and the first substrate intersects with the gate bus line provided corresponding to the pixel region arranged in the row direction, and the gate bus line through an insulating film.
  • the above-mentioned base corresponding to the pixel electrode A switching element for turning on and off the electrical connection with the voltage bus line, and the second substrate is a data bus line provided for each of the sub-pixel regions corresponding to the pixel regions arranged in the column direction. It is characterized by having.
  • each pixel region includes at least two subpixel regions arranged in the row direction, and the reference voltage bus line intersecting with the gate bus line is provided for each subpixel region.
  • a pixel electrode having a large area and a pixel electrode having a small area can be arranged in the row direction and formed in one pixel region without causing a dead space.
  • a voltage having an arbitrary value can be applied to two sub-pixel areas provided in one pixel area.
  • the counter matrix type liquid crystal panel having a configuration in which two sub-pixel regions are arranged side by side in one pixel region, a multi-pixel structure that does not cause useless space can be obtained, and viewing angle characteristics can be improved.
  • a voltage of an arbitrary value can be applied to at least two subpixel regions arranged in the row direction of each pixel region, a potential difference between the subpixel regions can be freely set after the liquid crystal panel is completed.
  • the voltage between the sub-pixel regions can be adjusted appropriately, and the yield can be improved.
  • each pixel region includes at least two subpixel regions arranged in the row direction includes, for example, two sets of two subpixel regions arranged in the row direction, and four subpixels in one pixel region. This means that it is allowed to provide a region.
  • a liquid crystal panel includes a first substrate, a second substrate disposed so as to face the first substrate, the first substrate, and the first substrate.
  • a plurality of pixel regions are two-dimensionally arranged along the row direction and the column direction, and each of the pixel regions is arranged at least in the column direction.
  • the second substrate includes a data bus line provided corresponding to the pixel region arranged in the column direction, and the gate bus line is formed in a meandering shape. It is characterized in that the areas of the two sub-pixel regions are different.
  • the first substrate When a pixel electrode is provided for each sub-pixel region, two pixel electrodes having different areas can be provided side by side in the column direction without creating a dead space in one pixel region.
  • the meandering center line is a bisector that divides the pixel region into two regions of equal area arranged in the column direction.
  • the gate bus line is displaced from the center line in the column direction, the two regions having the same area aligned in the column direction naturally have different areas.
  • a pixel electrode having a small area is formed by simply reducing one pixel electrode of the two regions having the same area without meandering the gate bus line, the sub-electrode on which the pixel electrode having a small area is formed. Dead space occurs in the pixel area.
  • the area of the sub-pixel region itself is made different by meandering the gate bus line, so that a pixel electrode having a large area can be obtained without causing a dead space in one pixel region. And a pixel electrode having a small area can be formed in one pixel region.
  • each pixel area includes at least two subpixel areas arranged in the column direction includes, for example, two sets of two subpixel areas arranged in the column direction, and four subpixels in one pixel area. This means that it is allowed to provide a region.
  • a liquid crystal panel includes a first substrate, a second substrate disposed so as to face the first substrate, the first substrate, and the first substrate.
  • a liquid crystal panel provided between the two substrates and a plurality of pixel regions arranged two-dimensionally along the row direction and the column direction, each of the pixel regions including at least the above-described pixel region
  • the first substrate includes two sub-pixel regions arranged in the row direction, and the first substrate intersects with the gate bus lines provided corresponding to the pixel regions arranged in the row direction, and the gate bus lines via an insulating film.
  • the reference voltage bus line provided for each sub-pixel region, the pixel electrode provided for each sub-pixel region, the gate electrode supplied to the gate bus line, the pixel electrode, Reference voltage corresponding to the pixel electrode
  • a data bus provided in common in the two sub-pixel regions corresponding to the pixel regions arranged in the column direction. It is characterized by having a line.
  • each pixel region includes at least two subpixel regions arranged in the row direction, and the reference voltage bus line intersecting with the gate bus line is provided for each subpixel region.
  • a pixel electrode having a large area and a pixel electrode having a small area can be arranged in the row direction and formed in one pixel region without causing a dead space.
  • the data bus line and the reference voltage can be changed by changing the voltage applied to the reference voltage bus line provided for each subpixel region according to the subpixel region.
  • the potential difference from the bus line can be changed for each sub-pixel region.
  • the counter matrix type liquid crystal panel having a configuration in which two sub-pixel regions are arranged side by side in one pixel region, a multi-pixel structure that does not cause useless space can be obtained, and viewing angle characteristics can be improved.
  • each pixel region includes at least two subpixel regions arranged in the row direction includes, for example, two sets of two subpixel regions arranged in the row direction, and four subpixels in one pixel region. This means that it is allowed to provide a region.
  • the areas of the two subpixel regions arranged in the row direction are made different, and of the two subpixel regions, the smaller subpixel region or the larger one of the two subpixel regions
  • the subpixel regions may be arranged so as to be aligned in the column direction.
  • a column of sub-pixel regions having a small area and a column of sub-pixel regions having a large area can be formed.
  • the color of the low gradation area to the halftone area is displayed on the column of the subpixel area having a small area
  • the color of the high gradation area from the halftone area is displayed on the column of the subpixel area having a large area.
  • a driving method of a liquid crystal panel according to the present invention is a driving method in the above-described liquid crystal panel, and at least the two subpixel regions arranged in the row direction are defined as a first subpixel region and a second subpixel region.
  • the reference voltage bus line corresponding to the first sub-pixel region is a first reference voltage bus line
  • the reference voltage bus line corresponding to the second sub-pixel region is a second reference voltage bus line
  • the voltages applied to the bus line and the second reference voltage bus line are made the same, and the voltages applied to the first data bus line and the second data bus line are made different.
  • the potential difference between the first data bus line and the first reference voltage bus line is made different from the potential difference between the second data bus line and the second reference voltage bus line. It is said.
  • the switching element when a gate signal is output to the gate bus line provided corresponding to the pixel region, the switching element is turned on, and at least the first sub-pixel region aligned in the row direction and The second subpixel region is selected at the same time, and the voltage applied to the reference voltage bus line corresponding to each subpixel region is written into the pixel electrode of each subpixel region.
  • each data bus line is opposed to the pixel electrode in each sub-pixel region, the liquid crystal layer in the first sub-pixel region has a potential difference between the first data bus line and the first reference voltage bus line.
  • a potential difference between the second data bus line and the second reference voltage bus line is applied to the liquid crystal layer in the second subpixel region.
  • the voltage applied to the first reference voltage bus line is the same as the voltage applied to the second reference voltage bus line, and is applied to the first data bus line and the second data bus line. Therefore, the voltage applied to the liquid crystal layer in the first subpixel region can be made different from the voltage applied to the liquid crystal layer in the second subpixel region.
  • the voltages applied to the first data bus line and the second data bus line based on the alignment state of the liquid crystal molecules in the first sub-pixel region and the alignment state of the liquid crystal molecules in the second sub-pixel region.
  • the viewing angle characteristics in the counter matrix type liquid crystal panel can be improved.
  • a driving method of a liquid crystal panel according to the present invention is a driving method in the above-described liquid crystal panel, and a reference voltage bus line corresponding to at least one of the two sub-pixel regions arranged in the column direction is connected to the first voltage line.
  • the reference voltage bus line corresponding to the other sub-pixel region is the second reference voltage bus line
  • the first reference voltage bus line is applied to the first reference voltage bus line and the second reference voltage bus line.
  • the potential difference between the data bus line and the first reference voltage bus line is made different from the potential difference between the data bus line and the second reference voltage bus line by making each voltage different. It is said.
  • the switching element when a gate signal is output to the gate bus line provided corresponding to the pixel region, the switching element is turned on, and at least two sub-pixel regions arranged in the column direction are simultaneously selected. Then, the voltage applied to the reference voltage bus line corresponding to each subpixel region is written into the pixel electrode of each subpixel region.
  • the voltage applied to the liquid crystal layer in the one sub-pixel region can be made different from the voltage applied to the liquid crystal layer in the other sub-pixel region.
  • the alignment state of the liquid crystal molecules in the one subpixel region can be made different from the alignment state of the liquid crystal molecules in the other subpixel region with respect to the voltage written to the data bus line. Viewing angle characteristics in a matrix type liquid crystal panel can be improved.
  • the areas of the two sub-pixel regions are different by making the gate bus line meandering.
  • the area of one subpixel area of two subpixel areas corresponding to a certain data bus line is smaller than the area of the other subpixel area, it corresponds to the data bus line adjacent to the data bus line.
  • the area of one of the two subpixel areas is larger than the area of the other subpixel area.
  • a driving method of a liquid crystal panel according to the present invention is a driving method in the above-described liquid crystal panel, and at least the two subpixel regions arranged in the row direction are defined as a first subpixel region and a second subpixel region.
  • the reference voltage bus line corresponding to the first sub-pixel region is a first reference voltage bus line
  • the reference voltage bus line corresponding to the second sub-pixel region is a second reference voltage bus line.
  • the switching element when a gate signal is output to the gate bus line provided corresponding to the pixel region, the switching element is turned on, and at least the first sub-pixel region aligned in the row direction and The second subpixel region is selected at the same time, and the voltage applied to the reference voltage bus line corresponding to each subpixel region is written into the pixel electrode of each subpixel region.
  • the voltage applied to the liquid crystal layer in the first subpixel region can be made different from the voltage applied to the liquid crystal layer in the second subpixel region.
  • the alignment state of the liquid crystal molecules in the first subpixel region can be made different from the alignment state of the liquid crystal molecules in the second subpixel region with respect to the voltage written to the data bus line. Viewing angle characteristics in a matrix type liquid crystal panel can be improved.
  • the liquid crystal panel according to the present invention includes the first substrate, the second substrate disposed so as to face the first substrate, the first substrate, and the second substrate.
  • the first substrate includes a gate bus line provided corresponding to the pixel region aligned in the row direction, and the pixel substrate aligned in the row direction, A reference voltage bus line provided for each sub-pixel region, a pixel electrode provided for each sub-pixel region, and a gate signal supplied to the gate bus line, between each pixel electrode and the reference voltage bus line.
  • the second substrate includes a data bus line provided corresponding to the pixel region arranged in the column direction, and the gate bus line has a meandering shape, whereby the two sub-pixels are provided. It is characterized by different areas.
  • FIG. 2 is a diagram showing an equivalent circuit of the TFT substrate shown in FIG. 1 and a voltage applied to a liquid crystal capacitor during x-frame display.
  • FIG. 2 is a diagram showing an equivalent circuit of the TFT substrate shown in FIG. 1 and a voltage applied to a liquid crystal capacitor during x + 1 frame display.
  • FIG. 5 is a diagram showing an equivalent circuit of a TFT substrate when the liquid crystal capacitance shown in FIGS. 4A and 4B is expressed as a capacitor.
  • FIG. 3 is a timing chart illustrating an operation of the liquid crystal panel illustrated in FIG. 1. It is a top view which shows the outline of a structure of the TFT substrate of the liquid crystal panel shown in FIG. It is a top view which shows the outline of a structure of the TFT substrate of the liquid crystal panel shown in FIG. It is a top view which shows the layout of the TFT substrate of the liquid crystal panel which concerns on other embodiment of this invention.
  • FIG. 10 is a diagram showing an equivalent circuit of the TFT substrate shown in FIG. 9 and a voltage applied to a liquid crystal capacitor during x-frame display.
  • FIG. 10 is a diagram showing an equivalent circuit of the TFT substrate shown in FIG. 9 and an applied voltage of a liquid crystal capacitor at the time of x + 1 frame display.
  • FIG. 10 is a timing chart showing the operation of the liquid crystal panel shown in FIG. 9. It is a top view which shows the layout of the TFT substrate of the liquid crystal panel which concerns on further another embodiment of this invention.
  • FIG. 13 is a diagram showing an equivalent circuit of the TFT substrate shown in FIG. 12 and a voltage applied to a liquid crystal capacitor during x frame display. 13 is a timing chart showing the operation of the liquid crystal panel shown in FIG. In the prior art, it is a top view of a liquid crystal panel when the area ratio of two sub-pixels constituting a multi-pixel is changed.
  • FIG. 16 is a diagram schematically showing the brightness of each sub-pixel in the liquid crystal panel shown in FIG. 15.
  • FIG. 16 is a diagram showing an example of display on the liquid crystal panel shown in FIG. 15.
  • a liquid crystal panel according to an embodiment of the present invention, a display device including the liquid crystal panel, and a driving method thereof will be described with reference to FIGS.
  • the dimensions, materials, shapes, relative arrangements, and the like of the components described in this embodiment are not intended to limit the scope of the present invention only, unless otherwise specified. It is just an example.
  • FIG. 2 is a perspective view of the liquid crystal panel 1 according to the present embodiment.
  • FIG. 3 is a diagram showing details of the liquid crystal panel 1 according to the present embodiment.
  • the liquid crystal panel 1 includes a TFT substrate (first substrate) 10 and a counter substrate (second substrate) 20 disposed to face the first substrate. ing. A liquid crystal layer (not shown) is formed between the TFT substrate 10 and the counter substrate 20.
  • the TFT substrate 10 includes a plurality of TFTs (switching elements) 12 and a plurality of pixels on one surface (hereinafter also referred to as a mounting surface of the TFT substrate 10).
  • the electrode 14 includes a plurality of gate bus lines 16 formed in parallel to each other, and a reference voltage bus line 18 formed in parallel to the gate bus lines 16.
  • the TFT 12 has a gate terminal connected to the gate bus line 16, a source terminal connected to the reference voltage bus line 18, and a drain terminal connected to the pixel electrode 14.
  • a terminal connected to the reference voltage bus line 18 is called a source terminal, and a terminal connected to the pixel electrode 14 is a drain. Called a terminal.
  • the gate bus line 16 supplies a scanning signal (gate signal) to the connected TFT 12.
  • the reference voltage bus line 18 supplies a reference voltage to the pixel electrode 14 via the TFT 12. Further, as shown in FIG. 3A, the gate bus line 16 includes a gate input terminal 16a, and the reference voltage bus line 18 includes a reference voltage input terminal 18c.
  • the counter substrate 20 includes data bus lines 22 formed in parallel with each other on one surface (hereinafter also referred to as a mounting surface of the counter substrate 20). .
  • the portion of the data bus line 22 that faces the pixel electrode 14 also serves as the counter electrode 24 of the pixel electrode 14.
  • a liquid crystal layer is formed by sandwiching a liquid crystal layer between the pixel electrode 14 and the counter electrode 24.
  • the data bus line 22 supplies a data (video) signal to the counter electrode 24.
  • the data bus line 22 includes a data input terminal 22a.
  • the TFT substrate 10 and the counter substrate 20 are arranged so that the mounting surface of the TFT substrate 10 and the mounting surface of the counter substrate 20 face each other, as shown in FIG.
  • the gate bus line 16 formed on the mounting surface of the TFT substrate 10 and the data bus line 22 formed on the mounting surface of the counter substrate 20 intersect via the liquid crystal layer.
  • FIG. 7 is a top view schematically showing the configuration of the TFT substrate 10 of the liquid crystal panel 1 according to this embodiment.
  • the gate input terminal 16a of the gate bus line 16 and the reference voltage input terminal 18c of the reference voltage bus line 18 supply a scanning signal to each gate bus line 16 at the end portion of the TFT substrate 10, and each reference voltage.
  • a gate drive circuit 32 that supplies a reference voltage to the bus line 18 is connected.
  • the data input terminal 22 a of the data bus line 22 is connected to a data driving circuit 34 that supplies a data signal to each data bus line 22 in the flexible printed circuit board 30.
  • FIG. 1 is a top view showing a layout of the TFT substrate 10 of the liquid crystal panel 1 according to the present embodiment.
  • M and m are natural numbers, M ⁇ m).
  • Lines 22 (m ⁇ 1) to 22 (m + 2) are indicated by broken lines.
  • the liquid crystal panel 1 includes pixels (pixel regions) 110 defined by the gate bus lines 16 and the data bus lines 22.
  • the pixels 110 are two-dimensionally arranged along the row direction and the column direction.
  • Each pixel includes Sub-pix1 which is the first sub-pixel 111 (first sub-pixel region) and Sub-pix2 which is the second sub-pixel 112 (second sub-pixel region).
  • the pixel electrode 14 includes a first pixel electrode 141 constituting the first subpixel 111 and a second pixel electrode 142 constituting the second subpixel 112.
  • the TFT 12 includes a first TFT 121 constituting the first subpixel 111 and a second TFT 122 constituting the second subpixel 112.
  • pixels defined by an nth gate bus line 16n are natural numbers, N ⁇ n
  • an mth data bus line 22m 110 is a pixel 110mn
  • a first subpixel 111 of the pixel 110mn is a first subpixel 111mn
  • a second subpixel 112 is a second subpixel 112mn.
  • the first pixel electrode 141 constituting the first subpixel 111mn is referred to as a first pixel electrode 141mn
  • the second pixel electrode 142 constituting the second subpixel 112mn is referred to as a second pixel electrode 142mn.
  • first TFT 121 constituting the first sub pixel 111mn is referred to as a first TFT 121mn
  • second TFT 122 constituting the second sub pixel 112 is referred to as a second TFT 122mn.
  • the first sub-pixel 111 and the second sub-pixel 112 are arranged in the column direction.
  • the gate terminal of the first TFT 121mn included in the first subpixel 111mn is connected to the gate bus line 16n
  • the source terminal is connected to the reference voltage bus line 18a (first reference voltage bus line)
  • the drain terminal is connected to the first pixel. It is connected to the electrode 141mn.
  • the gate terminal of the second TFT 122mn included in the second subpixel 112 is connected to the gate bus line 16n
  • the source terminal is connected to the reference voltage bus line 18b (second reference voltage bus line)
  • the drain terminal is connected to the second pixel. It is connected to the electrode 142mn.
  • the TFT substrate 10 of the liquid crystal panel 1 in this embodiment is configured such that the area ratio of the second subpixel 112 to the first subpixel 111 is greater than 1 and 4 or less. Preferably it is.
  • the potential difference between the data bus line 22 and the reference voltage bus line 18 in the first sub-pixel 111 (small sub-pixel region) having a small area is made larger than the potential difference in the second sub-pixel 112 (large sub-pixel region) having a large area. Since the voltage is increased, the voltage applied to the liquid crystal layer of the first subpixel 111 exceeds the liquid crystal threshold earlier than the liquid crystal layer of the second subpixel 112. That is, when the voltage applied to the liquid crystal layer of the first subpixel 111 exceeds the threshold value of the liquid crystal, the voltage applied to the liquid crystal layer of the second subpixel 112 does not exceed the threshold value of the liquid crystal.
  • the first sub-pixel 111 starts to display first from the color of the low gradation region, reaches a higher luminance than the second sub-pixel 112,
  • the second sub-pixel 112 emits light so as to supplement the light emission amount from the halftone area to the high gradation area. That is, the first sub-pixel 111 having a small area mainly contributes to display from a low gradation to a halftone, while the second sub-pixel 112 having a large area mainly contributes to display from a half-tone to a high gradation. This makes it easy to control the viewing angle characteristic to a desired characteristic.
  • the low gradation region is more reduced when the low gradation region is the first sub-pixel 111 having a smaller area.
  • the viewing angle characteristic can be further improved as compared with the second sub-pixel 112 having a large area.
  • the gate bus line 16 is formed in a meandering shape as shown in FIG. Accordingly, two first pixel electrodes 141 and second pixel electrodes 142 having different areas can be provided side by side in the column direction without creating a dead space in one pixel 110.
  • the meandering center line is a bisector that divides the pixel 110 into two equal-area regions arranged in the column direction.
  • the gate bus line 16 is displaced from the center line with respect to the column direction, the two areas having the same area arranged in the column direction naturally have different areas.
  • a pixel electrode having a small area is formed by simply reducing one of the pixel electrodes in two regions having the same area without causing the gate bus line 16 to meander. There was a dead space in the pixel.
  • the area of the sub-pixel itself is made different by meandering the gate bus line 16, so that the first area 110 has a small area without causing unnecessary dead space.
  • One pixel electrode 141 and a second pixel electrode 142 having a large area can be formed in one pixel 110.
  • the counter matrix type liquid crystal panel 1 having a configuration in which two sub-pixels are vertically arranged in one pixel region, a multi-pixel structure that does not cause useless space can be obtained, and viewing angle characteristics can be improved.
  • each pixel 110 is not limited to a configuration including two sub-pixels arranged in the column direction.
  • two sets of two sub-pixels arranged in the column direction are provided, and four sub-pixels are provided in one pixel region. Also good.
  • the meandering center line is more preferably a bisector that divides each pixel 110mn into two regions arranged with the same width in the column direction. Accordingly, it is possible to select a configuration in which the width of the meander from the bisector when the gate bus line 16 meanders along the row direction can be selected, and thereby the second pixel electrode 142 having a large area, the area The small first pixel electrodes 141 can be arranged along the row direction at a constant area ratio.
  • first TFT 121 and the second TFT 122 are alternately provided for each bent portion of the gate bus line 16 formed in a meandering shape. Thereby, the layout of the arrangement of the first TFT 121 and the second TFT 122 can be simplified.
  • FIG. 4A is a diagram showing an equivalent circuit of the TFT substrate 10 of the liquid crystal panel 1 according to the present embodiment and a voltage applied to the liquid crystal capacitor during x-frame display.
  • FIG. 4B is a diagram showing an equivalent circuit of the TFT substrate 10 of the liquid crystal panel 1 according to the present embodiment, and a voltage applied to the liquid crystal capacitor during x + 1 frame display.
  • FIG. 5 is a diagram showing an equivalent circuit of the TFT substrate 10 when the first liquid crystal capacitor 131 and the second liquid crystal capacitor 132 shown in FIGS. 4A and 4B are represented as the first capacitor 151 and the second capacitor 152.
  • the liquid crystal panel 1 includes a pixel 110mn (first pixel region) defined by the data bus line 22m and the gate bus line 16n, a data bus line 22 (m + 1), and the like.
  • the pixels 110mn to 110 (m + 2) n and the pixels 110m (n + 1) to 110 (m + 2) (n + 1) are arranged adjacent to each other in the row direction, and the pixel 110mn, the pixel 110m (n + 1), and the pixel 110 (m + 1) n
  • the pixels 110 (m + 1) (n + 1) and the like are arranged adjacent to each other in the column direction.
  • the pixel 110mn includes two subpixels in the order of the second subpixel 112mn (first subpixel area) and the first subpixel 111mn (second subpixel area) in the column direction from the reference voltage bus line 18a.
  • the pixel 110 (m + 1) n includes two subpixels in the column direction from the reference voltage bus line 18a in the order of the first subpixel 111 (m + 1) n and the second subpixel 112 (m + 1) n. Yes.
  • the pixel 110m (n + 1) includes two subpixels in the column direction from the reference voltage bus line 18b, the first subpixel 111m (n + 1) (third subpixel region) and the second subpixel 112m (n + 1).
  • the pixel 110 (m + 1) (n + 1) includes two subpixels in the column direction from the reference voltage bus line 18b in the order of (fourth subpixel region), and the second subpixel 112 (m + 1) (n + 1) , First sub-pixels 111 (m + 1) (n + 1) in this order. That is, the pixel 110m (n + 1) and the pixel 110 (m + 1) (n + 1) are arranged to be line-symmetric with the pixel 110mn and the pixel 110 (m + 1) n with respect to the reference voltage bus line 18b.
  • the second subpixel 112mn as the first subpixel region in which the pixels 110mn are arranged in the column direction
  • the second subpixel region The first sub-pixel 111m and the second sub-pixel 112m as the fourth sub-pixel region and the first sub-pixel 111m (n + 1) as the third sub-pixel region in which the pixels 110m (n + 1) are arranged in the column direction.
  • N + 1) and the reference voltage bus line 18b is shared by the first sub-pixel 111mn and the first sub-pixel 111m (n + 1) that are adjacent to each other in the column direction.
  • the pixel 110 (m + 2) n has the same configuration as the pixel 110mn
  • the pixel 110 (m + 2) (n + 1) has the same configuration as the pixel 110m (n + 1).
  • each subpixel includes a TFT 12 and a liquid crystal capacitor.
  • the liquid crystal capacitor includes a pixel electrode 14, a counter electrode 24 formed by the data bus line 22, and a liquid crystal layer sandwiched between the pixel electrode 14 and the counter electrode 24.
  • the liquid crystal capacitors include a first liquid crystal capacitor 131mn and a second liquid crystal capacitor 132mn. As shown in FIG. 5, the first liquid crystal capacitor 131mn and the second liquid crystal capacitor 132mn can be expressed as a first capacitor 151mn and a second capacitor 152mn in an equivalent circuit.
  • the gate terminal of the first TFT 121mn included in the first sub-pixel 111mn of the pixel 110mn is connected to the gate bus line 16n, the source terminal is connected to the reference voltage bus line 18b, and the drain terminal is connected to the first terminal.
  • One liquid crystal capacitor 131mn is connected to the data bus line 22m.
  • the gate terminal of the second TFT 122mn included in the second subpixel 112mn is connected to the gate bus line 16n, the source terminal is connected to the reference voltage bus line 18a, and the drain terminal is connected to the data bus line 22m via the second liquid crystal capacitor 132mn. It is connected to the.
  • the gate terminal of the first TFT 121 (m + 1) n included in the first sub-pixel 111 (m + 1) n of the pixel 110 (m + 1) n is connected to the gate bus line 16n, the source terminal is connected to the reference voltage bus line 18a, and the drain terminal. Is connected to the data bus line 22 (m + 1) through the first liquid crystal capacitor 131 (m + 1) n.
  • the second TFT 122 (m + 1) n included in the second subpixel 112 (m + 1) n has a gate terminal connected to the gate bus line 16n, a source terminal connected to the reference voltage bus line 18b, and a drain terminal connected to the second liquid crystal capacitor. It is connected to the data bus line 22 (m + 1) through 132 (m + 1) n.
  • the first sub-pixel 111 (m + 2) n and the second sub-pixel 112 (m + 2) n of the pixel 110 (m + 2) n have the drain terminals of the first TFT 121 (m + 2) n and the second TFT 122 (m + 2) n as the first. Except for being connected to the data bus line 22 (m + 2) via the liquid crystal capacitor 131 (m + 2) n and the second liquid crystal capacitor 132 (m + 2) n, it has the same configuration as the first sub-pixel 111mn and the second sub-pixel 112mn. is there.
  • the pixel 110mn corresponds to red
  • the pixel 110 (m + 1) n corresponds to green
  • the pixel 110 (m + 2) n becomes blue.
  • the present invention is not limited to this.
  • FIG. FIG. 6 is a timing chart showing the operation of the liquid crystal panel 1 according to the present embodiment.
  • the operation of the first sub pixel 111mn shown in FIG. 4A when displaying the xth frame (x frame) will be described as an example.
  • the reference voltage of the reference voltage bus line 18a that was controlled to the L level when the x-1 frame was displayed is controlled to the H level.
  • the reference voltage of the reference voltage bus line 18b that has been controlled to the H level when the x-1 frame is displayed is controlled to the L level.
  • the first gate bus line 16 is scanned.
  • the H level reference voltage is set to +1 V and the L level reference voltage is set to 0 V.
  • the present invention is not limited to this.
  • a scanning signal is supplied to the gate terminals of the first TFT 121mn and the second TFT 122mn, and the first TFT 121mn and the second TFT 122mn. Turns on. Similarly, a scanning signal is also supplied to the gate terminals of the first TFT 121 (m + 1) n, the second TFT 122 (m + 1) n, the first TFT 121 (m + 2) n, and the second TFT 122 (m + 2) n, and is turned on.
  • the first liquid crystal capacitor 131mn is applied with a potential difference nodeX ⁇ nodeY between nodeX and nodeY of the first liquid crystal capacitor 131mn, that is, + 5V that is a potential difference between the counter electrode and the pixel electrode. Will be.
  • + 5V is applied to nodeX of the second liquid crystal capacitor 132mn of the pixel 110mn, and + 1V of the same voltage as that of the reference voltage bus line 18a is applied to nodeY.
  • +4 V which is the potential difference between nodeX and nodeY of the second liquid crystal capacitor 132mn, is applied to the second liquid crystal capacitor 132mn.
  • + 4V which is the same voltage as the data bus line 22m
  • 0V of the same voltage as that of the reference voltage bus line 18b is applied to nodeY of the first liquid crystal capacitor 131m (n + 1).
  • + 4V which is a potential difference nodeX ⁇ nodeY between nodeX and nodeY is applied to the first liquid crystal capacitor 131m (n + 1).
  • + 4V is applied to nodeX of the second liquid crystal capacitor 132m (n + 1), and + 1V of the same voltage as the reference voltage bus line 18a is applied to nodeY. Is done.
  • +3 V which is a potential difference between nodeX and nodeY, is applied to the second liquid crystal capacitor 132m (n + 1).
  • the voltage of the first liquid crystal capacitor 131mn does not change, and the voltage applied at time txn is maintained. That is, the voltage applied to the first liquid crystal capacitor 131mn when the gate bus line 16n is scanned to display the x frame until the gate bus line 16n is scanned again to display the x + 1 frame. Will be maintained.
  • the second liquid crystal capacitor 132mn the first liquid crystal capacitor 131 (m + 1) n, the second liquid crystal capacitor 132 (m + 1) n, the first liquid crystal capacitor 131 (m + 2) n, and the second liquid crystal capacitor 132 (m + 2) n.
  • the voltage applied at time txn is maintained.
  • a scanning signal is supplied to the gate terminals of the first TFT 121mn and the second TFT 122mn, The first TFT 121mn and the second TFT 122mn are turned on. Similarly, a scanning signal is also supplied to the gate terminals of the first TFT 121 (m + 1) n, the second TFT 122 (m + 1) n, the first TFT 121 (m + 2) n, and the second TFT 122 (m + 2) n, and is turned on.
  • ⁇ 4V is applied to the node X of the second liquid crystal capacitor 132mn of the pixel 110mn, and 0V of the same voltage as the reference voltage bus line 18a is applied to the node Y. Applied. As a result, ⁇ 4V that is a potential difference between nodeX and nodeY of the second liquid crystal capacitor 132mn is applied to the second liquid crystal capacitor 132mn.
  • the first liquid crystal capacitor 131 (m + 1) (n + 1) of the pixel 110 (m + 1) (n + 1) has + 4V.
  • the second liquid crystal capacitance 132 (m + 1) (n + 1) becomes + 3V.
  • the data bus line 22 (m + 2) is controlled to ⁇ 3V
  • the first liquid crystal capacitor 131 (m + 2) (n + 1) of the pixel 110 (m + 2) (n + 1) becomes ⁇ 4V
  • the second liquid crystal capacitor 132 ( m + 2) (n + 1) becomes ⁇ 3V.
  • the voltage of the first liquid crystal capacitor 131mn does not change, and the voltage applied at time t (x + 1) n is maintained. That is, the voltage applied to the first liquid crystal capacitor 131mn when the gate bus line 16n is scanned to display the x + 1 frame until the gate bus line 16n is scanned again to display the x + 1 frame. Will be maintained.
  • the driving method of the liquid crystal panel 1 is the driving method in the liquid crystal panel 1 having the configuration described based on FIGS. 4A, 4B, and 6, and is the first that is arranged in the column direction.
  • the data bus The potential difference between the line 22m and the reference voltage bus line 18a is different from the potential difference between the data bus line 22m and the reference voltage bus line 18b.
  • a potential difference between the data bus line 22m and the reference voltage bus line 18a is applied to the liquid crystal layer of one pixel, while the data bus line 22m and the reference voltage bus line are applied to the liquid crystal layer of the other sub-pixel.
  • a potential difference from 18b is applied.
  • the voltage applied to the liquid crystal layer of the first sub-pixel 111 mn can be made different from the voltage applied to the liquid crystal layer of the second sub-pixel 112 mn.
  • the alignment state of the liquid crystal molecules in the first sub pixel 111mn and the alignment state of the liquid crystal molecules in the second sub pixel 112mn can be made different from each other with respect to the voltage written to the data bus line 22m.
  • the viewing angle characteristics of the liquid crystal panel 1 can be improved.
  • the areas of the two sub-pixel regions are different by making the gate bus line meandering.
  • the area of one subpixel area of two subpixel areas corresponding to a certain data bus line is smaller than the area of the other subpixel area, it corresponds to the data bus line adjacent to the data bus line.
  • the area of one of the two subpixel areas is larger than the area of the other subpixel area.
  • FIG. 8 is a top view schematically showing the configuration of the TFT substrate 10 of the liquid crystal panel 2 according to this embodiment. As shown in FIG. 8, the interval between the gate bus lines 16 ′ is narrow, the width of the data bus line 22 ′ is different, and the reference voltage bus line 18 ′ (not shown) is arranged to intersect the gate bus line 16 ′. Except for this, the configuration is the same as that of the liquid crystal panel 1 of the first embodiment.
  • FIG. 9 is a top view showing a layout of the TFT substrate 10 of the liquid crystal panel 2 according to the present embodiment.
  • FIG. 9 of the total number M of data bus lines 22 ′ formed on the counter substrate 20, data bus lines 22m ′ to 22 (m + 4) ′ arranged near the m-th data bus line 22m ′. Is indicated by a broken line.
  • the liquid crystal panel 2 includes an nth gate bus line 16n ′, an mth data bus line 22m ′, and an m + 1th data bus line 22 out of a total of N gate bus lines 16 ′.
  • the pixel 210mn defined by (m + 1) ′.
  • the pixel 210mn includes a first sub-pixel 211mn and a second sub-pixel 212 (m + 1) n.
  • the first subpixel 211mn includes a first pixel electrode 241mn and a first TFT 221mn.
  • the second sub pixel 212 (m + 1) n includes a second pixel electrode 242 (m + 1) n and a second TFT 222 (m + 1) n. Further, as shown in FIG. 9, in the area of one pixel 210, the first sub-pixel 211 and the second sub-pixel 212 are arranged in the row direction.
  • the TFT substrate 10 of the liquid crystal panel 1 in this embodiment is configured such that the area ratio of the second subpixel 212 to the first subpixel 211 is greater than 1 and 4 or less. Preferably it is.
  • the potential difference between the data bus line 22 ′ and the reference voltage bus line 18 ′ in the first sub-pixel 211 having a small area is made larger than the potential difference in the second sub-pixel 212 having a large area.
  • the voltage applied to the liquid crystal layer exceeds the threshold value of the liquid crystal earlier than the liquid crystal layer of the second subpixel 212. In other words, when the voltage applied to the liquid crystal layer of the first sub-pixel 211 exceeds the threshold value of the liquid crystal, the voltage applied to the liquid crystal layer of the second sub-pixel 212 does not exceed the threshold value of the liquid crystal.
  • the first sub-pixel 211 starts to display the color of the low gradation region first, reaches a higher luminance than the second sub-pixel 212,
  • the second sub-pixel 212 emits light so as to compensate for the amount of light emission from the halftone area to the high gradation area. That is, the first sub-pixel 211 having a small area mainly contributes to display from a low gradation to a halftone, while the second sub-pixel 212 having a large area mainly contributes to display from a halftone to a high gradation. This makes it easy to control the viewing angle characteristic to a desired characteristic.
  • the low gradation region is less affected when the low gradation region is the first sub-pixel 211 having a smaller area.
  • the viewing angle characteristics can be further improved as compared with the second sub-pixel 212 having a large area.
  • the data bus line 22 ′ is provided in each of the first sub-pixel 211 and the second sub-pixel 212, the two sub-pixels 211 and 212 included in one pixel 210 have an arbitrary polarity and an arbitrary value. Can be applied.
  • the counter matrix type liquid crystal panel 2 having a configuration in which two sub-pixels 211 and 212 are arranged side by side in one pixel 210, a multi-pixel structure that does not cause useless space is obtained, and viewing angle characteristics are improved. Can do.
  • each pixel 210 is not limited to the configuration including the two sub-pixels 211 and 212 arranged in the row direction, and for example, four sub-pixels may be provided in one pixel region.
  • FIG. 10A is a diagram showing an equivalent circuit of the TFT substrate 10 of the liquid crystal panel 2 according to the present embodiment and a voltage applied to the liquid crystal capacitor during x-frame display.
  • FIG. 10B is a diagram showing an equivalent circuit of the TFT substrate 10 of the liquid crystal panel 2 according to the present embodiment and a voltage applied to the liquid crystal capacitor during x + 1 frame display.
  • the liquid crystal panel 2 in this embodiment is defined by a data bus line 22 (m + i) ′, a data bus line 22 (m + i + 1) ′, and a gate bus line 16 (n + j) ′.
  • Pixel 210 (m + i) (n + j) is provided.
  • i is 0 and a natural number that satisfies m ⁇ i
  • j is 0 and a natural number that satisfies n ⁇ j.
  • Each pixel includes two sub-pixels.
  • the pixel 210 (m + i) (n + j) and the pixel 210 (m + i + 1) (n + j) are arranged adjacent to each other in the row direction, and the pixel 210 (m + i) (n + j) and the pixel 210 (m + i) (n + j + 1) are adjacent to each other in the column direction. Are arranged.
  • the pixel 210 (m + i) (n + j) includes two sub-pixels in the order of the first sub-pixel and the second sub-pixel in the row direction.
  • each subpixel includes a TFT 12 and a liquid crystal capacitor.
  • the liquid crystal capacitance is constituted by the pixel electrode 14, the counter electrode 24 formed by the data bus line 22 ′, and a liquid crystal layer sandwiched between the pixel electrode 14 and the counter electrode 24.
  • the liquid crystal capacitance of the pixel 210 (m + i) (n + j) illustrated in FIGS. 10A and 10B includes a first liquid crystal capacitance 231mn and a second liquid crystal capacitance 232 (m + 1) n.
  • the gate terminal of the first TFT 221mn included in the first sub-pixel 211mn of the pixel 210mn is connected to the gate bus line 16n ′, the source terminal is connected to the reference voltage bus line 18a ′, and the drain terminal is It is connected to the data bus line 22m ′ via the first liquid crystal capacitor 231mn.
  • the gate terminal of the second TFT 222 (m + 1) n included in the second subpixel 212 (m + 1) n is connected to the gate bus line 16n ′, the source terminal is connected to the reference voltage bus line 18b ′, and the drain terminal is the second terminal.
  • the liquid crystal capacitor 232 (m + 1) n is connected to the data bus line 22 (m + 1) ′.
  • the gate terminal of the first TFT 221 (m + 2) n included in the first sub-pixel 211 (m + 2) n of the pixel 210 (m + 2) n is connected to the gate bus line 16n ′, the source terminal is connected to the reference voltage bus line 18a ′, The drain terminal is connected to the data bus line 22 (m + 2) ′ via the first liquid crystal capacitor 231 (m + 2) n.
  • the gate terminal of the second TFT 222 (m + 3) n included in the second subpixel 212 (m + 3) n is connected to the gate bus line 16n ′, the source terminal is connected to the reference voltage bus line 18b ′, and the drain terminal is the second.
  • the liquid crystal capacitor 232 (m + 3) n is connected to the data bus line 22 (m + 3) ′.
  • the first TFT 221 (m + i) (n + j) included in the first subpixel 211 (m + i) (n + j) of the pixel 210 (m + i) (n + j) has a gate terminal connected to the gate bus line 16 (n + j) ′ and a drain. The terminal is connected to the data bus line 22 (m + i) ′ via the first liquid crystal capacitor 231 (m + i) (n + j).
  • the gate terminal of the second TFT 222 (m + i + 1) (n + j) is connected to the gate bus line 16 (n + j) ′, and the drain terminal is the second liquid crystal capacitor 232 (m + i + 1). It is connected to the data bus line 22 (m + i + 1) ′ via (n + j).
  • the reference voltage bus line 18b ′ is shared by, for example, the second sub-pixel 212 (m + 1) n of the pixel 210mn and the first sub-pixel 211 (m + 2) n of the pixel 210 (m + 2) n. .
  • the wiring layout can be simplified.
  • the pixel 210mn corresponds to red
  • the pixel 210m (n + 1) corresponds to green
  • the pixel 210m (n + 2) corresponds to blue.
  • the present invention is not limited to this.
  • FIG. 11 is a timing chart showing the operation of the liquid crystal panel 2 according to the present embodiment.
  • the operation of the first sub-pixel 211mn shown in FIG. 10 when displaying the x frame will be described as an example.
  • the voltages of the reference voltage bus lines 18a ′ and 18b ′ are always constant, and are constant at 0V when displaying either the x frame or the x + 1 frame.
  • a scanning signal is supplied to the gate terminals of the first TFT 221mn and the second TFT 222 (m + 1) n.
  • the first TFT 221mn and the second TFT 222 (m + 1) n are turned on.
  • a scanning signal is also supplied to the gate terminals of the first TFT 221 (m + 2) n and the second TFT 222 (m + 3) n, and is turned on.
  • + 5V of the same voltage as the data bus line 22m' is applied to the nodeX of the first liquid crystal capacitor 231mn of the pixel 210mn.
  • 0V of the same voltage as that of the reference voltage bus line 18a ' is applied to nodeY of the first liquid crystal capacitor 231mn.
  • + 5V that is a potential difference nodeX ⁇ nodeY between nodeX and nodeY of the first liquid crystal capacitor 231mn is applied to the first liquid crystal capacitor 231mn.
  • + 4V is applied to nodeX of the second liquid crystal capacitor 232 (m + 1) n of the pixel 210mn, and nodeY is the same as the reference voltage bus line 18b ′.
  • a voltage of 0V is applied.
  • + 4V which is the potential difference between nodeX and nodeY of the second liquid crystal capacitor 232 (m + 1) n, is applied to the second liquid crystal capacitor 232 (m + 1) n.
  • the voltage of the first liquid crystal capacitor 231mn does not change, and the voltage applied at time txn is maintained. That is, the voltage applied to the first liquid crystal capacitor 231mn by scanning the gate bus line 16n ′ to display the x frame causes the gate bus line 16n ′ to be scanned again to display the x + 1 frame. Until it will be maintained.
  • the voltage applied to the second liquid crystal capacitor 232 (m + 1) n, the first liquid crystal capacitor 231 (m + 2) n, and the second liquid crystal capacitor 232 (m + 3) n is also applied at time txn at time tx (n + 1). Is maintained.
  • the scanning signal is applied to the gate terminals of the first TFT 221mn, the second TFT 222 (m + 1) n, the first TFT 221 (m + 2) n, and the second TFT 222 (m + 3) n. Is supplied and turned ON.
  • the data bus line 22m ′ is controlled to ⁇ 5V, 22 (m + 2) ′ to + 5V, the data bus line 22 (m + 1) ′ is controlled to ⁇ 4V, and 22 (m + 3) ′ to + 4V, FIG.
  • the applied voltage of the first liquid crystal capacitor 231mn is ⁇ 5V
  • the applied voltage of the first liquid crystal capacitor 231 (m + 2) n is + 5V
  • the applied voltage of the second liquid crystal capacitor 232 (m + 1) n is ⁇ 4V.
  • the applied voltage of the second liquid crystal capacitor 232 (m + 3) n is + 4V.
  • the scanning signal is supplied to the gate terminals of the first TFT 221 (m + 2) (n + 1), and the second TFT 222 (m + 3) (n + 1), and is turned on.
  • the data bus line 22m ′ is controlled to ⁇ 4V, 22 (m + 2) ′ to + 4V, the data bus line 22 (m + 1) ′ is ⁇ 3V, and 22 (m + 3) ′ is + 3V.
  • the applied voltage of the first liquid crystal capacitor 231m (n + 1) becomes ⁇ 4V
  • the applied voltage of the first liquid crystal capacitor 231 (m + 2) (n + 1) becomes + 4V
  • the second The applied voltage of the liquid crystal capacitor 232 (m + 1) (n + 1) is ⁇ 3V
  • the applied voltage of the second liquid crystal capacitor 232 (m + 3) (n + 1) is + 3V.
  • the data bus line 22m ′ is controlled to ⁇ 3V, 22 (m + 2) ′ to + 3V, the data bus line 22 (m + 2) ′ is controlled to ⁇ 2V, and 22 (m + 3) ′ to + 2V, as shown in FIG. 10B.
  • the applied voltage of the first liquid crystal capacitor 231m (n + 2) is ⁇ 3V
  • the applied voltage of the first liquid crystal capacitor 231 (m + 2) (n + 2) is + 3V
  • the second liquid crystal capacitor 232 (m + 1) (n + 2) is applied.
  • the voltage is -2V
  • the voltage applied to the second liquid crystal capacitor 232 (m + 3) (n + 2) is + 2V.
  • the driving method of the liquid crystal panel 2 is a driving method in the liquid crystal panel having the configuration described based on FIG. 9, FIG. 10A, and FIG.
  • a reference voltage bus line 18a ′ corresponding to the first sub-pixel 211mn and a reference voltage bus line 18b ′ corresponding to the second sub-pixel 212 (m + 1) n are applied to the data bus line 22m ′ corresponding to the first sub-pixel 211mn and applied to the data bus line 22 (m + 1) ′ corresponding to the second sub-pixel 212 (m + 1) n.
  • the potential difference between the data bus line 22m ′ and the reference voltage bus line 18a ′ can be reduced. 22 and (m + 1) 'and the reference voltage bus line 18b' is different from the potential difference between.
  • a potential difference between the data bus line 22m ′ and the reference voltage bus line 18a ′ is applied to the liquid crystal layer of the first subpixel 211mn, while the liquid crystal layer of the second subpixel 212 (m + 1) n is applied to the liquid crystal layer of the first subpixel 211mn.
  • a potential difference between the data bus line 22 (m + 1) ′ and the reference voltage bus line 18b ′ is applied.
  • the voltage applied to the reference voltage bus line 18a ′ and the voltage applied to the reference voltage bus line 18b ′ are the same, and are applied to the data bus line 22m ′ and the data bus line 22 (m + 1) ′. Since the voltages are different, the voltage applied to the liquid crystal layer of the first sub-pixel 211mn and the voltage applied to the liquid crystal layer of the second sub-pixel 212 (m + 1) n can be made different.
  • the voltages applied to the data bus lines 22m ′ and 22 (m + 1) ′ are the liquid crystal molecule alignment state in the first sub-pixel 211mn and the liquid crystal molecule alignment state in the second sub-pixel 212 (m + 1) n.
  • the viewing angle characteristics in the counter matrix type liquid crystal panel can be improved.
  • the burn-in of the liquid crystal panel 2 can be reduced by performing the driving with the polarity reversed for each pixel arranged in the column direction.
  • FIG. 12 is a top view showing a layout of the TFT substrate 10 of the liquid crystal panel 3 according to the present embodiment.
  • FIG. 12 of the total number M of data bus lines 22 ′′ formed on the counter substrate 20, data bus lines 22m ′′ to 22 (m + 4) ′′ arranged in the vicinity of the mth data bus line 22m ′′. Is indicated by a broken line.
  • the liquid crystal panel 3 includes a pixel 310mn defined by an nth gate bus line 16n ′′ and an mth data bus line 22m ′′ among a total of N gate bus lines 16 ′′.
  • the pixel 310mn includes a first sub pixel 311mn and a second sub pixel 312mn.
  • the first subpixel 311mn includes a first pixel electrode 341mn and a first TFT 321mn.
  • the second subpixel 312mn includes a second pixel electrode 342mn and a second TFT 322mn. Also, as shown in FIG. 12, in the area of one pixel 310, the first sub-pixel 311 and the second sub-pixel 312 are arranged in the row direction.
  • a pixel electrode having a large area and a pixel electrode having a small area can be arranged in the row direction and formed in one pixel 310 without causing unnecessary dead space in one pixel 310.
  • the data bus line 22 ′′ is provided in common for the first sub-pixel 311 and the second sub-pixel 312, the voltage applied to the reference voltage bus line 18 ′′ provided for each sub-pixel is changed for each sub-pixel.
  • the potential difference between the data bus line 22 ′′ and the reference voltage bus line 18 ′′ can be changed for each sub-pixel.
  • a counter matrix type liquid crystal panel having a configuration in which two sub-pixels 311 and 312 are arranged side by side in one pixel 310, a multi-pixel structure that does not cause useless space can be obtained, and viewing angle characteristics can be improved. it can.
  • each pixel 310 is not limited to the configuration including the two sub-pixels 311 and 312 arranged in the row direction, and for example, a configuration in which four sub-pixels are provided in one pixel region may be employed.
  • the TFT substrate 10 of the liquid crystal panel 3 in this embodiment is configured such that the area ratio of the second subpixel 312 to the first subpixel 311 is greater than 1 and 4 or less. Preferably it is.
  • the potential difference between the data bus line 22 ′′ and the reference voltage bus line 18 ′′ in the first sub-pixel 311 having a small area is made larger than the potential difference in the second sub-pixel 312 having a large area.
  • the voltage applied to the liquid crystal layer exceeds the liquid crystal threshold earlier than the liquid crystal layer of the second subpixel 312. That is, when the voltage applied to the liquid crystal layer of the first sub-pixel 311 exceeds the threshold value of the liquid crystal, the voltage applied to the liquid crystal layer of the second sub-pixel 312 does not exceed the threshold value of the liquid crystal.
  • the first sub-pixel 311 starts to display the color of the low gradation region first, reaches a higher luminance than the second sub-pixel 312,
  • the second sub-pixel 312 emits light so as to compensate for the light emission amount from the halftone area to the high gradation area. That is, the first sub-pixel 311 having a small area mainly contributes to display from a low gradation to a halftone, while the second sub-pixel 312 having a large area mainly contributes to display from a half-tone to a high gradation. This makes it easy to control the viewing angle characteristic to a desired characteristic.
  • the low gradation region is more reduced when the low gradation region is the first sub-pixel 311 having a smaller area.
  • the viewing angle characteristic can be further improved as compared with the second sub-pixel 312 having a large area.
  • FIG. 13 is a diagram showing an equivalent circuit of the TFT substrate 10 of the liquid crystal panel 3 according to the present embodiment, and a voltage applied to the liquid crystal capacitor during x frame display.
  • the liquid crystal panel 3 in this embodiment includes pixels 210 (m + p) (n + q) defined by data bus lines 22 (m + p) ′′ and gate bus lines 16 (n + q) ′′.
  • p is 0 and a natural number satisfying m ⁇ p
  • q is 0 and a natural number satisfying n ⁇ q.
  • Each pixel includes two sub-pixels.
  • the pixel 310 (m + p) (n + q) and the pixel 310 (m + p + 1) (n + q) are arranged adjacent to each other in the row direction, and the pixel 310 (m + p) (n + q) and the pixel 310 (m + p) (n + q + 1) are adjacent to each other in the column direction. Are arranged.
  • the pixel 310 (m + p) (n + q) includes two subpixels in the row direction in the order of the first subpixel and the second subpixel.
  • the pixel 310mn and the pixel 310 (m + 1) n, the pixel 310m (n + 1), the pixel 310 (m + 1) (n + 1), the pixel 310m (n + 2), and the pixel 310 (m + 1) (n + 2) are arranged adjacent to each other in the row direction.
  • the pixels 310mn to 310m (n + 2) and the pixels 310 (m + 1) n to 310 (m + 1) (n + 2) are arranged adjacent to each other in the column direction.
  • Each pixel 310 includes two subpixels in the order of the first subpixel and the second subpixel in the row direction.
  • each subpixel includes a TFT 12 and a liquid crystal capacitor.
  • the liquid crystal capacitance includes a pixel electrode 14, a counter electrode 24 formed by the data bus line 22 ′′, and a liquid crystal layer sandwiched between the pixel electrode 14 and the counter electrode 24.
  • the liquid crystal capacitor provided in the pixel 310mn includes a first liquid crystal capacitor 331mn and a second liquid crystal capacitor 332mn.
  • the gate terminal of the first TFT 321mn included in the first sub-pixel 311mn of the pixel 310mn is connected to the gate bus line 16n ", the source terminal is connected to the reference voltage bus line 18a", and the drain terminal is The first liquid crystal capacitor 331 mn is connected to the data bus line 22 m ′′.
  • the gate terminal of the second TFT 322mn included in the second subpixel 312mn is connected to the gate bus line 16n ", the source terminal is connected to the reference voltage bus line 18b", and the drain terminal is connected to the data bus via the second liquid crystal capacitor 332mn. Connected to line 22m ".
  • the gate terminal of the first TFT 321 (m + 1) n included in the first sub-pixel 311 (m + 1) n of the pixel 310 (m + 1) n is connected to the gate bus line 16n ′′, and the source terminal is connected to the reference voltage bus line 18a ′′.
  • the drain terminal is connected to the data bus line 22m ′′ via the first liquid crystal capacitor 331 (m + 1) n.
  • the gate terminal of the second TFT 322 (m + 1) n included in the second subpixel 312 (m + 1) n is connected to the gate bus line 16n ′′, the source terminal is connected to the reference voltage bus line 18b ′′, and the drain terminal is the second terminal. It is connected to the data bus line 22 (m + 1) ′′ via the liquid crystal capacitor 332 (m + 1) n.
  • the gate terminal is connected to the gate bus line 16 (n + q) ′′ and the source terminal Is connected to the reference voltage bus line 18a ′′, and the drain terminal is connected to the data bus line 22 (m + p) ′′ via the first liquid crystal capacitor 331 (m + p) (n + q).
  • the second sub-pixel 312 In (m + p) (n + q)
  • the gate terminal of the second TFT 322 (m + p) (n + q) is connected to the gate bus line 16 (n + q) ′′
  • the source terminal is connected to the reference voltage bus line 18b ′′
  • the drain terminal is the second liquid crystal.
  • the capacitor is connected to the data bus line 22 (m + p) ′′ via a capacitor 232 (m + p) (n + q).
  • the pixel 310mn corresponds to red
  • the pixel 310m (n + 1) corresponds to green
  • the pixel 310m (n + 2) corresponds to blue.
  • the present invention is not limited to this.
  • FIG. 14 is a timing chart showing the operation of the liquid crystal panel 3 according to the present embodiment.
  • the operation of the first sub-pixel 311mn shown in FIG. 13 when displaying the x frame will be described as an example.
  • a scanning signal is supplied to the gate terminals of the first TFT 321mn and the second TFT 322mn, and the first TFT 321mn and The second TFT 322mn is turned on.
  • a scanning signal is also supplied to the gate terminals of the first TFT 321 (m + 1) n and the second TFT 322 (m + 2) n, which are turned on.
  • the first liquid crystal capacitor 331mn has a first liquid crystal capacitor. A potential difference nodeX ⁇ nodeY of + 5V between nodeX and nodeY of 331 mn is applied.
  • the voltage applied to the first liquid crystal capacitor 331 (m + 1) n of the pixel 310 (m + 1) n is the reference voltage bus line 18b ′′. Is ⁇ 5V, and the voltage applied to the second liquid crystal capacitor 332 (m + 1) n is ⁇ 4V, which is the potential difference from the reference voltage bus line 18a ′′.
  • the voltage of the first liquid crystal capacitor 331mn does not change, and the voltage applied at time txn is maintained. That is, when the gate bus line 16n ′′ is scanned to display the x frame, the voltage applied to the first liquid crystal capacitor 331mn is scanned again to display the x + 1 frame. Until it will be maintained.
  • the second liquid crystal capacitor 332mn, the first liquid crystal capacitor 331 (m + 1) n, and the second liquid crystal capacitor 332 (m + 1) n are also maintained at the time txn at time tx (n + 1). .
  • a scanning signal is supplied to the gate terminal of the first TFT 321mn, and is turned on.
  • the second TFT 322mn, the first TFT 321 (m + 1) n, and The scanning signal is also supplied to the gate terminal of the second TFT 322 (m + 1) n, and the second TFT 322 (m + 1) n is turned on.
  • the voltage of the first liquid crystal capacitor 331mn does not change, and the voltage applied at time txn is maintained. That is, when the gate bus line 16n ′′ is scanned to display the x frame, the voltage applied to the first liquid crystal capacitor 331mn is scanned again to display the x + 1 frame. Until it will be maintained.
  • the second liquid crystal capacitor 332mn, the first liquid crystal capacitor 331 (m + 1) n, and the second liquid crystal capacitor 332 (m + 1) n are also maintained at the time txn at time tx (n + 1). .
  • the driving method of the liquid crystal panel 3 is a driving method in the liquid crystal panel having the configuration described with reference to FIGS. 13 and 14, and at least the first sub-pixels arranged in the row direction.
  • the voltages applied to the reference voltage bus line 18a “corresponding to the first sub pixel 311mn and the reference voltage bus line 18b" corresponding to the second sub pixel 312mn differ between the 311mn and the second sub pixel 312mn.
  • the potential difference between the data bus line 22m ′′ and the reference voltage bus line 18a ′′ is different from the potential difference between the data bus line 22m ′′ and the reference voltage bus line 18b ′′.
  • a potential difference between the data bus line 22m ′′ and the reference voltage bus line 18a ′′ is applied to the liquid crystal layer of the first sub-pixel 311mn, while the data bus line 22m is applied to the liquid crystal layer of the second sub-pixel 312mn.
  • the potential difference between “and the reference voltage bus line 18b” is applied.
  • the voltage applied to the liquid crystal layer of the first sub-pixel 311mn and the voltage applied to the liquid crystal layer of the second sub-pixel 312mn can be made different.
  • the alignment state of the liquid crystal molecules in the first sub-pixel 311 mn can be made different from the alignment state of the liquid crystal molecules in the second sub-pixel 312 mn with respect to the voltage written to the data bus line 22 m ′′. Viewing angle characteristics in a matrix type liquid crystal panel can be improved.
  • the liquid crystal panel shown in FIG. 15 it is possible to prevent a decrease in visibility that occurs when the area ratio of two sub-pixels constituting a multi-pixel is changed.
  • the bright pixels 98 and the dark pixels 99 are alternately arranged in the row direction and the column direction to form a checkered pattern. As shown in the figure, a rough surface occurs in the image.
  • FIG. 16 is a diagram schematically showing the brightness of each sub-pixel when the area ratio of two sub-pixels constituting a multi-pixel is changed in the conventional technique.
  • FIG. 17 is a diagram showing an example of display when the area ratio of two sub-pixels constituting a multi-pixel is changed in the related art.
  • the first sub-pixel 311 and the second sub-pixel 312 are alternately arranged in the row direction, but the first sub-pixel 311 and the second sub-pixel 312 are arranged. Are arranged so as to be aligned in the column direction, so that a column of sub-pixels with a small area and a column of sub-pixels with a large area can be formed.
  • a liquid crystal panel includes a first substrate, a second substrate disposed so as to face the first substrate, the first substrate, and the first substrate.
  • a liquid crystal panel provided between the two substrates and a plurality of pixel regions arranged two-dimensionally along the row direction and the column direction, each of the pixel regions including at least the above-described pixel region
  • the first substrate includes two sub-pixel regions arranged in the row direction, and the first substrate intersects with the gate bus line provided corresponding to the pixel region arranged in the row direction, and the gate bus line through an insulating film.
  • the above standard corresponding to the pixel electrode A data bus line provided for each of the sub-pixel regions corresponding to the pixel regions arranged in the column direction. It is characterized by having.
  • each pixel region includes at least two subpixel regions arranged in the row direction, and the reference voltage bus line intersecting with the gate bus line is provided for each subpixel region.
  • a pixel electrode having a large area and a pixel electrode having a small area can be arranged in the row direction and formed in one pixel region without causing a dead space.
  • a voltage having an arbitrary value can be applied to two sub-pixel areas provided in one pixel area.
  • the counter matrix type liquid crystal panel having a configuration in which two sub-pixel regions are arranged side by side in one pixel region, a multi-pixel structure that does not cause useless space can be obtained, and viewing angle characteristics can be improved.
  • a voltage of an arbitrary value can be applied to at least two subpixel regions arranged in the row direction of each pixel region, a potential difference between the subpixel regions can be freely set after the liquid crystal panel is completed.
  • the voltage between the sub-pixel regions can be adjusted appropriately, and the yield can be improved.
  • each pixel region includes at least two subpixel regions arranged in the row direction includes, for example, two sets of two subpixel regions arranged in the row direction, and four subpixels in one pixel region. This means that it is allowed to provide a region.
  • the potential difference between the data bus line and the reference voltage bus line which are provided for each sub-pixel region and make a pair is different for each sub-pixel region.
  • the data bus line and the reference voltage bus line are provided in pairs for each sub-pixel region, various voltages can be applied to the data bus line and the reference voltage bus line.
  • the potential difference between the data bus line and the reference voltage bus line can be changed in various ways.
  • the counter matrix type liquid crystal panel having a configuration in which two sub-pixel regions are arranged side by side in one pixel region, a multi-pixel structure that does not cause useless space can be obtained, and viewing angle characteristics can be improved.
  • the two sub-pixel regions provided in each of the pixel regions have different areas, and a data bus line and a reference voltage that are provided for each sub-pixel region and make a pair.
  • a data bus line and a reference voltage that are provided for each sub-pixel region and make a pair.
  • the potential difference between the bus lines it is preferable that the potential difference in the sub-pixel region having a small area out of the two sub-pixel regions is larger than the potential difference in the sub-pixel region having a large area.
  • the potential difference in a sub-pixel region having a small area (hereinafter referred to as a small sub-pixel region) is made larger than the potential difference in a sub-pixel region having a large area (hereinafter referred to as a large sub-pixel region). Therefore, the voltage applied to the liquid crystal layer in the small sub-pixel region exceeds the threshold value earlier than the liquid crystal layer in the large sub-pixel region. That is, when the voltage applied to the liquid crystal layer in the small sub-pixel region exceeds the threshold value, the voltage applied to the liquid crystal layer in the large sub-pixel region does not exceed the threshold value.
  • the small sub-pixel area starts to display the color of the low gradation area first, reaches a higher brightness than the large sub-pixel area, Thus, light is emitted so as to compensate the light emission amount from the halftone area to the high gradation area.
  • the small sub-pixel region mainly contributes to the display from low gradation to halftone, while the large sub-pixel region mainly contributes to the display from halftone to high gradation. This makes it easy to control the viewing angle characteristic to a desired characteristic.
  • the low gradation area is the large subpixel area when the low gradation area is the small subpixel area.
  • the viewing angle characteristics can be further improved than the above.
  • a liquid crystal panel includes a first substrate, a second substrate disposed so as to face the first substrate, the first substrate, and the first substrate.
  • a plurality of pixel regions are two-dimensionally arranged along the row direction and the column direction, and each of the pixel regions is arranged at least in the column direction.
  • the second substrate includes a data bus line provided corresponding to the pixel region arranged in the column direction, and the gate bus line is formed in a meandering shape. It is characterized in that the areas of the two sub-pixel regions are different.
  • the first substrate When a pixel electrode is provided for each sub-pixel region, two pixel electrodes having different areas can be provided side by side in the column direction without creating a dead space in one pixel region.
  • the meandering center line is a bisector that divides the pixel region into two regions of equal area arranged in the column direction.
  • the gate bus line is displaced from the center line in the column direction, the two regions having the same area aligned in the column direction naturally have different areas.
  • a pixel electrode having a small area is formed by simply reducing one pixel electrode of the two regions having the same area without meandering the gate bus line, the sub-electrode on which the pixel electrode having a small area is formed. Dead space occurs in the pixel area.
  • the area of the sub-pixel region itself is made different by meandering the gate bus line, so that a pixel electrode having a large area can be obtained without causing a dead space in one pixel region. And a pixel electrode having a small area can be formed in one pixel region.
  • each pixel area includes at least two subpixel areas arranged in the column direction includes, for example, two sets of two subpixel areas arranged in the column direction, and four subpixels in one pixel area. This means that it is allowed to provide a region.
  • the meandering center line is a bisector that divides the pixel region into two regions arranged with the same width in the column direction, and is provided for each pixel electrode.
  • One switching element is preferably provided for each meandering bent portion.
  • the layout of the switching element arrangement can be simplified.
  • the first pixel region is arranged in the column direction.
  • a pixel region and a second sub-pixel region, and the second pixel region includes a third sub-pixel region and a fourth sub-pixel region arranged in the column direction
  • the reference voltage bus line includes the column It is preferable that the second subpixel region and the third subpixel region which are adjacent to each other in the direction are shared.
  • pixel regions adjacent in the column direction can share one reference voltage bus line, so that a simple wiring layout can be achieved.
  • a liquid crystal panel includes a first substrate, a second substrate disposed so as to face the first substrate, the first substrate, and the first substrate.
  • a liquid crystal panel provided between the two substrates and a plurality of pixel regions arranged two-dimensionally along the row direction and the column direction, each of the pixel regions including at least the above-described pixel region
  • the first substrate includes two sub-pixel regions arranged in the row direction, and the first substrate intersects with the gate bus lines provided corresponding to the pixel regions arranged in the row direction, and the gate bus lines via an insulating film.
  • the reference voltage bus line provided for each sub-pixel region, the pixel electrode provided for each sub-pixel region, the gate electrode supplied to the gate bus line, the pixel electrode, Reference voltage corresponding to the pixel electrode
  • a data bus provided in common in the two sub-pixel regions corresponding to the pixel regions arranged in the column direction. It is characterized by having a line.
  • each pixel region includes at least two subpixel regions arranged in the row direction, and the reference voltage bus line intersecting with the gate bus line is provided for each subpixel region.
  • a pixel electrode having a large area and a pixel electrode having a small area can be arranged in the row direction and formed in one pixel region without causing a dead space.
  • the data bus line and the reference voltage can be changed by changing the voltage applied to the reference voltage bus line provided for each subpixel region according to the subpixel region.
  • the potential difference from the bus line can be changed for each sub-pixel region.
  • the counter matrix type liquid crystal panel having a configuration in which two sub-pixel regions are arranged side by side in one pixel region, a multi-pixel structure that does not cause useless space can be obtained, and viewing angle characteristics can be improved.
  • each pixel region includes at least two subpixel regions arranged in the row direction includes, for example, two sets of two subpixel regions arranged in the row direction, and four subpixels in one pixel region. This means that it is allowed to provide a region.
  • the areas of the two subpixel regions arranged in the row direction are made different, and of the two subpixel regions, the smaller subpixel region or the larger one of the two subpixel regions
  • the subpixel regions may be arranged so as to be aligned in the column direction.
  • a column of sub-pixel regions having a small area and a column of sub-pixel regions having a large area can be formed.
  • the color of the low gradation area to the halftone area is displayed on the column of the subpixel area having a small area
  • the color of the high gradation area from the halftone area is displayed on the column of the subpixel area having a large area.
  • the first sub-regions are arranged in the row direction.
  • a pixel region and a second sub-pixel region, and the second pixel region includes a third sub-pixel region and a fourth sub-pixel region arranged in the row direction
  • the reference voltage bus line includes the row It is preferable that the second subpixel region and the third subpixel region which are adjacent to each other in the direction are shared.
  • pixel regions adjacent in the row direction can share one reference voltage bus line, so that a simple wiring layout can be achieved.
  • a display device including the liquid crystal panel according to the present invention is also included in the scope of the present invention.
  • a driving method of a liquid crystal panel according to the present invention is a driving method in the above-described liquid crystal panel, and at least the two subpixel regions arranged in the row direction are defined as a first subpixel region and a second subpixel region.
  • the reference voltage bus line corresponding to the first sub-pixel region is a first reference voltage bus line
  • the reference voltage bus line corresponding to the second sub-pixel region is a second reference voltage bus line
  • the voltages applied to the bus line and the second reference voltage bus line are made the same, and the voltages applied to the first data bus line and the second data bus line are made different.
  • the potential difference between the first data bus line and the first reference voltage bus line is made different from the potential difference between the second data bus line and the second reference voltage bus line. It is said.
  • the switching element when a gate signal is output to the gate bus line provided corresponding to the pixel region, the switching element is turned on, and at least the first sub-pixel region aligned in the row direction and The second subpixel region is selected at the same time, and the voltage applied to the reference voltage bus line corresponding to each subpixel region is written into the pixel electrode of each subpixel region.
  • each data bus line is opposed to the pixel electrode in each sub-pixel region, the liquid crystal layer in the first sub-pixel region has a potential difference between the first data bus line and the first reference voltage bus line.
  • a potential difference between the second data bus line and the second reference voltage bus line is applied to the liquid crystal layer in the second subpixel region.
  • the voltage applied to the first reference voltage bus line is the same as the voltage applied to the second reference voltage bus line, and is applied to the first data bus line and the second data bus line. Therefore, the voltage applied to the liquid crystal layer in the first subpixel region can be made different from the voltage applied to the liquid crystal layer in the second subpixel region.
  • the voltages applied to the first data bus line and the second data bus line based on the alignment state of the liquid crystal molecules in the first sub-pixel region and the alignment state of the liquid crystal molecules in the second sub-pixel region.
  • the viewing angle characteristics in the counter matrix type liquid crystal panel can be improved.
  • a driving method of a liquid crystal panel according to the present invention is a driving method in the above-described liquid crystal panel, and a reference voltage bus line corresponding to at least one of the two sub-pixel regions arranged in the column direction is connected to the first voltage line.
  • the reference voltage bus line corresponding to the other sub-pixel region is the second reference voltage bus line
  • the first reference voltage bus line is applied to the first reference voltage bus line and the second reference voltage bus line.
  • the potential difference between the data bus line and the first reference voltage bus line is made different from the potential difference between the data bus line and the second reference voltage bus line by making each voltage different. It is said.
  • the switching element when a gate signal is output to the gate bus line provided corresponding to the pixel region, the switching element is turned on, and at least two sub-pixel regions arranged in the column direction are simultaneously selected. Then, the voltage applied to the reference voltage bus line corresponding to each subpixel region is written into the pixel electrode of each subpixel region.
  • the voltage applied to the liquid crystal layer in the one sub-pixel region can be made different from the voltage applied to the liquid crystal layer in the other sub-pixel region.
  • the alignment state of the liquid crystal molecules in the one subpixel region can be made different from the alignment state of the liquid crystal molecules in the other subpixel region with respect to the voltage written to the data bus line. Viewing angle characteristics in a matrix type liquid crystal panel can be improved.
  • the areas of the two sub-pixel regions are different by making the gate bus line meandering.
  • the area of one subpixel area of two subpixel areas corresponding to a certain data bus line is smaller than the area of the other subpixel area, it corresponds to the data bus line adjacent to the data bus line.
  • the area of one of the two subpixel areas is larger than the area of the other subpixel area.
  • a driving method of a liquid crystal panel according to the present invention is a driving method in the above-described liquid crystal panel, and at least the two subpixel regions arranged in the row direction are defined as a first subpixel region and a second subpixel region.
  • the reference voltage bus line corresponding to the first sub-pixel region is a first reference voltage bus line
  • the reference voltage bus line corresponding to the second sub-pixel region is a second reference voltage bus line.
  • the switching element when a gate signal is output to the gate bus line provided corresponding to the pixel region, the switching element is turned on, and at least the first sub-pixel region aligned in the row direction and The second subpixel region is selected at the same time, and the voltage applied to the reference voltage bus line corresponding to each subpixel region is written into the pixel electrode of each subpixel region.
  • the voltage applied to the liquid crystal layer in the first subpixel region can be made different from the voltage applied to the liquid crystal layer in the second subpixel region.
  • the alignment state of the liquid crystal molecules in the first subpixel region can be made different from the alignment state of the liquid crystal molecules in the second subpixel region with respect to the voltage written to the data bus line. Viewing angle characteristics in a matrix type liquid crystal panel can be improved.
  • the liquid crystal panel according to the present invention can be suitably applied to TVs, personal computer monitors, mobile phones and the like.

Abstract

A liquid crystal panel (1) of the present invention is characterized in that a pixel (210) provided in the liquid crystal panel is provided with at least two sub-pixels (211, 212) that are aligned in the row direction, a TFT substrate (10) is provided with a gate bus line (16), a reference voltage bus line (18), a pixel electrode (14), and a TFT (12), which turns on and off the electrical connection between the pixel electrode (14) and the reference voltage bus line (18), and that a facing substrate (20) is provided with a data bus line (22).

Description

液晶パネル、表示装置、及び、その駆動方法Liquid crystal panel, display device, and driving method thereof
 本発明は、対向マトリクス型の液晶パネル、対向マトリクス型の液晶パネルを備える表示装置、及び、その駆動方法に関する。 The present invention relates to a counter matrix type liquid crystal panel, a display device including the counter matrix type liquid crystal panel, and a driving method thereof.
 液晶表示装置は、近年、高画質化が求められ、例えばVA(Vertically Alignment;垂直配向)型液晶ディスプレイでは、視野角特性を改善するために、1画素を複数のサブ画素に分割する駆動法が一般的に用いられている。マルチ画素駆動によれば、1つの画素に明副画素と暗副画素とを形成して中間調を表示する結果、中間調表示時の白浮き等の抑制を図ることができる。そして、マルチ画素駆動では、この2つのサブ画素に接続されている各補助容量Csの電位を変動させ、各サブ画素に電位差を生じさせることで、各サブ画素の輝度をコントロールしている。 In recent years, liquid crystal display devices are required to have high image quality. For example, in a VA (Vertically Aligned) type liquid crystal display, a driving method that divides one pixel into a plurality of subpixels is used to improve viewing angle characteristics. Commonly used. According to the multi-pixel driving, bright subpixels and dark subpixels are formed in one pixel and halftones are displayed. As a result, whitening or the like during halftone display can be suppressed. In multi-pixel driving, the luminance of each sub-pixel is controlled by varying the potential of each auxiliary capacitor Cs connected to the two sub-pixels and causing a potential difference in each sub-pixel.
 また、下掲の特許文献1には、マルチ画素駆動方式の液晶表示装置において、2つの副画素の面積比を1/2以上4以下に設定することが、高い視覚特性を得るために望ましいと記載されている。 Further, in Patent Document 1 listed below, in a multi-pixel driving type liquid crystal display device, it is desirable to set the area ratio of two sub-pixels to 1/2 or more and 4 or less in order to obtain high visual characteristics. Are listed.
 一方、液晶表示装置の構成手法として、対向マトリクス型が提案されている。対向マトリクス型は、第1の基板上にゲートバスライン、基準電圧バスライン、スイッチング素子、及び表示電極が設けられ、第2の基板上にデータバスラインとして兼用される対向電極が設けられている。この対向マトリクス型の構成は、データバスラインとゲートバスラインとが積層していないため、対向マトリクス型以外の構成と比べ、層間の短絡欠陥の発生頻度を大幅に減少させることができる。 On the other hand, a counter matrix type has been proposed as a configuration method of the liquid crystal display device. In the counter matrix type, a gate bus line, a reference voltage bus line, a switching element, and a display electrode are provided on a first substrate, and a counter electrode that is also used as a data bus line is provided on a second substrate. . In this opposed matrix type configuration, since the data bus lines and the gate bus lines are not stacked, the frequency of occurrence of short-circuit defects between layers can be greatly reduced as compared with configurations other than the opposed matrix type.
 下掲の特許文献2には、対向マトリクス型の液晶表示装置の1つの画素を2つのサブ画素に分割することによって、いずれか一方のサブ画素に不良が生じた場合でも、画素欠けを生じさせず、良好な表示品位を維持する技術が開示されている。 In Patent Document 2 listed below, by dividing one pixel of a counter-matrix liquid crystal display device into two sub-pixels, even if one of the sub-pixels is defective, a pixel defect occurs. However, a technique for maintaining good display quality is disclosed.
日本国公開特許公報「特開2006-133577号公報(2006年5月25日公開)」Japanese Patent Publication “Japanese Patent Laid-Open No. 2006-133577 (published May 25, 2006)” 日本国公開特許公報「特開2000-75318号公報(2000年3月4日公開)」Japanese Patent Publication “Japanese Patent Laid-Open No. 2000-75318 (published on March 4, 2000)”
 しかしながら、特許文献2に記載の技術では、各サブ画素に同じ電圧が印加されるため、各サブ画素に印加する電圧を異ならせるマルチ画素についての技術については何ら記載されていない。 However, in the technique described in Patent Document 2, since the same voltage is applied to each sub-pixel, there is no description about a technique related to a multi-pixel that varies the voltage applied to each sub-pixel.
 また、特許文献2に記載された構成を基にして、マルチ画素を構成する2つのサブ画素のうち、一方のサブ画素の面積を単に小さくすることによって2つのサブ画素の面積比を変えてみた場合の思考実験的な液晶パネルの上面図を図15に示す。図15に示すように、データバスライン92とゲートバスライン96とにより画定された画素を構成する2つのサブ画素のうち、何れか一方のサブ画素の面積を単に小さくすると、画素の開口率に寄与しないデッドスペース90が生じてしまうことが判る。 In addition, based on the configuration described in Patent Document 2, the area ratio of two sub-pixels was changed by simply reducing the area of one of the two sub-pixels constituting the multi-pixel. FIG. 15 shows a top view of a liquid crystal panel that is an experimental experiment for the case. As shown in FIG. 15, when the area of one of the two subpixels constituting the pixel defined by the data bus line 92 and the gate bus line 96 is simply reduced, the aperture ratio of the pixel is increased. It turns out that the dead space 90 which does not contribute arises.
 本発明は、上記の課題を解決するためになされたものであり、その主たる目的は、対向マトリクス型の液晶パネルにおいて、マルチ画素を構成する複数のサブ画素の面積比を変えた場合にもデッドスペースが生じない液晶パネルを提供することにある。 The present invention has been made to solve the above-mentioned problems, and its main object is to dead even when the area ratio of a plurality of sub-pixels constituting a multi-pixel is changed in a counter matrix type liquid crystal panel. The object is to provide a liquid crystal panel in which no space is generated.
 本発明に係る液晶パネルは、上記の課題を解決するために、第1の基板と、上記第1の基板に対向するように配置された第2の基板と、上記第1の基板と上記第2の基板との間に設けられた液晶層とを備え、複数の画素領域が行方向及び列方向に沿って二次元的に配列した液晶パネルであって、上記画素領域のそれぞれは、少なくとも上記行方向に並ぶ2つの副画素領域を備え、上記第1の基板は、上記行方向に並ぶ上記画素領域に対応して設けられたゲートバスラインと、上記ゲートバスラインに絶縁膜を介して交差するように、上記副画素領域毎に設けられた基準電圧バスラインと、上記副画素領域毎に設けられた画素電極と、上記ゲートバスラインに供給されるゲート信号によって、上記画素電極と、当該画素電極に対応する上記基準電圧バスラインとの電気的な接続をオンオフするスイッチング素子とを備え、上記第2の基板は、上記列方向に並ぶ上記画素領域に対応して、上記副画素領域毎に設けられたデータバスラインを備えたことを特徴としている。 In order to solve the above problems, a liquid crystal panel according to the present invention includes a first substrate, a second substrate disposed so as to face the first substrate, the first substrate, and the first substrate. A liquid crystal panel provided between the two substrates and a plurality of pixel regions arranged two-dimensionally along the row direction and the column direction, each of the pixel regions including at least the above-described pixel region The first substrate includes two sub-pixel regions arranged in the row direction, and the first substrate intersects with the gate bus line provided corresponding to the pixel region arranged in the row direction, and the gate bus line through an insulating film. The reference voltage bus line provided for each sub-pixel region, the pixel electrode provided for each sub-pixel region, the gate electrode supplied to the gate bus line, the pixel electrode, The above-mentioned base corresponding to the pixel electrode A switching element for turning on and off the electrical connection with the voltage bus line, and the second substrate is a data bus line provided for each of the sub-pixel regions corresponding to the pixel regions arranged in the column direction. It is characterized by having.
 上記の構成によれば、各画素領域は、少なくとも行方向に並ぶ2つの副画素領域を備え、ゲートバスラインと交差する基準電圧バスラインを副画素領域毎に設けたので、1つの画素領域に無駄なデッドスペースを生じさせることなく、面積が大きい画素電極と、面積が小さい画素電極とを行方向に並べて1つの画素領域に形成することができる。 According to the above configuration, each pixel region includes at least two subpixel regions arranged in the row direction, and the reference voltage bus line intersecting with the gate bus line is provided for each subpixel region. A pixel electrode having a large area and a pixel electrode having a small area can be arranged in the row direction and formed in one pixel region without causing a dead space.
 しかも、副画素領域毎にデータバスラインを設けたので、1つの画素領域に備えられた2つの副画素領域に、任意の値の電圧を印加することができる。 In addition, since a data bus line is provided for each sub-pixel area, a voltage having an arbitrary value can be applied to two sub-pixel areas provided in one pixel area.
 これにより、1つの画素領域に2つの副画素領域が横並びした構成を有する対向マトリクス型の液晶パネルにおいて、無駄なスペースを生じないマルチ画素構造が得られ、視野角特性を向上させることができる。 Thereby, in the counter matrix type liquid crystal panel having a configuration in which two sub-pixel regions are arranged side by side in one pixel region, a multi-pixel structure that does not cause useless space can be obtained, and viewing angle characteristics can be improved.
 また、各画素領域の少なくとも行方向に並ぶ2つの副画素領域に、任意の値の電圧を印加することができるため、液晶パネル完成後に副画素領域間の電位差を自由に設定することができる。これによって、液晶パネルの製造プロセスにバラツキが発生した場合にも、副画素領域間の電圧を適切に調整することができ、歩留まりを向上させることができる。 In addition, since a voltage of an arbitrary value can be applied to at least two subpixel regions arranged in the row direction of each pixel region, a potential difference between the subpixel regions can be freely set after the liquid crystal panel is completed. Thus, even when variations occur in the manufacturing process of the liquid crystal panel, the voltage between the sub-pixel regions can be adjusted appropriately, and the yield can be improved.
 なお、各画素領域が、少なくとも上記行方向に並ぶ2つの副画素領域を備えた構成とは、例えば、行方向に並ぶ2つの副画素領域を2組備え、1つの画素領域に4つの副画素領域を設けることを許容するとの意味である。 The configuration in which each pixel region includes at least two subpixel regions arranged in the row direction includes, for example, two sets of two subpixel regions arranged in the row direction, and four subpixels in one pixel region. This means that it is allowed to provide a region.
 本発明に係る液晶パネルは、上記の課題を解決するために、第1の基板と、上記第1の基板に対向するように配置された第2の基板と、上記第1の基板と上記第2の基板との間に設けられた液晶層とを備え、複数の画素領域が行方向及び列方向に沿って二次元的に配列し、かつ上記画素領域のそれぞれは、少なくとも上記列方向に並ぶ2つの副画素領域を備えた液晶パネルであって、上記第1の基板は、上記行方向に並ぶ上記画素領域に対応して設けられたゲートバスラインと、上記行方向に並ぶ上記画素領域に対応して、上記副画素領域毎に設けられた基準電圧バスラインと、上記副画素領域毎に設けられた画素電極と、上記ゲートバスラインに供給されるゲート信号によって、上記画素電極と上記基準電圧バスラインとの電気的な接続をオンオフするスイッチング素子とを備え、上記第2の基板は、上記列方向に並ぶ上記画素領域に対応して設けられたデータバスラインを備え、上記ゲートバスラインを蛇行形状とすることによって、上記2つの副画素領域の面積を異ならせることを特徴としている。 In order to solve the above problems, a liquid crystal panel according to the present invention includes a first substrate, a second substrate disposed so as to face the first substrate, the first substrate, and the first substrate. A plurality of pixel regions are two-dimensionally arranged along the row direction and the column direction, and each of the pixel regions is arranged at least in the column direction. A liquid crystal panel having two sub-pixel regions, wherein the first substrate is formed on gate bus lines provided corresponding to the pixel regions arranged in the row direction and in the pixel regions arranged in the row direction. Correspondingly, the reference voltage bus line provided for each sub-pixel region, the pixel electrode provided for each sub-pixel region, and the gate signal supplied to the gate bus line, the pixel electrode and the reference Electrical connection to the voltage bus line The second substrate includes a data bus line provided corresponding to the pixel region arranged in the column direction, and the gate bus line is formed in a meandering shape. It is characterized in that the areas of the two sub-pixel regions are different.
 上記の構成によれば、ゲートバスラインとデータバスラインとが、液晶層を挟んで対向する第1の基板と第2の基板とに分かれて設けられた構成の液晶パネルにおいて、第1の基板に副画素領域毎に画素電極を設ける場合に、1つの画素領域にデッドスペースを作らずに、面積の異なる2つの画素電極を列方向に並べて設けることができる。 According to the above configuration, in the liquid crystal panel having the configuration in which the gate bus line and the data bus line are separately provided on the first substrate and the second substrate facing each other with the liquid crystal layer interposed therebetween, the first substrate When a pixel electrode is provided for each sub-pixel region, two pixel electrodes having different areas can be provided side by side in the column direction without creating a dead space in one pixel region.
 その理由は以下のとおりである。例えば、上記蛇行形状の中心線が、上記画素領域を上記列方向に並ぶ等面積の2つの領域に分割する2等分線であるとする。その中心線から上記列方向に対してゲートバスラインが変位すると、列方向に並ぶ等面積の2つの領域は、自ずと面積の異なる領域となる。 The reason is as follows. For example, it is assumed that the meandering center line is a bisector that divides the pixel region into two regions of equal area arranged in the column direction. When the gate bus line is displaced from the center line in the column direction, the two regions having the same area aligned in the column direction naturally have different areas.
 仮に、ゲートバスラインを蛇行させず、上記の等面積の2つの領域の一方の画素電極を単に小さくすることによって、面積の小さい画素電極を形成するとすれば、面積の小さい画素電極を形成した副画素領域にデッドスペースが生じる。 If a pixel electrode having a small area is formed by simply reducing one pixel electrode of the two regions having the same area without meandering the gate bus line, the sub-electrode on which the pixel electrode having a small area is formed. Dead space occurs in the pixel area.
 これに対し、本発明では、ゲートバスラインを蛇行させることによって、副画素領域自体の面積を異ならせているので、1つの画素領域に無駄なデッドスペースを生じさせることなく、面積が大きい画素電極と、面積が小さい画素電極とを1つの画素領域に形成することができる。 On the other hand, in the present invention, the area of the sub-pixel region itself is made different by meandering the gate bus line, so that a pixel electrode having a large area can be obtained without causing a dead space in one pixel region. And a pixel electrode having a small area can be formed in one pixel region.
 これにより、1つの画素領域に2つの副画素領域が縦並びした構成を有する対向マトリクス型の液晶パネルにおいて、無駄なスペースを生じないマルチ画素構造が得られ、視野角特性を向上させることができる。 As a result, in a counter matrix type liquid crystal panel having a configuration in which two sub-pixel regions are vertically arranged in one pixel region, a multi-pixel structure that does not cause useless space can be obtained, and viewing angle characteristics can be improved. .
 なお、各画素領域が、少なくとも上記列方向に並ぶ2つの副画素領域を備えた構成とは、例えば、列方向に並ぶ2つの副画素領域を2組備え、1つの画素領域に4つの副画素領域を設けることを許容するとの意味である。 Note that the configuration in which each pixel area includes at least two subpixel areas arranged in the column direction includes, for example, two sets of two subpixel areas arranged in the column direction, and four subpixels in one pixel area. This means that it is allowed to provide a region.
 本発明に係る液晶パネルは、上記の課題を解決するために、第1の基板と、上記第1の基板に対向するように配置された第2の基板と、上記第1の基板と上記第2の基板との間に設けられた液晶層とを備え、複数の画素領域が行方向及び列方向に沿って二次元的に配列した液晶パネルであって、上記画素領域のそれぞれは、少なくとも上記行方向に並ぶ2つの副画素領域を備え、記第1の基板は、上記行方向に並ぶ上記画素領域に対応して設けられたゲートバスラインと、上記ゲートバスラインに絶縁膜を介して交差するように、上記副画素領域毎に設けられた基準電圧バスラインと、上記副画素領域毎に設けられた画素電極と、上記ゲートバスラインに供給されるゲート信号によって、上記画素電極と、当該画素電極に対応する基準電圧バスラインとの電気的な接続をオンオフするスイッチング素子とを備え、上記第2の基板は、上記列方向に並ぶ上記画素領域に対応して、上記2つの副画素領域に共通に設けられたデータバスラインを備えたことを特徴としている。 In order to solve the above problems, a liquid crystal panel according to the present invention includes a first substrate, a second substrate disposed so as to face the first substrate, the first substrate, and the first substrate. A liquid crystal panel provided between the two substrates and a plurality of pixel regions arranged two-dimensionally along the row direction and the column direction, each of the pixel regions including at least the above-described pixel region The first substrate includes two sub-pixel regions arranged in the row direction, and the first substrate intersects with the gate bus lines provided corresponding to the pixel regions arranged in the row direction, and the gate bus lines via an insulating film. The reference voltage bus line provided for each sub-pixel region, the pixel electrode provided for each sub-pixel region, the gate electrode supplied to the gate bus line, the pixel electrode, Reference voltage corresponding to the pixel electrode A data bus provided in common in the two sub-pixel regions corresponding to the pixel regions arranged in the column direction. It is characterized by having a line.
 上記の構成によれば、各画素領域は、少なくとも行方向に並ぶ2つの副画素領域を備え、ゲートバスラインと交差する基準電圧バスラインを副画素領域毎に設けたので、1つの画素領域に無駄なデッドスペースを生じさせることなく、面積が大きい画素電極と、面積が小さい画素電極とを行方向に並べて1つの画素領域に形成することができる。 According to the above configuration, each pixel region includes at least two subpixel regions arranged in the row direction, and the reference voltage bus line intersecting with the gate bus line is provided for each subpixel region. A pixel electrode having a large area and a pixel electrode having a small area can be arranged in the row direction and formed in one pixel region without causing a dead space.
 しかも、2つの副画素領域に共通にデータバスラインを設けたので、副画素領域毎に設けた基準電圧バスラインに印加する電圧を副画素領域に応じて変えることにより、データバスラインと基準電圧バスラインとの電位差を、副画素領域毎に変えることができる。 In addition, since the data bus line is provided in common in the two subpixel regions, the data bus line and the reference voltage can be changed by changing the voltage applied to the reference voltage bus line provided for each subpixel region according to the subpixel region. The potential difference from the bus line can be changed for each sub-pixel region.
 これにより、1つの画素領域に2つの副画素領域が横並びした構成を有する対向マトリクス型の液晶パネルにおいて、無駄なスペースを生じないマルチ画素構造が得られ、視野角特性を向上させることができる。 Thereby, in the counter matrix type liquid crystal panel having a configuration in which two sub-pixel regions are arranged side by side in one pixel region, a multi-pixel structure that does not cause useless space can be obtained, and viewing angle characteristics can be improved.
 なお、各画素領域が、少なくとも上記行方向に並ぶ2つの副画素領域を備えた構成とは、例えば、行方向に並ぶ2つの副画素領域を2組備え、1つの画素領域に4つの副画素領域を設けることを許容するとの意味である。 The configuration in which each pixel region includes at least two subpixel regions arranged in the row direction includes, for example, two sets of two subpixel regions arranged in the row direction, and four subpixels in one pixel region. This means that it is allowed to provide a region.
 また、列方向に並ぶ各画素領域について、行方向に並ぶ2つの副画素領域の面積を異ならせるとともに、上記2つの副画素領域のうち、面積が小さい方の副画素領域または面積が大きい方の副画素領域が、列方向に整列するように配置してもよい。 In addition, for each pixel region arranged in the column direction, the areas of the two subpixel regions arranged in the row direction are made different, and of the two subpixel regions, the smaller subpixel region or the larger one of the two subpixel regions The subpixel regions may be arranged so as to be aligned in the column direction.
 この場合、小さな面積の副画素領域の列と、大きな面積の副画素領域の列とを形成することができる。このような構成では、例えば、小さな面積の副画素領域の列に低階調領域から中間調領域の色を表示させ、大きな面積の副画素領域の列に中間調領域から高階調領域の色を表示させることができる。すなわち市松模様を作らないようにすることができる。この結果、中間調の色に、市松模様の場合に生じるざらつき感を発生しにくくすることができる。 In this case, a column of sub-pixel regions having a small area and a column of sub-pixel regions having a large area can be formed. In such a configuration, for example, the color of the low gradation area to the halftone area is displayed on the column of the subpixel area having a small area, and the color of the high gradation area from the halftone area is displayed on the column of the subpixel area having a large area. Can be displayed. In other words, it is possible to avoid making a checkered pattern. As a result, it is possible to make it difficult to generate a rough feeling that occurs in the case of a checkered pattern in a halftone color.
 本発明に係る液晶パネルの駆動方法は、上述した液晶パネルにおける駆動方法であって、少なくとも上記行方向に並ぶ上記2つの副画素領域を、第1の副画素領域及び第2の副画素領域とし、上記第1の副画素領域に対応した基準電圧バスラインを第1の基準電圧バスラインとし、上記第2の副画素領域に対応した基準電圧バスラインを第2の基準電圧バスラインとし、上記第1の副画素領域に対応したデータバスラインを第1のデータバスラインとし、上記第2の副画素領域に対応したデータバスラインを第2のデータバスラインとすると、上記第1の基準電圧バスライン及び上記第2の基準電圧バスラインに印加する各電圧を同一にし、上記第1のデータバスライン及び上記第2のデータバスラインに印加する電圧を相違させることによって、上記第1のデータバスライン及び上記第1の基準電圧バスライン間の電位差と、上記第2のデータバスライン及び上記第2の基準電圧バスライン間の電位差とを相違させることを特徴としている。 A driving method of a liquid crystal panel according to the present invention is a driving method in the above-described liquid crystal panel, and at least the two subpixel regions arranged in the row direction are defined as a first subpixel region and a second subpixel region. The reference voltage bus line corresponding to the first sub-pixel region is a first reference voltage bus line, the reference voltage bus line corresponding to the second sub-pixel region is a second reference voltage bus line, and If the data bus line corresponding to the first sub-pixel region is the first data bus line and the data bus line corresponding to the second sub-pixel region is the second data bus line, the first reference voltage The voltages applied to the bus line and the second reference voltage bus line are made the same, and the voltages applied to the first data bus line and the second data bus line are made different. The potential difference between the first data bus line and the first reference voltage bus line is made different from the potential difference between the second data bus line and the second reference voltage bus line. It is said.
 上記の構成によれば、画素領域に対応して設けられたゲートバスラインにゲート信号が出力されると、上記スイッチング素子がオンになり、少なくとも上記行方向に並ぶ上記第1の副画素領域及び第2の副画素領域が同時に選択され、各副画素領域の画素電極に、各副画素領域に対応した基準電圧バスラインに印加された電圧が書き込まれる。 According to the above configuration, when a gate signal is output to the gate bus line provided corresponding to the pixel region, the switching element is turned on, and at least the first sub-pixel region aligned in the row direction and The second subpixel region is selected at the same time, and the voltage applied to the reference voltage bus line corresponding to each subpixel region is written into the pixel electrode of each subpixel region.
 各副画素領域の画素電極には各データバスラインが対向しているから、第1の副画素領域の液晶層には、第1のデータバスラインと第1の基準電圧バスラインとの電位差が印加される一方、第2の副画素領域の液晶層には、第2のデータバスラインと第2の基準電圧バスラインとの電位差が印加される。 Since each data bus line is opposed to the pixel electrode in each sub-pixel region, the liquid crystal layer in the first sub-pixel region has a potential difference between the first data bus line and the first reference voltage bus line. On the other hand, a potential difference between the second data bus line and the second reference voltage bus line is applied to the liquid crystal layer in the second subpixel region.
 このとき、第1の基準電圧バスラインに印加された電圧と、第2の基準電圧バスラインに印加された電圧とは同一であり、第1のデータバスライン及び第2のデータバスラインに印加する電圧を相違させているから、第1の副画素領域の液晶層にかかる電圧と、第2の副画素領域の液晶層にかかる電圧とを相違させることができる。 At this time, the voltage applied to the first reference voltage bus line is the same as the voltage applied to the second reference voltage bus line, and is applied to the first data bus line and the second data bus line. Therefore, the voltage applied to the liquid crystal layer in the first subpixel region can be made different from the voltage applied to the liquid crystal layer in the second subpixel region.
 これにより、第1の副画素領域における液晶分子の配向状態と、第2の副画素領域における液晶分子の配向状態とを、第1のデータバスライン及び第2のデータバスラインに印加する各電圧に応じて相違させることができる結果、対向マトリクス型の液晶パネルにおける視野角特性を向上させることができる。 As a result, the voltages applied to the first data bus line and the second data bus line based on the alignment state of the liquid crystal molecules in the first sub-pixel region and the alignment state of the liquid crystal molecules in the second sub-pixel region. As a result, the viewing angle characteristics in the counter matrix type liquid crystal panel can be improved.
 本発明に係る液晶パネルの駆動方法は、上述した液晶パネルにおける駆動方法であって、少なくとも上記列方向に並ぶ上記2つの副画素領域のうち一方の副画素領域に対応した基準電圧バスラインを第1の基準電圧バスラインとし、他方の副画素領域に対応した基準電圧バスラインを第2の基準電圧バスラインとすると、上記第1の基準電圧バスライン及び上記第2の基準電圧バスラインに印加する各電圧を相違させることによって、上記データバスライン及び上記第1の基準電圧バスライン間の電位差と、上記データバスライン及び上記第2の基準電圧バスライン間の電位差とを相違させることを特徴としている。 A driving method of a liquid crystal panel according to the present invention is a driving method in the above-described liquid crystal panel, and a reference voltage bus line corresponding to at least one of the two sub-pixel regions arranged in the column direction is connected to the first voltage line. When the reference voltage bus line corresponding to the other sub-pixel region is the second reference voltage bus line, the first reference voltage bus line is applied to the first reference voltage bus line and the second reference voltage bus line. The potential difference between the data bus line and the first reference voltage bus line is made different from the potential difference between the data bus line and the second reference voltage bus line by making each voltage different. It is said.
 上記の構成によれば、画素領域に対応して設けられたゲートバスラインにゲート信号が出力されると、上記スイッチング素子がオンになり、少なくとも上記列方向に並ぶ2つの副画素領域が同時に選択され、各副画素領域の画素電極に、各副画素領域に対応した基準電圧バスラインに印加された電圧が書き込まれる。 According to the above configuration, when a gate signal is output to the gate bus line provided corresponding to the pixel region, the switching element is turned on, and at least two sub-pixel regions arranged in the column direction are simultaneously selected. Then, the voltage applied to the reference voltage bus line corresponding to each subpixel region is written into the pixel electrode of each subpixel region.
 各副画素領域の画素電極にはデータバスラインが対向しているから、上記一方の副画素領域の液晶層には、データバスラインと第1の基準電圧バスラインとの電位差が印加される一方、上記他方の副画素領域の液晶層には、データバスラインと第2の基準電圧バスラインとの電位差が印加される。 Since the data bus line is opposed to the pixel electrode of each sub-pixel region, a potential difference between the data bus line and the first reference voltage bus line is applied to the liquid crystal layer of the one sub-pixel region. The potential difference between the data bus line and the second reference voltage bus line is applied to the liquid crystal layer in the other sub-pixel region.
 このとき、それぞれの電位差を相違させているから、上記一方の副画素領域の液晶層にかかる電圧と、上記他方の副画素領域の液晶層にかかる電圧とを相違させることができる。 At this time, since the respective potential differences are made different, the voltage applied to the liquid crystal layer in the one sub-pixel region can be made different from the voltage applied to the liquid crystal layer in the other sub-pixel region.
 これにより、データバスラインに書き込んだ電圧に対して、上記一方の副画素領域における液晶分子の配向状態と、上記他方の副画素領域における液晶分子の配向状態とを相違させることができる結果、対向マトリクス型の液晶パネルにおける視野角特性を向上させることができる。 As a result, the alignment state of the liquid crystal molecules in the one subpixel region can be made different from the alignment state of the liquid crystal molecules in the other subpixel region with respect to the voltage written to the data bus line. Viewing angle characteristics in a matrix type liquid crystal panel can be improved.
 なお、上記ゲートバスラインを蛇行形状とすることによって、上記2つの副画素領域の面積は異なっている。この場合、あるデータバスラインに対応した2つの副画素領域の一方の副画素領域の面積が、他方の副画素領域の面積より小さいとすると、上記あるデータバスラインに隣り合うデータバスラインに対応した2つの副画素領域の一方の副画素領域の面積は、他方の副画素領域の面積より大きくなる。 Note that the areas of the two sub-pixel regions are different by making the gate bus line meandering. In this case, if the area of one subpixel area of two subpixel areas corresponding to a certain data bus line is smaller than the area of the other subpixel area, it corresponds to the data bus line adjacent to the data bus line. The area of one of the two subpixel areas is larger than the area of the other subpixel area.
 本発明に係る液晶パネルの駆動方法は、上述した液晶パネルにおける駆動方法であって、少なくとも上記行方向に並ぶ上記2つの副画素領域を、第1の副画素領域及び第2の副画素領域とし、上記第1の副画素領域に対応した基準電圧バスラインを第1の基準電圧バスラインとし、上記第2の副画素領域に対応した基準電圧バスラインを第2の基準電圧バスラインとすると、上記第1の基準電圧バスライン及び上記第2の基準電圧バスラインに印加する各電圧を相違させることによって、上記データバスライン及び上記第1の基準電圧バスライン間の電位差と、上記データバスライン及び上記第2の基準電圧バスライン間の電位差とを相違させること特徴としている。 A driving method of a liquid crystal panel according to the present invention is a driving method in the above-described liquid crystal panel, and at least the two subpixel regions arranged in the row direction are defined as a first subpixel region and a second subpixel region. The reference voltage bus line corresponding to the first sub-pixel region is a first reference voltage bus line, and the reference voltage bus line corresponding to the second sub-pixel region is a second reference voltage bus line. By making each voltage applied to the first reference voltage bus line and the second reference voltage bus line different, a potential difference between the data bus line and the first reference voltage bus line, and the data bus line And the potential difference between the second reference voltage bus lines is different.
 上記の構成によれば、画素領域に対応して設けられたゲートバスラインにゲート信号が出力されると、上記スイッチング素子がオンになり、少なくとも上記行方向に並ぶ上記第1の副画素領域及び第2の副画素領域が同時に選択され、各副画素領域の画素電極に、各副画素領域に対応した基準電圧バスラインに印加された電圧が書き込まれる。 According to the above configuration, when a gate signal is output to the gate bus line provided corresponding to the pixel region, the switching element is turned on, and at least the first sub-pixel region aligned in the row direction and The second subpixel region is selected at the same time, and the voltage applied to the reference voltage bus line corresponding to each subpixel region is written into the pixel electrode of each subpixel region.
 各副画素領域の画素電極には共通のデータバスラインが対向しているから、第1の副画素領域の液晶層には、データバスラインと第1の基準電圧バスラインとの電位差が印加される一方、第2の副画素領域の液晶層には、データバスラインと第2の基準電圧バスラインとの電位差が印加される。 Since the common data bus line is opposed to the pixel electrode in each sub-pixel region, a potential difference between the data bus line and the first reference voltage bus line is applied to the liquid crystal layer in the first sub-pixel region. On the other hand, a potential difference between the data bus line and the second reference voltage bus line is applied to the liquid crystal layer in the second subpixel region.
 このとき、それぞれの電位差を相違させているから、第1の副画素領域の液晶層にかかる電圧と、第2の副画素領域の液晶層にかかる電圧とを相違させることができる。 At this time, since the respective potential differences are made different, the voltage applied to the liquid crystal layer in the first subpixel region can be made different from the voltage applied to the liquid crystal layer in the second subpixel region.
 これにより、データバスラインに書き込んだ電圧に対して、第1の副画素領域における液晶分子の配向状態と、第2の副画素領域における液晶分子の配向状態とを相違させることができる結果、対向マトリクス型の液晶パネルにおける視野角特性を向上させることができる。 As a result, the alignment state of the liquid crystal molecules in the first subpixel region can be made different from the alignment state of the liquid crystal molecules in the second subpixel region with respect to the voltage written to the data bus line. Viewing angle characteristics in a matrix type liquid crystal panel can be improved.
 本発明に係る液晶パネルは、上記のように、第1の基板と、上記第1の基板に対向するように配置された第2の基板と、上記第1の基板と上記第2の基板との間に設けられた液晶層とを備え、複数の画素領域が行方向及び列方向に沿って二次元的に配列し、かつ各画素領域には、少なくとも上記列方向に並ぶ2つの副画素領域を備えた液晶パネルであって、上記第1の基板は、上記行方向に並ぶ上記画素領域に対応して設けられたゲートバスラインと、上記行方向に並ぶ上記画素領域に対応して、上記副画素領域毎に設けられた基準電圧バスラインと、上記副画素領域毎に設けられた画素電極と、上記ゲートバスラインに供給されるゲート信号によって、各画素電極と上記基準電圧バスラインとの電気的な接続をオンオフするスイッチング素子とを備え、上記第2の基板は、上記列方向に並ぶ上記画素領域に対応して設けられたデータバスラインを備え、上記ゲートバスラインを蛇行形状とすることによって、上記2つの副画素領域の面積を異ならせることを特徴としている。 As described above, the liquid crystal panel according to the present invention includes the first substrate, the second substrate disposed so as to face the first substrate, the first substrate, and the second substrate. A plurality of pixel regions arranged two-dimensionally along the row direction and the column direction, and each pixel region includes at least two sub-pixel regions arranged in the column direction. The first substrate includes a gate bus line provided corresponding to the pixel region aligned in the row direction, and the pixel substrate aligned in the row direction, A reference voltage bus line provided for each sub-pixel region, a pixel electrode provided for each sub-pixel region, and a gate signal supplied to the gate bus line, between each pixel electrode and the reference voltage bus line. Switching to turn on / off electrical connection And the second substrate includes a data bus line provided corresponding to the pixel region arranged in the column direction, and the gate bus line has a meandering shape, whereby the two sub-pixels are provided. It is characterized by different areas.
 これにより、1つの画素領域に2つの副画素領域が縦並びした構成を有する対向マトリクス型の液晶パネルにおいて、無駄なスペースを生じないマルチ画素構造が得られ、視野角特性を向上させることができる。 As a result, in a counter matrix type liquid crystal panel having a configuration in which two sub-pixel regions are vertically arranged in one pixel region, a multi-pixel structure that does not cause useless space can be obtained, and viewing angle characteristics can be improved. .
本発明の一実施形態に係る液晶パネルのTFT基板のレイアウトを示す上面図である。It is a top view which shows the layout of the TFT substrate of the liquid crystal panel which concerns on one Embodiment of this invention. 図1に示す液晶パネルの斜視図である。It is a perspective view of the liquid crystal panel shown in FIG. 図1に示す液晶パネルの詳細を示す図である。It is a figure which shows the detail of the liquid crystal panel shown in FIG. 図1に示すTFT基板の等価回路、及び、xフレーム表示時の液晶容量の印加電圧を示す図である。FIG. 2 is a diagram showing an equivalent circuit of the TFT substrate shown in FIG. 1 and a voltage applied to a liquid crystal capacitor during x-frame display. 図1に示すTFT基板の等価回路、及び、x+1フレーム表示時の液晶容量の印加電圧を示す図である。FIG. 2 is a diagram showing an equivalent circuit of the TFT substrate shown in FIG. 1 and a voltage applied to a liquid crystal capacitor during x + 1 frame display. 図4A及び図4Bに示す液晶容量をコンデンサとして表した場合のTFT基板の等価回路を示す図である。FIG. 5 is a diagram showing an equivalent circuit of a TFT substrate when the liquid crystal capacitance shown in FIGS. 4A and 4B is expressed as a capacitor. 図1に示す液晶パネルの動作を示すタイミングチャートである。3 is a timing chart illustrating an operation of the liquid crystal panel illustrated in FIG. 1. 図1に示す液晶パネルのTFT基板の構成の概略を示す上面図である。It is a top view which shows the outline of a structure of the TFT substrate of the liquid crystal panel shown in FIG. 図9に示す液晶パネルのTFT基板の構成の概略を示す上面図である。It is a top view which shows the outline of a structure of the TFT substrate of the liquid crystal panel shown in FIG. 本発明の他の実施形態に係る液晶パネルのTFT基板のレイアウトを示す上面図である。It is a top view which shows the layout of the TFT substrate of the liquid crystal panel which concerns on other embodiment of this invention. 図9に示すTFT基板の等価回路、及び、xフレーム表示時の液晶容量の印加電圧を示す図である。FIG. 10 is a diagram showing an equivalent circuit of the TFT substrate shown in FIG. 9 and a voltage applied to a liquid crystal capacitor during x-frame display. 図9に示すTFT基板の等価回路、及び、x+1フレーム表示時の液晶容量の印加電圧を示す図である。FIG. 10 is a diagram showing an equivalent circuit of the TFT substrate shown in FIG. 9 and an applied voltage of a liquid crystal capacitor at the time of x + 1 frame display. 図9に示す液晶パネルの動作を示すタイミングチャートである。10 is a timing chart showing the operation of the liquid crystal panel shown in FIG. 9. 本発明のさらに他の実施形態に係る液晶パネルのTFT基板のレイアウトを示す上面図である。It is a top view which shows the layout of the TFT substrate of the liquid crystal panel which concerns on further another embodiment of this invention. 図12に示すTFT基板の等価回路、及び、xフレーム表示時の液晶容量の印加電圧を示す図である。FIG. 13 is a diagram showing an equivalent circuit of the TFT substrate shown in FIG. 12 and a voltage applied to a liquid crystal capacitor during x frame display. 図12に示す液晶パネルの動作を示すタイミングチャートである。13 is a timing chart showing the operation of the liquid crystal panel shown in FIG. 従来技術において、マルチ画素を構成する2つのサブ画素の面積比を変えたときの液晶パネルの上面図である。In the prior art, it is a top view of a liquid crystal panel when the area ratio of two sub-pixels constituting a multi-pixel is changed. 図15に示す液晶パネルにおいて、それぞれのサブ画素の明暗を模式的に表した図である。FIG. 16 is a diagram schematically showing the brightness of each sub-pixel in the liquid crystal panel shown in FIG. 15. 図15に示す液晶パネルにおける表示の一例を示す図である。FIG. 16 is a diagram showing an example of display on the liquid crystal panel shown in FIG. 15.
 <実施形態1>
 本発明の一実施形態に係る液晶パネル、液晶パネルを備えた表示装置及びその駆動方法について、図1から図7を参照して説明する。但し、この実施形態に記載されている構成部品の寸法、材質、形状、その相対配置などは、特に特定的な記載がない限り、この発明の範囲をそれのみに限定する趣旨ではなく、単なる説明例に過ぎない。
<Embodiment 1>
A liquid crystal panel according to an embodiment of the present invention, a display device including the liquid crystal panel, and a driving method thereof will be described with reference to FIGS. However, the dimensions, materials, shapes, relative arrangements, and the like of the components described in this embodiment are not intended to limit the scope of the present invention only, unless otherwise specified. It is just an example.
 〔液晶パネルの構成〕
 本実施形態に係る表示装置が備える液晶パネルについて、図2及び図3を参照して説明する。図2は、本実施形態に係る液晶パネル1の斜視図である。図3は、本実施形態に係る液晶パネル1の詳細を示す図である。
[Configuration of LCD panel]
A liquid crystal panel included in the display device according to the present embodiment will be described with reference to FIGS. FIG. 2 is a perspective view of the liquid crystal panel 1 according to the present embodiment. FIG. 3 is a diagram showing details of the liquid crystal panel 1 according to the present embodiment.
 図2に示すように、本実施形態に係る液晶パネル1は、TFT基板(第1の基板)10と、第1基板に対して対向配置された対向基板(第2の基板)20とを備えている。また、TFT基板10と対向基板20との間には、不図示の液晶層が形成されている。 As shown in FIG. 2, the liquid crystal panel 1 according to the present embodiment includes a TFT substrate (first substrate) 10 and a counter substrate (second substrate) 20 disposed to face the first substrate. ing. A liquid crystal layer (not shown) is formed between the TFT substrate 10 and the counter substrate 20.
 図2及び図3の(a)に示すように、TFT基板10は、一方の面(以降、TFT基板10の実装面とも呼称する)上に、複数のTFT(スイッチング素子)12、複数の画素電極14、互いに並列に形成された複数のゲートバスライン16、及び、ゲートバスライン16に並列に形成された基準電圧バスライン18を備えている。TFT12のゲート端子はゲートバスライン16に接続され、ソース端子は基準電圧バスライン18に接続され、ドレイン端子は画素電極14に接続される。 As shown in FIGS. 2 and 3A, the TFT substrate 10 includes a plurality of TFTs (switching elements) 12 and a plurality of pixels on one surface (hereinafter also referred to as a mounting surface of the TFT substrate 10). The electrode 14 includes a plurality of gate bus lines 16 formed in parallel to each other, and a reference voltage bus line 18 formed in parallel to the gate bus lines 16. The TFT 12 has a gate terminal connected to the gate bus line 16, a source terminal connected to the reference voltage bus line 18, and a drain terminal connected to the pixel electrode 14.
 なお、説明の便宜上、TFT12が備えている3端子のうち、ゲート端子以外の2端子について、基準電圧バスライン18に接続された端子をソース端子と呼び、画素電極14に接続された端子をドレイン端子と呼ぶ。 For convenience of explanation, of the three terminals of the TFT 12, of the two terminals other than the gate terminal, a terminal connected to the reference voltage bus line 18 is called a source terminal, and a terminal connected to the pixel electrode 14 is a drain. Called a terminal.
 ゲートバスライン16は、接続されたTFT12に走査信号(ゲート信号)を供給する。基準電圧バスライン18は、TFT12を介して画素電極14に基準電圧を供給する。また、図3の(a)に示すように、ゲートバスライン16はゲート入力端子16aを備え、基準電圧バスライン18は基準電圧入力端子18cを備えている。 The gate bus line 16 supplies a scanning signal (gate signal) to the connected TFT 12. The reference voltage bus line 18 supplies a reference voltage to the pixel electrode 14 via the TFT 12. Further, as shown in FIG. 3A, the gate bus line 16 includes a gate input terminal 16a, and the reference voltage bus line 18 includes a reference voltage input terminal 18c.
 図2及び図3の(b)に示すように、対向基板20は、一方の面(以降、対向基板20の実装面とも呼称する)に互いに並列に形成されたデータバスライン22を備えている。なお、図2に示すように、データバスライン22のうち、画素電極14と対向する部分は、画素電極14の対向電極24を兼ねている。また、画素電極14と対向電極24とに液晶層が挟持されることにより、液晶容量が構成されている。データバスライン22は、データ(映像)信号を対向電極24に供給する。なお、図3の(b)に示すように、データバスライン22はデータ入力端子22aを備えている。 As shown in FIG. 2 and FIG. 3B, the counter substrate 20 includes data bus lines 22 formed in parallel with each other on one surface (hereinafter also referred to as a mounting surface of the counter substrate 20). . As shown in FIG. 2, the portion of the data bus line 22 that faces the pixel electrode 14 also serves as the counter electrode 24 of the pixel electrode 14. In addition, a liquid crystal layer is formed by sandwiching a liquid crystal layer between the pixel electrode 14 and the counter electrode 24. The data bus line 22 supplies a data (video) signal to the counter electrode 24. As shown in FIG. 3B, the data bus line 22 includes a data input terminal 22a.
 TFT基板10及び対向基板20は、図3の(c)に示すように、TFT基板10の実装面と対向基板20の実装面とが向かい合うように配置されている。なお、TFT基板10及び対向基板20は、TFT基板10の実装面に形成されたゲートバスライン16と、対向基板20の実装面に形成されたデータバスライン22とが液晶層を介して交差するように配置されることによって、画素領域がN行M列に2次元的に配列された対向マトリクスを構成している。 The TFT substrate 10 and the counter substrate 20 are arranged so that the mounting surface of the TFT substrate 10 and the mounting surface of the counter substrate 20 face each other, as shown in FIG. In the TFT substrate 10 and the counter substrate 20, the gate bus line 16 formed on the mounting surface of the TFT substrate 10 and the data bus line 22 formed on the mounting surface of the counter substrate 20 intersect via the liquid crystal layer. By arranging in this manner, a counter matrix is formed in which pixel regions are two-dimensionally arranged in N rows and M columns.
 なお、画素領域の詳細な構成については後述するが、図7に示すように、基本的には、1つの画素領域が、例えば赤緑青の三原色のうち、1つの色に対応している。図7は本実施形態に係る液晶パネル1のTFT基板10の構成の概略を示す上面図である。 Although a detailed configuration of the pixel area will be described later, as shown in FIG. 7, basically, one pixel area corresponds to one color among the three primary colors of red, green, and blue, for example. FIG. 7 is a top view schematically showing the configuration of the TFT substrate 10 of the liquid crystal panel 1 according to this embodiment.
 また、ゲートバスライン16のゲート入力端子16a、及び、基準電圧バスライン18の基準電圧入力端子18cは、TFT基板10の端部において、各ゲートバスライン16に走査信号を供給し、各基準電圧バスライン18に基準電圧を供給するゲート駆動回路32と接続されている。また、データバスライン22のデータ入力端子22aは、フレキシブルプリント基板30において各データバスライン22にデータ信号を供給するデータ駆動回路34と接続されている。 Further, the gate input terminal 16a of the gate bus line 16 and the reference voltage input terminal 18c of the reference voltage bus line 18 supply a scanning signal to each gate bus line 16 at the end portion of the TFT substrate 10, and each reference voltage. A gate drive circuit 32 that supplies a reference voltage to the bus line 18 is connected. The data input terminal 22 a of the data bus line 22 is connected to a data driving circuit 34 that supplies a data signal to each data bus line 22 in the flexible printed circuit board 30.
 〔TFT基板のレイアウト〕
 次に、本実施形態に係る液晶パネル1のTFT基板10のレイアウトの詳細を、図1を参照して説明する。図1は、本実施形態に係る液晶パネル1のTFT基板10のレイアウトを示す上面図である。なお、図1において、対向基板20に形成された総数M本のデータバスライン22のうち、m本目のデータバスライン22m(M及びmは自然数、M≧m)の付近に配置されたデータバスライン22(m-1)~22(m+2)を破線で示している。
[TFT substrate layout]
Next, details of the layout of the TFT substrate 10 of the liquid crystal panel 1 according to the present embodiment will be described with reference to FIG. FIG. 1 is a top view showing a layout of the TFT substrate 10 of the liquid crystal panel 1 according to the present embodiment. In FIG. 1, of the total number M of data bus lines 22 formed on the counter substrate 20, the data bus is arranged near the m-th data bus line 22m (M and m are natural numbers, M ≧ m). Lines 22 (m−1) to 22 (m + 2) are indicated by broken lines.
 液晶パネル1は、ゲートバスライン16とデータバスライン22とにより画定される画素(画素領域)110を備えている。画素110は、行方向及び列方向に沿って二次元的に配置される。各画素は第1サブ画素111(第1の副画素領域)であるSub-pix1と第2サブ画素112(第2の副画素領域)であるSub-pix2とを備えている。また、画素電極14は、第1サブ画素111を構成する第1画素電極141、及び、第2サブ画素112を構成する第2画素電極142を備えている。TFT12は、第1サブ画素111を構成する第1TFT121、及び、第2サブ画素112を構成する第2TFT122を備えている。 The liquid crystal panel 1 includes pixels (pixel regions) 110 defined by the gate bus lines 16 and the data bus lines 22. The pixels 110 are two-dimensionally arranged along the row direction and the column direction. Each pixel includes Sub-pix1 which is the first sub-pixel 111 (first sub-pixel region) and Sub-pix2 which is the second sub-pixel 112 (second sub-pixel region). The pixel electrode 14 includes a first pixel electrode 141 constituting the first subpixel 111 and a second pixel electrode 142 constituting the second subpixel 112. The TFT 12 includes a first TFT 121 constituting the first subpixel 111 and a second TFT 122 constituting the second subpixel 112.
 図1に示すように、総数N本のゲートバスライン16のうち、n本目のゲートバスライン16n(N及びnは自然数、N≧n)とm本目のデータバスライン22mとにより画定される画素110を画素110mnとし、画素110mnの第1サブ画素111を第1サブ画素111mn、第2サブ画素112を第2サブ画素112mnとする。また、第1サブ画素111mnを構成する第1画素電極141を第1画素電極141mnとし、第2サブ画素112mnを構成する第2画素電極142を第2画素電極142mnとする。さらに、第1サブ画素111mnを構成する第1TFT121を第1TFT121mnとし、第2サブ画素112を構成する第2TFT122を第2TFT122mnとする。 As shown in FIG. 1, of the total number N of gate bus lines 16, pixels defined by an nth gate bus line 16n (N and n are natural numbers, N ≧ n) and an mth data bus line 22m. 110 is a pixel 110mn, a first subpixel 111 of the pixel 110mn is a first subpixel 111mn, and a second subpixel 112 is a second subpixel 112mn. The first pixel electrode 141 constituting the first subpixel 111mn is referred to as a first pixel electrode 141mn, and the second pixel electrode 142 constituting the second subpixel 112mn is referred to as a second pixel electrode 142mn. Further, the first TFT 121 constituting the first sub pixel 111mn is referred to as a first TFT 121mn, and the second TFT 122 constituting the second sub pixel 112 is referred to as a second TFT 122mn.
 図1に示すように、1つの画素110の領域において、第1サブ画素111と第2サブ画素112とは、上記列方向に配列している。また、第1サブ画素111mnが備える第1TFT121mnのゲート端子はゲートバスライン16nに接続され、ソース端子は基準電圧バスライン18a(第1の基準電圧バスライン)に接続され、ドレイン端子は第1画素電極141mnに接続されている。また、第2サブ画素112が備える第2TFT122mnのゲート端子はゲートバスライン16nに接続され、ソース端子は基準電圧バスライン18b(第2の基準電圧バスライン)に接続され、ドレイン端子は第2画素電極142mnに接続されている。 As shown in FIG. 1, in the area of one pixel 110, the first sub-pixel 111 and the second sub-pixel 112 are arranged in the column direction. The gate terminal of the first TFT 121mn included in the first subpixel 111mn is connected to the gate bus line 16n, the source terminal is connected to the reference voltage bus line 18a (first reference voltage bus line), and the drain terminal is connected to the first pixel. It is connected to the electrode 141mn. The gate terminal of the second TFT 122mn included in the second subpixel 112 is connected to the gate bus line 16n, the source terminal is connected to the reference voltage bus line 18b (second reference voltage bus line), and the drain terminal is connected to the second pixel. It is connected to the electrode 142mn.
 なお、図1に示すように、本実施形態における液晶パネル1のTFT基板10は、第1サブ画素111に対する第2サブ画素112の面積比が、1より大きく4以下になるように構成されていることが好ましい。 As shown in FIG. 1, the TFT substrate 10 of the liquid crystal panel 1 in this embodiment is configured such that the area ratio of the second subpixel 112 to the first subpixel 111 is greater than 1 and 4 or less. Preferably it is.
 これによって、面積の小さい第1サブ画素111(小副画素領域)におけるデータバスライン22及び基準電圧バスライン18間の電位差を、面積の大きい第2サブ画素112(大副画素領域)における電位差より大きくするので、第1サブ画素111の液晶層にかかる電圧は、第2サブ画素112の液晶層に比べて、早く液晶のしきい値を超える。すなわち、第1サブ画素111の液晶層にかかる電圧が、液晶のしきい値を超える時点では、第2サブ画素112の液晶層にかかる電圧は、液晶のしきい値を超えていない。 Accordingly, the potential difference between the data bus line 22 and the reference voltage bus line 18 in the first sub-pixel 111 (small sub-pixel region) having a small area is made larger than the potential difference in the second sub-pixel 112 (large sub-pixel region) having a large area. Since the voltage is increased, the voltage applied to the liquid crystal layer of the first subpixel 111 exceeds the liquid crystal threshold earlier than the liquid crystal layer of the second subpixel 112. That is, when the voltage applied to the liquid crystal layer of the first subpixel 111 exceeds the threshold value of the liquid crystal, the voltage applied to the liquid crystal layer of the second subpixel 112 does not exceed the threshold value of the liquid crystal.
 この場合、面積の大きい第2サブ画素112が発光を開始する前に、第1サブ画素111が低階調領域の色から先に表示し始め、第2サブ画素112より高い輝度に到達し、第2サブ画素112はあとから中間調領域から高階調領域の発光量を補うように発光する。つまり、面積の小さい第1サブ画素111は、低階調から中間調の表示に主に寄与する一方、面積の大きい第2サブ画素112は、中間調から高階調の表示に主に寄与する。このようにすると、視野角特性を所望の特性に制御しやすくなる。 In this case, before the second sub-pixel 112 having a large area starts to emit light, the first sub-pixel 111 starts to display first from the color of the low gradation region, reaches a higher luminance than the second sub-pixel 112, The second sub-pixel 112 emits light so as to supplement the light emission amount from the halftone area to the high gradation area. That is, the first sub-pixel 111 having a small area mainly contributes to display from a low gradation to a halftone, while the second sub-pixel 112 having a large area mainly contributes to display from a half-tone to a high gradation. This makes it easy to control the viewing angle characteristic to a desired characteristic.
 また、人の視覚は、高階調領域の色よりも低階調領域の色に敏感に反応するため、低階調領域を面積の小さい第1サブ画素111にする方が、低階調領域を面積の大きい第2サブ画素112にするよりも、視野角特性をより向上させることができる。 In addition, since human vision reacts more sensitively to the color of the low gradation region than the color of the high gradation region, the low gradation region is more reduced when the low gradation region is the first sub-pixel 111 having a smaller area. The viewing angle characteristic can be further improved as compared with the second sub-pixel 112 having a large area.
 なお、第1サブ画素111及び第2サブ画素112の面積が異なる場合には、図1に示すように、ゲートバスライン16が蛇行形状に形成されることが好ましい。これにより、1つの画素110にデッドスペースを作らずに、面積の異なる2つの第1画素電極141及び第2画素電極142を列方向に並べて設けることができる。 If the areas of the first sub-pixel 111 and the second sub-pixel 112 are different, it is preferable that the gate bus line 16 is formed in a meandering shape as shown in FIG. Accordingly, two first pixel electrodes 141 and second pixel electrodes 142 having different areas can be provided side by side in the column direction without creating a dead space in one pixel 110.
 その理由は以下のとおりである。例えば、上記蛇行形状の中心線が、上記画素110を上記列方向に並ぶ等面積の2つの領域に分割する2等分線であるとする。その中心線から上記列方向に対してゲートバスライン16が変位すると、列方向に並ぶ等面積の2つの領域は、自ずと面積の異なる領域となる。 The reason is as follows. For example, it is assumed that the meandering center line is a bisector that divides the pixel 110 into two equal-area regions arranged in the column direction. When the gate bus line 16 is displaced from the center line with respect to the column direction, the two areas having the same area arranged in the column direction naturally have different areas.
 従来は、ゲートバスライン16を蛇行させず、等面積の2つの領域の一方の画素電極を単に小さくすることによって、面積の小さい画素電極を形成していたため、面積の小さい画素電極を形成したサブ画素にデッドスペースが生じていた。 Conventionally, a pixel electrode having a small area is formed by simply reducing one of the pixel electrodes in two regions having the same area without causing the gate bus line 16 to meander. There was a dead space in the pixel.
 これに対し、本実施形態では、ゲートバスライン16を蛇行させることによって、サブ画素自体の面積を異ならせているので、1つの画素110に無駄なデッドスペースを生じさせることなく、面積が小さい第1画素電極141と、面積が大きい第2画素電極142とを1つの画素110に形成することができる。 On the other hand, in the present embodiment, the area of the sub-pixel itself is made different by meandering the gate bus line 16, so that the first area 110 has a small area without causing unnecessary dead space. One pixel electrode 141 and a second pixel electrode 142 having a large area can be formed in one pixel 110.
 これにより、1つの画素領域に2つのサブ画素が縦並びした構成を有する対向マトリクス型の液晶パネル1において、無駄なスペースを生じないマルチ画素構造が得られ、視野角特性を向上させることができる。 Thereby, in the counter matrix type liquid crystal panel 1 having a configuration in which two sub-pixels are vertically arranged in one pixel region, a multi-pixel structure that does not cause useless space can be obtained, and viewing angle characteristics can be improved. .
 なお、各画素110が、列方向に並ぶ2つのサブ画素を備えた構成に限らず、例えば、列方向に並ぶ2つのサブ画素を2組備え、1つの画素領域に4つのサブ画素を設けてもよい。 Note that each pixel 110 is not limited to a configuration including two sub-pixels arranged in the column direction. For example, two sets of two sub-pixels arranged in the column direction are provided, and four sub-pixels are provided in one pixel region. Also good.
 また、蛇行形状の中心線は、各画素110mnを列方向に等しい幅で並ぶ2つの領域に分割する2等分線であることがさらに好ましい。これにより、ゲートバスライン16が行方向に沿って蛇行するときの2等分線からの蛇行の幅を揃える構成を選択することができ、それによって、面積大の第2画素電極142と、面積小の第1画素電極141とを、一定の面積比率で、行方向に沿って配置することができる。 Further, the meandering center line is more preferably a bisector that divides each pixel 110mn into two regions arranged with the same width in the column direction. Accordingly, it is possible to select a configuration in which the width of the meander from the bisector when the gate bus line 16 meanders along the row direction can be selected, and thereby the second pixel electrode 142 having a large area, the area The small first pixel electrodes 141 can be arranged along the row direction at a constant area ratio.
 また、蛇行形状に形成されたゲートバスライン16の折曲部毎には、第1TFT121及び第2TFT122が交互に設けられている。これにより、第1TFT121及び第2TFT122の配置のレイアウトをシンプルにすることができる。 Further, the first TFT 121 and the second TFT 122 are alternately provided for each bent portion of the gate bus line 16 formed in a meandering shape. Thereby, the layout of the arrangement of the first TFT 121 and the second TFT 122 can be simplified.
 〔等価回路〕
 次に、本実施形態に係るTFT基板10の等価回路について、図4A、図4B及び図5を参照して説明する。図4Aは、本実施形態に係る液晶パネル1のTFT基板10の等価回路、及び、xフレーム表示時の液晶容量への印加電圧を示す図である。図4Bは、本実施形態に係る液晶パネル1のTFT基板10の等価回路、及び、x+1フレーム表示時の液晶容量への印加電圧を示す図である。なお、1フレームは、例えば、60Hz駆動の液晶パネルであれば、1/60秒である。図5は、図4A及び図4Bに示す第1液晶容量131及び第2液晶容量132を第1コンデンサ151及び第2コンデンサ152として表した場合のTFT基板10の等価回路を示す図である。
[Equivalent circuit]
Next, an equivalent circuit of the TFT substrate 10 according to the present embodiment will be described with reference to FIGS. 4A, 4B, and 5. FIG. FIG. 4A is a diagram showing an equivalent circuit of the TFT substrate 10 of the liquid crystal panel 1 according to the present embodiment and a voltage applied to the liquid crystal capacitor during x-frame display. FIG. 4B is a diagram showing an equivalent circuit of the TFT substrate 10 of the liquid crystal panel 1 according to the present embodiment, and a voltage applied to the liquid crystal capacitor during x + 1 frame display. For example, in the case of a liquid crystal panel driven at 60 Hz, one frame is 1/60 second. FIG. 5 is a diagram showing an equivalent circuit of the TFT substrate 10 when the first liquid crystal capacitor 131 and the second liquid crystal capacitor 132 shown in FIGS. 4A and 4B are represented as the first capacitor 151 and the second capacitor 152.
 図4A及び図4Bのように、本実施形態における液晶パネル1は、データバスライン22mとゲートバスライン16nとで画定される画素110mn(第1の画素領域)、データバスライン22(m+1)とゲートバスライン16nとで画定される画素110(m+1)n、データバスライン22(m+2)とゲートバスライン16nとで画定される画素110(m+2)n、データバスライン22mとゲートバスライン16(n+1)とで画定される画素110m(n+1)(第2の画素領域)、データバスライン22(m+1)とゲートバスライン16(n+1)とで画定される画素110(m+1)(n+1)、及び、データバスライン22(m+2)とゲートバスライン16(n+1)とで画定される画素110(m+2)(n+1)などを備えている。各画素は、それぞれ2つのサブ画素を備えている。 As shown in FIGS. 4A and 4B, the liquid crystal panel 1 according to the present embodiment includes a pixel 110mn (first pixel region) defined by the data bus line 22m and the gate bus line 16n, a data bus line 22 (m + 1), and the like. Pixel 110 (m + 1) n defined by gate bus line 16n, pixel 110 (m + 2) n defined by data bus line 22 (m + 2) and gate bus line 16n, data bus line 22m and gate bus line 16 ( n + 1) defined pixels 110m (n + 1) (second pixel region), data bus lines 22 (m + 1) and gate bus lines 16 (n + 1) defined pixels 110 (m + 1) (n + 1), and , A pixel 110 (m + 2) (n +) defined by the data bus line 22 (m + 2) and the gate bus line 16 (n + 1) ) Are and the like. Each pixel includes two sub-pixels.
 画素110mn~110(m+2)n、及び、画素110m(n+1)~110(m+2)(n+1)はそれぞれ行方向に隣接して配置され、画素110mn及び画素110m(n+1)、画素110(m+1)n及び画素110(m+1)(n+1)などはそれぞれ列方向に隣接して配置されている。 The pixels 110mn to 110 (m + 2) n and the pixels 110m (n + 1) to 110 (m + 2) (n + 1) are arranged adjacent to each other in the row direction, and the pixel 110mn, the pixel 110m (n + 1), and the pixel 110 (m + 1) n The pixels 110 (m + 1) (n + 1) and the like are arranged adjacent to each other in the column direction.
 画素110mnは、2つのサブ画素を、基準電圧バスライン18aから列方向に、第2サブ画素112mn(第1の副画素領域)、第1サブ画素111mn(第2の副画素領域)の順で備え、画素110(m+1)nは、2つのサブ画素を、基準電圧バスライン18aから列方向に、第1サブ画素111(m+1)n、第2サブ画素112(m+1)nの順で備えている。 The pixel 110mn includes two subpixels in the order of the second subpixel 112mn (first subpixel area) and the first subpixel 111mn (second subpixel area) in the column direction from the reference voltage bus line 18a. The pixel 110 (m + 1) n includes two subpixels in the column direction from the reference voltage bus line 18a in the order of the first subpixel 111 (m + 1) n and the second subpixel 112 (m + 1) n. Yes.
 また、画素110m(n+1)は、2つのサブ画素を、基準電圧バスライン18bから列方向に、第1サブ画素111m(n+1)(第3の副画素領域)、第2サブ画素112m(n+1)(第4の副画素領域)の順で備え、画素110(m+1)(n+1)は、2つのサブ画素を、基準電圧バスライン18bから列方向に、第2サブ画素112(m+1)(n+1)、第1サブ画素111(m+1)(n+1)の順で備えている。すなわち、画素110m(n+1)及び画素110(m+1)(n+1)は、基準電圧バスライン18bに関して画素110mn及び画素110(m+1)nと線対称になるように配置されている。 The pixel 110m (n + 1) includes two subpixels in the column direction from the reference voltage bus line 18b, the first subpixel 111m (n + 1) (third subpixel region) and the second subpixel 112m (n + 1). The pixel 110 (m + 1) (n + 1) includes two subpixels in the column direction from the reference voltage bus line 18b in the order of (fourth subpixel region), and the second subpixel 112 (m + 1) (n + 1) , First sub-pixels 111 (m + 1) (n + 1) in this order. That is, the pixel 110m (n + 1) and the pixel 110 (m + 1) (n + 1) are arranged to be line-symmetric with the pixel 110mn and the pixel 110 (m + 1) n with respect to the reference voltage bus line 18b.
 言い換えると、上記列方向に隣り合う2つの画素110mn及び画素110m(n+1)において、画素110mnが列方向に並ぶ第1の副画素領域としての第2サブ画素112mnと、第2の副画素領域としての第1サブ画素111mnを備え、画素110m(n+1)が列方向に並ぶ第3の副画素領域としての第1サブ画素111m(n+1)と、第4の副画素領域としての第2サブ画素112m(n+1)を備え、上記基準電圧バスライン18bは、上記列方向に隣り合う第1サブ画素111mnと第1サブ画素111m(n+1)とに共有されている。 In other words, in the two pixels 110mn and 110m (n + 1) adjacent in the column direction, the second subpixel 112mn as the first subpixel region in which the pixels 110mn are arranged in the column direction, and the second subpixel region The first sub-pixel 111m and the second sub-pixel 112m as the fourth sub-pixel region and the first sub-pixel 111m (n + 1) as the third sub-pixel region in which the pixels 110m (n + 1) are arranged in the column direction. (N + 1) and the reference voltage bus line 18b is shared by the first sub-pixel 111mn and the first sub-pixel 111m (n + 1) that are adjacent to each other in the column direction.
 これにより、列方向に隣り合う画素領域が、1つの基準電圧バスラインを共有できるので、シンプルな配線レイアウトにすることができる。 Thereby, since pixel regions adjacent in the column direction can share one reference voltage bus line, a simple wiring layout can be achieved.
 また、画素110(m+2)nは画素110mnと同様の構成であり、画素110(m+2)(n+1)は画素110m(n+1)と同様の構成である。 Further, the pixel 110 (m + 2) n has the same configuration as the pixel 110mn, and the pixel 110 (m + 2) (n + 1) has the same configuration as the pixel 110m (n + 1).
 さらに、各サブ画素は、TFT12及び液晶容量を含んでいる。なお、液晶容量は、画素電極14、データバスライン22が形成する対向電極24、及び、画素電極14と対向電極24との間に挟まれた液晶層により構成されている。図4A及び図4Bでは、液晶容量は、第1液晶容量131mn及び第2液晶容量132mnを含んでいる。なお、第1液晶容量131mn及び第2液晶容量132mnは、図5に示すように、等価回路にて第1コンデンサ151mn及び第2コンデンサ152mnと表現することができる。 Furthermore, each subpixel includes a TFT 12 and a liquid crystal capacitor. The liquid crystal capacitor includes a pixel electrode 14, a counter electrode 24 formed by the data bus line 22, and a liquid crystal layer sandwiched between the pixel electrode 14 and the counter electrode 24. 4A and 4B, the liquid crystal capacitors include a first liquid crystal capacitor 131mn and a second liquid crystal capacitor 132mn. As shown in FIG. 5, the first liquid crystal capacitor 131mn and the second liquid crystal capacitor 132mn can be expressed as a first capacitor 151mn and a second capacitor 152mn in an equivalent circuit.
 図4A及び図4Bに示すように、画素110mnの第1サブ画素111mnが備える第1TFT121mnのゲート端子はゲートバスライン16nに接続され、ソース端子は基準電圧バスライン18bに接続され、ドレイン端子は第1液晶容量131mnを介してデータバスライン22mに接続されている。 4A and 4B, the gate terminal of the first TFT 121mn included in the first sub-pixel 111mn of the pixel 110mn is connected to the gate bus line 16n, the source terminal is connected to the reference voltage bus line 18b, and the drain terminal is connected to the first terminal. One liquid crystal capacitor 131mn is connected to the data bus line 22m.
 また、第2サブ画素112mnが備える第2TFT122mnのゲート端子はゲートバスライン16nに接続され、ソース端子は基準電圧バスライン18aに接続され、ドレイン端子は第2液晶容量132mnを介してデータバスライン22mに接続されている。 In addition, the gate terminal of the second TFT 122mn included in the second subpixel 112mn is connected to the gate bus line 16n, the source terminal is connected to the reference voltage bus line 18a, and the drain terminal is connected to the data bus line 22m via the second liquid crystal capacitor 132mn. It is connected to the.
 画素110(m+1)nの第1サブ画素111(m+1)nが備える第1TFT121(m+1)nのゲート端子はゲートバスライン16nに接続され、ソース端子は基準電圧バスライン18aに接続され、ドレイン端子は第1液晶容量131(m+1)nを介してデータバスライン22(m+1)に接続されている。 The gate terminal of the first TFT 121 (m + 1) n included in the first sub-pixel 111 (m + 1) n of the pixel 110 (m + 1) n is connected to the gate bus line 16n, the source terminal is connected to the reference voltage bus line 18a, and the drain terminal. Is connected to the data bus line 22 (m + 1) through the first liquid crystal capacitor 131 (m + 1) n.
 また、第2サブ画素112(m+1)nが備える第2TFT122(m+1)nのゲート端子はゲートバスライン16nに接続され、ソース端子は基準電圧バスライン18bに接続され、ドレイン端子は第2液晶容量132(m+1)nを介してデータバスライン22(m+1)に接続されている。 The second TFT 122 (m + 1) n included in the second subpixel 112 (m + 1) n has a gate terminal connected to the gate bus line 16n, a source terminal connected to the reference voltage bus line 18b, and a drain terminal connected to the second liquid crystal capacitor. It is connected to the data bus line 22 (m + 1) through 132 (m + 1) n.
 また、画素110(m+2)nの第1サブ画素111(m+2)n及び第2サブ画素112(m+2)nは、第1TFT121(m+2)n及び第2TFT122(m+2)nのドレイン端子が、第1液晶容量131(m+2)n及び第2液晶容量132(m+2)nを介してデータバスライン22(m+2)に接続されること以外は、第1サブ画素111mn及び第2サブ画素112mnと同じ構成である。 The first sub-pixel 111 (m + 2) n and the second sub-pixel 112 (m + 2) n of the pixel 110 (m + 2) n have the drain terminals of the first TFT 121 (m + 2) n and the second TFT 122 (m + 2) n as the first. Except for being connected to the data bus line 22 (m + 2) via the liquid crystal capacitor 131 (m + 2) n and the second liquid crystal capacitor 132 (m + 2) n, it has the same configuration as the first sub-pixel 111mn and the second sub-pixel 112mn. is there.
 なお、液晶パネル1が赤緑青の三原色のカラー表示を行う場合には、例えば、画素110mnが赤に相当し、画素110(m+1)nが緑に相当し、画素110(m+2)nが青に相当すればよいが、これに限定されるものではない。 When the liquid crystal panel 1 performs color display of the three primary colors of red, green, and blue, for example, the pixel 110mn corresponds to red, the pixel 110 (m + 1) n corresponds to green, and the pixel 110 (m + 2) n becomes blue. However, the present invention is not limited to this.
 〔液晶パネルの動作〕
 次に、本実施形態に係る液晶パネル1の動作について、図4A、図4B及び図6を参照して説明する。図6は、本実施形態に係る液晶パネル1の動作を示すタイミングチャートである。ここでは、x番目のフレーム(xフレーム)を表示する際の、図4Aに示す第1サブ画素111mnの動作を例に挙げて説明する。
[Operation of LCD panel]
Next, the operation of the liquid crystal panel 1 according to the present embodiment will be described with reference to FIGS. 4A, 4B, and 6. FIG. FIG. 6 is a timing chart showing the operation of the liquid crystal panel 1 according to the present embodiment. Here, the operation of the first sub pixel 111mn shown in FIG. 4A when displaying the xth frame (x frame) will be described as an example.
 (xフレーム)
 図6に示すように、時刻tx1においてxフレームの表示が開始されると、x-1フレームを表示する際にLレベルに制御されていた基準電圧バスライン18aの基準電圧がHレベルに制御され、x-1フレームを表示する際にHレベルに制御されていた基準電圧バスライン18bの基準電圧がLレベルに制御される。また、時刻tx1では、1本目のゲートバスライン16が走査される。なお、本実施形態では、Hレベルの基準電圧を+1V、Lレベルの基準電圧を0Vとしているが、これに限定されるものではない。
(X frame)
As shown in FIG. 6, when the display of the x frame is started at time tx1, the reference voltage of the reference voltage bus line 18a that was controlled to the L level when the x-1 frame was displayed is controlled to the H level. , The reference voltage of the reference voltage bus line 18b that has been controlled to the H level when the x-1 frame is displayed is controlled to the L level. At time tx1, the first gate bus line 16 is scanned. In this embodiment, the H level reference voltage is set to +1 V and the L level reference voltage is set to 0 V. However, the present invention is not limited to this.
 時刻txnにおいて、m本目のデータバスライン22mが+5Vに制御され、n本目のゲートバスライン16nが走査されると、第1TFT121mn及び第2TFT122mnのゲート端子に走査信号が供給され、第1TFT121mn及び第2TFT122mnがON状態になる。同様に、第1TFT121(m+1)n、第2TFT122(m+1)n、第1TFT121(m+2)n、及び、第2TFT122(m+2)nのゲート端子にも走査信号が供給され、ON状態になる。 At time txn, when the m-th data bus line 22m is controlled to + 5V and the n-th gate bus line 16n is scanned, a scanning signal is supplied to the gate terminals of the first TFT 121mn and the second TFT 122mn, and the first TFT 121mn and the second TFT 122mn. Turns on. Similarly, a scanning signal is also supplied to the gate terminals of the first TFT 121 (m + 1) n, the second TFT 122 (m + 1) n, the first TFT 121 (m + 2) n, and the second TFT 122 (m + 2) n, and is turned on.
 データバスライン22mから+5Vのデータ信号が供給されることにより、画素110mnの第1液晶容量131mnのnodeX(すなわち、第1液晶容量131mnの対向電極側)に、データバスライン22mと同電圧の+5Vが印加される。また、第1液晶容量131mnのnodeY(すなわち、第1液晶容量131mnの画素電極側)には、基準電圧バスライン18bと同電圧の0Vが印加される。これによって、第1液晶容量131mnには、図4Aに示すように、第1液晶容量131mnのnodeXとnodeYとの電位差nodeX-nodeY、すなわち、対向電極と画素電極との電位差である+5Vが印加されることになる。 When a data signal of +5 V is supplied from the data bus line 22m, + 5V of the same voltage as that of the data bus line 22m is supplied to the nodeX of the first liquid crystal capacitor 131mn of the pixel 110mn (that is, the counter electrode side of the first liquid crystal capacitor 131mn). Is applied. Further, 0V, which is the same voltage as the reference voltage bus line 18b, is applied to nodeY of the first liquid crystal capacitor 131mn (that is, the pixel electrode side of the first liquid crystal capacitor 131mn). Accordingly, as shown in FIG. 4A, the first liquid crystal capacitor 131mn is applied with a potential difference nodeX−nodeY between nodeX and nodeY of the first liquid crystal capacitor 131mn, that is, + 5V that is a potential difference between the counter electrode and the pixel electrode. Will be.
 また、データバスライン22mから+5Vのデータ信号が供給されることにより、画素110mnの第2液晶容量132mnのnodeXに+5Vが印加され、nodeYには基準電圧バスライン18aと同電圧の+1Vが印加される。これによって、第2液晶容量132mnには、第2液晶容量132mnのnodeXとnodeYとの電位差である+4Vが印加されることになる。 Further, by supplying a data signal of + 5V from the data bus line 22m, + 5V is applied to nodeX of the second liquid crystal capacitor 132mn of the pixel 110mn, and + 1V of the same voltage as that of the reference voltage bus line 18a is applied to nodeY. The As a result, +4 V, which is the potential difference between nodeX and nodeY of the second liquid crystal capacitor 132mn, is applied to the second liquid crystal capacitor 132mn.
 同様に、時刻txnにおいて、データバスライン22(m+1)が-4Vに制御されると、画素110(m+1)nの第1液晶容量131(m+1)nの印加電圧は-5Vになり、第2液晶容量132(m+1)nの印加電圧は-4Vになる。また、データバスライン22(m+2)が+5Vに制御されると、画素110(m+2)nの第1液晶容量131(m+2)nの印加電圧は+5Vになり、第2液晶容量132(m+2)nの印加電圧は+4Vになる。 Similarly, when the data bus line 22 (m + 1) is controlled to −4V at time txn, the applied voltage of the first liquid crystal capacitor 131 (m + 1) n of the pixel 110 (m + 1) n becomes −5V, and the second The applied voltage of the liquid crystal capacitor 132 (m + 1) n is −4V. When the data bus line 22 (m + 2) is controlled to + 5V, the voltage applied to the first liquid crystal capacitor 131 (m + 2) n of the pixel 110 (m + 2) n becomes + 5V, and the second liquid crystal capacitor 132 (m + 2) n. The applied voltage becomes + 4V.
 次に、時刻tx(n+1)において、n本目のゲートバスライン16nの走査が停止され、新たにn+1本目のゲートバスライン16(n+1)が走査されると、第1TFT121m(n+1)及び第2TFT122m(n+1)のゲート端子に走査信号が供給され、ON状態になる。同様に、第1TFT121(m+1)(n+1)、第2TFT122(m+1)(n+1)、第1TFT121(m+2)(n+1)、及び、第2TFT122(m+2)(n+1)のゲート端子にも走査信号が供給され、ON状態になる。 Next, at time tx (n + 1), scanning of the nth gate bus line 16n is stopped, and when the n + 1th gate bus line 16 (n + 1) is newly scanned, the first TFT 121m (n + 1) and the second TFT 122m ( A scanning signal is supplied to the gate terminal of (n + 1), and is turned on. Similarly, a scanning signal is supplied to the gate terminals of the first TFT 121 (m + 1) (n + 1), the second TFT 122 (m + 1) (n + 1), the first TFT 121 (m + 2) (n + 1), and the second TFT 122 (m + 2) (n + 1). , Will be in the ON state.
 また、時刻tx(n+1)においてm本目のデータバスライン22mが+4Vに制御されると、第1液晶容量131m(n+1)のnodeXに、データバスライン22mと同電圧の+4Vが印加される。また、第1液晶容量131m(n+1)のnodeYには、基準電圧バスライン18bと同電圧の0Vが印加される。これによって、図4Aに示すように、第1液晶容量131m(n+1)には、nodeXとnodeYとの電位差nodeX-nodeYである+4Vが印加されることになる。 Further, when the m-th data bus line 22m is controlled to + 4V at time tx (n + 1), + 4V, which is the same voltage as the data bus line 22m, is applied to nodeX of the first liquid crystal capacitor 131m (n + 1). In addition, 0V of the same voltage as that of the reference voltage bus line 18b is applied to nodeY of the first liquid crystal capacitor 131m (n + 1). As a result, as shown in FIG. 4A, + 4V which is a potential difference nodeX−nodeY between nodeX and nodeY is applied to the first liquid crystal capacitor 131m (n + 1).
 また、データバスライン22mから+4Vのデータ信号が供給されることにより、第2液晶容量132m(n+1)のnodeXには+4Vが印加され、nodeYには基準電圧バスライン18aと同電圧の+1Vが印加される。これによって、第2液晶容量132m(n+1)には、nodeXとnodeYとの電位差である+3Vが印加されることになる。 In addition, by supplying a data signal of + 4V from the data bus line 22m, + 4V is applied to nodeX of the second liquid crystal capacitor 132m (n + 1), and + 1V of the same voltage as the reference voltage bus line 18a is applied to nodeY. Is done. As a result, +3 V, which is a potential difference between nodeX and nodeY, is applied to the second liquid crystal capacitor 132m (n + 1).
 同様に、時刻tx(n+1)において、データバスライン22(m+1)が-3Vに制御されると、第1液晶容量131(m+1)(n+1)の印加電圧は-4Vになり、第2液晶容量132(m+1)(n+1)の印加電圧は-3Vになる。また、時刻tx(n+1)において、データバスライン22(m+2)が+4Vに制御されると、第1液晶容量131(m+2)(n+1)は+4Vになり、第2液晶容量132(m+2)(n+1)は+3Vになる。 Similarly, when the data bus line 22 (m + 1) is controlled to −3V at time tx (n + 1), the applied voltage of the first liquid crystal capacitor 131 (m + 1) (n + 1) becomes −4V, and the second liquid crystal capacitor The applied voltage of 132 (m + 1) (n + 1) is −3V. At time tx (n + 1), when the data bus line 22 (m + 2) is controlled to + 4V, the first liquid crystal capacitor 131 (m + 2) (n + 1) becomes + 4V, and the second liquid crystal capacitor 132 (m + 2) (n + 1). ) Becomes + 3V.
 これに対し、時刻tx(n+1)において、n本目のゲートバスライン16nの走査が停止されることにより、第1TFT121mn及び第2TFT122mnのゲート端子への走査信号の供給が停止され、第1TFT121mn及び第2TFT122mnはOFF状態になる。これによって、第1液晶容量131mn及び第2液晶容量132mnはフローティング状態になる。 On the other hand, at time tx (n + 1), scanning of the nth gate bus line 16n is stopped, whereby supply of scanning signals to the gate terminals of the first TFT 121mn and the second TFT 122mn is stopped, and the first TFT 121mn and the second TFT 122mn. Becomes OFF. As a result, the first liquid crystal capacitor 131mn and the second liquid crystal capacitor 132mn are in a floating state.
 時刻tx(n+1)においては、データバスライン22mが+4Vに制御されているため、第1液晶容量131mnのnodeX側にデータバスライン22mと同じ+4Vが印加される。さらに、第1液晶容量131mnはフローティング状態であるため、時刻txnにおける第1液晶容量131mnのnodeX側の電圧とnodeY側の電圧との電位差+5Vを維持するよう、nodeY側の電圧が-1Vに遷移する。 At time tx (n + 1), since the data bus line 22m is controlled to + 4V, the same + 4V as the data bus line 22m is applied to the nodeX side of the first liquid crystal capacitor 131mn. Further, since the first liquid crystal capacitor 131mn is in a floating state, the voltage on the node Y side transitions to −1V so that the potential difference + 5V between the nodeX side voltage and the nodeY side voltage of the first liquid crystal capacitor 131mn at time txn is maintained. To do.
 これにより、時刻tx(n+1)において、第1液晶容量131mnの電圧は変化せず、時刻txnにおいて印加された電圧が維持される。すなわち、xフレームを表示するためにゲートバスライン16nが走査されることで第1液晶容量131mnに印加された電圧は、x+1フレームを表示するために、再びゲートバスライン16nが走査されるまで、維持されることになる。 Thereby, at time tx (n + 1), the voltage of the first liquid crystal capacitor 131mn does not change, and the voltage applied at time txn is maintained. That is, the voltage applied to the first liquid crystal capacitor 131mn when the gate bus line 16n is scanned to display the x frame until the gate bus line 16n is scanned again to display the x + 1 frame. Will be maintained.
 第2液晶容量132mn、第1液晶容量131(m+1)n、第2液晶容量132(m+1)n、第1液晶容量131(m+2)n、及び、第2液晶容量132(m+2)nも同様に、時刻tx(n+1)においても、時刻txnにおいて印加された電圧が維持される。 Similarly, the second liquid crystal capacitor 132mn, the first liquid crystal capacitor 131 (m + 1) n, the second liquid crystal capacitor 132 (m + 1) n, the first liquid crystal capacitor 131 (m + 2) n, and the second liquid crystal capacitor 132 (m + 2) n. At time tx (n + 1), the voltage applied at time txn is maintained.
 (x+1フレーム)
 TFT基板10に形成されるN本全てのゲートバスライン16に対して、xフレームを表示するための走査が行われると、次に、x+1フレームを表示するための走査が開始される。図6に示すように、時刻t(x+1)1においてx+1フレームの表示が開始されると、xフレームを表示する際にHレベルに制御されていた基準電圧バスライン18aの基準電圧がLレベルに制御され、xフレームを表示する際にLレベルに制御されていた基準電圧バスライン18bの基準電圧がHレベルに制御される。また、時刻t(x+1)1から時刻t(x+1)2までの間、1本目のゲートバスライン16が走査される。データバスライン22には、1フレーム前のxフレームでの極性を反転させたデータ信号が供給される。
(X + 1 frame)
When scanning for displaying x frames is performed on all N gate bus lines 16 formed on the TFT substrate 10, scanning for displaying x + 1 frames is started. As shown in FIG. 6, when the display of the x + 1 frame is started at time t (x + 1) 1, the reference voltage of the reference voltage bus line 18a that has been controlled to the H level when the x frame is displayed becomes the L level. The reference voltage of the reference voltage bus line 18b that is controlled and controlled to the L level when displaying the x frame is controlled to the H level. Further, the first gate bus line 16 is scanned from time t (x + 1) 1 to time t (x + 1) 2. The data bus line 22 is supplied with a data signal in which the polarity of the previous x frame is inverted.
 時刻t(x+1)nにおいて、m本目のデータバスライン22mが-4Vに制御され、n本目のゲートバスライン16nが走査されると、第1TFT121mn及び第2TFT122mnのゲート端子に走査信号が供給され、第1TFT121mn及び第2TFT122mnはON状態になる。同様に、第1TFT121(m+1)n、第2TFT122(m+1)n、第1TFT121(m+2)n、及び、第2TFT122(m+2)nのゲート端子にも走査信号が供給され、ON状態になる。 At time t (x + 1) n, when the m-th data bus line 22m is controlled to −4V and the n-th gate bus line 16n is scanned, a scanning signal is supplied to the gate terminals of the first TFT 121mn and the second TFT 122mn, The first TFT 121mn and the second TFT 122mn are turned on. Similarly, a scanning signal is also supplied to the gate terminals of the first TFT 121 (m + 1) n, the second TFT 122 (m + 1) n, the first TFT 121 (m + 2) n, and the second TFT 122 (m + 2) n, and is turned on.
 データバスライン22mから-4Vのデータ信号が供給されることにより、画素110mnの第1液晶容量131mnのnodeXに、データバスライン22mと同電圧の-4Vが印加される。また、第1液晶容量131mnのnodeYには、基準電圧バスライン18bと同電圧の+1Vが印加される。これによって、第1液晶容量131mnには、図4Bに示すように、第1液晶容量131mnのnodeXとnodeYとの電位差nodeX-nodeYである-5Vが印加されることになる。 When a data signal of −4V is supplied from the data bus line 22m, −4V of the same voltage as the data bus line 22m is applied to the nodeX of the first liquid crystal capacitor 131mn of the pixel 110mn. Further, + 1V of the same voltage as the reference voltage bus line 18b is applied to nodeY of the first liquid crystal capacitor 131mn. As a result, as shown in FIG. 4B, −5V that is a potential difference nodeX−nodeY between nodeX and nodeY of the first liquid crystal capacitor 131mn is applied to the first liquid crystal capacitor 131mn.
 また、データバスライン22mから-4Vのデータ信号が供給されることにより、画素110mnの第2液晶容量132mnのnodeXに-4Vが印加され、nodeYには基準電圧バスライン18aと同電圧の0Vが印加される。これによって、第2液晶容量132mnには、第2液晶容量132mnのnodeXとnodeYとの電位差である-4Vが印加されることになる。 Further, by supplying a −4V data signal from the data bus line 22m, −4V is applied to the node X of the second liquid crystal capacitor 132mn of the pixel 110mn, and 0V of the same voltage as the reference voltage bus line 18a is applied to the node Y. Applied. As a result, −4V that is a potential difference between nodeX and nodeY of the second liquid crystal capacitor 132mn is applied to the second liquid crystal capacitor 132mn.
 同様に、時刻t(x+1)nにおいて、データバスライン22(m+1)が+5Vに制御されると、画素110(m+1)nの第1液晶容量131(m+1)nは+5Vになり、第2液晶容量132(m+1)nは+4Vになる。また、データバスライン22(m+2)が-4Vに制御されると、画素110(m+2)nの第1液晶容量131(m+2)nは-5Vになり、第2液晶容量132(m+2)nは-4Vになる。 Similarly, when the data bus line 22 (m + 1) is controlled to + 5V at time t (x + 1) n, the first liquid crystal capacitor 131 (m + 1) n of the pixel 110 (m + 1) n becomes + 5V, and the second liquid crystal The capacity 132 (m + 1) n is + 4V. When the data bus line 22 (m + 2) is controlled to −4V, the first liquid crystal capacitor 131 (m + 2) n of the pixel 110 (m + 2) n becomes −5V, and the second liquid crystal capacitor 132 (m + 2) n is -4V.
 次に、時刻t(x+1)(n+1)において、n本目のゲートバスライン16nの走査が停止され、新たにn+1本目のゲートバスライン16(n+1)が走査されると、第1TFT121m(n+1)及び第2TFT122m(n+1)のゲート端子に走査信号が供給され、ON状態になる。同様に、第1TFT121(m+1)(n+1)、第2TFT122(m+1)(n+1)、第1TFT121(m+2)(n+1)、及び、第2TFT122(m+2)(n+1)のゲート端子にも走査信号が供給され、ON状態になる。 Next, at time t (x + 1) (n + 1), scanning of the nth gate bus line 16n is stopped, and when the n + 1th gate bus line 16 (n + 1) is newly scanned, the first TFT 121m (n + 1) and A scanning signal is supplied to the gate terminal of the second TFT 122m (n + 1), and the second TFT 122m (n + 1) is turned on. Similarly, a scanning signal is supplied to the gate terminals of the first TFT 121 (m + 1) (n + 1), the second TFT 122 (m + 1) (n + 1), the first TFT 121 (m + 2) (n + 1), and the second TFT 122 (m + 2) (n + 1). , Will be in the ON state.
 また、時刻t(x+1)(n+1)においてm本目のデータバスライン22mが-3Vに制御されると、第1液晶容量131m(n+1)のnodeXに、データバスライン22mと同電圧の-3Vが印加される。また、第1液晶容量131m(n+1)のnodeYには、基準電圧バスライン18bと同電圧の+1Vが印加される。これによって、図4Bに示すように、第1液晶容量131m(n+1)には、nodeXとnodeYとの電位差nodeX-nodeYである-4Vが印加されることになる。 Further, when the m-th data bus line 22m is controlled to -3V at time t (x + 1) (n + 1), -3V having the same voltage as the data bus line 22m is applied to nodeX of the first liquid crystal capacitor 131m (n + 1). Applied. Further, + 1V of the same voltage as that of the reference voltage bus line 18b is applied to nodeY of the first liquid crystal capacitor 131m (n + 1). As a result, as shown in FIG. 4B, −4V that is a potential difference nodeX−nodeY between nodeX and nodeY is applied to the first liquid crystal capacitor 131m (n + 1).
 また、データバスライン22mから-3Vのデータ信号が供給されることにより、第2液晶容量132m(n+1)のnodeXには-3Vが印加され、nodeYには基準電圧バスライン18aと同電圧の0Vが印加される。これによって、第2液晶容量132mnは、nodeXとnodeYとの電位差である-3Vが印加されることになる。 Further, by supplying a -3V data signal from the data bus line 22m, -3V is applied to nodeX of the second liquid crystal capacitor 132m (n + 1), and 0V of the same voltage as the reference voltage bus line 18a is applied to nodeY. Is applied. As a result, −3 V, which is the potential difference between nodeX and nodeY, is applied to the second liquid crystal capacitor 132mn.
 同様に、時刻t(x+1)(n+1)において、データバスライン22(m+1)が+4Vに制御されると、画素110(m+1)(n+1)の第1液晶容量131(m+1)(n+1)は+4Vになり、第2液晶容量132(m+1)(n+1)は+3Vになる。また、データバスライン22(m+2)が-3Vに制御されると、画素110(m+2)(n+1)の第1液晶容量131(m+2)(n+1)は-4Vになり、第2液晶容量132(m+2)(n+1)は-3Vになる。 Similarly, when the data bus line 22 (m + 1) is controlled to + 4V at time t (x + 1) (n + 1), the first liquid crystal capacitor 131 (m + 1) (n + 1) of the pixel 110 (m + 1) (n + 1) has + 4V. Thus, the second liquid crystal capacitance 132 (m + 1) (n + 1) becomes + 3V. When the data bus line 22 (m + 2) is controlled to −3V, the first liquid crystal capacitor 131 (m + 2) (n + 1) of the pixel 110 (m + 2) (n + 1) becomes −4V, and the second liquid crystal capacitor 132 ( m + 2) (n + 1) becomes −3V.
 これに対し、時刻t(x+1)(n+1)において、n本目のゲートバスライン16nの走査が停止されることにより、第1TFT121mn及び第2TFT122mnのゲート端子への走査信号の供給が停止され、第1TFT121mn及び第2TFT122mnはOFF状態になる。これによって、第1液晶容量131mn及び第2液晶容量132mnはフローティング状態になる。 On the other hand, at time t (x + 1) (n + 1), scanning of the nth gate bus line 16n is stopped, whereby supply of scanning signals to the gate terminals of the first TFT 121mn and the second TFT 122mn is stopped, and the first TFT 121mn. The second TFT 122mn is turned off. As a result, the first liquid crystal capacitor 131mn and the second liquid crystal capacitor 132mn are in a floating state.
 時刻t(x+1)(n+1)においては、データバスライン22mが-3Vに制御されているため、第1液晶容量131mnのnodeX側にデータバスライン22mと同じ-3Vが印加される。さらに、第1液晶容量131mnはフローティング状態であるため、時刻txnにおける第1液晶容量131mnのnodeX側の電圧とnodeY側の電圧との電位差-4Vを維持するよう、nodeY側の電圧が+1Vに遷移する。 At time t (x + 1) (n + 1), since the data bus line 22m is controlled to -3V, the same -3V as the data bus line 22m is applied to the nodeX side of the first liquid crystal capacitor 131mn. Further, since the first liquid crystal capacitor 131 mn is in a floating state, the voltage on the node Y side transitions to +1 V so as to maintain the potential difference −4 V between the voltage on the node X side and the voltage on the node Y side of the first liquid crystal capacitor 131 mn at time txn. To do.
 これにより、時刻t(x+1)(n+1)において、第1液晶容量131mnの電圧は変化せず、時刻t(x+1)nにおいて印加された電圧が維持される。すなわち、x+1フレームを表示するためにゲートバスライン16nが走査されることで第1液晶容量131mnに印加された電圧は、x+1フレームを表示するために、再びゲートバスライン16nが走査されるまで、維持されることになる。 Thus, at time t (x + 1) (n + 1), the voltage of the first liquid crystal capacitor 131mn does not change, and the voltage applied at time t (x + 1) n is maintained. That is, the voltage applied to the first liquid crystal capacitor 131mn when the gate bus line 16n is scanned to display the x + 1 frame until the gate bus line 16n is scanned again to display the x + 1 frame. Will be maintained.
 以上のように、本実施形態に係る液晶パネル1の駆動方法は、図4A、図4B及び図6に基づいて説明した構成を有する液晶パネル1における駆動方法であって、列方向に並ぶ第1サブ画素111mn及び第2サブ画素112mnのうち、一方のサブ画素に対応した基準電圧バスライン18と、他方のサブ画素に対応した基準電圧バスライン18bに印加する電圧を相違させることによって、データバスライン22m及び基準電圧バスライン18a間の電位差と、データバスライン22m及び基準電圧バスライン18b間の電位差とを相違させることを特徴としている。 As described above, the driving method of the liquid crystal panel 1 according to the present embodiment is the driving method in the liquid crystal panel 1 having the configuration described based on FIGS. 4A, 4B, and 6, and is the first that is arranged in the column direction. By making the voltage applied to the reference voltage bus line 18 corresponding to one subpixel out of the subpixel 111mn and the second subpixel 112mn different from the voltage applied to the reference voltage bus line 18b corresponding to the other subpixel, the data bus The potential difference between the line 22m and the reference voltage bus line 18a is different from the potential difference between the data bus line 22m and the reference voltage bus line 18b.
 これにより、一方の画素の液晶層には、データバスライン22mと基準電圧バスライン18aとの電位差が印加される一方、他方のサブ画素の液晶層には、データバスライン22mと基準電圧バスライン18bとの電位差が印加される。 Thus, a potential difference between the data bus line 22m and the reference voltage bus line 18a is applied to the liquid crystal layer of one pixel, while the data bus line 22m and the reference voltage bus line are applied to the liquid crystal layer of the other sub-pixel. A potential difference from 18b is applied.
 このとき、それぞれの電位差を相違させているから、第1サブ画素111mnの液晶層にかかる電圧と、第2サブ画素112mnの液晶層にかかる電圧とを相違させることができる。 At this time, since the respective potential differences are made different, the voltage applied to the liquid crystal layer of the first sub-pixel 111 mn can be made different from the voltage applied to the liquid crystal layer of the second sub-pixel 112 mn.
 これにより、データバスライン22mに書き込んだ電圧に対して、第1サブ画素111mnにおける液晶分子の配向状態と、第2サブ画素112mnにおける液晶分子の配向状態とを相違させることができる結果、対向マトリクス型の液晶パネル1における視野角特性を向上させることができる。 As a result, the alignment state of the liquid crystal molecules in the first sub pixel 111mn and the alignment state of the liquid crystal molecules in the second sub pixel 112mn can be made different from each other with respect to the voltage written to the data bus line 22m. The viewing angle characteristics of the liquid crystal panel 1 can be improved.
 なお、上記ゲートバスラインを蛇行形状とすることによって、上記2つの副画素領域の面積は異なっている。この場合、あるデータバスラインに対応した2つの副画素領域の一方の副画素領域の面積が、他方の副画素領域の面積より小さいとすると、上記あるデータバスラインに隣り合うデータバスラインに対応した2つの副画素領域の一方の副画素領域の面積は、他方の副画素領域の面積より大きくなる。 Note that the areas of the two sub-pixel regions are different by making the gate bus line meandering. In this case, if the area of one subpixel area of two subpixel areas corresponding to a certain data bus line is smaller than the area of the other subpixel area, it corresponds to the data bus line adjacent to the data bus line. The area of one of the two subpixel areas is larger than the area of the other subpixel area.
 <実施形態2>
 本発明の他の実施形態について図8から図11に基づいて以下に説明する。なお、説明の便宜上、実施形態1に係る構成要素と同様の機能を有する構成要素には同一の番号を付し、その説明を省略する。本実施形態では、主に、実施形態1との相違点について説明するものとする。
<Embodiment 2>
Another embodiment of the present invention will be described below with reference to FIGS. For convenience of explanation, components having the same functions as those of the components according to the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. In the present embodiment, differences from the first embodiment will be mainly described.
 図8は本実施形態に係る液晶パネル2のTFT基板10の構成の概略を示す上面図である。図8に示すように、各ゲートバスライン16’間の間隔が狭く、データバスライン22’の幅が異なり、不図示の基準電圧バスライン18’がゲートバスライン16’と交差するように配置されていること以外は、実施形態1の液晶パネル1と同じ構成である。 FIG. 8 is a top view schematically showing the configuration of the TFT substrate 10 of the liquid crystal panel 2 according to this embodiment. As shown in FIG. 8, the interval between the gate bus lines 16 ′ is narrow, the width of the data bus line 22 ′ is different, and the reference voltage bus line 18 ′ (not shown) is arranged to intersect the gate bus line 16 ′. Except for this, the configuration is the same as that of the liquid crystal panel 1 of the first embodiment.
 〔TFT基板のレイアウト〕
 本実施形態に係る液晶パネル2のTFT基板10のレイアウトの詳細を、図9を参照して説明する。図9は、本実施形態に係る液晶パネル2のTFT基板10のレイアウトを示す上面図である。なお、図9において、対向基板20に形成された総数M本のデータバスライン22’のうち、m本目のデータバスライン22m’の付近に配置されたデータバスライン22m’~22(m+4)’を破線で示している。
[TFT substrate layout]
Details of the layout of the TFT substrate 10 of the liquid crystal panel 2 according to the present embodiment will be described with reference to FIG. FIG. 9 is a top view showing a layout of the TFT substrate 10 of the liquid crystal panel 2 according to the present embodiment. In FIG. 9, of the total number M of data bus lines 22 ′ formed on the counter substrate 20, data bus lines 22m ′ to 22 (m + 4) ′ arranged near the m-th data bus line 22m ′. Is indicated by a broken line.
 図9に示すように、液晶パネル2は、総数N本のゲートバスライン16’のうち、n本目のゲートバスライン16n’と、m本目のデータバスライン22m’及びm+1本目のデータバスライン22(m+1)’とにより画定される画素210mnを備えている。画素210mnは、第1サブ画素211mnと第2サブ画素212(m+1)nとを備えている。 As shown in FIG. 9, the liquid crystal panel 2 includes an nth gate bus line 16n ′, an mth data bus line 22m ′, and an m + 1th data bus line 22 out of a total of N gate bus lines 16 ′. The pixel 210mn defined by (m + 1) ′. The pixel 210mn includes a first sub-pixel 211mn and a second sub-pixel 212 (m + 1) n.
 第1サブ画素211mnは、第1画素電極241mnと第1TFT221mnとを備えている。第2サブ画素212(m+1)nは、第2画素電極242(m+1)nと第2TFT222(m+1)nとを備えている。また、図9に示すように、1つの画素210の領域において、第1サブ画素211と第2サブ画素212とは、行方向に配列している。 The first subpixel 211mn includes a first pixel electrode 241mn and a first TFT 221mn. The second sub pixel 212 (m + 1) n includes a second pixel electrode 242 (m + 1) n and a second TFT 222 (m + 1) n. Further, as shown in FIG. 9, in the area of one pixel 210, the first sub-pixel 211 and the second sub-pixel 212 are arranged in the row direction.
 なお、図9に示すように、本実施形態における液晶パネル1のTFT基板10は、第1サブ画素211に対する第2サブ画素212の面積比が、1より大きく4以下になるように構成されていることが好ましい。 As shown in FIG. 9, the TFT substrate 10 of the liquid crystal panel 1 in this embodiment is configured such that the area ratio of the second subpixel 212 to the first subpixel 211 is greater than 1 and 4 or less. Preferably it is.
 これによって、面積の小さい第1サブ画素211におけるデータバスライン22’及び基準電圧バスライン18’間の電位差を、面積の大きい第2サブ画素212における電位差より大きくするので、第1サブ画素211の液晶層にかかる電圧は、第2サブ画素212の液晶層に比べて、早く液晶のしきい値を超える。すなわち、第1サブ画素211の液晶層にかかる電圧が、液晶のしきい値を超える時点では、第2サブ画素212の液晶層にかかる電圧は、液晶のしきい値を超えていない。 Accordingly, the potential difference between the data bus line 22 ′ and the reference voltage bus line 18 ′ in the first sub-pixel 211 having a small area is made larger than the potential difference in the second sub-pixel 212 having a large area. The voltage applied to the liquid crystal layer exceeds the threshold value of the liquid crystal earlier than the liquid crystal layer of the second subpixel 212. In other words, when the voltage applied to the liquid crystal layer of the first sub-pixel 211 exceeds the threshold value of the liquid crystal, the voltage applied to the liquid crystal layer of the second sub-pixel 212 does not exceed the threshold value of the liquid crystal.
 この場合、面積の大きい第2サブ画素212が発光を開始する前に、第1サブ画素211が低階調領域の色から先に表示し始め、第2サブ画素212より高い輝度に到達し、第2サブ画素212はあとから中間調領域から高階調領域の発光量を補うように発光する。つまり、面積の小さい第1サブ画素211は、低階調から中間調の表示に主に寄与する一方、面積の大きい第2サブ画素212は、中間調から高階調の表示に主に寄与する。このようにすると、視野角特性を所望の特性に制御しやすくなる。 In this case, before the second sub-pixel 212 having a large area starts light emission, the first sub-pixel 211 starts to display the color of the low gradation region first, reaches a higher luminance than the second sub-pixel 212, The second sub-pixel 212 emits light so as to compensate for the amount of light emission from the halftone area to the high gradation area. That is, the first sub-pixel 211 having a small area mainly contributes to display from a low gradation to a halftone, while the second sub-pixel 212 having a large area mainly contributes to display from a halftone to a high gradation. This makes it easy to control the viewing angle characteristic to a desired characteristic.
 また、人の視覚は、高階調領域の色よりも低階調領域の色に敏感に反応するため、低階調領域を面積の小さい第1サブ画素211にする方が、低階調領域を面積の大きい第2サブ画素212にするよりも、視野角特性をより向上させることができる。 In addition, since human vision reacts more sensitively to the color of the low gradation region than to the color of the high gradation region, the low gradation region is less affected when the low gradation region is the first sub-pixel 211 having a smaller area. The viewing angle characteristics can be further improved as compared with the second sub-pixel 212 having a large area.
 しかも、第1サブ画素211及び第2サブ画素212のそれぞれにデータバスライン22’を設けたので、1つの画素210に備えられた2つのサブ画素211、212に、任意の極性及び任意の値の電圧を印加することができる。 In addition, since the data bus line 22 ′ is provided in each of the first sub-pixel 211 and the second sub-pixel 212, the two sub-pixels 211 and 212 included in one pixel 210 have an arbitrary polarity and an arbitrary value. Can be applied.
 これにより、1つの画素210に2つのサブ画素211、212が横並びした構成を有する対向マトリクス型の液晶パネル2において、無駄なスペースを生じないマルチ画素構造が得られ、視野角特性を向上させることができる。 As a result, in the counter matrix type liquid crystal panel 2 having a configuration in which two sub-pixels 211 and 212 are arranged side by side in one pixel 210, a multi-pixel structure that does not cause useless space is obtained, and viewing angle characteristics are improved. Can do.
 なお、各画素210が、行方向に並ぶ2つのサブ画素211、212を備えた構成に限らず、例えば、1つの画素領域に4つのサブ画素を設けてもよい。 Note that each pixel 210 is not limited to the configuration including the two sub-pixels 211 and 212 arranged in the row direction, and for example, four sub-pixels may be provided in one pixel region.
 〔等価回路〕
 次に、本実施形態に係るTFT基板10の等価回路について、図10A及び図10Bを参照して説明する。図10Aは、本実施形態に係る液晶パネル2のTFT基板10の等価回路、及び、xフレーム表示時の液晶容量への印加電圧を示す図である。図10Bは、本実施形態に係る液晶パネル2のTFT基板10の等価回路、及び、x+1フレーム表示時の液晶容量への印加電圧を示す図である。
[Equivalent circuit]
Next, an equivalent circuit of the TFT substrate 10 according to the present embodiment will be described with reference to FIGS. 10A and 10B. FIG. 10A is a diagram showing an equivalent circuit of the TFT substrate 10 of the liquid crystal panel 2 according to the present embodiment and a voltage applied to the liquid crystal capacitor during x-frame display. FIG. 10B is a diagram showing an equivalent circuit of the TFT substrate 10 of the liquid crystal panel 2 according to the present embodiment and a voltage applied to the liquid crystal capacitor during x + 1 frame display.
 図10A及び図10Bに示すように、本実施形態における液晶パネル2は、データバスライン22(m+i)’及びデータバスライン22(m+i+1)’とゲートバスライン16(n+j)’とで画定される画素210(m+i)(n+j)を備えている。但し、iはm≧iを満たす0および自然数であり、jはn≧jを満たす0および自然数である。各画素は、それぞれ2つのサブ画素を備えている。 As shown in FIGS. 10A and 10B, the liquid crystal panel 2 in this embodiment is defined by a data bus line 22 (m + i) ′, a data bus line 22 (m + i + 1) ′, and a gate bus line 16 (n + j) ′. Pixel 210 (m + i) (n + j) is provided. However, i is 0 and a natural number that satisfies m ≧ i, and j is 0 and a natural number that satisfies n ≧ j. Each pixel includes two sub-pixels.
 画素210(m+i)(n+j)及び画素210(m+i+1)(n+j)は行方向に隣接して配置され、画素210(m+i)(n+j)及び画素210(m+i)(n+j+1)は列方向に隣接して配置されている。 The pixel 210 (m + i) (n + j) and the pixel 210 (m + i + 1) (n + j) are arranged adjacent to each other in the row direction, and the pixel 210 (m + i) (n + j) and the pixel 210 (m + i) (n + j + 1) are adjacent to each other in the column direction. Are arranged.
 画素210(m+i)(n+j)は、2つのサブ画素を、行方向に第1サブ画素、第2サブ画素の順で備えている。 The pixel 210 (m + i) (n + j) includes two sub-pixels in the order of the first sub-pixel and the second sub-pixel in the row direction.
 さらに、各サブ画素は、TFT12及び液晶容量を含んでいる。なお、液晶容量は、画素電極14、データバスライン22’が形成する対向電極24、及び、画素電極14と対向電極24との間に挟まれた液晶層により構成されている。例えば、図10A及び図10Bに示す画素210(m+i)(n+j)の液晶容量は、第1液晶容量231mn及び第2液晶容量232(m+1)nを含んでいる。 Furthermore, each subpixel includes a TFT 12 and a liquid crystal capacitor. The liquid crystal capacitance is constituted by the pixel electrode 14, the counter electrode 24 formed by the data bus line 22 ′, and a liquid crystal layer sandwiched between the pixel electrode 14 and the counter electrode 24. For example, the liquid crystal capacitance of the pixel 210 (m + i) (n + j) illustrated in FIGS. 10A and 10B includes a first liquid crystal capacitance 231mn and a second liquid crystal capacitance 232 (m + 1) n.
 図10Aに示すように、例えば、画素210mnの第1サブ画素211mnが備える第1TFT221mnのゲート端子はゲートバスライン16n’に接続され、ソース端子は基準電圧バスライン18a’に接続され、ドレイン端子は第1液晶容量231mnを介してデータバスライン22m’に接続されている。 As shown in FIG. 10A, for example, the gate terminal of the first TFT 221mn included in the first sub-pixel 211mn of the pixel 210mn is connected to the gate bus line 16n ′, the source terminal is connected to the reference voltage bus line 18a ′, and the drain terminal is It is connected to the data bus line 22m ′ via the first liquid crystal capacitor 231mn.
 また、第2サブ画素212(m+1)nが備える第2TFT222(m+1)nのゲート端子はゲートバスライン16n’に接続され、ソース端子は基準電圧バスライン18b’に接続され、ドレイン端子は第2液晶容量232(m+1)nを介してデータバスライン22(m+1)’に接続されている。 The gate terminal of the second TFT 222 (m + 1) n included in the second subpixel 212 (m + 1) n is connected to the gate bus line 16n ′, the source terminal is connected to the reference voltage bus line 18b ′, and the drain terminal is the second terminal. The liquid crystal capacitor 232 (m + 1) n is connected to the data bus line 22 (m + 1) ′.
 画素210(m+2)nの第1サブ画素211(m+2)nが備える第1TFT221(m+2)nのゲート端子はゲートバスライン16n’に接続され、ソース端子は基準電圧バスライン18a’に接続され、ドレイン端子は第1液晶容量231(m+2)nを介してデータバスライン22(m+2)’に接続されている。 The gate terminal of the first TFT 221 (m + 2) n included in the first sub-pixel 211 (m + 2) n of the pixel 210 (m + 2) n is connected to the gate bus line 16n ′, the source terminal is connected to the reference voltage bus line 18a ′, The drain terminal is connected to the data bus line 22 (m + 2) ′ via the first liquid crystal capacitor 231 (m + 2) n.
 また、第2サブ画素212(m+3)nが備える第2TFT222(m+3)nのゲート端子はゲートバスライン16n’に接続され、ソース端子は基準電圧バスライン18b’に接続され、ドレイン端子は第2液晶容量232(m+3)nを介してデータバスライン22(m+3)’に接続されている。 The gate terminal of the second TFT 222 (m + 3) n included in the second subpixel 212 (m + 3) n is connected to the gate bus line 16n ′, the source terminal is connected to the reference voltage bus line 18b ′, and the drain terminal is the second. The liquid crystal capacitor 232 (m + 3) n is connected to the data bus line 22 (m + 3) ′.
 すなわち、画素210(m+i)(n+j)の第1サブ画素211(m+i)(n+j)が備える第1TFT221(m+i)(n+j)は、ゲート端子がゲートバスライン16(n+j)’に接続され、ドレイン端子は第1液晶容量231(m+i)(n+j)を介してデータバスライン22(m+i)’に接続されている。また、第2サブ画素212(m+i+1)(n+j)では、第2TFT222(m+i+1)(n+j)のゲート端子がゲートバスライン16(n+j)’に接続され、ドレイン端子は第2液晶容量232(m+i+1)(n+j)を介してデータバスライン22(m+i+1)’に接続されている。 That is, the first TFT 221 (m + i) (n + j) included in the first subpixel 211 (m + i) (n + j) of the pixel 210 (m + i) (n + j) has a gate terminal connected to the gate bus line 16 (n + j) ′ and a drain. The terminal is connected to the data bus line 22 (m + i) ′ via the first liquid crystal capacitor 231 (m + i) (n + j). In the second sub-pixel 212 (m + i + 1) (n + j), the gate terminal of the second TFT 222 (m + i + 1) (n + j) is connected to the gate bus line 16 (n + j) ′, and the drain terminal is the second liquid crystal capacitor 232 (m + i + 1). It is connected to the data bus line 22 (m + i + 1) ′ via (n + j).
 このように、基準電圧バスライン18b’は、例えば、画素210mnの第2サブ画素212(m+1)nと、画素210(m+2)nの第1サブ画素211(m+2)nとに共有されている。これにより、配線レイアウトをシンプルにすることができる。 Thus, the reference voltage bus line 18b ′ is shared by, for example, the second sub-pixel 212 (m + 1) n of the pixel 210mn and the first sub-pixel 211 (m + 2) n of the pixel 210 (m + 2) n. . Thereby, the wiring layout can be simplified.
 なお、液晶パネル2が赤緑青の三原色のカラー表示を行う場合には、例えば、画素210mnが赤に相当し、画素210m(n+1)が緑に相当し、画素210m(n+2)が青に相当すればよいが、これに限定されるものではない。 When the liquid crystal panel 2 performs color display of the three primary colors red, green, and blue, for example, the pixel 210mn corresponds to red, the pixel 210m (n + 1) corresponds to green, and the pixel 210m (n + 2) corresponds to blue. However, the present invention is not limited to this.
 〔液晶パネルの動作〕
 次に、本実施形態に係る液晶パネル2の動作について、図10A、図10B及び図11を参照して説明する。図11は、本実施形態に係る液晶パネル2の動作を示すタイミングチャートである。ここでは、xフレームを表示する際の、図10に示す第1サブ画素211mnの動作を例に挙げて説明する。
[Operation of LCD panel]
Next, the operation of the liquid crystal panel 2 according to the present embodiment will be described with reference to FIGS. 10A, 10B, and 11. FIG. FIG. 11 is a timing chart showing the operation of the liquid crystal panel 2 according to the present embodiment. Here, the operation of the first sub-pixel 211mn shown in FIG. 10 when displaying the x frame will be described as an example.
 (xフレーム)
 図11に示すように、基準電圧バスライン18a’、18b’の電圧は常に一定であり、xフレーム、x+1フレームのいずれを表示する場合にも0Vで一定である。
(X frame)
As shown in FIG. 11, the voltages of the reference voltage bus lines 18a ′ and 18b ′ are always constant, and are constant at 0V when displaying either the x frame or the x + 1 frame.
 時刻txnにおいて、m本目のデータバスライン22m’が+5Vに制御され、n本目のゲートバスライン16n’が走査されると、第1TFT221mn及び第2TFT222(m+1)nのゲート端子に走査信号が供給され、第1TFT221mn及び第2TFT222(m+1)nがON状態になる。同様に、第1TFT221(m+2)n、及び、第2TFT222(m+3)nのゲート端子にも走査信号が供給され、ON状態になる。 At time txn, when the m-th data bus line 22m ′ is controlled to + 5V and the n-th gate bus line 16n ′ is scanned, a scanning signal is supplied to the gate terminals of the first TFT 221mn and the second TFT 222 (m + 1) n. The first TFT 221mn and the second TFT 222 (m + 1) n are turned on. Similarly, a scanning signal is also supplied to the gate terminals of the first TFT 221 (m + 2) n and the second TFT 222 (m + 3) n, and is turned on.
 データバスライン22m’から+5Vのデータ信号が供給されることにより、画素210mnの第1液晶容量231mnのnodeXに、データバスライン22m’と同電圧の+5Vが印加される。また、第1液晶容量231mnのnodeYには、基準電圧バスライン18a’と同電圧の0Vが印加される。これによって、第1液晶容量231mnには、図10Aに示すように、第1液晶容量231mnのnodeXとnodeYとの電位差nodeX-nodeYである+5Vが印加されることになる。 By supplying a data signal of + 5V from the data bus line 22m ', + 5V of the same voltage as the data bus line 22m' is applied to the nodeX of the first liquid crystal capacitor 231mn of the pixel 210mn. In addition, 0V of the same voltage as that of the reference voltage bus line 18a 'is applied to nodeY of the first liquid crystal capacitor 231mn. As a result, as shown in FIG. 10A, + 5V that is a potential difference nodeX−nodeY between nodeX and nodeY of the first liquid crystal capacitor 231mn is applied to the first liquid crystal capacitor 231mn.
 また、データバスライン22(m+1)’が+4Vに制御されることにより、画素210mnの第2液晶容量232(m+1)nのnodeXに+4Vが印加され、nodeYには基準電圧バスライン18b’と同電圧の0Vが印加される。これによって、第2液晶容量232(m+1)nには、第2液晶容量232(m+1)nのnodeXとnodeYとの電位差である+4Vが印加されることになる。 Further, by controlling the data bus line 22 (m + 1) ′ to + 4V, + 4V is applied to nodeX of the second liquid crystal capacitor 232 (m + 1) n of the pixel 210mn, and nodeY is the same as the reference voltage bus line 18b ′. A voltage of 0V is applied. As a result, + 4V, which is the potential difference between nodeX and nodeY of the second liquid crystal capacitor 232 (m + 1) n, is applied to the second liquid crystal capacitor 232 (m + 1) n.
 同様に、時刻txnにおいて、データバスライン22(m+2)’が-5Vに制御され、データバスライン22(m+3)’が-4Vに制御されると、画素210(m+2)nの第1液晶容量231(m+2)nの印加電圧は-5Vになり、第2液晶容量232(m+3)nの印加電圧は-4Vになる。 Similarly, at time txn, when the data bus line 22 (m + 2) ′ is controlled to −5V and the data bus line 22 (m + 3) ′ is controlled to −4V, the first liquid crystal capacitor of the pixel 210 (m + 2) n The applied voltage of 231 (m + 2) n is −5V, and the applied voltage of the second liquid crystal capacitor 232 (m + 3) n is −4V.
 次に、時刻tx(n+1)において、n本目のゲートバスライン16n’の走査が停止され、新たにn+1本目のゲートバスライン16(n+1)’が走査されると、第1TFT221m(n+1)及び第2TFT222(m+1)(n+1)のゲート端子に走査信号が供給され、ON状態になる。同様に、第1TFT221(m+2)(n+1)、及び、第2TFT222(m+3)(n+1)のゲート端子にも走査信号が供給され、ON状態になる。 Next, at time tx (n + 1), scanning of the nth gate bus line 16n ′ is stopped, and when the n + 1th gate bus line 16 (n + 1) ′ is newly scanned, the first TFT 221m (n + 1) and the first TFT A scanning signal is supplied to the gate terminal of the 2TFT 222 (m + 1) (n + 1), and it is turned on. Similarly, a scanning signal is supplied to the gate terminals of the first TFT 221 (m + 2) (n + 1) and the second TFT 222 (m + 3) (n + 1), and is turned on.
 また、時刻tx(n+1)においてデータバスライン22m’が+4Vに制御され、データバスライン22(m+1)’が+3Vに制御されると、図10Aに示すように、第1液晶容量231m(n+1)の印加電圧は+4Vになり、第2液晶容量232(m+1)(n+1)の印加電圧は+3Vになる。 When the data bus line 22m ′ is controlled to + 4V and the data bus line 22 (m + 1) ′ is controlled to + 3V at time tx (n + 1), as shown in FIG. 10A, the first liquid crystal capacitor 231m (n + 1) Applied voltage becomes + 4V, and the applied voltage of the second liquid crystal capacitor 232 (m + 1) (n + 1) becomes + 3V.
 同様に、時刻tx(n+1)において、データバスライン22(m+2)’が-4Vに制御され、データバスライン22(m+3)’が-3Vに制御されると、図10Aに示すように、第1液晶容量231(m+2)(n+1)の印加電圧は-4Vになり、第2液晶容量232(m+3)(n+1)の印加電圧は-3Vになる。 Similarly, at time tx (n + 1), when the data bus line 22 (m + 2) ′ is controlled to −4V and the data bus line 22 (m + 3) ′ is controlled to −3V, as shown in FIG. The applied voltage of one liquid crystal capacitor 231 (m + 2) (n + 1) is −4V, and the applied voltage of the second liquid crystal capacitor 232 (m + 3) (n + 1) is −3V.
 これに対し、時刻tx(n+1)において、n本目のゲートバスライン16n’の走査が停止されることにより、第1TFT221mn及び第2TFT222(m+1)nのゲート端子への走査信号の供給が停止され、第1TFT221mn及び第2TFT222(m+1)nはOFF状態になる。これによって、第1液晶容量231mn及び第2液晶容量232(m+1)nはフローティング状態になる。 On the other hand, at time tx (n + 1), the scanning of the nth gate bus line 16n ′ is stopped, whereby the supply of the scanning signal to the gate terminals of the first TFT 221mn and the second TFT 222 (m + 1) n is stopped. The first TFT 221mn and the second TFT 222 (m + 1) n are turned off. Accordingly, the first liquid crystal capacitor 231mn and the second liquid crystal capacitor 232 (m + 1) n are in a floating state.
 時刻tx(n+1)においては、データバスライン22m’が+4Vに制御されているため、第1液晶容量231mnのnodeX側にデータバスライン22m’と同じ+4Vが印加される。さらに、第1液晶容量231mnはフローティング状態であるため、時刻txnにおける第1液晶容量231mnのnodeX側の電圧とnodeY側の電圧との電位差+5Vを維持するよう、nodeY側の電圧が-1Vに遷移する。 At time tx (n + 1), since the data bus line 22m ′ is controlled to + 4V, the same + 4V as the data bus line 22m ′ is applied to the nodeX side of the first liquid crystal capacitor 231mn. Furthermore, since the first liquid crystal capacitor 231mn is in a floating state, the voltage on the node Y side transitions to −1V so that the potential difference + 5V between the voltage on the node X side and the voltage on the node Y side of the first liquid crystal capacitor 231mn at the time txn is maintained. To do.
 これにより、時刻tx(n+1)において、第1液晶容量231mnの電圧は変化せず、時刻txnにおいて印加された電圧が維持される。すなわち、xフレームを表示するためにゲートバスライン16n’が走査されることで第1液晶容量231mnに印加された電圧は、x+1フレームを表示するために、再びゲートバスライン16n’が走査されるまで、維持されることになる。 Thereby, at time tx (n + 1), the voltage of the first liquid crystal capacitor 231mn does not change, and the voltage applied at time txn is maintained. That is, the voltage applied to the first liquid crystal capacitor 231mn by scanning the gate bus line 16n ′ to display the x frame causes the gate bus line 16n ′ to be scanned again to display the x + 1 frame. Until it will be maintained.
 第2液晶容量232(m+1)n、第1液晶容量231(m+2)n、及び、第2液晶容量232(m+3)nも同様に、時刻tx(n+1)においても、時刻txnにおいて印加された電圧が維持される。 Similarly, the voltage applied to the second liquid crystal capacitor 232 (m + 1) n, the first liquid crystal capacitor 231 (m + 2) n, and the second liquid crystal capacitor 232 (m + 3) n is also applied at time txn at time tx (n + 1). Is maintained.
 同様に、時刻tx(n+2)において、n+1本目のゲートバスライン16(n+1)’の走査が停止され、新たにn+2本目のゲートバスライン16(n+2)’が走査されると、第1TFT221m(n+2)、第2TFT222(m+1)(n+2)、第1TFT221(m+2)(n+2)、及び、第2TFT222(m+3)(n+2)のゲート端子に走査信号が供給され、ON状態になる。 Similarly, when the scanning of the (n + 1) th gate bus line 16 (n + 1) ′ is stopped and the n + 2th gate bus line 16 (n + 2) ′ is newly scanned at time tx (n + 2), the first TFT 221m (n + 2) is scanned. ), The scanning signal is supplied to the gate terminals of the second TFT 222 (m + 1) (n + 2), the first TFT 221 (m + 2) (n + 2), and the second TFT 222 (m + 3) (n + 2), and the ON state is obtained.
 データバスライン22m’が+3Vに、22(m+2)’が-3Vに制御され、データバスライン22(m+1)’が+2Vに、22(m+3)’が-2Vに制御されると、第1液晶容量231m(n+2)の印加電圧は+3Vに、第1液晶容量231(m+2)(n+2)の印加電圧は-3Vになり、第2液晶容量232(m+2)(n+2)の印加電圧は+2Vに、第2液晶容量232(m+3)(n+2)の印加電圧は-2Vになる。 When the data bus line 22m ′ is controlled to + 3V, 22 (m + 2) ′ is controlled to −3V, the data bus line 22 (m + 1) ′ is controlled to + 2V, and 22 (m + 3) ′ is controlled to −2V, the first liquid crystal The applied voltage of the capacitor 231m (n + 2) is + 3V, the applied voltage of the first liquid crystal capacitor 231 (m + 2) (n + 2) is −3V, and the applied voltage of the second liquid crystal capacitor 232 (m + 2) (n + 2) is + 2V. The applied voltage of the second liquid crystal capacitor 232 (m + 3) (n + 2) is −2V.
 (x+1フレーム)
 TFT基板10に形成されるN本全てのゲートバスライン16’に対して、xフレームを表示するための走査が行われると、次に、x+1フレームを表示するための走査が、1本目のゲートバスライン16’から順に開始される。データバスライン22’には、1フレーム前のxフレームでの極性を反転させたデータ信号が供給される。
(X + 1 frame)
When scanning for displaying the x frame is performed on all N gate bus lines 16 ′ formed on the TFT substrate 10, the scanning for displaying the x + 1 frame is performed next. Starting from the bus line 16 ′. A data signal in which the polarity in the x frame one frame before is inverted is supplied to the data bus line 22 ′.
 時刻t(x+1)nにおいて、ゲートバスライン16n’が走査されると、第1TFT221mn、第2TFT222(m+1)n、第1TFT221(m+2)n、及び、第2TFT222(m+3)nのゲート端子に走査信号が供給され、ON状態になる。 When the gate bus line 16n ′ is scanned at time t (x + 1) n, the scanning signal is applied to the gate terminals of the first TFT 221mn, the second TFT 222 (m + 1) n, the first TFT 221 (m + 2) n, and the second TFT 222 (m + 3) n. Is supplied and turned ON.
 また、データバスライン22m’が-5V、22(m+2)’が+5Vに制御され、データバスライン22(m+1)’が-4V、22(m+3)’が+4Vに制御されると、図10Bに示すように、第1液晶容量231mnの印加電圧は-5Vに、第1液晶容量231(m+2)nの印加電圧は+5Vになり、第2液晶容量232(m+1)nの印加電圧は-4Vに、第2液晶容量232(m+3)nの印加電圧は+4Vになる。 Further, when the data bus line 22m ′ is controlled to −5V, 22 (m + 2) ′ to + 5V, the data bus line 22 (m + 1) ′ is controlled to −4V, and 22 (m + 3) ′ to + 4V, FIG. As shown, the applied voltage of the first liquid crystal capacitor 231mn is −5V, the applied voltage of the first liquid crystal capacitor 231 (m + 2) n is + 5V, and the applied voltage of the second liquid crystal capacitor 232 (m + 1) n is −4V. The applied voltage of the second liquid crystal capacitor 232 (m + 3) n is + 4V.
 次に、時刻t(x+1)(n+1)において、ゲートバスライン16n’の走査が停止され、新たにゲートバスライン16(n+1)’が走査されると、第1TFT221m(n+1)、第2TFT222(m+1)(n+1)、第1TFT221(m+2)(n+1)、及び、第2TFT222(m+3)(n+1)のゲート端子に走査信号が供給され、ON状態になる。 Next, when the scanning of the gate bus line 16n ′ is stopped and the gate bus line 16 (n + 1) ′ is newly scanned at the time t (x + 1) (n + 1), the first TFT 221m (n + 1) and the second TFT 222 (m + 1) are scanned. ) (N + 1), the scanning signal is supplied to the gate terminals of the first TFT 221 (m + 2) (n + 1), and the second TFT 222 (m + 3) (n + 1), and is turned on.
 また、時刻t(x+1)(n+1)においてデータバスライン22m’が-4V、22(m+2)’が+4Vに制御され、データバスライン22(m+1)’が-3V、22(m+3)’が+3Vに制御されると、図10Bに示すように、第1液晶容量231m(n+1)の印加電圧は-4Vに、第1液晶容量231(m+2)(n+1)の印加電圧は+4Vになり、第2液晶容量232(m+1)(n+1)の印加電圧は-3Vに、第2液晶容量232(m+3)(n+1)の印加電圧は+3Vになる。 At time t (x + 1) (n + 1), the data bus line 22m ′ is controlled to −4V, 22 (m + 2) ′ to + 4V, the data bus line 22 (m + 1) ′ is −3V, and 22 (m + 3) ′ is + 3V. 10B, as shown in FIG. 10B, the applied voltage of the first liquid crystal capacitor 231m (n + 1) becomes −4V, the applied voltage of the first liquid crystal capacitor 231 (m + 2) (n + 1) becomes + 4V, and the second The applied voltage of the liquid crystal capacitor 232 (m + 1) (n + 1) is −3V, and the applied voltage of the second liquid crystal capacitor 232 (m + 3) (n + 1) is + 3V.
 なお、時刻t(x+1)(n+1)において、ゲートバスライン16n’の走査が停止されることにより、第1液晶容量231mn、第2液晶容量232(m+1)n、第1液晶容量231(m+2)n、及び、第2液晶容量232(m+3)nにそれぞれ印加された電圧は、再びゲートバスライン16n’が走査されるまで、維持されることになる。 At time t (x + 1) (n + 1), scanning of the gate bus line 16n ′ is stopped, whereby the first liquid crystal capacitor 231mn, the second liquid crystal capacitor 232 (m + 1) n, and the first liquid crystal capacitor 231 (m + 2). The voltages applied to n and the second liquid crystal capacitor 232 (m + 3) n are maintained until the gate bus line 16n ′ is scanned again.
 同様に、時刻t(x+2)(n+2)において、ゲートバスライン16(n+1)’の走査が停止され、新たにゲートバスライン16(n+2)’が走査されると、第1TFT221m(n+2)、第2TFT222(m+1)(n+2)、第1TFT221(m+2)(n+2)、及び、第2TFT222(m+3)(n+2)のゲート端子に走査信号が供給され、ON状態になる。 Similarly, when the scanning of the gate bus line 16 (n + 1) ′ is stopped and the gate bus line 16 (n + 2) ′ is newly scanned at time t (x + 2) (n + 2), the first TFT 221m (n + 2), A scanning signal is supplied to the gate terminals of the 2 TFTs 222 (m + 1) (n + 2), the first TFTs 221 (m + 2) (n + 2), and the second TFTs 222 (m + 3) (n + 2) to be turned on.
 データバスライン22m’が-3V、22(m+2)’が+3Vに制御され、データバスライン22(m+2)’が-2V、22(m+3)’が+2Vに制御されると、図10Bに示すように、第1液晶容量231m(n+2)の印加電圧は-3Vに、第1液晶容量231(m+2)(n+2)の印加電圧は+3Vになり、第2液晶容量232(m+1)(n+2)の印加電圧は-2Vに、第2液晶容量232(m+3)(n+2)の印加電圧は+2Vになる。 When the data bus line 22m ′ is controlled to −3V, 22 (m + 2) ′ to + 3V, the data bus line 22 (m + 2) ′ is controlled to −2V, and 22 (m + 3) ′ to + 2V, as shown in FIG. 10B. In addition, the applied voltage of the first liquid crystal capacitor 231m (n + 2) is −3V, the applied voltage of the first liquid crystal capacitor 231 (m + 2) (n + 2) is + 3V, and the second liquid crystal capacitor 232 (m + 1) (n + 2) is applied. The voltage is -2V, and the voltage applied to the second liquid crystal capacitor 232 (m + 3) (n + 2) is + 2V.
 以上のように、本実施形態に係る液晶パネル2の駆動方法は、図9、図10A及び図10Bに基づいて説明した構成を有する液晶パネルにおける駆動方法であって、少なくとも行方向に並ぶ第1サブ画素211mn及び第2サブ画素212(m+1)nについて、第1サブ画素211mnに対応した基準電圧バスライン18a’と、第2サブ画素212(m+1)nに対応した基準電圧バスライン18b’とに印加する各電圧を同一にし、第1サブ画素211mnに対応したデータバスライン22m’に印加する電圧と、第2サブ画素212(m+1)nに対応したデータバスライン22(m+1)’に印加する電圧とを相違させることによって、データバスライン22m’及び基準電圧バスライン18a’間の電位差と、データバスライン22(m+1)’及び基準電圧バスライン18b’間の電位差とを相違させている。 As described above, the driving method of the liquid crystal panel 2 according to the present embodiment is a driving method in the liquid crystal panel having the configuration described based on FIG. 9, FIG. 10A, and FIG. For the sub-pixel 211mn and the second sub-pixel 212 (m + 1) n, a reference voltage bus line 18a ′ corresponding to the first sub-pixel 211mn and a reference voltage bus line 18b ′ corresponding to the second sub-pixel 212 (m + 1) n Are applied to the data bus line 22m ′ corresponding to the first sub-pixel 211mn and applied to the data bus line 22 (m + 1) ′ corresponding to the second sub-pixel 212 (m + 1) n. By making the voltages different from each other, the potential difference between the data bus line 22m ′ and the reference voltage bus line 18a ′ can be reduced. 22 and (m + 1) 'and the reference voltage bus line 18b' is different from the potential difference between.
 これにより、第1サブ画素211mnの液晶層には、データバスライン22m’と基準電圧バスライン18a’との電位差が印加される一方、第2サブ画素212(m+1)nの液晶層には、データバスライン22(m+1)’と基準電圧バスライン18b’との電位差が印加される。 Accordingly, a potential difference between the data bus line 22m ′ and the reference voltage bus line 18a ′ is applied to the liquid crystal layer of the first subpixel 211mn, while the liquid crystal layer of the second subpixel 212 (m + 1) n is applied to the liquid crystal layer of the first subpixel 211mn. A potential difference between the data bus line 22 (m + 1) ′ and the reference voltage bus line 18b ′ is applied.
 このとき、基準電圧バスライン18a’に印加された電圧と、基準電圧バスライン18b’に印加された電圧とは同一であり、データバスライン22m’及びデータバスライン22(m+1)’に印加する電圧を相違させているから、第1サブ画素211mnの液晶層にかかる電圧と、第2サブ画素212(m+1)nの液晶層にかかる電圧とを相違させることができる。 At this time, the voltage applied to the reference voltage bus line 18a ′ and the voltage applied to the reference voltage bus line 18b ′ are the same, and are applied to the data bus line 22m ′ and the data bus line 22 (m + 1) ′. Since the voltages are different, the voltage applied to the liquid crystal layer of the first sub-pixel 211mn and the voltage applied to the liquid crystal layer of the second sub-pixel 212 (m + 1) n can be made different.
 これにより、第1サブ画素211mnにおける液晶分子の配向状態と、第2サブ画素212(m+1)nにおける液晶分子の配向状態とを、データバスライン22m’、22(m+1)’に印加する各電圧に応じて相違させることができる結果、対向マトリクス型の液晶パネルにおける視野角特性を向上させることができる。 As a result, the voltages applied to the data bus lines 22m ′ and 22 (m + 1) ′ are the liquid crystal molecule alignment state in the first sub-pixel 211mn and the liquid crystal molecule alignment state in the second sub-pixel 212 (m + 1) n. As a result, the viewing angle characteristics in the counter matrix type liquid crystal panel can be improved.
 また、上述のように、列方向に配列されている画素毎に極性を反転させた駆動を行うことにより、液晶パネル2の焼きつきを低減することができる。 Further, as described above, the burn-in of the liquid crystal panel 2 can be reduced by performing the driving with the polarity reversed for each pixel arranged in the column direction.
 <実施形態3>
 本発明の他の実施形態について図12から図14に基づいて以下に説明する。なお、説明の便宜上、実施形態1に係る構成要素と同様の機能を有する構成要素には同一の番号を付し、その説明を省略する。本実施形態では、主に、実施形態1との相違点について説明するものとする。
<Embodiment 3>
Another embodiment of the present invention will be described below with reference to FIGS. For convenience of explanation, components having the same functions as those of the components according to the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. In the present embodiment, differences from the first embodiment will be mainly described.
 〔TFT基板のレイアウト〕
 本実施形態に係る液晶パネル3のTFT基板10のレイアウトの詳細を、図12を参照して説明する。図12は、本実施形態に係る液晶パネル3のTFT基板10のレイアウトを示す上面図である。なお、図12において、対向基板20に形成された総数M本のデータバスライン22”のうち、m本目のデータバスライン22m”の付近に配置されたデータバスライン22m”~22(m+4)”を破線で示している。
[TFT substrate layout]
Details of the layout of the TFT substrate 10 of the liquid crystal panel 3 according to the present embodiment will be described with reference to FIG. FIG. 12 is a top view showing a layout of the TFT substrate 10 of the liquid crystal panel 3 according to the present embodiment. In FIG. 12, of the total number M of data bus lines 22 ″ formed on the counter substrate 20, data bus lines 22m ″ to 22 (m + 4) ″ arranged in the vicinity of the mth data bus line 22m ″. Is indicated by a broken line.
 図12に示すように、各ゲートバスライン16”間の間隔が、データバスライン22”の幅よりも狭く、基準電圧バスライン18”がゲートバスライン16”と交差するように配置されていること以外は、実施形態1の液晶パネル1と同じ構成である。 As shown in FIG. 12, the interval between the gate bus lines 16 "is narrower than the width of the data bus line 22", and the reference voltage bus line 18 "is arranged to cross the gate bus line 16". Except for this, the configuration is the same as that of the liquid crystal panel 1 of the first embodiment.
 図12に示すように、液晶パネル3は、総数N本のゲートバスライン16”のうち、n本目のゲートバスライン16n”とm本目のデータバスライン22m”とにより画定される画素310mnを備えている。画素310mnは、第1サブ画素311mnと第2サブ画素312mnを備えている。 As shown in FIG. 12, the liquid crystal panel 3 includes a pixel 310mn defined by an nth gate bus line 16n ″ and an mth data bus line 22m ″ among a total of N gate bus lines 16 ″. The pixel 310mn includes a first sub pixel 311mn and a second sub pixel 312mn.
 第1サブ画素311mnは、第1画素電極341mnと第1TFT321mnとを備えている。第2サブ画素312mnは、第2画素電極342mnと第2TFT322mnとを備えている。また、図12に示すように、1つの画素310の領域において、第1サブ画素311と第2サブ画素312とは、行方向に配列している。 The first subpixel 311mn includes a first pixel electrode 341mn and a first TFT 321mn. The second subpixel 312mn includes a second pixel electrode 342mn and a second TFT 322mn. Also, as shown in FIG. 12, in the area of one pixel 310, the first sub-pixel 311 and the second sub-pixel 312 are arranged in the row direction.
 これにより、1つの画素310に無駄なデッドスペースを生じさせることなく、面積が大きい画素電極と、面積が小さい画素電極とを行方向に並べて1つの画素310に形成することができる。 Thus, a pixel electrode having a large area and a pixel electrode having a small area can be arranged in the row direction and formed in one pixel 310 without causing unnecessary dead space in one pixel 310.
 しかも、第1サブ画素311及び第2サブ画素312に共通にデータバスライン22”を設けたので、サブ画素毎に設けた基準電圧バスライン18”に印加する電圧をサブ画素毎に変えることにより、データバスライン22”と基準電圧バスライン18”との電位差を、サブ画素毎に変えることができる。 In addition, since the data bus line 22 ″ is provided in common for the first sub-pixel 311 and the second sub-pixel 312, the voltage applied to the reference voltage bus line 18 ″ provided for each sub-pixel is changed for each sub-pixel. The potential difference between the data bus line 22 ″ and the reference voltage bus line 18 ″ can be changed for each sub-pixel.
 これにより、1つの画素310に2つのサブ画素311、312が横並びした構成を有する対向マトリクス型の液晶パネルにおいて、無駄なスペースを生じないマルチ画素構造が得られ、視野角特性を向上させることができる。 Accordingly, in a counter matrix type liquid crystal panel having a configuration in which two sub-pixels 311 and 312 are arranged side by side in one pixel 310, a multi-pixel structure that does not cause useless space can be obtained, and viewing angle characteristics can be improved. it can.
 なお、各画素310が、行方向に並ぶ2つのサブ画素311、312を備えた構成に限らず、例えば、1つの画素領域に4つのサブ画素を設ける構成を採用してもよい。 Note that each pixel 310 is not limited to the configuration including the two sub-pixels 311 and 312 arranged in the row direction, and for example, a configuration in which four sub-pixels are provided in one pixel region may be employed.
 なお、図12に示すように、本実施形態における液晶パネル3のTFT基板10は、第1サブ画素311に対する第2サブ画素312の面積比が、1より大きく4以下になるように構成されていることが好ましい。 As shown in FIG. 12, the TFT substrate 10 of the liquid crystal panel 3 in this embodiment is configured such that the area ratio of the second subpixel 312 to the first subpixel 311 is greater than 1 and 4 or less. Preferably it is.
 これによって、面積の小さい第1サブ画素311におけるデータバスライン22”及び基準電圧バスライン18”間の電位差を、面積の大きい第2サブ画素312における電位差より大きくするので、第1サブ画素311の液晶層にかかる電圧は、第2サブ画素312の液晶層に比べて、早く液晶のしきい値を超える。すなわち、第1サブ画素311の液晶層にかかる電圧が、液晶のしきい値を超える時点では、第2サブ画素312の液晶層にかかる電圧は、液晶のしきい値を超えていない。 Accordingly, the potential difference between the data bus line 22 ″ and the reference voltage bus line 18 ″ in the first sub-pixel 311 having a small area is made larger than the potential difference in the second sub-pixel 312 having a large area. The voltage applied to the liquid crystal layer exceeds the liquid crystal threshold earlier than the liquid crystal layer of the second subpixel 312. That is, when the voltage applied to the liquid crystal layer of the first sub-pixel 311 exceeds the threshold value of the liquid crystal, the voltage applied to the liquid crystal layer of the second sub-pixel 312 does not exceed the threshold value of the liquid crystal.
 この場合、面積の大きい第2サブ画素312が発光を開始する前に、第1サブ画素311が低階調領域の色から先に表示し始め、第2サブ画素312より高い輝度に到達し、第2サブ画素312はあとから中間調領域から高階調領域の発光量を補うように発光する。つまり、面積の小さい第1サブ画素311は、低階調から中間調の表示に主に寄与する一方、面積の大きい第2サブ画素312は、中間調から高階調の表示に主に寄与する。このようにすると、視野角特性を所望の特性に制御しやすくなる。 In this case, before the second sub-pixel 312 having a large area starts to emit light, the first sub-pixel 311 starts to display the color of the low gradation region first, reaches a higher luminance than the second sub-pixel 312, The second sub-pixel 312 emits light so as to compensate for the light emission amount from the halftone area to the high gradation area. That is, the first sub-pixel 311 having a small area mainly contributes to display from a low gradation to a halftone, while the second sub-pixel 312 having a large area mainly contributes to display from a half-tone to a high gradation. This makes it easy to control the viewing angle characteristic to a desired characteristic.
 また、人の視覚は、高階調領域の色よりも低階調領域の色に敏感に反応するため、低階調領域を面積の小さい第1サブ画素311にする方が、低階調領域を面積の大きい第2サブ画素312にするよりも、視野角特性をより向上させることができる。 In addition, since human vision reacts more sensitively to the color of the low gradation region than the color of the high gradation region, the low gradation region is more reduced when the low gradation region is the first sub-pixel 311 having a smaller area. The viewing angle characteristic can be further improved as compared with the second sub-pixel 312 having a large area.
 〔等価回路〕
 次に、本実施形態に係るTFT基板10の等価回路について、図13を参照して説明する。図13は、本実施形態に係る液晶パネル3のTFT基板10の等価回路、及び、xフレーム表示時の液晶容量への印加電圧を示す図である。
[Equivalent circuit]
Next, an equivalent circuit of the TFT substrate 10 according to the present embodiment will be described with reference to FIG. FIG. 13 is a diagram showing an equivalent circuit of the TFT substrate 10 of the liquid crystal panel 3 according to the present embodiment, and a voltage applied to the liquid crystal capacitor during x frame display.
 図13に示すように、本実施形態における液晶パネル3は、データバスライン22(m+p)”とゲートバスライン16(n+q)”とで画定される画素210(m+p)(n+q)を備えている。但し、pはm≧pを満たす0および自然数であり、qはn≧qを満たす0および自然数である。各画素は、それぞれ2つのサブ画素を備えている。 As shown in FIG. 13, the liquid crystal panel 3 in this embodiment includes pixels 210 (m + p) (n + q) defined by data bus lines 22 (m + p) ″ and gate bus lines 16 (n + q) ″. . However, p is 0 and a natural number satisfying m ≧ p, and q is 0 and a natural number satisfying n ≧ q. Each pixel includes two sub-pixels.
 画素310(m+p)(n+q)及び画素310(m+p+1)(n+q)は行方向に隣接して配置され、画素310(m+p)(n+q)及び画素310(m+p)(n+q+1)は列方向に隣接して配置されている。また、画素310(m+p)(n+q)は、2つのサブ画素を、行方向に第1サブ画素、第2サブ画素の順で備えている。 The pixel 310 (m + p) (n + q) and the pixel 310 (m + p + 1) (n + q) are arranged adjacent to each other in the row direction, and the pixel 310 (m + p) (n + q) and the pixel 310 (m + p) (n + q + 1) are adjacent to each other in the column direction. Are arranged. The pixel 310 (m + p) (n + q) includes two subpixels in the row direction in the order of the first subpixel and the second subpixel.
 例えば、画素310mn及び画素310(m+1)n、画素310m(n+1)及び画素310(m+1)(n+1)、画素310m(n+2)及び画素310(m+1)(n+2)はそれぞれ行方向に隣接して配置され、画素310mn~画素310m(n+2)、画素310(m+1)n~画素310(m+1)(n+2)、はそれぞれ列方向に隣接して配置されている。また、各画素310は、2つのサブ画素を、行方向に第1サブ画素、第2サブ画素の順で備えている。 For example, the pixel 310mn and the pixel 310 (m + 1) n, the pixel 310m (n + 1), the pixel 310 (m + 1) (n + 1), the pixel 310m (n + 2), and the pixel 310 (m + 1) (n + 2) are arranged adjacent to each other in the row direction. The pixels 310mn to 310m (n + 2) and the pixels 310 (m + 1) n to 310 (m + 1) (n + 2) are arranged adjacent to each other in the column direction. Each pixel 310 includes two subpixels in the order of the first subpixel and the second subpixel in the row direction.
 さらに、各サブ画素は、TFT12及び液晶容量を含んでいる。なお、液晶容量は、画素電極14、データバスライン22”が形成する対向電極24、及び、画素電極14と対向電極24との間に挟まれた液晶層により構成されている。図13では、画素310mnに備えられている液晶容量は、第1液晶容量331mn及び第2液晶容量332mnを含んでいる。 Furthermore, each subpixel includes a TFT 12 and a liquid crystal capacitor. Note that the liquid crystal capacitance includes a pixel electrode 14, a counter electrode 24 formed by the data bus line 22 ″, and a liquid crystal layer sandwiched between the pixel electrode 14 and the counter electrode 24. In FIG. The liquid crystal capacitor provided in the pixel 310mn includes a first liquid crystal capacitor 331mn and a second liquid crystal capacitor 332mn.
 図13に示すように、例えば、画素310mnの第1サブ画素311mnが備える第1TFT321mnのゲート端子はゲートバスライン16n”に接続され、ソース端子は基準電圧バスライン18a”に接続され、ドレイン端子は第1液晶容量331mnを介してデータバスライン22m”に接続されている。 As shown in FIG. 13, for example, the gate terminal of the first TFT 321mn included in the first sub-pixel 311mn of the pixel 310mn is connected to the gate bus line 16n ", the source terminal is connected to the reference voltage bus line 18a", and the drain terminal is The first liquid crystal capacitor 331 mn is connected to the data bus line 22 m ″.
 また、第2サブ画素312mnが備える第2TFT322mnのゲート端子はゲートバスライン16n”に接続され、ソース端子は基準電圧バスライン18b”に接続され、ドレイン端子は第2液晶容量332mnを介してデータバスライン22m”に接続されている。 The gate terminal of the second TFT 322mn included in the second subpixel 312mn is connected to the gate bus line 16n ", the source terminal is connected to the reference voltage bus line 18b", and the drain terminal is connected to the data bus via the second liquid crystal capacitor 332mn. Connected to line 22m ".
 画素310(m+1)nの第1サブ画素311(m+1)nが備える第1TFT321(m+1)nのゲート端子はゲートバスライン16n”に接続され、ソース端子は基準電圧バスライン18a”に接続され、ドレイン端子は第1液晶容量331(m+1)nを介してデータバスライン22m”に接続されている。 The gate terminal of the first TFT 321 (m + 1) n included in the first sub-pixel 311 (m + 1) n of the pixel 310 (m + 1) n is connected to the gate bus line 16n ″, and the source terminal is connected to the reference voltage bus line 18a ″. The drain terminal is connected to the data bus line 22m ″ via the first liquid crystal capacitor 331 (m + 1) n.
 また、第2サブ画素312(m+1)nが備える第2TFT322(m+1)nのゲート端子はゲートバスライン16n”に接続され、ソース端子は基準電圧バスライン18b”に接続され、ドレイン端子は第2液晶容量332(m+1)nを介してデータバスライン22(m+1)”に接続されている。 In addition, the gate terminal of the second TFT 322 (m + 1) n included in the second subpixel 312 (m + 1) n is connected to the gate bus line 16n ″, the source terminal is connected to the reference voltage bus line 18b ″, and the drain terminal is the second terminal. It is connected to the data bus line 22 (m + 1) ″ via the liquid crystal capacitor 332 (m + 1) n.
 すなわち、画素310(m+p)(n+q)の第1サブ画素311(m+p)(n+q)の第1TFT321(m+p)(n+q)では、ゲート端子がゲートバスライン16(n+q)”に接続され、ソース端子は基準電圧バスライン18a”に接続され、ドレイン端子は第1液晶容量331(m+p)(n+q)を介してデータバスライン22(m+p)”に接続されている。また、第2サブ画素312(m+p)(n+q)では、第2TFT322(m+p)(n+q)のゲート端子がゲートバスライン16(n+q)”に接続され、ソース端子は基準電圧バスライン18b”に接続され、ドレイン端子は第2液晶容量232(m+p)(n+q)を介してデータバスライン22(m+p)”に接続されている。 That is, in the first TFT 321 (m + p) (n + q) of the first sub-pixel 311 (m + p) (n + q) of the pixel 310 (m + p) (n + q), the gate terminal is connected to the gate bus line 16 (n + q) ″ and the source terminal Is connected to the reference voltage bus line 18a ″, and the drain terminal is connected to the data bus line 22 (m + p) ″ via the first liquid crystal capacitor 331 (m + p) (n + q). The second sub-pixel 312 ( In (m + p) (n + q), the gate terminal of the second TFT 322 (m + p) (n + q) is connected to the gate bus line 16 (n + q) ″, the source terminal is connected to the reference voltage bus line 18b ″, and the drain terminal is the second liquid crystal. The capacitor is connected to the data bus line 22 (m + p) ″ via a capacitor 232 (m + p) (n + q).
 これによって、行方向に隣り合う画素領域が、1つの基準電圧バスラインを共有できるので、シンプルな配線レイアウトにすることができる。 Thereby, since pixel regions adjacent in the row direction can share one reference voltage bus line, a simple wiring layout can be achieved.
 なお、液晶パネル3が赤緑青の三原色のカラー表示を行う場合には、例えば、画素310mnが赤に相当し、画素310m(n+1)が緑に相当し、画素310m(n+2)が青に相当すればよいが、これに限定されるものではない。 When the liquid crystal panel 3 performs color display of the three primary colors of red, green, and blue, for example, the pixel 310mn corresponds to red, the pixel 310m (n + 1) corresponds to green, and the pixel 310m (n + 2) corresponds to blue. However, the present invention is not limited to this.
 〔液晶パネルの動作〕
 次に、本実施形態に係る液晶パネル3の動作について、図13及び図14を参照して説明する。図14は、本実施形態に係る液晶パネル3の動作を示すタイミングチャートである。ここでは、xフレームを表示する際の、図13に示す第1サブ画素311mnの動作を例に挙げて説明する。
[Operation of LCD panel]
Next, the operation of the liquid crystal panel 3 according to the present embodiment will be described with reference to FIGS. FIG. 14 is a timing chart showing the operation of the liquid crystal panel 3 according to the present embodiment. Here, the operation of the first sub-pixel 311mn shown in FIG. 13 when displaying the x frame will be described as an example.
 (xフレーム)
 図14に示すように、時刻tx1においてxフレームの表示が開始されると、x-1フレームを表示する際にHレベルに制御されていた基準電圧バスライン18a”の基準電圧がLレベルに制御され、x-1フレームを表示する際にLレベルに制御されていた基準電圧バスライン18b”の基準電圧がHレベルに制御される。また、時刻tx1では、1本目のゲートバスライン16”が走査される。なお、本実施形態では、Hレベルの基準電圧を+1V、Lレベルの基準電圧を0Vとしているが、これに限定されるものではない。
(X frame)
As shown in FIG. 14, when display of the x frame is started at time tx1, the reference voltage of the reference voltage bus line 18a ″ that was controlled to H level when displaying the x−1 frame is controlled to L level. Then, the reference voltage of the reference voltage bus line 18b ″ that has been controlled to the L level when the x−1 frame is displayed is controlled to the H level. At time tx1, the first gate bus line 16 ″ is scanned. In this embodiment, the H level reference voltage is set to +1 V and the L level reference voltage is set to 0 V. However, the present invention is not limited to this. It is not a thing.
 時刻txnにおいて、m本目のデータバスライン22m”が+5Vに制御され、n本目のゲートバスライン16n”が走査されると、第1TFT321mn及び第2TFT322mnのゲート端子に走査信号が供給され、第1TFT321mn及び第2TFT322mnがON状態になる。同様に、第1TFT321(m+1)n、及び、第2TFT322(m+2)nのゲート端子にも走査信号が供給され、ON状態になる。 At time txn, when the m-th data bus line 22m ″ is controlled to + 5V and the n-th gate bus line 16n ″ is scanned, a scanning signal is supplied to the gate terminals of the first TFT 321mn and the second TFT 322mn, and the first TFT 321mn and The second TFT 322mn is turned on. Similarly, a scanning signal is also supplied to the gate terminals of the first TFT 321 (m + 1) n and the second TFT 322 (m + 2) n, which are turned on.
 データバスライン22m”から+5Vのデータ信号が供給されることにより、画素310mnの第1液晶容量331mnのnodeXに、データバスライン22m”と同電圧の+5Vが印加される。また、第1液晶容量331mnのnodeYには、基準電圧バスライン18a”と同電圧の0Vが印加される。これによって、第1液晶容量331mnには、図13に示すように、第1液晶容量331mnのnodeXとnodeYとの電位差nodeX-nodeYである+5Vが印加されることになる。 By supplying a data signal of + 5V from the data bus line 22m ″, + 5V of the same voltage as the data bus line 22m ″ is applied to the nodeX of the first liquid crystal capacitor 331mn of the pixel 310mn. Further, 0V, which is the same voltage as the reference voltage bus line 18a ″, is applied to nodeY of the first liquid crystal capacitor 331mn. As a result, as shown in FIG. 13, the first liquid crystal capacitor 331mn has a first liquid crystal capacitor. A potential difference nodeX−nodeY of + 5V between nodeX and nodeY of 331 mn is applied.
 また、画素310mnの第2液晶容量332mnのnodeXには+5Vが印加され、nodeYには基準電圧バスライン18b”と同電圧の1Vが印加される。これによって、第2液晶容量332mnには、第2液晶容量332mnのnodeXとnodeYとの電位差である+4Vが印加されることになる。 Further, +5 V is applied to nodeX of the second liquid crystal capacitor 332 mn of the pixel 310 mn, and 1 V of the same voltage as the reference voltage bus line 18 b ″ is applied to node Y. Thereby, the second liquid crystal capacitor 332 mn + 4V which is a potential difference between nodeX and nodeY of the two liquid crystal capacitors 332 mn is applied.
 同様に、時刻txnにおいて、データバスライン22(m+1)”が-4Vに制御されると、画素310(m+1)nの第1液晶容量331(m+1)nの印加電圧は基準電圧バスライン18b”との電位差である-5Vになり、第2液晶容量332(m+1)nの印加電圧は基準電圧バスライン18a”との電位差である-4Vになる。 Similarly, when the data bus line 22 (m + 1) ″ is controlled to −4V at time txn, the voltage applied to the first liquid crystal capacitor 331 (m + 1) n of the pixel 310 (m + 1) n is the reference voltage bus line 18b ″. Is −5V, and the voltage applied to the second liquid crystal capacitor 332 (m + 1) n is −4V, which is the potential difference from the reference voltage bus line 18a ″.
 次に、時刻tx(n+1)において、n本目のゲートバスライン16n”の走査が停止され、新たにn+1本目のゲートバスライン16(n+1)”が走査されると、第1TFT321m(n+1)及び第2TFT322m(n+1)のゲート端子に走査信号が供給され、ON状態になる。同様に、第1TFT321(m+1)(n+1)、及び、第2TFT322(m+1)(n+1)のゲート端子にも走査信号が供給され、ON状態になる。 Next, at time tx (n + 1), when the scanning of the nth gate bus line 16n ″ is stopped and the n + 1th gate bus line 16 (n + 1) ″ is newly scanned, the first TFT 321m (n + 1) and the second TFT A scanning signal is supplied to the gate terminal of the 2TFT 322m (n + 1), and it is turned on. Similarly, a scanning signal is supplied to the gate terminals of the first TFT 321 (m + 1) (n + 1) and the second TFT 322 (m + 1) (n + 1), and is turned on.
 また、時刻tx(n+1)においてデータバスライン22m”が+4Vに制御されると、図13に示すように、第1液晶容量331m(n+1)の印加電圧は+4Vになり、第2液晶容量332m(n+1)の印加電圧は+3Vになる。同様に、データバスライン22(m+1)”が-3Vに制御されると、第1液晶容量331(m+1)(n+1)の印加電圧は-4Vになり、第2液晶容量332(m+1)(n+1)の印加電圧は-3Vになる。 When the data bus line 22m ″ is controlled to + 4V at time tx (n + 1), as shown in FIG. 13, the applied voltage to the first liquid crystal capacitor 331m (n + 1) becomes + 4V, and the second liquid crystal capacitor 332m ( n + 1) is applied to +3 V. Similarly, when the data bus line 22 (m + 1) ″ is controlled to −3 V, the applied voltage of the first liquid crystal capacitor 331 (m + 1) (n + 1) is −4 V, The applied voltage of the second liquid crystal capacitor 332 (m + 1) (n + 1) is −3V.
 これに対し、時刻tx(n+1)において、n本目のゲートバスライン16n”の走査が停止されることにより、第1TFT321mn及び第2TFT322mnのゲート端子への走査信号の供給が停止され、第1TFT321mn及び第2TFT322mnはOFF状態になる。これによって、第1液晶容量331mn及び第2液晶容量332mnはフローティング状態になる。 On the other hand, at time tx (n + 1), the scanning of the nth gate bus line 16n ″ is stopped, so that the supply of the scanning signal to the gate terminals of the first TFT 321mn and the second TFT 322mn is stopped, and the first TFT 321mn and the first TFT 321mn The 2TFT 322mn is turned off, whereby the first liquid crystal capacitor 331mn and the second liquid crystal capacitor 332mn are in a floating state.
 時刻tx(n+1)においては、データバスライン22m”が+4Vに制御されているため、第1液晶容量331mnのnodeX側にデータバスライン22m”と同じ+4Vが印加される。さらに、第1液晶容量331mnはフローティング状態であるため、時刻txnにおける第1液晶容量331mnのnodeX側の電圧とnodeY側の電圧との電位差+5Vを維持するよう、nodeY側の電圧が-1Vに遷移する。 At time tx (n + 1), since the data bus line 22m ″ is controlled to + 4V, the same + 4V as the data bus line 22m ″ is applied to the nodeX side of the first liquid crystal capacitor 331mn. Further, since the first liquid crystal capacitor 331mn is in a floating state, the voltage on the nodeY side transitions to −1V so that the potential difference + 5V between the nodeX side voltage and the nodeY side voltage of the first liquid crystal capacitor 331mn at time txn is maintained. To do.
 これにより、時刻tx(n+1)において、第1液晶容量331mnの電圧は変化せず、時刻txnにおいて印加された電圧が維持される。すなわち、xフレームを表示するためにゲートバスライン16n”が走査されることで第1液晶容量331mnに印加された電圧は、x+1フレームを表示するために、再びゲートバスライン16n”が走査されるまで、維持されることになる。 Thereby, at time tx (n + 1), the voltage of the first liquid crystal capacitor 331mn does not change, and the voltage applied at time txn is maintained. That is, when the gate bus line 16n ″ is scanned to display the x frame, the voltage applied to the first liquid crystal capacitor 331mn is scanned again to display the x + 1 frame. Until it will be maintained.
 第2液晶容量332mn、第1液晶容量331(m+1)n、及び、第2液晶容量332(m+1)nも同様に、時刻tx(n+1)においても、時刻txnにおいて印加された電圧が維持される。 Similarly, the second liquid crystal capacitor 332mn, the first liquid crystal capacitor 331 (m + 1) n, and the second liquid crystal capacitor 332 (m + 1) n are also maintained at the time txn at time tx (n + 1). .
 (x+1フレーム)
 TFT基板10に形成されるN本全てのゲートバスライン16”に対して、xフレームを表示するための走査が行われると、次に、x+1フレームを表示するための走査が、1本目のゲートバスライン16”から順に開始される。データバスライン22”には、1フレーム前のxフレームでの極性を反転させたデータ信号が供給される。
(X + 1 frame)
When the scan for displaying the x frame is performed on all the N gate bus lines 16 ″ formed on the TFT substrate 10, the scan for displaying the x + 1 frame is performed next. Starting from the bus line 16 ″. A data signal in which the polarity in the x frame one frame before is inverted is supplied to the data bus line 22 ″.
 時刻t(x+1)nにおいて、ゲートバスライン16n”が走査されると、第1TFT321mnのゲート端子に走査信号が供給され、ON状態になる。同様に、第2TFT322mn、第1TFT321(m+1)n、及び、第2TFT322(m+1)nのゲート端子にも走査信号が供給され、ON状態になる。 When the gate bus line 16n ″ is scanned at time t (x + 1) n, a scanning signal is supplied to the gate terminal of the first TFT 321mn, and is turned on. Similarly, the second TFT 322mn, the first TFT 321 (m + 1) n, and The scanning signal is also supplied to the gate terminal of the second TFT 322 (m + 1) n, and the second TFT 322 (m + 1) n is turned on.
 また、時刻t(x+1)nにおいて、データバスライン22m”が-4Vに制御されると、図14に示すように、画素310mnの第1液晶容量331mnのnodeXにデータバスライン22m”と同電圧の-4Vが印加され、nodeYに基準電圧バスライン18a”と同電圧の+1Vが印加される。これによって、第1液晶容量331mnには、図13に示すように、第1液晶容量331mnのnodeXとnodeYとの電位差nodeX-nodeYである-5Vが印加されることになる。 Further, when the data bus line 22m ″ is controlled to −4V at time t (x + 1) n, the same voltage as the data bus line 22m ″ is applied to the nodeX of the first liquid crystal capacitor 331mn of the pixel 310mn as shown in FIG. −4V is applied, and + 1V of the same voltage as that of the reference voltage bus line 18a ″ is applied to nodeY. As a result, nodeX of the first liquid crystal capacitor 331mn is applied to the first liquid crystal capacitor 331mn as shown in FIG. And −5V, which is a potential difference nodeX−nodeY between nodeY and nodeY.
 なお、時刻t(x+1)(n+1)において、ゲートバスライン16n’の走査が停止されることにより、第1TFT321mnはOFF状態になる。これによって、第1液晶容量331mnはフローティング状態になる。 Note that at the time t (x + 1) (n + 1), the scanning of the gate bus line 16n 'is stopped, so that the first TFT 321mn is turned off. As a result, the first liquid crystal capacitor 331mn is in a floating state.
 時刻tx(n+1)においては、データバスライン22m”が-3Vに制御されると、第1液晶容量331mnのnodeX側にデータバスライン22m”と同じ-3Vが印加される。さらに、第1液晶容量331mnはフローティング状態であるため、時刻txnにおける第1液晶容量331mnのnodeX側の電圧とnodeY側の電圧との電位差-5Vを維持するよう、nodeY側の電圧が+1Vに遷移する。 At time tx (n + 1), when the data bus line 22m ″ is controlled to −3V, the same −3V as the data bus line 22m ″ is applied to the nodeX side of the first liquid crystal capacitor 331mn. Further, since the first liquid crystal capacitor 331mn is in a floating state, the voltage on the nodeY side transitions to + 1V so as to maintain the potential difference of −5V between the nodeX side voltage and the nodeY side voltage of the first liquid crystal capacitor 331mn at time txn. To do.
 これにより、時刻tx(n+1)において、第1液晶容量331mnの電圧は変化せず、時刻txnにおいて印加された電圧が維持される。すなわち、xフレームを表示するためにゲートバスライン16n”が走査されることで第1液晶容量331mnに印加された電圧は、x+1フレームを表示するために、再びゲートバスライン16n”が走査されるまで、維持されることになる。 Thereby, at time tx (n + 1), the voltage of the first liquid crystal capacitor 331mn does not change, and the voltage applied at time txn is maintained. That is, when the gate bus line 16n ″ is scanned to display the x frame, the voltage applied to the first liquid crystal capacitor 331mn is scanned again to display the x + 1 frame. Until it will be maintained.
 第2液晶容量332mn、第1液晶容量331(m+1)n、及び、第2液晶容量332(m+1)nも同様に、時刻tx(n+1)においても、時刻txnにおいて印加された電圧が維持される。 Similarly, the second liquid crystal capacitor 332mn, the first liquid crystal capacitor 331 (m + 1) n, and the second liquid crystal capacitor 332 (m + 1) n are also maintained at the time txn at time tx (n + 1). .
 以上のように、本実施形態に係る液晶パネル3の駆動方法は、図13及び図14に基づいて説明した構成を有する液晶パネルにおける駆動方法であって、少なくとも上記行方向に並ぶ第1サブ画素311mn及び第2サブ画素312mnを、第1サブ画素311mnに対応した基準電圧バスライン18a”、及び、第2サブ画素312mnに対応した基準電圧バスライン18b”に印加する各電圧を相違させることによって、データバスライン22m”及び基準電圧バスライン18a”間の電位差と、データバスライン22m”及び基準電圧バスライン18b”間の電位差とを相違させること特徴としている。 As described above, the driving method of the liquid crystal panel 3 according to the present embodiment is a driving method in the liquid crystal panel having the configuration described with reference to FIGS. 13 and 14, and at least the first sub-pixels arranged in the row direction. By making the voltages applied to the reference voltage bus line 18a "corresponding to the first sub pixel 311mn and the reference voltage bus line 18b" corresponding to the second sub pixel 312mn differ between the 311mn and the second sub pixel 312mn. The potential difference between the data bus line 22m ″ and the reference voltage bus line 18a ″ is different from the potential difference between the data bus line 22m ″ and the reference voltage bus line 18b ″.
 これにより、第1サブ画素311mnの液晶層には、データバスライン22m”と基準電圧バスライン18a”との電位差が印加される一方、第2サブ画素312mnの液晶層には、データバスライン22m”と基準電圧バスライン18b”との電位差が印加される。 Accordingly, a potential difference between the data bus line 22m ″ and the reference voltage bus line 18a ″ is applied to the liquid crystal layer of the first sub-pixel 311mn, while the data bus line 22m is applied to the liquid crystal layer of the second sub-pixel 312mn. The potential difference between “and the reference voltage bus line 18b” is applied.
 このとき、それぞれの電位差を相違させているから、第1サブ画素311mnの液晶層にかかる電圧と、第2サブ画素312mnの液晶層にかかる電圧とを相違させることができる。 At this time, since the respective potential differences are made different, the voltage applied to the liquid crystal layer of the first sub-pixel 311mn and the voltage applied to the liquid crystal layer of the second sub-pixel 312mn can be made different.
 これにより、データバスライン22m”に書き込んだ電圧に対して、第1サブ画素311mnにおける液晶分子の配向状態と、第2サブ画素312mnにおける液晶分子の配向状態とを相違させることができる結果、対向マトリクス型の液晶パネルにおける視野角特性を向上させることができる。 As a result, the alignment state of the liquid crystal molecules in the first sub-pixel 311 mn can be made different from the alignment state of the liquid crystal molecules in the second sub-pixel 312 mn with respect to the voltage written to the data bus line 22 m ″. Viewing angle characteristics in a matrix type liquid crystal panel can be improved.
 また、図15に示す液晶パネルのように、マルチ画素を構成する2つのサブ画素の面積比を変えた場合に生じる、視認性の低下を防ぐことができる。例えば、図15に示す液晶パネルでは、図16に示すように、明画素98と暗画素99とが行方向及び列方向に交互に配置され、市松模様を作るため、中間調において、図17に示すように、画像にざらつき間が発生してしまう。 Further, as in the liquid crystal panel shown in FIG. 15, it is possible to prevent a decrease in visibility that occurs when the area ratio of two sub-pixels constituting a multi-pixel is changed. For example, in the liquid crystal panel shown in FIG. 15, as shown in FIG. 16, the bright pixels 98 and the dark pixels 99 are alternately arranged in the row direction and the column direction to form a checkered pattern. As shown in the figure, a rough surface occurs in the image.
 ここで、図16は、従来技術においてマルチ画素を構成する2つのサブ画素の面積比を変えた場合の、それぞれのサブ画素の明暗を模式的に表した図である。また、図17は、従来技術においてマルチ画素を構成する2つのサブ画素の面積比を変えた場合の、表示の一例を示す図である。 Here, FIG. 16 is a diagram schematically showing the brightness of each sub-pixel when the area ratio of two sub-pixels constituting a multi-pixel is changed in the conventional technique. FIG. 17 is a diagram showing an example of display when the area ratio of two sub-pixels constituting a multi-pixel is changed in the related art.
 これに対し、本実施形態に係る液晶パネル3は、行方向に第1サブ画素311及び第2サブ画素312が交互に並んで配置されているが、第1サブ画素311及び第2サブ画素312がそれぞれ列方向に整列するように配置されているため、小さな面積のサブ画素の列と、大きな面積のサブ画素の列とを形成することができる。 In contrast, in the liquid crystal panel 3 according to the present embodiment, the first sub-pixel 311 and the second sub-pixel 312 are alternately arranged in the row direction, but the first sub-pixel 311 and the second sub-pixel 312 are arranged. Are arranged so as to be aligned in the column direction, so that a column of sub-pixels with a small area and a column of sub-pixels with a large area can be formed.
 このような構成では、例えば、小さな面積のサブ画素の列に低階調領域の色から表示させ始め、大きな面積のサブ画素より高い輝度に到達させることができ、大きな面積のサブ画素の列にあとから中間調領域から高階調領域の発光量を補うように発光させることができる。すなわち、市松模様を作らないようにすることができる。この結果、中間調の色に、市松模様の場合に生じるざらつき感を発生しにくくすることができる。 In such a configuration, for example, it is possible to start displaying from a color of a low gradation region in a column of sub pixels of a small area, and to reach a higher luminance than a sub pixel of a large area, Later, light can be emitted so as to compensate for the amount of light emission from the halftone area to the high gradation area. That is, a checkerboard pattern can be avoided. As a result, it is possible to make it difficult to generate a rough feeling that occurs in the case of a checkered pattern in a halftone color.
 (付記事項)
 本発明に係る液晶パネルは、上記の課題を解決するために、第1の基板と、上記第1の基板に対向するように配置された第2の基板と、上記第1の基板と上記第2の基板との間に設けられた液晶層とを備え、複数の画素領域が行方向及び列方向に沿って二次元的に配列した液晶パネルであって、上記画素領域のそれぞれは、少なくとも上記行方向に並ぶ2つの副画素領域を備え、上記第1の基板は、上記行方向に並ぶ上記画素領域に対応して設けられたゲートバスラインと、上記ゲートバスラインに絶縁膜を介して交差するように、上記副画素領域毎に設けられた基準電圧バスラインと、上記副画素領域毎に設けられた画素電極と、上記ゲートバスラインに供給されるゲート信号によって、上記画素電極と、当該画素電極に対応する上記基準電圧バスラインとの電気的な接続をオンオフするスイッチング素子とを備え、上記第2の基板は、上記列方向に並ぶ上記画素領域に対応して、上記副画素領域毎に設けられたデータバスラインを備えたことを特徴としている。
(Additional notes)
In order to solve the above problems, a liquid crystal panel according to the present invention includes a first substrate, a second substrate disposed so as to face the first substrate, the first substrate, and the first substrate. A liquid crystal panel provided between the two substrates and a plurality of pixel regions arranged two-dimensionally along the row direction and the column direction, each of the pixel regions including at least the above-described pixel region The first substrate includes two sub-pixel regions arranged in the row direction, and the first substrate intersects with the gate bus line provided corresponding to the pixel region arranged in the row direction, and the gate bus line through an insulating film. The reference voltage bus line provided for each sub-pixel region, the pixel electrode provided for each sub-pixel region, the gate electrode supplied to the gate bus line, the pixel electrode, The above standard corresponding to the pixel electrode A data bus line provided for each of the sub-pixel regions corresponding to the pixel regions arranged in the column direction. It is characterized by having.
 上記の構成によれば、各画素領域は、少なくとも行方向に並ぶ2つの副画素領域を備え、ゲートバスラインと交差する基準電圧バスラインを副画素領域毎に設けたので、1つの画素領域に無駄なデッドスペースを生じさせることなく、面積が大きい画素電極と、面積が小さい画素電極とを行方向に並べて1つの画素領域に形成することができる。 According to the above configuration, each pixel region includes at least two subpixel regions arranged in the row direction, and the reference voltage bus line intersecting with the gate bus line is provided for each subpixel region. A pixel electrode having a large area and a pixel electrode having a small area can be arranged in the row direction and formed in one pixel region without causing a dead space.
 しかも、副画素領域毎にデータバスラインを設けたので、1つの画素領域に備えられた2つの副画素領域に、任意の値の電圧を印加することができる。 In addition, since a data bus line is provided for each sub-pixel area, a voltage having an arbitrary value can be applied to two sub-pixel areas provided in one pixel area.
 これにより、1つの画素領域に2つの副画素領域が横並びした構成を有する対向マトリクス型の液晶パネルにおいて、無駄なスペースを生じないマルチ画素構造が得られ、視野角特性を向上させることができる。 Thereby, in the counter matrix type liquid crystal panel having a configuration in which two sub-pixel regions are arranged side by side in one pixel region, a multi-pixel structure that does not cause useless space can be obtained, and viewing angle characteristics can be improved.
 また、各画素領域の少なくとも行方向に並ぶ2つの副画素領域に、任意の値の電圧を印加することができるため、液晶パネル完成後に副画素領域間の電位差を自由に設定することができる。これによって、液晶パネルの製造プロセスにバラツキが発生した場合にも、副画素領域間の電圧を適切に調整することができ、歩留まりを向上させることができる。 In addition, since a voltage of an arbitrary value can be applied to at least two subpixel regions arranged in the row direction of each pixel region, a potential difference between the subpixel regions can be freely set after the liquid crystal panel is completed. Thus, even when variations occur in the manufacturing process of the liquid crystal panel, the voltage between the sub-pixel regions can be adjusted appropriately, and the yield can be improved.
 なお、各画素領域が、少なくとも上記行方向に並ぶ2つの副画素領域を備えた構成とは、例えば、行方向に並ぶ2つの副画素領域を2組備え、1つの画素領域に4つの副画素領域を設けることを許容するとの意味である。 The configuration in which each pixel region includes at least two subpixel regions arranged in the row direction includes, for example, two sets of two subpixel regions arranged in the row direction, and four subpixels in one pixel region. This means that it is allowed to provide a region.
 本発明に係る液晶パネルにおいて、上記副画素領域毎に設けられて対をなすデータバスライン及び基準電圧バスライン間の電位差を、上記副画素領域毎に異ならせることが好ましい。 In the liquid crystal panel according to the present invention, it is preferable that the potential difference between the data bus line and the reference voltage bus line which are provided for each sub-pixel region and make a pair is different for each sub-pixel region.
 上記の構成によれば、データバスライン及び基準電圧バスラインが副画素領域毎に対をなして設けられているので、データバスラインに印加する電圧、及び基準電圧バスラインに印加する電圧を様々に変えることによって、データバスライン及び基準電圧バスライン間の電位差を多様に変えることができる。 According to the above configuration, since the data bus line and the reference voltage bus line are provided in pairs for each sub-pixel region, various voltages can be applied to the data bus line and the reference voltage bus line. The potential difference between the data bus line and the reference voltage bus line can be changed in various ways.
 これにより、1つの画素領域に2つの副画素領域が横並びした構成を有する対向マトリクス型の液晶パネルにおいて、無駄なスペースを生じないマルチ画素構造が得られ、視野角特性を向上させることができる。 Thereby, in the counter matrix type liquid crystal panel having a configuration in which two sub-pixel regions are arranged side by side in one pixel region, a multi-pixel structure that does not cause useless space can be obtained, and viewing angle characteristics can be improved.
 本発明に係る液晶パネルにおいて、上記画素領域のそれぞれが備えている上記2つの副画素領域の面積が相違しているとともに、上記副画素領域毎に設けられて対をなすデータバスライン及び基準電圧バスライン間の電位差に関して、上記2つの副画素領域のうち、面積の小さい副画素領域における上記電位差を、面積の大きい副画素領域における上記電位差より大きくすることが好ましい。 In the liquid crystal panel according to the present invention, the two sub-pixel regions provided in each of the pixel regions have different areas, and a data bus line and a reference voltage that are provided for each sub-pixel region and make a pair. Regarding the potential difference between the bus lines, it is preferable that the potential difference in the sub-pixel region having a small area out of the two sub-pixel regions is larger than the potential difference in the sub-pixel region having a large area.
 上記の構成によれば、面積の小さい副画素領域(以下、小副画素領域と呼ぶ)における上記電位差を、面積の大きい副画素領域(以下、大副画素領域と呼ぶ)における上記電位差より大きくするので、小副画素領域の液晶層にかかる電圧は、大副画素領域の液晶層に比べて、早くしきい値を超える。すなわち、小副画素領域の液晶層にかかる電圧が、しきい値を超える時点では、大副画素領域の液晶層にかかる電圧は、しきい値を超えていない。 According to the above configuration, the potential difference in a sub-pixel region having a small area (hereinafter referred to as a small sub-pixel region) is made larger than the potential difference in a sub-pixel region having a large area (hereinafter referred to as a large sub-pixel region). Therefore, the voltage applied to the liquid crystal layer in the small sub-pixel region exceeds the threshold value earlier than the liquid crystal layer in the large sub-pixel region. That is, when the voltage applied to the liquid crystal layer in the small sub-pixel region exceeds the threshold value, the voltage applied to the liquid crystal layer in the large sub-pixel region does not exceed the threshold value.
 この場合、大副画素領域が発光を開始する前に、小副画素領域が低階調領域の色から先に表示し始め、大副画素領域より高い輝度に到達し、大副画素領域はあとから中間調領域から高階調領域の発光量を補うように発光する。つまり、小副画素領域は、低階調から中間調の表示に主に寄与する一方、大副画素領域は、中間調から高階調の表示に主に寄与する。このようにすると、視野角特性を所望の特性に制御しやすくなる。 In this case, before the large sub-pixel area starts to emit light, the small sub-pixel area starts to display the color of the low gradation area first, reaches a higher brightness than the large sub-pixel area, Thus, light is emitted so as to compensate the light emission amount from the halftone area to the high gradation area. In other words, the small sub-pixel region mainly contributes to the display from low gradation to halftone, while the large sub-pixel region mainly contributes to the display from halftone to high gradation. This makes it easy to control the viewing angle characteristic to a desired characteristic.
 また、人の視覚は、高階調領域の色よりも低階調領域の色に敏感に反応するため、低階調領域を小副画素領域にする方が、低階調領域を大副画素領域にするよりも、視野角特性をより向上させることができる。 In addition, since human vision reacts more sensitively to colors in the low gradation area than in the high gradation area, the low gradation area is the large subpixel area when the low gradation area is the small subpixel area. The viewing angle characteristics can be further improved than the above.
 上記小副画素領域と大副画素領域との適切な面積比としては、例えば、1より大きく4以下である場合を例に挙げることができる。 As an appropriate area ratio between the small sub-pixel region and the large sub-pixel region, for example, a case where it is greater than 1 and 4 or less can be cited as an example.
 本発明に係る液晶パネルは、上記の課題を解決するために、第1の基板と、上記第1の基板に対向するように配置された第2の基板と、上記第1の基板と上記第2の基板との間に設けられた液晶層とを備え、複数の画素領域が行方向及び列方向に沿って二次元的に配列し、かつ上記画素領域のそれぞれは、少なくとも上記列方向に並ぶ2つの副画素領域を備えた液晶パネルであって、上記第1の基板は、上記行方向に並ぶ上記画素領域に対応して設けられたゲートバスラインと、上記行方向に並ぶ上記画素領域に対応して、上記副画素領域毎に設けられた基準電圧バスラインと、上記副画素領域毎に設けられた画素電極と、上記ゲートバスラインに供給されるゲート信号によって、上記画素電極と上記基準電圧バスラインとの電気的な接続をオンオフするスイッチング素子とを備え、上記第2の基板は、上記列方向に並ぶ上記画素領域に対応して設けられたデータバスラインを備え、上記ゲートバスラインを蛇行形状とすることによって、上記2つの副画素領域の面積を異ならせることを特徴としている。 In order to solve the above problems, a liquid crystal panel according to the present invention includes a first substrate, a second substrate disposed so as to face the first substrate, the first substrate, and the first substrate. A plurality of pixel regions are two-dimensionally arranged along the row direction and the column direction, and each of the pixel regions is arranged at least in the column direction. A liquid crystal panel having two sub-pixel regions, wherein the first substrate is formed on gate bus lines provided corresponding to the pixel regions arranged in the row direction and in the pixel regions arranged in the row direction. Correspondingly, the reference voltage bus line provided for each sub-pixel region, the pixel electrode provided for each sub-pixel region, and the gate signal supplied to the gate bus line, the pixel electrode and the reference Electrical connection to the voltage bus line The second substrate includes a data bus line provided corresponding to the pixel region arranged in the column direction, and the gate bus line is formed in a meandering shape. It is characterized in that the areas of the two sub-pixel regions are different.
 上記の構成によれば、ゲートバスラインとデータバスラインとが、液晶層を挟んで対向する第1の基板と第2の基板とに分かれて設けられた構成の液晶パネルにおいて、第1の基板に副画素領域毎に画素電極を設ける場合に、1つの画素領域にデッドスペースを作らずに、面積の異なる2つの画素電極を列方向に並べて設けることができる。 According to the above configuration, in the liquid crystal panel having the configuration in which the gate bus line and the data bus line are separately provided on the first substrate and the second substrate facing each other with the liquid crystal layer interposed therebetween, the first substrate When a pixel electrode is provided for each sub-pixel region, two pixel electrodes having different areas can be provided side by side in the column direction without creating a dead space in one pixel region.
 その理由は以下のとおりである。例えば、上記蛇行形状の中心線が、上記画素領域を上記列方向に並ぶ等面積の2つの領域に分割する2等分線であるとする。その中心線から上記列方向に対してゲートバスラインが変位すると、列方向に並ぶ等面積の2つの領域は、自ずと面積の異なる領域となる。 The reason is as follows. For example, it is assumed that the meandering center line is a bisector that divides the pixel region into two regions of equal area arranged in the column direction. When the gate bus line is displaced from the center line in the column direction, the two regions having the same area aligned in the column direction naturally have different areas.
 仮に、ゲートバスラインを蛇行させず、上記の等面積の2つの領域の一方の画素電極を単に小さくすることによって、面積の小さい画素電極を形成するとすれば、面積の小さい画素電極を形成した副画素領域にデッドスペースが生じる。 If a pixel electrode having a small area is formed by simply reducing one pixel electrode of the two regions having the same area without meandering the gate bus line, the sub-electrode on which the pixel electrode having a small area is formed. Dead space occurs in the pixel area.
 これに対し、本発明では、ゲートバスラインを蛇行させることによって、副画素領域自体の面積を異ならせているので、1つの画素領域に無駄なデッドスペースを生じさせることなく、面積が大きい画素電極と、面積が小さい画素電極とを1つの画素領域に形成することができる。 On the other hand, in the present invention, the area of the sub-pixel region itself is made different by meandering the gate bus line, so that a pixel electrode having a large area can be obtained without causing a dead space in one pixel region. And a pixel electrode having a small area can be formed in one pixel region.
 これにより、1つの画素領域に2つの副画素領域が縦並びした構成を有する対向マトリクス型の液晶パネルにおいて、無駄なスペースを生じないマルチ画素構造が得られ、視野角特性を向上させることができる。 As a result, in a counter matrix type liquid crystal panel having a configuration in which two sub-pixel regions are vertically arranged in one pixel region, a multi-pixel structure that does not cause useless space can be obtained, and viewing angle characteristics can be improved. .
 なお、各画素領域が、少なくとも上記列方向に並ぶ2つの副画素領域を備えた構成とは、例えば、列方向に並ぶ2つの副画素領域を2組備え、1つの画素領域に4つの副画素領域を設けることを許容するとの意味である。 Note that the configuration in which each pixel area includes at least two subpixel areas arranged in the column direction includes, for example, two sets of two subpixel areas arranged in the column direction, and four subpixels in one pixel area. This means that it is allowed to provide a region.
 本発明に係る液晶パネルにおいて、上記蛇行形状の中心線は、上記画素領域を上記列方向に等しい幅で並ぶ2つの領域に分割する2等分線であり、上記画素電極毎に設けられた上記スイッチング素子は、上記蛇行形状の折曲部毎に1つずつ設けられていることが好ましい。 In the liquid crystal panel according to the present invention, the meandering center line is a bisector that divides the pixel region into two regions arranged with the same width in the column direction, and is provided for each pixel electrode. One switching element is preferably provided for each meandering bent portion.
 上記の構成によれば、ゲートバスラインが行方向に沿って蛇行するときの2等分線からの蛇行の幅を揃える構成を選択することができ、それによって、面積大の画素電極と、面積小の画素電極とを、一定の面積比率で、行方向に沿って配置することができる。 According to the above configuration, it is possible to select a configuration in which the width of the meander from the bisector when the gate bus line meanders along the row direction can be selected. Small pixel electrodes can be arranged along the row direction at a constant area ratio.
 また、各画素電極毎に設けられたスイッチング素子を、上記蛇行形状の折曲部毎に1つずつ設けることによって、スイッチング素子の配置のレイアウトをシンプルにすることができる。 Also, by providing one switching element provided for each pixel electrode for each meander-shaped bent portion, the layout of the switching element arrangement can be simplified.
 本発明に係る液晶パネルにおいて、上記列方向に隣り合う2つの上記画素領域を第1の画素領域及び第2の画素領域とした場合、当該第1の画素領域が列方向に並ぶ第1の副画素領域と第2の副画素領域とを備え、当該第2の画素領域が列方向に並ぶ第3の副画素領域と第4の副画素領域とを備え、上記基準電圧バスラインは、上記列方向に隣り合う上記第2の副画素領域と上記第3の副画素領域とに共有されていることが好ましい。 In the liquid crystal panel according to the present invention, when the two pixel regions adjacent to each other in the column direction are a first pixel region and a second pixel region, the first pixel region is arranged in the column direction. A pixel region and a second sub-pixel region, and the second pixel region includes a third sub-pixel region and a fourth sub-pixel region arranged in the column direction, and the reference voltage bus line includes the column It is preferable that the second subpixel region and the third subpixel region which are adjacent to each other in the direction are shared.
 上記の構成によれば、列方向に隣り合う画素領域が、1つの基準電圧バスラインを共有できるので、シンプルな配線レイアウトにすることができる。 According to the above configuration, pixel regions adjacent in the column direction can share one reference voltage bus line, so that a simple wiring layout can be achieved.
 本発明に係る液晶パネルは、上記の課題を解決するために、第1の基板と、上記第1の基板に対向するように配置された第2の基板と、上記第1の基板と上記第2の基板との間に設けられた液晶層とを備え、複数の画素領域が行方向及び列方向に沿って二次元的に配列した液晶パネルであって、上記画素領域のそれぞれは、少なくとも上記行方向に並ぶ2つの副画素領域を備え、記第1の基板は、上記行方向に並ぶ上記画素領域に対応して設けられたゲートバスラインと、上記ゲートバスラインに絶縁膜を介して交差するように、上記副画素領域毎に設けられた基準電圧バスラインと、上記副画素領域毎に設けられた画素電極と、上記ゲートバスラインに供給されるゲート信号によって、上記画素電極と、当該画素電極に対応する基準電圧バスラインとの電気的な接続をオンオフするスイッチング素子とを備え、上記第2の基板は、上記列方向に並ぶ上記画素領域に対応して、上記2つの副画素領域に共通に設けられたデータバスラインを備えたことを特徴としている。 In order to solve the above problems, a liquid crystal panel according to the present invention includes a first substrate, a second substrate disposed so as to face the first substrate, the first substrate, and the first substrate. A liquid crystal panel provided between the two substrates and a plurality of pixel regions arranged two-dimensionally along the row direction and the column direction, each of the pixel regions including at least the above-described pixel region The first substrate includes two sub-pixel regions arranged in the row direction, and the first substrate intersects with the gate bus lines provided corresponding to the pixel regions arranged in the row direction, and the gate bus lines via an insulating film. The reference voltage bus line provided for each sub-pixel region, the pixel electrode provided for each sub-pixel region, the gate electrode supplied to the gate bus line, the pixel electrode, Reference voltage corresponding to the pixel electrode A data bus provided in common in the two sub-pixel regions corresponding to the pixel regions arranged in the column direction. It is characterized by having a line.
 上記の構成によれば、各画素領域は、少なくとも行方向に並ぶ2つの副画素領域を備え、ゲートバスラインと交差する基準電圧バスラインを副画素領域毎に設けたので、1つの画素領域に無駄なデッドスペースを生じさせることなく、面積が大きい画素電極と、面積が小さい画素電極とを行方向に並べて1つの画素領域に形成することができる。 According to the above configuration, each pixel region includes at least two subpixel regions arranged in the row direction, and the reference voltage bus line intersecting with the gate bus line is provided for each subpixel region. A pixel electrode having a large area and a pixel electrode having a small area can be arranged in the row direction and formed in one pixel region without causing a dead space.
 しかも、2つの副画素領域に共通にデータバスラインを設けたので、副画素領域毎に設けた基準電圧バスラインに印加する電圧を副画素領域に応じて変えることにより、データバスラインと基準電圧バスラインとの電位差を、副画素領域毎に変えることができる。 In addition, since the data bus line is provided in common in the two subpixel regions, the data bus line and the reference voltage can be changed by changing the voltage applied to the reference voltage bus line provided for each subpixel region according to the subpixel region. The potential difference from the bus line can be changed for each sub-pixel region.
 これにより、1つの画素領域に2つの副画素領域が横並びした構成を有する対向マトリクス型の液晶パネルにおいて、無駄なスペースを生じないマルチ画素構造が得られ、視野角特性を向上させることができる。 Thereby, in the counter matrix type liquid crystal panel having a configuration in which two sub-pixel regions are arranged side by side in one pixel region, a multi-pixel structure that does not cause useless space can be obtained, and viewing angle characteristics can be improved.
 なお、各画素領域が、少なくとも上記行方向に並ぶ2つの副画素領域を備えた構成とは、例えば、行方向に並ぶ2つの副画素領域を2組備え、1つの画素領域に4つの副画素領域を設けることを許容するとの意味である。 The configuration in which each pixel region includes at least two subpixel regions arranged in the row direction includes, for example, two sets of two subpixel regions arranged in the row direction, and four subpixels in one pixel region. This means that it is allowed to provide a region.
 また、列方向に並ぶ各画素領域について、行方向に並ぶ2つの副画素領域の面積を異ならせるとともに、上記2つの副画素領域のうち、面積が小さい方の副画素領域または面積が大きい方の副画素領域が、列方向に整列するように配置してもよい。 In addition, for each pixel region arranged in the column direction, the areas of the two subpixel regions arranged in the row direction are made different, and of the two subpixel regions, the smaller subpixel region or the larger one of the two subpixel regions The subpixel regions may be arranged so as to be aligned in the column direction.
 この場合、小さな面積の副画素領域の列と、大きな面積の副画素領域の列とを形成することができる。このような構成では、例えば、小さな面積の副画素領域の列に低階調領域から中間調領域の色を表示させ、大きな面積の副画素領域の列に中間調領域から高階調領域の色を表示させることができる。すなわち市松模様を作らないようにすることができる。この結果、中間調の色に、市松模様の場合に生じるざらつき感を発生しにくくすることができる。 In this case, a column of sub-pixel regions having a small area and a column of sub-pixel regions having a large area can be formed. In such a configuration, for example, the color of the low gradation area to the halftone area is displayed on the column of the subpixel area having a small area, and the color of the high gradation area from the halftone area is displayed on the column of the subpixel area having a large area. Can be displayed. In other words, it is possible to avoid making a checkered pattern. As a result, it is possible to make it difficult to generate a rough feeling that occurs in the case of a checkered pattern in a halftone color.
 本発明に係る液晶パネルにおいて、上記行方向に隣り合う2つの上記画素領域を第1の画素領域及び第2の画素領域とした場合、当該第1の画素領域が行方向に並ぶ第1の副画素領域と第2の副画素領域とを備え、当該第2の画素領域が行方向に並ぶ第3の副画素領域と第4の副画素領域とを備え、上記基準電圧バスラインは、上記行方向に隣り合う上記第2の副画素領域と上記第3の副画素領域とに共有されていることが好ましい。 In the liquid crystal panel according to the present invention, when the two pixel regions adjacent to each other in the row direction are a first pixel region and a second pixel region, the first sub-regions are arranged in the row direction. A pixel region and a second sub-pixel region, and the second pixel region includes a third sub-pixel region and a fourth sub-pixel region arranged in the row direction, and the reference voltage bus line includes the row It is preferable that the second subpixel region and the third subpixel region which are adjacent to each other in the direction are shared.
 上記の構成によれば、行方向に隣り合う画素領域が、1つの基準電圧バスラインを共有できるので、シンプルな配線レイアウトにすることができる。 According to the above configuration, pixel regions adjacent in the row direction can share one reference voltage bus line, so that a simple wiring layout can be achieved.
 本発明に係る液晶パネルを備える表示装置も、本発明の範疇に含まれる。 A display device including the liquid crystal panel according to the present invention is also included in the scope of the present invention.
 本発明に係る液晶パネルの駆動方法は、上述した液晶パネルにおける駆動方法であって、少なくとも上記行方向に並ぶ上記2つの副画素領域を、第1の副画素領域及び第2の副画素領域とし、上記第1の副画素領域に対応した基準電圧バスラインを第1の基準電圧バスラインとし、上記第2の副画素領域に対応した基準電圧バスラインを第2の基準電圧バスラインとし、上記第1の副画素領域に対応したデータバスラインを第1のデータバスラインとし、上記第2の副画素領域に対応したデータバスラインを第2のデータバスラインとすると、上記第1の基準電圧バスライン及び上記第2の基準電圧バスラインに印加する各電圧を同一にし、上記第1のデータバスライン及び上記第2のデータバスラインに印加する電圧を相違させることによって、上記第1のデータバスライン及び上記第1の基準電圧バスライン間の電位差と、上記第2のデータバスライン及び上記第2の基準電圧バスライン間の電位差とを相違させることを特徴としている。 A driving method of a liquid crystal panel according to the present invention is a driving method in the above-described liquid crystal panel, and at least the two subpixel regions arranged in the row direction are defined as a first subpixel region and a second subpixel region. The reference voltage bus line corresponding to the first sub-pixel region is a first reference voltage bus line, the reference voltage bus line corresponding to the second sub-pixel region is a second reference voltage bus line, and If the data bus line corresponding to the first sub-pixel region is the first data bus line and the data bus line corresponding to the second sub-pixel region is the second data bus line, the first reference voltage The voltages applied to the bus line and the second reference voltage bus line are made the same, and the voltages applied to the first data bus line and the second data bus line are made different. The potential difference between the first data bus line and the first reference voltage bus line is made different from the potential difference between the second data bus line and the second reference voltage bus line. It is said.
 上記の構成によれば、画素領域に対応して設けられたゲートバスラインにゲート信号が出力されると、上記スイッチング素子がオンになり、少なくとも上記行方向に並ぶ上記第1の副画素領域及び第2の副画素領域が同時に選択され、各副画素領域の画素電極に、各副画素領域に対応した基準電圧バスラインに印加された電圧が書き込まれる。 According to the above configuration, when a gate signal is output to the gate bus line provided corresponding to the pixel region, the switching element is turned on, and at least the first sub-pixel region aligned in the row direction and The second subpixel region is selected at the same time, and the voltage applied to the reference voltage bus line corresponding to each subpixel region is written into the pixel electrode of each subpixel region.
 各副画素領域の画素電極には各データバスラインが対向しているから、第1の副画素領域の液晶層には、第1のデータバスラインと第1の基準電圧バスラインとの電位差が印加される一方、第2の副画素領域の液晶層には、第2のデータバスラインと第2の基準電圧バスラインとの電位差が印加される。 Since each data bus line is opposed to the pixel electrode in each sub-pixel region, the liquid crystal layer in the first sub-pixel region has a potential difference between the first data bus line and the first reference voltage bus line. On the other hand, a potential difference between the second data bus line and the second reference voltage bus line is applied to the liquid crystal layer in the second subpixel region.
 このとき、第1の基準電圧バスラインに印加された電圧と、第2の基準電圧バスラインに印加された電圧とは同一であり、第1のデータバスライン及び第2のデータバスラインに印加する電圧を相違させているから、第1の副画素領域の液晶層にかかる電圧と、第2の副画素領域の液晶層にかかる電圧とを相違させることができる。 At this time, the voltage applied to the first reference voltage bus line is the same as the voltage applied to the second reference voltage bus line, and is applied to the first data bus line and the second data bus line. Therefore, the voltage applied to the liquid crystal layer in the first subpixel region can be made different from the voltage applied to the liquid crystal layer in the second subpixel region.
 これにより、第1の副画素領域における液晶分子の配向状態と、第2の副画素領域における液晶分子の配向状態とを、第1のデータバスライン及び第2のデータバスラインに印加する各電圧に応じて相違させることができる結果、対向マトリクス型の液晶パネルにおける視野角特性を向上させることができる。 As a result, the voltages applied to the first data bus line and the second data bus line based on the alignment state of the liquid crystal molecules in the first sub-pixel region and the alignment state of the liquid crystal molecules in the second sub-pixel region. As a result, the viewing angle characteristics in the counter matrix type liquid crystal panel can be improved.
 本発明に係る液晶パネルの駆動方法は、上述した液晶パネルにおける駆動方法であって、少なくとも上記列方向に並ぶ上記2つの副画素領域のうち一方の副画素領域に対応した基準電圧バスラインを第1の基準電圧バスラインとし、他方の副画素領域に対応した基準電圧バスラインを第2の基準電圧バスラインとすると、上記第1の基準電圧バスライン及び上記第2の基準電圧バスラインに印加する各電圧を相違させることによって、上記データバスライン及び上記第1の基準電圧バスライン間の電位差と、上記データバスライン及び上記第2の基準電圧バスライン間の電位差とを相違させることを特徴としている。 A driving method of a liquid crystal panel according to the present invention is a driving method in the above-described liquid crystal panel, and a reference voltage bus line corresponding to at least one of the two sub-pixel regions arranged in the column direction is connected to the first voltage line. When the reference voltage bus line corresponding to the other sub-pixel region is the second reference voltage bus line, the first reference voltage bus line is applied to the first reference voltage bus line and the second reference voltage bus line. The potential difference between the data bus line and the first reference voltage bus line is made different from the potential difference between the data bus line and the second reference voltage bus line by making each voltage different. It is said.
 上記の構成によれば、画素領域に対応して設けられたゲートバスラインにゲート信号が出力されると、上記スイッチング素子がオンになり、少なくとも上記列方向に並ぶ2つの副画素領域が同時に選択され、各副画素領域の画素電極に、各副画素領域に対応した基準電圧バスラインに印加された電圧が書き込まれる。 According to the above configuration, when a gate signal is output to the gate bus line provided corresponding to the pixel region, the switching element is turned on, and at least two sub-pixel regions arranged in the column direction are simultaneously selected. Then, the voltage applied to the reference voltage bus line corresponding to each subpixel region is written into the pixel electrode of each subpixel region.
 各副画素領域の画素電極にはデータバスラインが対向しているから、上記一方の副画素領域の液晶層には、データバスラインと第1の基準電圧バスラインとの電位差が印加される一方、上記他方の副画素領域の液晶層には、データバスラインと第2の基準電圧バスラインとの電位差が印加される。 Since the data bus line is opposed to the pixel electrode of each sub-pixel region, a potential difference between the data bus line and the first reference voltage bus line is applied to the liquid crystal layer of the one sub-pixel region. The potential difference between the data bus line and the second reference voltage bus line is applied to the liquid crystal layer in the other sub-pixel region.
 このとき、それぞれの電位差を相違させているから、上記一方の副画素領域の液晶層にかかる電圧と、上記他方の副画素領域の液晶層にかかる電圧とを相違させることができる。 At this time, since the respective potential differences are made different, the voltage applied to the liquid crystal layer in the one sub-pixel region can be made different from the voltage applied to the liquid crystal layer in the other sub-pixel region.
 これにより、データバスラインに書き込んだ電圧に対して、上記一方の副画素領域における液晶分子の配向状態と、上記他方の副画素領域における液晶分子の配向状態とを相違させることができる結果、対向マトリクス型の液晶パネルにおける視野角特性を向上させることができる。 As a result, the alignment state of the liquid crystal molecules in the one subpixel region can be made different from the alignment state of the liquid crystal molecules in the other subpixel region with respect to the voltage written to the data bus line. Viewing angle characteristics in a matrix type liquid crystal panel can be improved.
 なお、上記ゲートバスラインを蛇行形状とすることによって、上記2つの副画素領域の面積は異なっている。この場合、あるデータバスラインに対応した2つの副画素領域の一方の副画素領域の面積が、他方の副画素領域の面積より小さいとすると、上記あるデータバスラインに隣り合うデータバスラインに対応した2つの副画素領域の一方の副画素領域の面積は、他方の副画素領域の面積より大きくなる。 Note that the areas of the two sub-pixel regions are different by making the gate bus line meandering. In this case, if the area of one subpixel area of two subpixel areas corresponding to a certain data bus line is smaller than the area of the other subpixel area, it corresponds to the data bus line adjacent to the data bus line. The area of one of the two subpixel areas is larger than the area of the other subpixel area.
 本発明に係る液晶パネルの駆動方法は、上述した液晶パネルにおける駆動方法であって、少なくとも上記行方向に並ぶ上記2つの副画素領域を、第1の副画素領域及び第2の副画素領域とし、上記第1の副画素領域に対応した基準電圧バスラインを第1の基準電圧バスラインとし、上記第2の副画素領域に対応した基準電圧バスラインを第2の基準電圧バスラインとすると、上記第1の基準電圧バスライン及び上記第2の基準電圧バスラインに印加する各電圧を相違させることによって、上記データバスライン及び上記第1の基準電圧バスライン間の電位差と、上記データバスライン及び上記第2の基準電圧バスライン間の電位差とを相違させること特徴としている。 A driving method of a liquid crystal panel according to the present invention is a driving method in the above-described liquid crystal panel, and at least the two subpixel regions arranged in the row direction are defined as a first subpixel region and a second subpixel region. The reference voltage bus line corresponding to the first sub-pixel region is a first reference voltage bus line, and the reference voltage bus line corresponding to the second sub-pixel region is a second reference voltage bus line. By making each voltage applied to the first reference voltage bus line and the second reference voltage bus line different, a potential difference between the data bus line and the first reference voltage bus line, and the data bus line And the potential difference between the second reference voltage bus lines is different.
 上記の構成によれば、画素領域に対応して設けられたゲートバスラインにゲート信号が出力されると、上記スイッチング素子がオンになり、少なくとも上記行方向に並ぶ上記第1の副画素領域及び第2の副画素領域が同時に選択され、各副画素領域の画素電極に、各副画素領域に対応した基準電圧バスラインに印加された電圧が書き込まれる。 According to the above configuration, when a gate signal is output to the gate bus line provided corresponding to the pixel region, the switching element is turned on, and at least the first sub-pixel region aligned in the row direction and The second subpixel region is selected at the same time, and the voltage applied to the reference voltage bus line corresponding to each subpixel region is written into the pixel electrode of each subpixel region.
 各副画素領域の画素電極には共通のデータバスラインが対向しているから、第1の副画素領域の液晶層には、データバスラインと第1の基準電圧バスラインとの電位差が印加される一方、第2の副画素領域の液晶層には、データバスラインと第2の基準電圧バスラインとの電位差が印加される。 Since the common data bus line is opposed to the pixel electrode in each sub-pixel region, a potential difference between the data bus line and the first reference voltage bus line is applied to the liquid crystal layer in the first sub-pixel region. On the other hand, a potential difference between the data bus line and the second reference voltage bus line is applied to the liquid crystal layer in the second subpixel region.
 このとき、それぞれの電位差を相違させているから、第1の副画素領域の液晶層にかかる電圧と、第2の副画素領域の液晶層にかかる電圧とを相違させることができる。 At this time, since the respective potential differences are made different, the voltage applied to the liquid crystal layer in the first subpixel region can be made different from the voltage applied to the liquid crystal layer in the second subpixel region.
 これにより、データバスラインに書き込んだ電圧に対して、第1の副画素領域における液晶分子の配向状態と、第2の副画素領域における液晶分子の配向状態とを相違させることができる結果、対向マトリクス型の液晶パネルにおける視野角特性を向上させることができる。 As a result, the alignment state of the liquid crystal molecules in the first subpixel region can be made different from the alignment state of the liquid crystal molecules in the second subpixel region with respect to the voltage written to the data bus line. Viewing angle characteristics in a matrix type liquid crystal panel can be improved.
 本発明に係る液晶パネルは、TV、パーソナル・コンピューターのモニタ、携帯電話などに好適に適用することができる。 The liquid crystal panel according to the present invention can be suitably applied to TVs, personal computer monitors, mobile phones and the like.
 1~3    液晶パネル
 10     TFT基板(第1の基板)
 12     TFT(スイッチング素子)
 13     液晶容量
 14     画素電極
 16     ゲートバスライン
 16a    ゲート入力端子
 18   基準電圧バスライン
 18c    基準電圧入力端子
 20     対向基板(第2の基板)
 22     データバスライン
 22a    データ入力端子
 24     対向電極
 30     フレキシブルプリント基板
 32     ゲート駆動回路
 34     データ駆動回路
 110、210、310  画素(画素領域)
 111、211、311  第1サブ画素(第1の副画素領域、第3の副画素領域)
 112、212、312  第2サブ画素(第2の副画素領域、第4の副画素領域)
 121、221、321  第1TFT
 122、222、322  第2TFT
 131、231、331  第1液晶容量
 132、232、332  第2液晶容量
 141、241、341  第1画素電極
 142、242、342  第2画素電極
 151  第1コンデンサ
 152  第2コンデンサ
1-3 Liquid crystal panel 10 TFT substrate (first substrate)
12 TFT (switching element)
13 Liquid crystal capacitance 14 Pixel electrode 16 Gate bus line 16a Gate input terminal 18 Reference voltage bus line 18c Reference voltage input terminal 20 Counter substrate (second substrate)
22 Data Bus Line 22a Data Input Terminal 24 Counter Electrode 30 Flexible Printed Circuit Board 32 Gate Drive Circuit 34 Data Drive Circuit 110, 210, 310 Pixel (Pixel Area)
111, 211, 311 First sub-pixel (first sub-pixel region, third sub-pixel region)
112, 212, 312 Second subpixel (second subpixel region, fourth subpixel region)
121, 221 and 321 1st TFT
122, 222, 322 second TFT
131,231,331 First liquid crystal capacitor 132,232,332 Second liquid crystal capacitor 141,241,341 First pixel electrode 142,242,342 Second pixel electrode 151 First capacitor 152 Second capacitor

Claims (12)

  1.  第1の基板と、上記第1の基板に対向するように配置された第2の基板と、上記第1の基板と上記第2の基板との間に設けられた液晶層とを備え、複数の画素領域が行方向及び列方向に沿って二次元的に配列した液晶パネルであって、
     上記画素領域のそれぞれは、少なくとも上記行方向に並ぶ2つの副画素領域を備え、
     上記第1の基板は、
      上記行方向に並ぶ上記画素領域に対応して設けられたゲートバスラインと、
      上記ゲートバスラインに絶縁膜を介して交差するように、上記副画素領域毎に設けられた基準電圧バスラインと、
      上記副画素領域毎に設けられた画素電極と、
      上記ゲートバスラインに供給されるゲート信号によって、上記画素電極と、当該画素電極に対応する上記基準電圧バスラインとの電気的な接続をオンオフするスイッチング素子とを備え、
     上記第2の基板は、
      上記列方向に並ぶ上記画素領域に対応して、上記副画素領域毎に設けられたデータバスラインを備えたこと
    を特徴とする液晶パネル。
    A plurality of first substrates; a second substrate disposed to face the first substrate; and a liquid crystal layer provided between the first substrate and the second substrate. A liquid crystal panel in which the pixel regions are two-dimensionally arranged along the row direction and the column direction,
    Each of the pixel regions includes at least two subpixel regions arranged in the row direction,
    The first substrate is
    Gate bus lines provided corresponding to the pixel regions arranged in the row direction;
    A reference voltage bus line provided for each sub-pixel region so as to intersect the gate bus line via an insulating film;
    A pixel electrode provided for each of the sub-pixel regions;
    A switching element for turning on and off the electrical connection between the pixel electrode and the reference voltage bus line corresponding to the pixel electrode by a gate signal supplied to the gate bus line;
    The second substrate is
    A liquid crystal panel comprising a data bus line provided for each of the sub-pixel areas corresponding to the pixel areas arranged in the column direction.
  2.  上記副画素領域毎に設けられて対をなすデータバスライン及び基準電圧バスライン間の電位差を、上記副画素領域毎に異ならせること
    を特徴とする請求項1に記載の液晶パネル。
    2. The liquid crystal panel according to claim 1, wherein a potential difference between a data bus line and a reference voltage bus line which are provided for each sub-pixel region and make a pair is different for each sub-pixel region.
  3.  上記画素領域のそれぞれが備えている上記2つの副画素領域の面積が相違しているとともに、上記副画素領域毎に設けられて対をなすデータバスライン及び基準電圧バスライン間の電位差に関して、上記2つの副画素領域のうち、面積の小さい副画素領域における上記電位差を、面積の大きい副画素領域における上記電位差より大きくすること
    を特徴とする請求項1または2に記載の液晶パネル。
    The areas of the two sub-pixel regions provided in each of the pixel regions are different, and the potential difference between the data bus line and the reference voltage bus line that are provided for each sub-pixel region and make a pair is described above. 3. The liquid crystal panel according to claim 1, wherein the potential difference in a sub-pixel region having a small area is larger than the potential difference in a sub-pixel region having a large area among two sub-pixel regions.
  4.  第1の基板と、上記第1の基板に対向するように配置された第2の基板と、上記第1の基板と上記第2の基板との間に設けられた液晶層とを備え、複数の画素領域が行方向及び列方向に沿って二次元的に配列し、かつ上記画素領域のそれぞれは、少なくとも上記列方向に並ぶ2つの副画素領域を備えた液晶パネルであって、
     上記第1の基板は、
      上記行方向に並ぶ上記画素領域に対応して設けられたゲートバスラインと、
      上記行方向に並ぶ上記画素領域に対応して、上記副画素領域毎に設けられた基準電圧バスラインと、
      上記副画素領域毎に設けられた画素電極と、
      上記ゲートバスラインに供給されるゲート信号によって、上記画素電極と上記基準電圧バスラインとの電気的な接続をオンオフするスイッチング素子とを備え、
     上記第2の基板は、
      上記列方向に並ぶ上記画素領域に対応して設けられたデータバスラインを備え、
     上記ゲートバスラインを蛇行形状とすることによって、上記2つの副画素領域の面積を異ならせること
    を特徴とする液晶パネル。
    A plurality of first substrates; a second substrate disposed to face the first substrate; and a liquid crystal layer provided between the first substrate and the second substrate. The pixel regions are two-dimensionally arranged along the row direction and the column direction, and each of the pixel regions is a liquid crystal panel including at least two sub-pixel regions arranged in the column direction,
    The first substrate is
    Gate bus lines provided corresponding to the pixel regions arranged in the row direction;
    A reference voltage bus line provided for each of the sub-pixel regions corresponding to the pixel regions arranged in the row direction,
    A pixel electrode provided for each of the sub-pixel regions;
    A switching element for turning on and off the electrical connection between the pixel electrode and the reference voltage bus line by a gate signal supplied to the gate bus line;
    The second substrate is
    A data bus line provided corresponding to the pixel region arranged in the column direction;
    The liquid crystal panel according to claim 1, wherein the gate bus lines have a meandering shape so that the areas of the two sub-pixel regions are different.
  5.  上記蛇行形状の中心線は、上記画素領域を上記列方向に等しい幅で並ぶ2つの領域に分割する2等分線であり、
     上記画素電極毎に設けられた上記スイッチング素子は、上記蛇行形状の折曲部毎に1つずつ設けられていること
    を特徴とする請求項4に記載の液晶パネル。
    The meandering center line is a bisector that divides the pixel region into two regions lined up with equal width in the column direction,
    5. The liquid crystal panel according to claim 4, wherein the switching element provided for each pixel electrode is provided one for each meandering bent portion.
  6.  上記列方向に隣り合う2つの上記画素領域を第1の画素領域及び第2の画素領域とした場合、
     当該第1の画素領域が列方向に並ぶ第1の副画素領域と第2の副画素領域とを備え、当該第2の画素領域が列方向に並ぶ第3の副画素領域と第4の副画素領域とを備え、
     上記基準電圧バスラインは、上記列方向に隣り合う上記第2の副画素領域と上記第3の副画素領域とに共有されていること
    を特徴とする請求項4または5に記載の液晶パネル。
    When the two pixel regions adjacent in the column direction are a first pixel region and a second pixel region,
    The first pixel region includes a first subpixel region and a second subpixel region arranged in the column direction, and the third subpixel region and the fourth subpixel region are arranged in the column direction. A pixel area,
    6. The liquid crystal panel according to claim 4, wherein the reference voltage bus line is shared by the second subpixel region and the third subpixel region adjacent in the column direction.
  7.  第1の基板と、上記第1の基板に対向するように配置された第2の基板と、上記第1の基板と上記第2の基板との間に設けられた液晶層とを備え、複数の画素領域が行方向及び列方向に沿って二次元的に配列した液晶パネルであって、
     上記画素領域のそれぞれは、少なくとも上記行方向に並ぶ2つの副画素領域を備え、
     上記第1の基板は、
      上記行方向に並ぶ上記画素領域に対応して設けられたゲートバスラインと、
      上記ゲートバスラインに絶縁膜を介して交差するように、上記副画素領域毎に設けられた基準電圧バスラインと、
      上記副画素領域毎に設けられた画素電極と、
      上記ゲートバスラインに供給されるゲート信号によって、上記画素電極と、当該画素電極に対応する上記基準電圧バスラインとの電気的な接続をオンオフするスイッチング素子とを備え、
     上記第2の基板は、
      上記列方向に並ぶ上記画素領域に対応して、上記2つの副画素領域に共通に設けられたデータバスラインを備えたこと
    を特徴とする液晶パネル。
    A plurality of first substrates; a second substrate disposed to face the first substrate; and a liquid crystal layer provided between the first substrate and the second substrate. A liquid crystal panel in which the pixel regions are two-dimensionally arranged along the row direction and the column direction,
    Each of the pixel regions includes at least two subpixel regions arranged in the row direction,
    The first substrate is
    Gate bus lines provided corresponding to the pixel regions arranged in the row direction;
    A reference voltage bus line provided for each sub-pixel region so as to intersect the gate bus line via an insulating film;
    A pixel electrode provided for each of the sub-pixel regions;
    A switching element for turning on and off the electrical connection between the pixel electrode and the reference voltage bus line corresponding to the pixel electrode by a gate signal supplied to the gate bus line;
    The second substrate is
    A liquid crystal panel comprising a data bus line provided in common to the two sub-pixel areas corresponding to the pixel areas arranged in the column direction.
  8.  上記行方向に隣り合う2つの上記画素領域を第1の画素領域及び第2の画素領域とした場合、
     当該第1の画素領域が行方向に並ぶ第1の副画素領域と第2の副画素領域とを備え、当該第2の画素領域が行方向に並ぶ第3の副画素領域と第4の副画素領域とを備え、
     上記基準電圧バスラインは、上記行方向に隣り合う上記第2の副画素領域と上記第3の副画素領域とに共有されていること
    を特徴とする請求項4から7のいずれか1項に記載の液晶パネル。
    When the two pixel areas adjacent in the row direction are a first pixel area and a second pixel area,
    The first pixel area includes a first subpixel area and a second subpixel area arranged in the row direction, and the third subpixel area and the fourth subpixel area are arranged in the row direction. A pixel area,
    8. The reference voltage bus line according to claim 4, wherein the reference voltage bus line is shared by the second subpixel region and the third subpixel region adjacent in the row direction. The liquid crystal panel described.
  9.  請求項1から8のいずれか1項に記載の液晶パネルを備えたこと
    を特徴とする表示装置。
    A display device comprising the liquid crystal panel according to claim 1.
  10.  請求項1から3のいずれか1項に記載の液晶パネルにおける駆動方法であって、
     少なくとも上記行方向に並ぶ上記2つの副画素領域を、第1の副画素領域及び第2の副画素領域とし、上記第1の副画素領域に対応した基準電圧バスラインを第1の基準電圧バスラインとし、上記第2の副画素領域に対応した基準電圧バスラインを第2の基準電圧バスラインとし、上記第1の副画素領域に対応したデータバスラインを第1のデータバスラインとし、上記第2の副画素領域に対応したデータバスラインを第2のデータバスラインとすると、
     上記第1の基準電圧バスライン及び上記第2の基準電圧バスラインに印加する各電圧を同一にし、上記第1のデータバスライン及び上記第2のデータバスラインに印加する電圧を相違させることによって、上記第1のデータバスライン及び上記第1の基準電圧バスライン間の電位差と、上記第2のデータバスライン及び上記第2の基準電圧バスライン間の電位差とを相違させること
    を特徴とする駆動方法。
    A driving method for a liquid crystal panel according to any one of claims 1 to 3,
    At least the two subpixel regions arranged in the row direction are defined as a first subpixel region and a second subpixel region, and a reference voltage bus line corresponding to the first subpixel region is defined as a first reference voltage bus. A reference voltage bus line corresponding to the second subpixel region is a second reference voltage bus line, a data bus line corresponding to the first subpixel region is a first data bus line, and When the data bus line corresponding to the second subpixel region is the second data bus line,
    By making the voltages applied to the first reference voltage bus line and the second reference voltage bus line the same, and making the voltages applied to the first data bus line and the second data bus line different The potential difference between the first data bus line and the first reference voltage bus line is different from the potential difference between the second data bus line and the second reference voltage bus line. Driving method.
  11.  請求項4から6のいずれか1項に記載の液晶パネルにおける駆動方法であって、
     少なくとも上記列方向に並ぶ上記2つの副画素領域のうち一方の副画素領域に対応した基準電圧バスラインを第1の基準電圧バスラインとし、他方の副画素領域に対応した基準電圧バスラインを第2の基準電圧バスラインとすると、
     上記第1の基準電圧バスライン及び上記第2の基準電圧バスラインに印加する各電圧を相違させることによって、上記データバスライン及び上記第1の基準電圧バスライン間の電位差と、上記データバスライン及び上記第2の基準電圧バスライン間の電位差とを相違させること
    を特徴とする駆動方法。
    A driving method for a liquid crystal panel according to any one of claims 4 to 6,
    At least a reference voltage bus line corresponding to one of the two subpixel regions arranged in the column direction is defined as a first reference voltage bus line, and a reference voltage bus line corresponding to the other subpixel region is defined as a first reference voltage bus line. 2 reference voltage bus line
    By making each voltage applied to the first reference voltage bus line and the second reference voltage bus line different, a potential difference between the data bus line and the first reference voltage bus line, and the data bus line And a difference in potential difference between the second reference voltage bus lines.
  12.  請求項7または8に記載の液晶パネルにおける駆動方法であって、
     少なくとも上記行方向に並ぶ上記2つの副画素領域を、第1の副画素領域及び第2の副画素領域とし、上記第1の副画素領域に対応した基準電圧バスラインを第1の基準電圧バスラインとし、上記第2の副画素領域に対応した基準電圧バスラインを第2の基準電圧バスラインとすると、
     上記第1の基準電圧バスライン及び上記第2の基準電圧バスラインに印加する各電圧を相違させることによって、上記データバスライン及び上記第1の基準電圧バスライン間の電位差と、上記データバスライン及び上記第2の基準電圧バスライン間の電位差とを相違させること
    を特徴とする駆動方法。
    A driving method for a liquid crystal panel according to claim 7 or 8,
    At least the two subpixel regions arranged in the row direction are defined as a first subpixel region and a second subpixel region, and a reference voltage bus line corresponding to the first subpixel region is a first reference voltage bus. A reference voltage bus line corresponding to the second sub-pixel region as a second reference voltage bus line,
    By making each voltage applied to the first reference voltage bus line and the second reference voltage bus line different, a potential difference between the data bus line and the first reference voltage bus line, and the data bus line And a difference in potential difference between the second reference voltage bus lines.
PCT/JP2011/078105 2010-12-10 2011-12-05 Liquid crystal panel, display device, and method for driving the liquid crystal panel WO2012077647A1 (en)

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WO2017130293A1 (en) * 2016-01-26 2017-08-03 堺ディスプレイプロダクト株式会社 Liquid crystal display device

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CN104020605A (en) * 2014-04-22 2014-09-03 友达光电股份有限公司 Display panel
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