WO2012075881A1 - 基于ieee1588多从钟的采样值多接口同步系统 - Google Patents

基于ieee1588多从钟的采样值多接口同步系统 Download PDF

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Publication number
WO2012075881A1
WO2012075881A1 PCT/CN2011/082358 CN2011082358W WO2012075881A1 WO 2012075881 A1 WO2012075881 A1 WO 2012075881A1 CN 2011082358 W CN2011082358 W CN 2011082358W WO 2012075881 A1 WO2012075881 A1 WO 2012075881A1
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interface
sample
universal
ieee
synchronization
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PCT/CN2011/082358
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English (en)
French (fr)
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李澄
陆玉军
陈颢
王伏亮
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江苏省电力公司
江苏方天电力技术有限公司
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Publication of WO2012075881A1 publication Critical patent/WO2012075881A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation

Definitions

  • the invention is directed to the problem that the power transmission of the digital secondary device in the digital substation relies on a single global sample synchronization source, and invents a multi-interface, independent global synchronization source, and generally applicable sample data. Receive synchronization technology. It belongs to the technical field of power system digital substation.
  • the digital substation adopts an electronic transformer (or a local intensive unit) to realize the conversion of the sample value from analog to digital, and the distributed collection. After digitization, each unit is transmitted to the process layer by communication.
  • the combiner also called the merging unit outputs the protection and control device, the meter, and the power quality monitoring device to the spacer layer through the interval combiner.
  • the synchronization problem of the sample-like value in the digital substation involves the synchronization of the voltage and current samples of each phase in the same interval and the synchronization of the sample values in multiple intervals.
  • the devices involved include a combiner, a protection and monitoring device, and a dedicated synchronization. Or multiple devices such as time devices and network switches.
  • IEEE 1588 is a high-precision network clock synchronization protocol with sub-microsecond synchronization for measurement and automation systems.
  • An IEEE 1588 precision clock system consists of a normal clock, a transparent clock, and a boundary clock. Each node in the system is considered to be a clock. The clock of the entire system is connected through Ethernet. The clock in the system works on the master clock, slave clock, Three states of passive clock. The specific clock state is determined by the optimized clock algorithm.
  • the IEEE 1588 clock synchronization process is determined by offset measurement and delay measurement. This synchronization method separates the measurement of the time scale from the transmission of the message, making the measurement of the time scale more accurate. With the cooperation of special hardware, the measurement of the time scale can be accurate. The text is sent from the PHY layer chip. When synchronizing messages The precise determination of the target generation point is an important feature of IEEE 1588.
  • FIG. 1 is a schematic diagram of a typical IEEE 1588 time-synchronous network structure.
  • the IEEE 1588 sample synchronization is affected by the reliability of the IEEE 1588 master clock.
  • the master clock loses the satellite pair, the master clock can work with its high-stable crystal oscillator for a period of time, but the cumulative error produced is accurate for the sample. Degree also has an impact.
  • the connection between the primary clock and the switch is disconnected for some reason, the entire synchronous system will not work properly, which will affect the safe and stable operation of the entire integrated system.
  • the technical problem to be solved by the present invention is to provide a universally applicable IEEE 1588-based multi-interface synchronization system that does not need to rely on a global synchronous clock source to meet the needs of network-like network transmission.
  • a multi-interface synchronization system based on IEEE 1588 multi-clock characterized in that:
  • Universal IEEE 1588 clock interface Communication receiving module with multiple IEEE 1588 slave clock interfaces, the number of slave clocks can be automatically extended according to the number of master clocks;
  • the general-purpose IEEE 1588 multi-slave clock-like multi-interface synchronization system is characterized in that: the universal IEEE 1588 clock interface has a plurality of IEEE 1588 slave clock receiving modules, which can be respectively combined with different merging units (including The IEEE 1588 pair is used between the main clocks to ensure accurate synchronization of the two clocks.
  • the foregoing universal IEEE 1588 multi-slave clock-like multi-interface synchronization system is characterized in that: the universal multi-sample synchronization interface includes an Ethernet data receiving module, It can receive the sample value message based on IEC 61850-9, and can check and analyze the sample value message, and determine whether there is an abnormality in the sample value message or the channel data according to the message.
  • the foregoing universal IEEE 1588 multi-slave clock-like multi-interface synchronization system is characterized in that: the universal multi-sample synchronization interface includes a software sample interpolation module, and according to a general case, the merging unit MU sample points Compared with the non-integer multiple of the sampling rate of the data receiving device, the simple linear interpolation method is used to extract the source data.
  • the foregoing universal IEEE 1588 multi-slave clock-like multi-interface synchronization system is characterized in that: the universal multi-sample synchronization interface includes a software PLL phase-locked loop, automatically tracks the merge unit, and eliminates the merge. The unit sends the delay jitter problem of the Ethernet packet.
  • the general-purpose IEEE 1588 multi-slave-based multi-interface synchronization system is characterized in that: the universal multi-sample synchronization interface includes a frequency tracking module, and according to the data of the merging unit MU and the like, The Fourier transform calculates the signal frequency, thereby adjusting the digital sampling interval of the receiving device to achieve the frequency tracking purpose.
  • the foregoing universal IEEE 1588 multi-slave clock-like multi-interface synchronization system is characterized in that: the universal multi-sample sample synchronization interface includes a multi-interface sample-value synchronization module, and uses a unified internal sample pulse.
  • the time synchronization of each merging unit MU sample data is completed by using the relative time difference between the slave clocks.
  • the beneficial effects of the present invention are as follows:
  • the present invention designs a general-purpose IEEE 1588-like sample multi-interface data synchronization technology, which supports process layer-like networking transmission based on IEC 61850-9. It can be used not only for digital relay protection devices, but also for electronic equipment such as electric energy meters and power quality monitoring devices that require synchronization. It can automatically receive the IEEE 1588 main clock signal from each combiner, calculate the relative time difference between each data source according to each slave clock receiving module, and then perform data synchronization, which is the global sampling source for the current sample network transmission. The problem provides a convenient solution.
  • FIG. 1 is a schematic structural diagram of a typical IEEE 1588 time synchronization network
  • FIG. 2 is a transmission diagram of a sample-like network based on an IEEE 1588 multi-clock
  • Figure 3 is a block diagram of an implementation based on IEEE 1588 multi-clock data synchronization technology.
  • FIG. 2 is a diagram showing the transmission of the sample-like value network based on the IEEE 1588 multi-clock from the present invention.
  • the merging unit MU collects the signals from the traditional/electronic voltage and current transformers and converts them into IEC 61850-9-compliant ⁇ sample value messages for uploading to the dedicated ⁇ sample value network.
  • the data receiving device (such as protection monitoring device, electric energy meter, etc.) obtains the sample data of the corresponding interval combining unit MU from the network, and realizes the functions of protection measurement and control or energy metering.
  • each merging unit has the IEEE 1588 master clock function, and the multiple IEEE1588 slave clocks of the data receiving device communicate with the merging unit of the corresponding interval, which can realize the precise IEEE 1588 time function.
  • FIG. 3 is a block diagram of the present invention based on IEEE 1588 multi-slave clock data synchronization technology.
  • the IEEE 1588 slave clock module completes the high-precision synchronization timing function of the MU master clock with the corresponding interval merging unit; the Ethernet data receiving module completes the data communication with the corresponding interval merging unit to obtain an equally spaced original according to the IEC 61850-9 standard. Data;
  • the frequency measurement module calculates the frequency value according to the original sample data, recursively, and adjusts the period of the sample timer to realize a complete cycle of data sampling.
  • the PLL phase-locked loop module ensures the synchronization of the merging unit and the data receiving module, and eliminates the delay jitter of the merging unit to send Ethernet packets.
  • the software interpolation module adjusts the sampling interval of the sampling timer according to the original sample data of IEEE 1588, frequency tracking and PLL phase lock, and the source is sampled according to the requirements of the number of protected sampling points (24 points, 32 points).
  • the data is subjected to cycle interpolation, and the data required for calculations such as protection, measurement and control are obtained. Finally, the voltage and current data of each interval that has undergone strict synchronization are sent to the CPU through the data bus for the next data processing.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Emergency Protection Circuit Devices (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Small-Scale Networks (AREA)

Description

说 明 书 基于 IEEE1588多从钟的釆样值多接口同步系统 技术领域
本发明针对电力系统在数字化变电站中数字式二次设备的釆样值传 输依赖单一全局釆样同步源的问题， 发明了一种多接口、 不依赖全局釆 样同步源、 普遍适用的釆样数据接收同步技术。 属于电力系统数字化变 电站技术领域。
背景技术
在变电站自动化系统中， 保护和测控装置等设备需要对接入装置的 同一间隔、或跨间隔的各相电压电流实现同步釆集和处理，如线路保护、 主变保护、 母线保护均需要各个输入的釆样数据同步， 同时釆样数据的 同步对于一次设备故障识别和处理也显得尤为重要。 数字化变电站釆用 电子式互感器（或釆用就地釆集单元）实现釆样值由模拟量到数字量的 转换、 分布式釆集， 数字化后各釆集单元以通讯方式传送至过程层的合 并器 （也称合并单元）， 经间隔合并器输出给间隔层的保护测控装置、 计量表计、 电能质量监测装置。 因此， 数字化变电站内的釆样值同步问 题涉及同一间隔内的各相电压电流釆样值的同步和多个间隔内釆样值 的同步，涉及的设备有合并器、保护测控装置及专用的同步或对时设备、 网络交换机等多个设备。
IEEE 1588是用于测量和自动化系统中， 具有亚微秒级同步功能的高 精度网络时钟同步协议。 一个 IEEE 1588精确时钟系统包括普通时钟、 透明时钟、 边界时钟， 系统中每个节点均被认为是一个时钟， 通过以太 网将整个系统的时钟相连， 系统中的时钟工作在主时钟、 从时钟、 无源 时钟 3种状态。 具体的时钟状态则是由最优化的时钟算法所确定。 IEEE 1588时钟同步过程通过偏移测量和延迟测量所确定，这种同步方法将时 标的测量和报文的传送分离， 使得时标的测量更加精确， 在专门硬件配 合下， 时标的测量能够精确到报文从 PHY层芯片发出时刻。 同步报文时 标生成点的精确确定是 IEEE 1588的重要特征。
基于 IEEE 1588 的釆样值组网传输对时方案如图 1 , 站内提供支持 IEEE 1588标准时钟， 时钟接受 GPS/北斗卫星对时， 站内过程层主时钟 通过过程层交换机（支持 IEEE 1588 ), 向各装置提供对时信号， 实现合 并器的釆样同步和输出同步。 图 1为典型 IEEE 1588对时同步网络结构 示意图。
IEEE 1588釆样值同步受 IEEE 1588主时钟的可靠性影响， 当主时钟 失去卫星对时后， 主时钟可以利用其高稳晶振工作一段时间， 但产生的 累积误差， 对釆样值的釆样准确度也有影响。 另外， 当主时钟与交换机 的连接由于某种原因断开后， 整个对时同步系统将无法正常工作， 进而 影响整个综自系统的安全、 稳定运行。
发明内容
本发明所要解决的技术问题在于提供一种不需依赖全局釆样同步 时钟源的、具有普遍适用性的基于 IEEE 1588的釆样值多接口同步系统， 以满足釆样值组网传输的需要。
为实现上述发明目的， 本发明是釆取以下的技术方案来实现的： 一种基于 IEEE 1588多从钟的釆样值多接口同步系统，其特征在于： 包括
通用的 IEEE 1588时钟接口： 具备多个 IEEE 1588从钟接口的通讯 接收模块， 从钟个数可根据主时钟数自动扩展配置；
通用的多釆样值同步接口： 具备能与合并单元组网连接的通讯接
P。
前述通用的基于 IEEE 1588多从钟的釆样值多接口同步系统， 其特 征在于： 所述通用的 IEEE 1588时钟接口， 具备多个 IEEE 1588从时钟 接收模块， 可分别与不同合并单元 （各含主时钟） 间进行 IEEE 1588对 时， 保证两者时钟精确同步。
前述通用的基于 IEEE 1588多从钟的釆样值多接口同步系统， 其特 征在于： 所述通用的多釆样值同步接口， 包括以太网数据接收模块， 能 够接收基于 IEC 61850-9的釆样值报文，并能够检验和分析釆样值报文， 根据报文确定釆样值报文或通道数据是否存在异常。
前述通用的基于 IEEE 1588多从钟的釆样值多接口同步系统， 其特 征在于： 所述通用的多釆样值同步接口， 包括软件釆样插值模块， 根据 一般情况下合并单元 MU釆样点数和数据接收装置釆样率的非整数倍关 系， 釆用简单线性插值方法实现源釆样数据的提取。
前述通用的基于 IEEE 1588多从钟的釆样值多接口同步系统， 其特 征在于： 所述通用的多釆样值同步接口， 包括软件 PLL锁相环， 自动跟 踪合并单元釆样节拍， 消除合并单元发送以太网数据包的时延抖动问 题。
前述通用的基于 IEEE 1588多从钟的釆样值多接口同步系统， 其特 征在于： 所述通用的多釆样值同步接口， 包括频率跟踪模块， 根据合并 单元 MU等间隔釆样的数据， 通过傅立叶变换计算出信号频率， 从而调 整接收装置的数字釆样间隔， 达到频率跟踪目的。
前述通用的基于 IEEE 1588多从钟的釆样值多接口同步系统， 其特 征在于： 所述通用的多釆样值同步接口， 包括多接口釆样值同步模块， 釆用统一的内部釆样脉冲， 利用各个从钟之间的相对时差， 完成各个合 并单元 MU釆样数据的时间同步。
本发明的有益效果是： 本发明设计了一种通用的基于 IEEE 1588釆 样值多接口数据同步技术， 支持基于 IEC 61850-9的过程层釆样组网传 输。 它不仅可用于数字式继电保护装置， 也可用于电能表、 电能质量监 测装置等需要釆样同步的电子设备。 它能自动接收来自各合并器 IEEE 1588 主时钟信号， 根据各从钟接收模块计算出各数据源间的相对时间 差， 然后进行数据同步， 为目前釆样值组网传输依赖全局釆样同步源的 问题提供了一种方便的解决方案。
附图说明
图 1为典型 IEEE 1588对时同步网络结构示意图；
图 2是基于 IEEE 1588多从钟的釆样值组网传输图； 图 3是基于 IEEE 1588多从钟数据同步技术实现框图。
具体实施方式
以下结合附图对本发明作具体的介绍。
图 2是本发明基于 IEEE 1588多从钟的釆样值组网传输图。
合并单元 MU釆集来自传统 /电子式电压电流互感器的信号， 转换为 符合 IEC 61850-9标准的釆样值报文上传至专用釆样值网络。 釆样数据 接收装置（如保护测控装置、 电能表等）从网络上获取相应间隔合并单 元 MU的釆样数据， 实现相应的保护测控或电能计量等功能。
同时， 各合并单元具有 IEEE 1588主时钟功能， 釆样数据接收装置 的多 IEEE1588 从钟与相应间隔的合并单元进行通讯， 能够实现精确的 IEEE 1588对时功能。
图 3是本发明基于 IEEE 1588多从钟数据同步技术实现框图。
IEEE 1588从时钟模块， 完成与相应间隔合并单元 MU主时钟的高精 度同步对时功能； 以太网数据接收模块， 完成与相应间隔合并单元的数 据通信， 获取符合 IEC 61850-9标准的等间隔原始数据； 频率测量模块, 根据原始釆样数据， 抽点递推计算出频率值， 调整釆样定时器的周期， 实现一个完整周期的数据釆样。 PLL锁相环模块， 保证合并单元与数据 接收模块的节拍同步， 消除合并单元发送以太网数据包的时延抖动问 题。 软件插值模块， 根据 IEEE 1588对时、 频率跟踪和 PLL锁相后的原 釆样值数据， 调整釆样定时器的取样间隔， 依据保护取样点数 （24点、 32点）的要求对源釆样数据进行周波插值釆样， 获得保护、 测控等计算 所需的数据， 最后将经过严格同步的各间隔的电压电流数据经过数据总 线送入 CPU中进行下一步数据处理。
上述实施例不以任何形式限定本发明， 凡釆取等同替换或等效变换 的形式所获得的技术方案， 均落在本发明的保护范围之内。

Claims

要 求 书
1. 一种基于 IEEE 1588 多从钟的釆样值多接口同步系统， 其特征 在于： 包括
通用的 IEEE 1588时钟接口： 具备多个 IEEE 1588从钟接口的通讯 接收模块， 从钟个数根据主时钟数自动扩展配置；
通用的多釆样值同步接口： 具备能与合并单元组网连接的通讯接
P。
2. 根据权利要求 1所述通用的基于 IEEE 1588多从钟的釆样值多 接口同步系统， 其特征在于： 所述通用的 IEEE 1588时钟接口， 具备多 个 IEEE 1588从时钟接收模块， 分别与不同合并单元间进行 IEEE 1588 对时， 保证两者时钟精确同步。
3. 根据权利要求 1所述通用的基于 IEEE 1588多从钟的釆样值多 接口同步系统， 其特征在于： 所述通用的多釆样值同步接口， 包括以太 网数据接收模块， 接收基于 IEC 61850-9的釆样值报文， 并检验和分析 釆样值报文， 根据报文确定釆样值报文或通道数据是否存在异常。
4. 根据权利要求 3所述通用的基于 IEEE 1588多从钟的釆样值多 接口同步系统， 其特征在于： 所述通用的多釆样值同步接口， 包括软件 釆样插值模块， 根据合并单元 MU釆样点数和数据接收装置釆样率的非 整数倍关系， 釆用简单线性插值方法实现源釆样数据的提取。
5. 根据权利要求 3所述通用的基于 IEEE 1588多从钟的釆样值多 接口同步系统， 其特征在于： 所述通用的多釆样值同步接口， 包括软件 PLL锁相环， 自动跟踪合并单元釆样节拍， 消除合并单元发送以太网数 据包的时延抖动问题。
6. 根据权利要求 3所述通用的基于 IEEE 1588多从钟的釆样值多 接口同步系统， 其特征在于： 所述通用的多釆样值同步接口， 包括频率 跟踪模块， 根据合并单元 MU等间隔釆样的数据， 通过傅立叶变换计算 出信号频率， 从而调整接收装置的数字釆样间隔， 达到频率跟踪目的。
1
7. 根据权利要求 3所述通用的基于 IEEE 1588多从钟的釆样值多 接口同步系统， 其特征在于： 所述通用的多釆样值同步接口， 包括多接 口釆样值同步模块， 釆用统一的内部釆样脉冲， 利用各个从钟之间的相 对时差， 完成各个合并单元 MU釆样数据的时间同步。
2
PCT/CN2011/082358 2010-12-08 2011-11-17 基于ieee1588多从钟的采样值多接口同步系统 WO2012075881A1 (zh)

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