WO2012073478A1

WO2012073478A1 - Plasma display device and method for driving plasma display device

Info

Publication number: WO2012073478A1
Application number: PCT/JP2011/006626
Authority: WO
Inventors: 岩見　隆
Original assignee: パナソニック株式会社
Priority date: 2010-11-30
Filing date: 2011-11-29
Publication date: 2012-06-07

Abstract

The present invention reduces the power consumption of a data-electrode drive circuit in a plasma display device. In order to do so, when the voltage of a write pulse is to be transitioned from a low-side voltage to a high-side voltage, the data-electrode drive circuit, during a first transition period: turns a recovery switch on and thereby makes the load capacitance of a data electrode resonate with a recovery coil and raises the output voltage; and then turns the recovery switch off and a high-voltage-side switch on and thereby clamps the output voltage to the high-side voltage. When the voltage of the write pulse is to be transitioned from the high-side voltage to the low-side voltage, the data-electrode drive circuit, during a second transition period: turns the recovery switch on and thereby makes the load capacitance of the data electrode resonate with the recovery coil and lowers the output voltage; and then turns the recovery switch off and a low-voltage-side switch on and thereby clamps the output voltage to the low-side voltage. The second transition period and the first transition period immediately after the second transition period are separated temporally.

Description

Plasma display apparatus and driving method of plasma display apparatus

The present invention relates to a plasma display device which is an image display device using an AC surface discharge type plasma display panel and a driving method of the plasma display device.

2. Description of the Related Art A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front substrate and a rear substrate that are arranged to face each other. In the front substrate, a plurality of pairs of display electrodes composed of a pair of scan electrodes and sustain electrodes are formed on the front glass substrate in parallel with each other. A dielectric layer and a protective layer are formed so as to cover the display electrode pairs.

The back substrate has a plurality of parallel data electrodes formed on the glass substrate on the back side, a dielectric layer is formed so as to cover the data electrodes, and a plurality of barrier ribs are formed thereon in parallel with the data electrodes. ing. And the fluorescent substance layer is formed in the surface of a dielectric material layer, and the side surface of a partition.

Then, the front substrate and the rear substrate are arranged opposite to each other and sealed so that the display electrode pair and the data electrode are three-dimensionally crossed. In the sealed internal discharge space, for example, a discharge gas containing xenon at a partial pressure ratio of 5% is sealed, and a discharge cell is formed in a portion where the display electrode pair and the data electrode face each other. In the panel having such a configuration, ultraviolet rays are generated by gas discharge in each discharge cell, and the phosphors of each color of red (R), green (G) and blue (B) are excited and emitted by the ultraviolet rays. Display an image.

The subfield method is generally used as a method for driving the panel. In the subfield method, one field is divided into a plurality of subfields, and gradation display is performed by causing each discharge cell to emit light or not emit light in each subfield. Each subfield has an initialization period, an address period, and a sustain period.

In the initialization period, an initialization waveform is applied to each scan electrode, and an initialization operation is performed to generate an initialization discharge in each discharge cell. Thereby, in each discharge cell, wall charges necessary for the subsequent address operation are formed, and priming particles (excited particles for generating the discharge) for generating the address discharge stably are generated.

In the address period, the scan pulse is sequentially applied to the scan electrodes, and the address pulse is selectively applied to the data electrodes based on the image signal to be displayed. As a result, an address discharge is generated between the scan electrode and the data electrode of the discharge cell to emit light, and a wall charge is formed in the discharge cell (hereinafter, these operations are also collectively referred to as “address”). ).

In the sustain period, the number of sustain pulses based on the luminance weight determined for each subfield is alternately applied to the display electrode pairs composed of the scan electrodes and the sustain electrodes. As a result, a sustain discharge is generated in the discharge cell that has generated the address discharge, and the phosphor layer of the discharge cell emits light (hereinafter referred to as “lighting” that the discharge cell emits light by the sustain discharge, and “non-emitting”). Also written as “lit”.) Thereby, each discharge cell is made to emit light with the luminance according to the luminance weight. In this way, each discharge cell of the panel is caused to emit light with a luminance corresponding to the gradation value of the image signal, and an image is displayed in the image display area of the panel.

The plasma display device has a scan electrode drive circuit, a sustain electrode drive circuit, and a data electrode drive circuit in order to generate a drive voltage waveform necessary for image display. The drive voltage waveform generated in the scan electrode drive circuit is applied to the scan electrode, the drive voltage waveform generated in the sustain electrode drive circuit is applied to the sustain electrode, and the drive voltage waveform generated in the data electrode drive circuit is applied to the data electrode. Apply.

In recent years, with the increase in screen size and resolution, the power consumed in write operations has increased. And the power consumption in the data electrode driving circuit increases the power consumption of the plasma display device.

Therefore, various methods for reducing the power consumption of the data electrode driving circuit have been proposed.

When viewed from the data electrode drive circuit, the data electrode is a capacitive load (load capacity). In view of this, a plasma display device is disclosed in which a power recovery unit is added to a power source that supplies power to a data electrode driving circuit (see, for example, Patent Document 1). In the technique described in Patent Document 1, this power supply reduces power consumption by resonating the load capacitance and the recovery coil and supplying power to the data electrode driving circuit.

However, the load capacity of the data electrode varies greatly depending on the image data. Therefore, in the technique described in Patent Document 1, the power consumption may increase depending on the design of the image. The image data is data generated based on an image signal in order to display an image on the panel.

A plasma display device that improves this point is also disclosed (see, for example, Patent Document 2). In the technique described in Patent Document 2, the output amplitude of the power recovery unit added to the power supply is controlled according to the image data.

Thus, the power consumption in the plasma display device can be reduced by adding the power recovery unit to the power source that supplies power to the data electrode driving circuit. However, if a power recovery unit is added to the power supply, the voltage supplied to the data electrode drive circuit tends to be unstable, and the address discharge may become unstable. When the address discharge becomes unstable, the image display quality in the plasma display device is degraded.

For these reasons, there is a demand for a plasma display device capable of stably supplying power to the data electrode driving circuit to perform a stable addressing operation and reducing power consumption of the data electrode driving circuit.

JP 2002-278509 A JP 2004-212699 A

The present invention is a plasma display device including a panel having a plurality of display electrode pairs and a plurality of data electrodes, and a data electrode driving circuit for applying a write pulse to the data electrodes. The data electrode driving circuit applies the high voltage side voltage of the write pulse or the low voltage side voltage of the write pulse to the data electrode for each write cycle in the write period. The data electrode drive circuit includes a recovery capacitor and a recovery coil connected in series with the recovery capacitor, and is connected to a high voltage side switch that outputs a high voltage side voltage, a low voltage side switch that outputs a low voltage side voltage, and the recovery capacitor. An output buffer having a recovery switch for each of the data electrodes. When the output buffer transitions the voltage of the write pulse from the low-voltage side voltage to the high-voltage side voltage, the output switch is turned on in the first transition period provided in the write cycle to recover the load capacity and the recovery of the data electrode. The output voltage is raised by resonating with the coil, and then the recovery switch is turned off and the high-voltage side switch is turned on to clamp the output voltage to the high-voltage side voltage. In addition, when the voltage of the write pulse transitions from the high voltage side voltage to the low voltage side voltage, the output buffer turns on the recovery switch during the second transition period provided in the write cycle and recovers the load capacity and recovery of the data electrode. The output voltage is lowered by resonating with the coil, and then the recovery switch is turned off and the low-voltage side switch is turned on to clamp the output voltage to the low-voltage side voltage. Then, the second transition period and the first transition period immediately after the second transition period are separated in time.

Thus, it is possible to stably supply power to the data electrode driving circuit to perform a stable addressing operation and reduce the power consumption of the data electrode driving circuit.

In the plasma display apparatus of the present invention, the data electrode driving circuit is configured by using a plurality of integrated circuits in which a plurality of output buffers are integrated, and the total sum of substantial load capacities of the plurality of data electrodes driven by the integrated circuit is calculated. calculate. The data electrode driving circuit is configured to output the output buffer unit based on the calculated sum so that when the calculated sum is large, the time length of the first transition period or the second transition period is longer than when the calculated sum is small. Controls the high-pressure side switch, low-pressure side switch, and recovery switch.

Further, the present invention provides a recovery capacitor for a data electrode of a panel having a plurality of display electrode pairs and a plurality of data electrodes in a writing period in which one field is composed of a plurality of subfields having an address period and a sustain period. And a recovery coil are resonated with each other to drive a plurality of data electrodes, and a write pulse is applied from a data driver that drives a plurality of data electrodes. In this driving method, the sum of substantial load capacities of a plurality of data electrodes driven by the data driver is calculated. Then, the calculated load capacity is obtained by calculating the time length of the first transition period in which the voltage of the write pulse is changed from the low voltage to the high voltage and the second transition period in which the voltage of the write pulse is changed from the high voltage to the low voltage. Control based on the sum of When the calculated sum of the load capacities is large, the time length of the first transition period or the second transition period is made longer than when the sum is small.

FIG. 1 is an exploded perspective view showing a structure of a panel used in a plasma display device according to an embodiment of the present invention. FIG. 2 is an electrode array diagram of a panel used in the plasma display device according to one embodiment of the present invention. FIG. 3 is a diagram schematically showing the interelectrode capacitance of the panel used in the plasma display device according to one embodiment of the present invention. FIG. 4 schematically shows drive voltage waveforms applied to the respective electrodes of the panel used in the plasma display device in accordance with the exemplary embodiment of the present invention. FIG. 5 is a diagram schematically showing an example of a circuit block constituting the plasma display device in one embodiment of the present invention. FIG. 6 is a circuit diagram schematically showing a configuration of a data electrode driving circuit of the plasma display device in accordance with the exemplary embodiment of the present invention. FIG. 7 is a circuit diagram schematically showing a configuration of an output buffer unit included in the data electrode driving circuit of the plasma display device in accordance with the exemplary embodiment of the present invention. FIG. 8 is a diagram schematically showing an example of an address pulse generated in the plasma display device according to one embodiment of the present invention. FIG. 9 is a circuit diagram schematically showing the configuration of the load calculation unit of the plasma display device in one embodiment of the present invention. FIG. 10 is a timing chart showing an example of the operation of the write timing generation unit of the plasma display device in one embodiment of the present invention. FIG. 11 is a circuit diagram schematically showing another configuration example of the output buffer unit of the plasma display device in accordance with the exemplary embodiment of the present invention.

Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment)
FIG. 1 is an exploded perspective view showing the structure of panel 10 used in the plasma display device according to one embodiment of the present invention.

A plurality of display electrode pairs 14 each including a scanning electrode 12 and a sustaining electrode 13 are formed on a glass front substrate 11. A dielectric layer 15 is formed so as to cover the scan electrode 12 and the sustain electrode 13, and a protective layer 16 is formed on the dielectric layer 15.

This protective layer 16 has been used as a panel material in order to lower the discharge start voltage in the discharge cell, and has a large secondary electron emission coefficient and durability when neon (Ne) and xenon (Xe) gas is sealed. It is made of a material mainly composed of magnesium oxide (MgO).

A plurality of data electrodes 22 are formed on the rear substrate 21, a dielectric layer 23 is formed so as to cover the data electrodes 22, and a grid-like partition wall 24 is further formed thereon. On the side surfaces of the barrier ribs 24 and on the dielectric layer 23, a phosphor layer 25R that emits red (R), a phosphor layer 25G that emits green (G), and a phosphor layer 25B that emits blue (B). Is provided. Hereinafter, the phosphor layer 25R, the phosphor layer 25G, and the phosphor layer 25B are collectively referred to as a phosphor layer 25.

The front substrate 11 and the rear substrate 21 are arranged to face each other so that the display electrode pair 14 and the data electrode 22 intersect each other with a minute space therebetween, and a discharge space is provided in the gap between the front substrate 11 and the rear substrate 21. . And the outer peripheral part is sealed with sealing materials, such as glass frit. Then, for example, a mixed gas of neon and xenon is sealed in the discharge space inside as a discharge gas.

The discharge space is divided into a plurality of sections by the partition walls 24, and discharge cells are formed at the intersections between the display electrode pairs 14 and the data electrodes 22.

Then, a discharge is generated in these discharge cells, and the phosphor layer 25 of the discharge cells emits light (lights the discharge cells), thereby displaying a color image on the panel 10.

In the panel 10, one pixel is composed of three consecutive discharge cells arranged in the direction in which the display electrode pair 14 extends. The three discharge cells are a discharge cell having a phosphor layer 25R and emitting red (R) (red discharge cell), and a discharge cell having a phosphor layer 25G and emitting green (G) (green). And a discharge cell having a phosphor layer 25B and emitting blue (B) light (blue discharge cell).

Note that the structure of the panel 10 is not limited to the above-described structure, and may be, for example, provided with a stripe-shaped partition wall.

FIG. 2 is an electrode array diagram of panel 10 used in the plasma display device according to one embodiment of the present invention.

The panel 10 includes n scan electrodes SC (1) to scan electrodes SC (n) (scan electrodes 12 in FIG. 1) and n sustain electrodes SU (1) to (horizontal direction (row direction)). Sustain electrodes SU (n) (sustain electrodes 13 in FIG. 1) are arranged and m data electrodes D (1) to D (m) (data electrodes in FIG. 1) extended in the vertical direction (column direction). 22) are arranged.

One discharge is generated in a region where a pair of scan electrodes SC (i) (i = 1 to n) and sustain electrodes SU (i) intersect with one data electrode D (j) (j = 1 to m). A cell is formed. In other words, m discharge cells are formed on one pair of display electrodes 14 and m / 3 pixels are formed. Then, m × n discharge cells are formed in the discharge space, and an area where m × n discharge cells are formed becomes an image display area of the panel 10. For example, in a panel having 1920 × 1080 pixels, m = 1920 × 3 and n = 1080.

The interelectrode capacitance exists between the electrodes of the electrodes arranged in this way.

FIG. 3 is a diagram schematically showing the interelectrode capacitance of panel 10 used in the plasma display device according to one embodiment of the present invention.

In FIG. 3, as an example, five scan electrodes SC (i−2) to scan electrode SC (i + 2), five sustain electrodes SU (i−2) to sustain electrode SU (i + 2), Data electrodes D (j−2) to data electrode D (j + 3) are shown, and the interelectrode capacitance related to the data electrode 22 is shown. In FIG. 3, a display electrode pair composed of scan electrode SC (i) and sustain electrode SU (i) is indicated by one thick horizontal line.

As shown in FIG. 3, in the panel 10, “capacitance Cs” exists in each of the regions where the display electrode pair 14 and the data electrode 22 intersect. Further, “capacitance Cc” exists between the data electrodes 22 adjacent to each other.

One data electrode D (j) intersects n scan electrodes SC (1) to scan electrode SC (n) and n sustain electrodes SU (1) to sustain electrode SU (n). That is, one data electrode D (j) intersects n display electrode pairs 14. Therefore, in the panel 10, a capacitance (n × Cs) exists between one data electrode D (j) and the display electrode pair 14. Hereinafter, the capacity (n × Cs) is expressed as “capacity Cg”.

Further, one data electrode D (j) has a capacitance Cc between the data electrode D (j + 1) adjacent to the right side and a capacitance between the data electrode D (j−1) adjacent to the left side. Cc exists.

Thus, since the capacitance Cg, the capacitance Cc, and the capacitance Cc exist in one data electrode D (j), the total load capacitance in one data electrode D (j) is the capacitance (Cg + 2Cc). . Therefore, in the panel 10, a capacitance (Cg + 2Cc) exists in each of the data electrodes 22.

Next, a driving voltage waveform for driving the panel 10 and an outline of its operation will be described.

The plasma display device in the present embodiment drives the panel 10 by the subfield method. In the subfield method, one field of an image signal is divided into a plurality of subfields on the time axis, and a luminance weight is set for each subfield. Therefore, each field has a plurality of subfields having different luminance weights.

Each subfield has an initialization period, an address period, and a sustain period. Based on the image signal, light emission / non-light emission of each discharge cell is controlled for each subfield. That is, a plurality of gradations based on the image signal are displayed on the panel 10 by combining the light-emitting subfield and the non-light-emitting subfield based on the image signal.

In the initializing period, an initializing operation is performed in which initializing discharge is generated in the discharge cells and wall charges necessary for the address discharge in the subsequent address period are formed on each electrode.

In the address period, a scan pulse is applied to the scan electrode 12 and an address pulse is selectively applied to the data electrode 22 to selectively generate an address discharge in the discharge cells to emit light. Then, an address operation is performed to form wall charges in the discharge cells for generating a sustain discharge in the subsequent sustain period.

In the sustain period, the sustain pulses of the number obtained by multiplying the luminance weight set in each subfield by a predetermined proportional constant are alternately applied to the scan electrode 12 and the sustain electrode 13 to generate the address discharge in the immediately preceding address period. A sustain discharge is generated in the discharge cell, and a sustain operation for emitting light from the discharge cell is performed. This proportionality constant is a luminance multiple. For example, when the luminance multiple is twice, the sustain pulse is applied four times to each of the scan electrode 12 and the sustain electrode 13 in the sustain period of the subfield having the luminance weight “2”. Therefore, the number of sustain pulses generated in the sustain period is 8.

The luminance weight represents a ratio of the luminance magnitudes displayed in each subfield, and the number of sustain pulses corresponding to the luminance weight is generated in the sustain period in each subfield. Therefore, for example, the subfield with the luminance weight “8” emits light with a luminance about eight times that of the subfield with the luminance weight “1”, and emits light with about four times the luminance of the subfield with the luminance weight “2”.

Thus, for example, one field is composed of eight subfields (subfield SF1, subfield SF2, subfield SF3, subfield SF4, subfield SF5, subfield SF6, subfield SF7, subfield SF8). If luminance weights of (1, 2, 4, 8, 16, 32, 64, 128) are set in each subfield of SF1 to subfield SF8, each discharge cell has a gradation value of “0”. The 256 gradation values up to the value “255” can be displayed.

In this way, by controlling the light emission / non-light emission of each discharge cell for each subfield in a combination according to the image signal, each subfield is selectively emitted to emit each discharge cell with various gradation values, An image can be displayed on the panel 10.

In the present invention, the number of subfields constituting one field, the luminance weight of each subfield, and the like are not limited to the above-described numerical values.

The initializing operation includes all-cell initializing operation that generates initializing discharge in the discharge cells regardless of the operation of the immediately preceding subfield, and the address discharge is generated in the immediately preceding subfield addressing period and is maintained in the sustaining period. There is a selective initializing operation in which initializing discharge is selectively generated only in the discharge cells that have generated discharge. In the all-cell initialization operation, an ascending rising waveform voltage and a descending falling waveform voltage are applied to the scan electrode 12 to generate an initializing discharge in all the discharge cells in the image display region. Then, among all the subfields, the all-cell initialization operation is performed in the initialization period of one subfield, and the selective initialization operation is performed in the initialization period of the other subfield. Hereinafter, the initialization period for performing the all-cell initialization operation is referred to as “all-cell initialization period”, and the subfield having the all-cell initialization period is referred to as “all-cell initialization subfield”. An initialization period for performing the selective initialization operation is referred to as “selective initialization period”, and a subfield having the selective initialization period is referred to as “selective initialization subfield”.

In this embodiment, the first subfield (subfield SF1) of each field is an all-cell initializing subfield, and the other subfields are selective initializing subfields.

Thereby, since the initializing discharge is generated in all the discharge cells at least once in one field, the addressing operation after the initializing operation for all the cells can be stabilized. Further, light emission not related to image display is only light emission due to discharge in the all-cell initializing operation in the subfield SF1. Therefore, the black luminance that is the luminance of the black display region where no sustain discharge occurs is only weak light emission in the all-cell initialization operation, and an image with high contrast can be displayed on the panel 10.

However, in the present embodiment, the number of subfields constituting one field and the luminance weight of each subfield are not limited to the above-described numerical values. Moreover, the structure which switches a subfield structure based on an image signal etc. may be sufficient.

FIG. 4 is a diagram schematically showing driving voltage waveforms applied to the respective electrodes of panel 10 used in the plasma display device according to one embodiment of the present invention.

FIG. 4 shows scan electrode SC (1) that performs the address operation first in the address period, scan electrode SC (n) that performs the address operation last in the address period (for example, scan electrode SC (1080)), and sustain electrode SU. (1) Drive voltage waveforms applied to sustain electrode SU (n) and data electrode D (1) to data electrode D (m) are shown. In addition, scan electrode SC (i), sustain electrode SU (i), and data electrode D (k) in the following are selected from each electrode based on image data (data indicating light emission / non-light emission for each subfield). Represents an electrode.

FIG. 4 shows driving voltage waveforms of two subfields, subfield SF1 and subfield SF2. The subfield SF1 is a subfield for performing an all-cell initialization operation, and the subfield SF2 is a subfield for performing a selective initialization operation. Therefore, the waveform shape of the drive voltage applied to the scan electrode 12 in the initialization period differs between the subfield SF1 and the subfield SF2. The drive voltage waveform in the other subfield is substantially the same as the drive voltage waveform in subfield SF2 except that the number of sustain pulses generated in the sustain period is different.

In the present embodiment, the number of subfields constituting one field and the luminance weight of each subfield are not limited to the above values.

First, the subfield SF1, which is an all-cell initialization subfield, will be described.

In the first half of the initialization period of the subfield SF1 that performs the all-cell initialization operation, the data electrode D (1) to the data electrode D (m) and the sustain electrode SU (1) to the sustain electrode SU (n) A voltage of 0 (V) is applied. A voltage Vi1 is applied to scan electrode SC (1) to scan electrode SC (n) after voltage 0 (V) is applied, and an upward ramp waveform voltage (ramp voltage) gradually rising from voltage Vi1 to voltage Vi2. ) Is applied. Voltage Vi1 is set to a voltage lower than the discharge start voltage with respect to sustain electrode SU (1) to sustain electrode SU (n), and voltage Vi2 is set to a voltage exceeding the discharge start voltage.

While this ramp voltage rises, scan electrode SC (1) to scan electrode SC (n) and sustain electrode SU (1) to sustain electrode SU (n) of each discharge cell, and scan electrode SC (1 ) To the scan electrode SC (n) and the data electrode D (1) to the data electrode D (m), weak initializing discharges are continuously generated. Then, negative wall voltage is accumulated on scan electrode SC (1) to scan electrode SC (n), and data electrode D (1) to data electrode D (m) and sustain electrode SU (1) to sustain electrode SU. (N) A positive wall voltage is accumulated on the top. The wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

In the second half of the initializing period of subfield SF1, positive voltage Ve is applied to sustain electrode SU (1) to sustain electrode SU (n), and data electrode D (1) to data electrode D (m) are applied to data electrode D (1) to data electrode D (m). A voltage of 0 (V) is applied. Scan electrode SC (1) to scan electrode SC (n) are applied with a downward ramp waveform voltage (ramp voltage) that gently falls from voltage Vi3 toward negative voltage Vi4. Voltage Vi3 is set to a voltage lower than the discharge start voltage with respect to sustain electrode SU (1) to sustain electrode SU (n), and voltage Vi4 is set to a voltage exceeding the discharge start voltage.

While this ramp voltage is applied to scan electrode SC (1) -scan electrode SC (n), scan electrode SC (1) -scan electrode SC (n) and sustain electrode SU (1) -sustain electrode of each discharge cell. A weak initializing discharge occurs between SU (n) and between scan electrode SC (1) -scan electrode SC (n) and data electrode D (1) -data electrode D (m). . Thus, negative wall voltage on scan electrode SC (1) to scan electrode SC (n), positive wall voltage on sustain electrode SU (1) to sustain electrode SU (n), and data electrode D (1) The positive wall voltage on the data electrode D (m) is adjusted to a value suitable for the write operation.

Thus, the all-cell initializing operation in the initializing period of the subfield SF1 is completed, and wall charges necessary for the subsequent addressing operation are formed on each electrode in all the discharge cells.

In this embodiment, a device for reducing power consumption is applied to the waveform shape of the address pulse applied to the data electrode D (1) to the data electrode D (m) in the subsequent address period. Details of this will be described later. Hereinafter, an outline of the write operation in the write period will be described.

In the address period of subfield SF1, first, voltage Ve is applied to sustain electrode SU (1) to sustain electrode SU (n), and voltage 0 (V) is applied to data electrode D (1) to data electrode D (m). ) And a voltage Vc is applied to scan electrode SC (1) to scan electrode SC (n).

Then, in the first address period, a negative scan pulse with a negative voltage Va is applied to the scan electrode SC (1) of the first line (first row). Then, a positive address pulse having a positive voltage Vd is applied to the data electrode D (k) of the discharge cell that should emit light in the first line among the data electrodes D (1) to D (m).

In the discharge cell at the intersection of the data electrode D (k) to which the address pulse voltage Vd is applied and the scan electrode SC (1) to which the scan pulse voltage Va is applied, the data electrode D (k) and the scan electrode SC ( Discharge occurs between 1) and 1).

In addition, since voltage Ve is applied to sustain electrode SU (1) to sustain electrode SU (n), it is induced by a discharge generated between data electrode D (k) and scan electrode SC (1). Discharge is also generated between sustain electrode SU (1) and scan electrode SC (1) in the region intersecting data electrode D (k). Thus, an address discharge occurs in the discharge cell (discharge cell to emit light) to which the voltage Va of the scan pulse and the voltage Vd of the address pulse are simultaneously applied, and a positive wall voltage is accumulated on the scan electrode SC (1). A negative wall voltage is accumulated on the sustain electrode SU (1), and a negative wall voltage is also accumulated on the data electrode D (k).

In this way, the address operation in the discharge cell on the first line is completed. In the discharge cells to which no address pulse is applied, the address discharge does not occur, and the wall voltage after the end of the initialization period is maintained.

Next, in the second address period, a scan pulse of voltage Va is applied to the scan electrode SC (2) of the second line (second row), and the data electrode corresponding to the discharge cell that should emit light on the second line. An address pulse of voltage Vd is applied to D (k). As a result, address discharge occurs in the discharge cells of the second line to which the scan pulse and address pulse are simultaneously applied. Thus, an address operation is performed in the discharge cell of the second line.

Similarly, a scan pulse of voltage Va is applied to the scan electrode SC (i) of the i-th line in the i-th write cycle, and the data electrode D (k) corresponding to the discharge cell to emit light on the i-th line is applied. An address pulse of voltage Vd is applied. As a result, an address discharge occurs in the i-th line discharge cell to which the scan pulse and the address pulse are simultaneously applied, and an address operation is performed in the i-th line discharge cell.

The same address operation is sequentially performed until the discharge cell on the n-th line, and the address period of the subfield SF1 ends.

Note that voltage Ve applied to sustain electrode SU (1) to sustain electrode SU (n) in the latter half of the initialization period and voltage Ve applied to sustain electrode SU (1) to sustain electrode SU (n) in the address period Different voltage values may be used.

In the subsequent sustain period of subfield SF1, voltage 0 (V) is first applied to sustain electrode SU (1) to sustain electrode SU (n). Then, sustain pulse of positive voltage Vs is applied to scan electrode SC (1) to scan electrode SC (n).

In the discharge cell in which the address discharge is generated by the application of the sustain pulse, the voltage difference between the scan electrode SC (i) and the sustain electrode SU (i) exceeds the discharge start voltage, and the sustain discharge is generated. And the fluorescent substance layer 25 light-emits with the ultraviolet-ray which generate | occur | produced by this discharge. Further, due to this discharge, a negative wall voltage is accumulated on scan electrode SC (i), and a positive wall voltage is accumulated on sustain electrode SU (i). Furthermore, a positive wall voltage is also accumulated on the data electrode D (k). However, no sustain discharge occurs in the discharge cells in which no address discharge has occurred during the address period.

Subsequently, voltage 0 (V) is applied to scan electrode SC (1) to scan electrode SC (n), and a sustain pulse of voltage Vs is applied to sustain electrode SU (1) to sustain electrode SU (n). . In the discharge cell that has generated a sustain discharge immediately before, a sustain discharge occurs again, a negative wall voltage is accumulated on sustain electrode SU (i), and a positive wall voltage is accumulated on scan electrode SC (i).

Thereafter, in the same manner, scan electrodes SC (1) to scan electrode SC (n) and sustain electrodes SU (1) to sustain electrode SU (n) are alternately supplied with the number of sustain pulses obtained by multiplying the brightness weight by a predetermined brightness multiple. Apply to. Thus, the discharge cells that have generated the address discharge in the address period emit light with a luminance corresponding to the luminance weight.

Then, after the sustain pulse is generated in the sustain period, scanning is performed with voltage 0 (V) applied to sustain electrode SU (1) to sustain electrode SU (n) and data electrode D (1) to data electrode D (m). A ramp waveform voltage (ramp voltage) that gently rises from voltage 0 (V) to voltage Vr is applied to electrode SC (1) to scan electrode SC (n).

During the application of this ramp voltage to scan electrode SC (1) to scan electrode SC (n), a weak discharge is generated in the discharge cell that has generated the sustain discharge. The charged particles generated by the weak discharge are on the sustain electrode SU (i) and the scan electrode SC (i) so as to alleviate the voltage difference between the sustain electrode SU (i) and the scan electrode SC (i). Accumulated as wall charges on top. Thereby, the wall voltage on scan electrode SC (i) and sustain electrode SU (i) is weakened while the positive wall voltage on data electrode D (k) remains. That is, unnecessary wall charges in the discharge cell are erased.

When the voltage applied to scan electrode SC (1) to scan electrode SC (n) reaches voltage Vr, the voltage applied to scan electrode SC (1) to scan electrode SC (n) is lowered to voltage 0 (V). . Thus, the sustain operation in the sustain period of subfield SF1 is completed.

Thus, subfield SF1 is completed.

Next, subfield SF2, which is a selective initialization subfield, will be described.

In the initializing period of subfield SF2, voltage Ve is applied to sustain electrode SU (1) to sustain electrode SU (n), and voltage 0 (V) is applied to data electrode D (1) to data electrode D (m). Is applied. Scan electrode SC (1) to scan electrode SC (n) have a ramp waveform voltage (ramp voltage) that gently falls from a voltage (for example, voltage 0 (V)) that is less than the discharge start voltage toward negative voltage Vi4. Is applied. Voltage Vi4 is set to a voltage exceeding the discharge start voltage with respect to sustain electrode SU (1) to sustain electrode SU (n).

In a discharge cell in which a sustain discharge is generated in the sustain period of the immediately preceding subfield (subfield SF1 in FIG. 4) while this ramp voltage is applied to scan electrode SC (1) to scan electrode SC (n), it is weak. Initializing discharge occurs. The initialization discharge weakens the wall voltage on scan electrode SC (i) and sustain electrode SU (i). In addition, an excessive portion of the wall voltage accumulated on the data electrode D (k) is discharged. Thus, the wall voltage in the discharge cell is adjusted to a wall voltage suitable for the address operation.

On the other hand, in the discharge cells that did not generate the sustain discharge in the sustain period of the immediately preceding subfield (subfield SF1), the initialization discharge does not occur and the previous wall voltage is maintained.

As described above, the initializing operation in the subfield SF2 is a selective initializing operation in which the initializing discharge is selectively generated in the discharge cells that have performed the addressing operation in the address period of the immediately preceding subfield.

Thus, the selective initialization operation in the initialization period of subfield SF2 is completed.

In the address period of the subfield SF2, a drive voltage waveform similar to that in the address period of the subfield SF1 is applied to each electrode, and an address operation for accumulating wall voltage on each electrode of the discharge cell to emit light is performed.

In the subsequent sustain period, similarly to the sustain period of subfield SF1, the number of sustain pulses corresponding to the luminance weight is applied to scan electrode SC (1) to scan electrode SC (n) and sustain electrode SU (1) to sustain electrode SU ( n) alternately, and sustain discharge is generated in the discharge cells that have generated address discharge in the address period.

In the initialization period and address period of each subfield after subfield SF3, the same drive voltage waveform as that in the initialization period and address period of subfield SF2 is applied to each electrode. In the sustain period of each subfield after subfield SF3, the drive voltage waveform similar to that of subfield SF2 is applied to each electrode except for the number of sustain pulses generated in the sustain period.

The above is the outline of the drive voltage waveform applied to each electrode of panel 10 in the present embodiment.

FIG. 5 is a diagram schematically showing an example of a circuit block constituting the plasma display device 30 according to the first embodiment of the present invention.

The plasma display device 30 shown in the present embodiment includes a panel 10 and a drive circuit that drives the panel 10. The drive circuit includes an image signal processing circuit 31, a data electrode drive circuit 32, a scan electrode drive circuit 33, a sustain electrode drive circuit 34, a timing generation circuit 35, and a power supply circuit (not shown) that supplies necessary power to each circuit block. It has.

The image signals input to the image signal processing circuit 31 are a red image signal, a green image signal, and a blue image signal. The image signal processing circuit 31 sets each gradation value of red, green, and blue in each discharge cell based on the red image signal, the green image signal, and the blue image signal. In the image signal processing circuit 31, the input image signal includes a luminance signal (Y signal) and a saturation signal (C signal, or RY signal and BY signal, or u signal and v signal, etc.). In some cases, a red image signal, a green image signal, and a blue image signal are calculated based on the luminance signal and the saturation signal, and then each of the red, green, and blue tone values (represented by one field) is stored in each discharge cell. Tone value). Then, the red, green, and blue gradation values set in each discharge cell are associated with image data indicating lighting / non-lighting for each subfield (light emission / non-light emission corresponds to digital signals “1” and “0”). Data). That is, the image signal processing circuit 31 converts the red image signal, the green image signal, and the blue image signal into red image data, green image data, and blue image data and outputs the converted image data.

The timing generation circuit 35 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal and the vertical synchronization signal. The generated timing signal is supplied to each circuit block (data electrode drive circuit 32, scan electrode drive circuit 33, sustain electrode drive circuit 34, image signal processing circuit 31, etc.).

The data electrode drive circuit 32 corresponds to each data electrode D (1) to data electrode D (m) based on the image data of each color output from the image signal processing circuit 31 and the timing signal supplied from the timing generation circuit 35. A write pulse is generated. Then, the data electrode drive circuit 32 applies the address pulse to the data electrodes D (1) to D (m) during the address period.

The data electrode drive circuit 32 has a plurality of integrated circuits. Each integrated circuit generates an address pulse that is applied to a predetermined number of data electrodes 22. This integrated circuit is hereinafter referred to as a “data driver”. In the present embodiment, the data driver 40 is configured as a monolithic IC, for example. Each data driver 40 generates an address pulse to be applied to, for example, 384 data electrodes 22. Panel 10 in the present embodiment has 1920 pixels in the horizontal direction. That is, the panel 10 has 1920 × 3 = 5760 discharge cells in one line. Therefore, the data electrode drive circuit 32 has, for example, 15 data drivers 40 (data driver 40 (1) to data driver 40 (15)), and drives 5760 data electrodes 22.

Scan electrode drive circuit 33 includes an initialization waveform generation circuit, a sustain pulse generation circuit, and a scan pulse generation circuit (not shown in FIG. 5), and generates a drive voltage waveform based on a timing signal supplied from timing generation circuit 35. It is prepared and applied to each of scan electrode SC (1) to scan electrode SC (n). The initialization waveform generation circuit generates an initialization waveform to be applied to scan electrode SC (1) to scan electrode SC (n) during the initialization period based on the timing signal. The sustain pulse generation circuit generates a sustain pulse to be applied to scan electrode SC (1) to scan electrode SC (n) during the sustain period based on the timing signal. The scan pulse generation circuit includes a plurality of scan electrode drive ICs (scan ICs), and generates scan pulses to be applied to scan electrode SC (1) to scan electrode SC (n) during an address period based on a timing signal.

Sustain electrode drive circuit 34 includes a sustain pulse generation circuit and a circuit (not shown in FIG. 5) for generating voltage Ve, creates a drive voltage waveform based on the timing signal supplied from timing generation circuit 35, The voltage is applied to each of sustain electrode SU (1) to sustain electrode SU (n). In the sustain period, a sustain pulse is generated based on the timing signal and applied to sustain electrode SU (1) to sustain electrode SU (n).

Next, details of the data electrode drive circuit 32 will be described.

FIG. 6 is a circuit diagram schematically showing the configuration of the data electrode drive circuit 32 of the plasma display device 30 in one embodiment of the present invention. In FIG. 6, only a part of the circuit blocks constituting the data electrode drive circuit 32 is shown, and other circuit blocks having the same configuration are omitted.

The data electrode drive circuit 32 includes fifteen data drivers 40 (data driver 40 (1) to data driver 40 (15)), a load calculation unit 52 provided corresponding to each of the data drivers 40, a data driver 40, a write timing generator 54 provided corresponding to each of the data drivers 40, a recovery capacitor C40 provided corresponding to each of the data drivers 40, and a recovery coil L40 provided corresponding to each of the data drivers 40. Have

Hereinafter, the data driver 40 (1) to the data driver 40 (15) are collectively referred to as “data driver 40 (p)”, and the load calculation unit 52 corresponding to the data driver 40 (p) is referred to as the load calculation unit 52 (p ), The write timing generator 54 corresponding to the data driver 40 (p) is referred to as a write timing generator 54 (p), and the recovery capacitor C40 corresponding to the data driver 40 (p) is referred to as a recovery capacitor C40 (p). The recovery coil L40 corresponding to the data driver 40 (p) is referred to as a recovery coil L40 (p). In the present embodiment, p is a numerical value from 1 to 15.

The load calculation unit 52 (p) calculates a substantial load capacity in each of the plurality of data electrodes 22 driven by the data driver 40 (p), and calculates a total of the calculated load capacity. That is, the load calculation unit 52 (p) calculates the sum of the load capacities of the plurality of data electrodes 22 driven by the data driver 40 (p). Details of the method of calculating the substantial load capacity of the data electrode 22 will be described later.

The write timing generation unit 54 (p) generates a write timing signal LLP (p) based on the total load capacity calculated by the load calculation unit 52 (p), and outputs the generated write timing signal LLP (p). .

Each of the data driver 40 (1) to the data driver 40 (15) includes a shift register unit 41, a data latch unit 43, and an output buffer unit 45.

The shift register unit 41 is a shift register. The shift register unit 41 has the same number of latches 42 as the number of N (for example, N = 384) data electrodes 22 driven by the data driver 40 or more than that. Each latch 42 is connected in series, and forwards (shifts) the input signal to the subsequent latch 42 in synchronization with the clock signal (clock Dck). Then, serial data transmitted from a data converter (not shown) is converted into parallel data.

Serial data is data expressed in the form of a plurality of bit signals that are temporally continuous so that a plurality of bit signals constituting one data can be transmitted by one signal line. For example, if the data is composed of 8 bits, it becomes 8 bit signals continuous in time.

Parallel data refers to data expressed in a format that can be transmitted through the same number of signal lines as bit signals so that a plurality of bit signals constituting one data can be transmitted at the same timing in synchronization with one clock signal. It is. For example, if the data is composed of 8 bits, it becomes 8 parallel bit signals that change at the same timing according to the change of the data, and can be transmitted in parallel by 8 signal lines.

Although not shown, the data converter is provided between the image signal processing circuit 31 and the data driver 40, and image data (image data assigned to each discharge) transmitted from the image signal processing circuit 31 is provided. Is converted into data for each subfield. This conversion will be described.

For example, if one field is composed of eight subfields (subfield SF1 to subfield SF8), the image data is 8-bit data. Each bit data of the image data represents light emission / non-light emission in each subfield of subfield SF1 to subfield SF8. Since the panel 10 is driven by the subfield method, each discharge cell of the panel 10 needs to be controlled to emit or not emit light for each subfield. Therefore, if the image data is used as it is, the light emission / non-light emission of each discharge cell cannot be controlled for each subfield.

In order to drive the panel 10 by the subfield method, for example, in the subfield SF1, only the bit data corresponding to the subfield SF1 of the image data assigned to each discharge cell is extracted as one data, In SF2, it is necessary to extract only the bit data corresponding to the subfield SF2 of the image data assigned to each discharge cell to be one data. The data conversion unit performs this conversion.

That is, for each subfield, the data conversion unit extracts only the bit data corresponding to the subfield from the image data assigned to each discharge cell and performs conversion into one data.

The data is transmitted as serial data to the shift register unit 41. The shift register unit 41 converts a plurality of bits of serial data corresponding to the subfield transmitted from the data conversion unit into parallel data.

Hereinafter, of the image data, the bit image data corresponding to the subfield SFQ is referred to as “image data Q”. That is, the shift register unit 41 receives N-bit serial image data Q corresponding to each of the N data electrodes 22 transmitted from the data conversion unit, and N-bit parallel image data corresponding to each of the N data electrodes 22. Is converted into image data Q and output.

The data latch unit 43 has N latches 44 corresponding to N (for example, N = 384) data electrodes 22 driven by the data driver 40. Each latch 44 latches the image data Q corresponding to each of the data electrodes 22 with the write timing signal LLP and outputs the latched data to the output buffer unit 45.

The output buffer unit 45 includes N output buffers 46 corresponding to each of N (for example, N = 384) data electrodes 22 driven by the data driver 40. Each output buffer 46 generates an address pulse to be applied to the data electrode 22.

Here, the output buffer unit 45 will be described.

FIG. 7 is a circuit diagram schematically showing the configuration of the output buffer unit 45 included in the data electrode drive circuit 32 of the plasma display device 30 in one embodiment of the present invention. FIG. 7 shows only a part of the circuit blocks constituting the output buffer unit 45, and other circuit blocks having the same configuration are omitted.

The output buffer unit 45 has N high-voltage switches QH, N low-voltage switches QL, and N recovery switches QC. The high voltage side switch QH outputs the high voltage side voltage Vd of the write pulse, and the low voltage side switch QL outputs the low voltage side voltage 0 (V) of the write pulse. For example, if N = 384, the output buffer unit 45 collects the high-voltage side switch QH (1) to the high-voltage side switch QH (384), the low-voltage side switch QL (1) to the low-voltage side switch QL (384), A switch QC (1) to a recovery switch QC (384).

In the present embodiment, each recovery switch QC is composed of one P-channel MOSFET.

As shown in FIG. 7, in the present embodiment, each output buffer 46 has a circuit in which one high-voltage side switch QH, one low-voltage side switch QL, and one recovery switch QC are combined. The circuit is controlled by a signal output from the latch 44 and a write timing signal LLP. This circuit operates in synchronization with the timing of the write timing signal LLP, and outputs a high voltage Vd or a low voltage 0 (V) based on the signal output from the latch 44. In this way, the output buffer 46 generates a write pulse and applies it to the data electrode 22.

The recovery capacitor C40 has a sufficiently large capacity compared to the interelectrode capacity, and is an intermediate voltage (Vd / 2) lower than the high-voltage side voltage Vd of the write pulse and higher than the low-voltage side voltage 0 (V) of the write pulse. ) Is charged.

The recovery coil L40 has one terminal connected to the recovery capacitor C40 and the other terminal connected to each of the N recovery switches QC (1) to QC (N) of the data driver 40. Then, the substantial load capacity of the data electrode 22 driven by the data driver 40 and the recovery coil L40 resonate, and the voltages of the N data electrodes 22 transition.

In this way, the data electrode driving circuit 32 includes a recovery capacitor C40 charged to an intermediate voltage (Vd / 2) lower than the high voltage Vd of the write pulse and higher than the low voltage 0 (V) of the write pulse, The number of recovery coils L40 connected in series to the recovery capacitor C40 is the same as the number of data drivers 40 (for example, 15 each), and the high voltage side switch QH that outputs the high voltage side voltage Vd and the low voltage side voltage 0 (V) are provided. An output buffer 46 having a low voltage side switch QL for outputting and a recovery switch QC connected to the recovery capacitor C40 is provided for each of the data electrodes D (1) to D (m) (for example, m = 5760). ing.

The data electrode drive circuit 32 is configured by using a plurality (for example, 15) of integrated circuits (data drivers 40) in which a plurality of (for example, 384) output buffers 46 are integrated on one chip. .

The data electrode driving circuit 32 applies the high voltage side voltage Vd of the write pulse or the low voltage side voltage 0 (V) of the write pulse to the data electrode D (1) to the data electrode D (m) for each write cycle of the write period to be described later. ).

Next, details of the address pulse applied to the data electrode D (1) to the data electrode D (m) will be described together with the operation of the data driver 40.

In the present embodiment, a first transition period Ta is provided at the beginning of each write cycle, and a second transition period Tb is provided at the end of each write cycle. This write cycle is a period from the start to the end of one write operation, for example, a cycle from the start of generation of one scan pulse to the end of generation.

When the address pulse is applied to the data electrode 22, the voltage applied to the data electrode 22 is changed from the low voltage side voltage 0 (V) to the high voltage side voltage Vd during the first transition period Ta. It is during the second transition period Tb that the voltage applied to is shifted from the high voltage Vd to the low voltage 0 (V).

FIG. 8 is a diagram schematically showing an example of the write pulse generated in the plasma display device 30 according to the embodiment of the present invention.

The details of the first transition period Ta and the second transition period Tb will be described later, and the outline when performing the write operation will be described below.

FIG. 8 shows three address periods (address period T (i−1), address period T (i), address period T (i + 1)) in the address period as an example, and scan electrode SC (i−1) ) To scanning electrode SC (i + 1) and data electrode D (j−2) to driving electrode waveform applied to data electrode D (j + 3) by way of example.

Hereinafter, the data electrode D (j-2) to the data electrode D (j + 3) will be described as being driven by the data driver 40 (1).

In FIG. 8, data electrode D (j-2), data electrode D (j-1), data electrode D (j), and data electrode D (j + 2) are written in address cycle T (i-1). A pulse is applied, no address pulse is applied to the data electrode D (j + 1) and the data electrode D (j + 3), and an address is written to the data electrode D (j + 1) and the data electrode D (j + 3) in the address period T (i). A pulse is applied, an address pulse is not applied to the data electrode D (j-2), the data electrode D (j-1), the data electrode D (j), and the data electrode D (j + 2), and the address period T (i + 1 ), An address pulse is applied to data electrode D (j−1), data electrode D (j) and data electrode D (j + 3), and data electrode D (j−2), data electrode D (j + 1) and data electrode are applied. Write to D (j + 2) An example applying no pulse.

Although not shown in FIG. 8, in the example described below, in the write cycle T (i-2) immediately before the write cycle T (i-1), the data electrode D (j-2) to the data electrode It is assumed that no write pulse is applied to D (j + 3).

In the write cycle T (i-1), a negative polarity scan pulse of voltage Va is applied to the scan electrode SC (i-1) of the (i-1) th line.

Then, at the start time t11 of the first transition period Ta in the write cycle T (i-1), the recovery switch QC (j-2) and the recovery switch QC of the output buffer unit 45 (1) included in the data driver 40 (1). (J-1), the recovery switch QC (j) and the recovery switch QC (j + 2) are turned on.

As a result, the sum of the substantial load capacities of the plurality of data electrodes 22 driven by the data driver 40 (1) resonates with the recovery coil L40 (1), and the recovery coil C40 (1) to the recovery coil L40 (1). , And each recovery switch QC (recovery switch QC (j-2), recovery switch QC (j-1), recovery switch QC (j), recovery switch QC (j + 2)) through the data electrode D (j-2 ), Current begins to flow through the data electrode D (j−1), the data electrode D (j), and the data electrode D (j + 2), and the voltage of these data electrodes 22 begins to rise.

At time t12, the voltage of these data electrodes 22 rises to near the voltage Vd. The time from the time t11 to the time t12 is ½ of the total sum of the substantial load capacities of the plurality of data electrodes 22 driven by the data driver 40 (1) and the resonance period of the recovery coil L40 (1). Approximately equal to time.

At time t12, the recovery switch QC (j-2), the recovery switch QC (j-1), the recovery switch QC (j) and the recovery switch QC (j + 2) are turned off, and the high voltage side switch QH (j-2) The high voltage side switch QH (j-1), the high voltage side switch QH (j) and the high voltage side switch QH (j + 2) are turned on, and the data electrodes 22 (data electrode D (j-2), data electrode D ( j-1), the voltage of the data electrode D (j) and the data electrode D (j + 2)) is clamped to the high voltage Vd. Thus, the first transition period Ta in the write cycle T (i−1) ends.

When an address pulse of voltage Vd is applied to data electrode D (j-2), data electrode D (j-1), data electrode D (j) and data electrode D (j + 2), a scan pulse and an address pulse are applied simultaneously. Address discharge occurs in the discharge cell on the (i-1) th line.

Then, after the occurrence of the address discharge until the time t21, the high voltage side switch QH (j-2), the high voltage side switch QH (j-1), the high voltage side switch QH (j) and the high voltage side switch QH (j + 2) Turn off.

Next, at the time t21 when the second transition period Tb in the write cycle T (i-1) starts, the recovery switch QC (j-2), the recovery switch QC (j-1) of the output buffer unit 45 (1), The recovery switch QC (j) and the recovery switch QC (j + 2) are turned on.

As a result, the sum of the substantial load capacities of the plurality of data electrodes 22 driven by the data driver 40 (1) and the recovery coil L40 (1) resonate, and the data electrode D (j-2) and the data electrode D ( j-1), the data electrode D (j), and the data electrode D (j + 2), respectively, the recovery switches QC (recovery switch QC (j-2), recovery switch QC (j-1), recovery switch QC (j) , The recovery switch QC (j + 2)) and the recovery coil L40 (1), current begins to flow to the recovery capacitor C40 (1), and the voltage of these data electrodes 22 starts to decrease.

Then, at time t22, the voltage of these data electrodes 22 decreases to near voltage 0 (V). The time from time t21 to time t22 is ½ of the total load capacity of the plurality of data electrodes 22 driven by the data driver 40 (1) and the resonance period of the recovery coil L40 (1). Approximately equal to time.

At time t22, the recovery switch QC (j-2), the recovery switch QC (j-1), the recovery switch QC (j), and the recovery switch QC (j + 2) are turned off, and the low-pressure side switch QL (j-2) The low voltage side switch QL (j−1), the low voltage side switch QL (j) and the low voltage side switch QL (j + 2) are turned on, and the data electrodes 22 (data electrode D (j−2), data electrode D ( j-1), the voltage of the data electrode D (j) and the data electrode D (j + 2)) is clamped to the low voltage 0 (V). Thus, the second transition period Tb in the write cycle T (i−1) ends.

During this time, the operation of returning the voltage of the scan electrode SC (i-1) of the (i-1) -th line from the voltage Va to the voltage Vc is started, and the voltage of the scan electrode SC (i-1) becomes the voltage Vc. Thus, the write cycle T (i−1) ends.

In the subsequent address period T (i), a negative scan pulse of voltage Va is applied to the scan electrode SC (i) on the (i) line.

Then, at the start time t31 of the first transition period Ta in the write cycle T (i), the recovery switch QC (j + 1) and the recovery switch QC (j + 3) of the output buffer unit 45 (1) are turned on. As a result, the sum of the substantial load capacities of the plurality of data electrodes 22 driven by the data driver 40 (1) resonates with the recovery coil L40 (1), and the data electrode D (j + 1) is recovered from the recovery capacitor C40 (1). In addition, current starts to flow through the data electrodes D (j + 3), and the voltages of these data electrodes 22 start to rise.

At time t32 when the voltage of these data electrodes 22 rises to near the voltage Vd, the recovery switch QC (j + 1) and the recovery switch QC (j + 3) are turned off, and the high voltage side switch QH (j + 1) and the high voltage side switch QH ( j + 3) is turned on, and the voltages of the data electrodes 22 (data electrode D (j + 1) and data electrode Dj + 3) are clamped to the high voltage Vd. Thus, the first transition period Ta in the write cycle T (i) ends.

In this way, when the address pulse of the voltage Vd is applied to the data electrode D (j + 1) and the data electrode D (j + 3), the address discharge is caused in the discharge cell on the (i) line where the scan pulse and the address pulse are simultaneously applied. Occurs.

Then, the high-voltage side switch QH (j + 1) is turned off between the occurrence of the address discharge and the time t41. Note that, in the subsequent address period T (i + 1), the address pulse is applied to the data electrode D (j + 3), so that the high voltage side switch QH (j + 3) is kept on.

Next, at time t41 when the second transition period Tb in the write cycle T (i) starts, the recovery switch QC (j + 1) of the output buffer unit 45 (1) is turned on.

As a result, the sum of the substantial load capacities of the plurality of data electrodes 22 driven by the data driver 40 (1) resonates with the recovery coil L40 (1), and the recovery capacitor C40 (1) is recovered from the data electrode D (j + 1). Current starts to flow, and the voltage of the data electrode D (j + 1) begins to drop.

At time t42 when the voltage of the data electrode D (j + 1) drops to near voltage 0 (V), the recovery switch QC (j + 1) is turned off, the low-voltage side switch QL (j + 1) is turned on, and the data electrode D ( The voltage of j + 1) is clamped to the low voltage 0 (V). Thus, the second transition period Tb in the write cycle T (i) ends.

During this time, the operation of returning the voltage of the scan electrode SC (i) on the (i) line from the voltage Va to the voltage Vc is started, and the voltage of the scan electrode SC (i) becomes the voltage Vc and the write cycle T (I) ends.

In the subsequent write cycle T (i + 1), a negative scan pulse of voltage Va is applied to the scan electrode SC (i + 1) of the (i + 1) th line.

Then, at the start time t51 of the first transition period Ta in the write cycle T (i + 1), the recovery switch QC (j−1) and the recovery switch QC (j) of the output buffer unit 45 (1) are turned on. As a result, the sum of the substantial load capacities of the plurality of data electrodes 22 driven by the data driver 40 (1) and the recovery coil L40 (1) resonate, and the recovery electrode C40 (1) and the data electrode D (j− 1) and the data electrode D (j) start to flow, and the voltage of these data electrodes 22 begins to rise.

At time t52 when the voltage of these data electrodes 22 rises to near the voltage Vd, the recovery switch QC (j-1) and the recovery switch QC (j) are turned off, and the high voltage side switch QH (j-1) and the high voltage switch The side switch QH (j) is turned on, and the voltages of the data electrodes 22 (data electrode D (j-1) and data electrode D (j)) are clamped to the high voltage side voltage Vd. Thus, the first transition period Ta in the write cycle T (i + 1) ends.

Note that, since the high-voltage side switch QH (j + 3) has been on since the second transition period Tb of the write cycle T (i), the data electrode D is output during the first transition period Ta of the write cycle T (i + 1). The voltage (j + 3) remains the high voltage Vd.

In this manner, when the address pulse of the voltage Vd is applied to the data electrode D (j−1), the data electrode D (j), and the data electrode D (j + 3), the scan pulse and the address pulse are simultaneously applied (i + 1). ) Address discharge occurs in the discharge cells on the line.

The high-voltage side switch QH (j−1) and the high-voltage side switch QH (j + 3) are turned off after the address discharge occurs until time t61. Note that, in the subsequent address period T (i + 2), the address pulse is applied to the data electrode D (j), so that the high-voltage side switch QH (j) remains on.

Next, at time t61 when the second transition period Tb in the write cycle T (i + 1) starts, the recovery switch QC (j−1) and the recovery switch QC (j + 3) of the output buffer unit 45 (1) are turned on.

As a result, the sum of the substantial load capacities of the plurality of data electrodes 22 driven by the data driver 40 (1) and the recovery coil L40 (1) resonate, and the data electrode D (j-1) and the data electrode D ( The current starts to flow from j + 3) to the recovery capacitor C40 (1), and the voltage of the data electrode D (j−1) and the data electrode D (j + 3) starts to drop.

The recovery switch QC (j−1) and the recovery switch QC (j + 3) are turned off at time t62 when the voltage of the data electrode D (j−1) and the data electrode D (j + 3) decreases to near the voltage 0 (V). The low voltage side switch QL (j-1) and the low voltage side switch QL (j + 3) are turned on, and the voltage of the data electrode D (j-1) and the data electrode D (j + 3) is set to the low voltage side voltage 0 (V). Clamp. Thus, the second transition period Tb in the write cycle T (i + 1) ends.

During this time, the operation of returning the voltage of the scan electrode SC (i + 1) of the (i + 1) -th line from the voltage Va to the voltage Vc is started, and the voltage of the scan electrode SC (i + 1) becomes the voltage Vc and the write cycle T (I + 1) ends.

Summarizing the above operations, the output buffer 46 in the present embodiment operates as follows when the output voltage is changed from the low voltage 0 (V) to the high voltage Vd. That is, in the first transition period Ta provided in each write cycle, the recovery switch QC is turned on, and the sum of substantial load capacities of the plurality of data electrodes 22 driven by the data driver 40 and the recovery coil L40 are Resonate and increase the output voltage. When the output voltage approaches the voltage Vd, the recovery switch QC is turned off, the high-voltage side switch QH is turned on, and the output voltage is clamped to the high-voltage side voltage Vd.

The output buffer 46 operates as follows when the output voltage is changed from the high-voltage side voltage Vd to the low-voltage side voltage 0 (V). That is, in the second transition period Tb that is provided in each of the write cycles and does not overlap with the first transition period Ta in time (separated in time), the recovery switch QC is turned on to drive the data driver 40. The total sum of the load capacities of the data electrodes 22 and the recovery coil L40 are resonated to lower the output voltage. When the output voltage approaches the low voltage 0 (V), the recovery switch QC is turned off, the low voltage switch QL is turned on, and the output voltage is clamped to the low voltage 0 (V).

Thus, power can be supplied from the power supply having a constant voltage Vd to the data electrode driving circuit 32 to perform a stable addressing operation, and the power consumption of the data electrode driving circuit 32 can be reduced. The reason will be described below.

As described above, in the present embodiment, when the voltage applied to the data electrode 22 is shifted from the low voltage side voltage 0 (V) to the high voltage side voltage Vd, the load capacitance of the data electrode 22 and the recovery coil L40 are resonated. The voltage of the data electrode 22 is raised to the vicinity of the voltage Vd by causing a current to flow from the recovery capacitor C40 to the data electrode 22.

When the voltage applied to the data electrode 22 is changed from the high-voltage side voltage Vd to the low-voltage side voltage 0 (V), the load capacitance of the data electrode 22 and the recovery coil L40 are resonated, and a current is supplied from the data electrode 22 to the recovery capacitor C40. By flowing, the voltage of the data electrode 22 is lowered to near the low voltage 0 (V).

In these operations, the power source is the recovery capacitor C40, and power supply from the power source of the voltage Vd to the data electrode 22 does not occur.

The power is supplied from the power source of the voltage Vd to the data electrode 22 when the voltage of the data electrode 22 is increased to the vicinity of the voltage Vd after the voltage of the data electrode 22 is clamped to the high voltage Vd and to the discharge cell. This is limited to supplying a discharge current generated when an address discharge occurs.

Therefore, according to the present embodiment, when the data electrode 22 is driven, the power used for charging and discharging the load capacity of the data electrode 22 can be greatly reduced.

Next, a method for obtaining the substantial load capacity of the data electrode 22 will be described in detail together with the configuration of the load calculation unit 52.

As described above, the load capacitance of one data electrode D (j) includes the capacitance Cg generated between the display electrode pair 14 and the capacitance Cc generated between the data electrode D (j + 1) adjacent to the right side. , The total capacitance (Cg + 2Cc) of the capacitance Cc generated between the data electrode D (j−1) adjacent on the left side.

However, the substantial load capacitance that affects the transition of the voltage applied to the data electrode D (j) depends on the voltage applied to the adjacent data electrode D (j + 1) and data electrode D (j−1). Change.

For example, in the first transition period Ta of the write cycle T (i−1) shown in FIG. 8, the voltage applied to the data electrode D (j−1) is changed from the low voltage side voltage 0 (V) to the high voltage side voltage Vd. Transition. Similarly, the voltage applied to each of the data electrode D (j-2) and the data electrode D (j) adjacent to the data electrode D (j-1) is also changed from the low voltage side voltage 0 (V) to the high voltage side voltage Vd. Transition to.

Therefore, with respect to the data electrode D (j−1) in the first transition period Ta of the write cycle T (i−1), the capacitance Cc between the data electrode D (j−2) whose voltage changes in the same direction and The capacitance Cc between the data electrode D (j) can be ignored. Therefore, the substantial load capacitance of the data electrode D (j−1) in the first transition period Ta of the write cycle T (i−1) is the capacitance Cg.

In the first transition period Ta of the write cycle T (i−1) shown in FIG. 8, the voltage applied to the data electrode D (j) transitions from the low voltage side voltage 0 (V) to the high voltage side voltage Vd. The voltage applied to the data electrode D (j−1) adjacent to the data electrode D (j) similarly changes from the low voltage side voltage 0 (V) to the high voltage side voltage Vd. However, the voltage applied to the data electrode D (j + 1) adjacent to the data electrode D (j) remains unchanged at the low voltage 0 (V).

Therefore, regarding the data electrode D (j) in the first transition period Ta of the write cycle T (i−1), the capacitance Cc between the data electrode D (j−1) whose voltage transitions in the same direction is ignored. be able to. However, the capacitance Cc between the data electrode D (j + 1) cannot be ignored. Therefore, the substantial load capacitance of the data electrode D (j) in the first transition period Ta of the write cycle T (i−1) is the capacitance (Cg + Cc).

In the first transition period Ta of the write cycle T (i−1) shown in FIG. 8, the voltage applied to the data electrode D (j + 2) transitions from the low voltage side voltage 0 (V) to the high voltage side voltage Vd. However, the voltage applied to the data electrode D (j + 1) and the data electrode D (j + 3) adjacent to the data electrode D (j + 2) remains the low voltage 0 (V).

Therefore, regarding the data electrode D (j + 2) in the first transition period Ta of the write cycle T (i−1), the capacitance Cc between the data electrode D (j + 1) and the capacitance between the data electrode D (j + 3). Both Cc cannot be ignored. Therefore, the substantial load capacity of the data electrode D (j + 2) in the first transition period Ta of the write cycle T (i−1) is the capacity (Cg + 2Cc).

These phenomena are the same as those in the first transition period Ta in the second transition period Tb in which the voltage applied to the data electrode 22 transitions from the high-voltage side voltage Vd to the low-voltage side voltage 0 (V).

For example, when the voltage applied to the data electrode D (j−1) transitions from the high voltage side voltage Vd to the low voltage side voltage 0 (V), the data electrode D (j−2) adjacent to the data electrode D (j−1). ) And the voltage applied to the data electrode D (j) are also substantially changed in the second transition period Tb of the data electrode D (j−1) if the voltage is changed from the high voltage Vd to the low voltage 0 (V). The load capacity is the capacity Cg.

Further, when the voltage applied to the data electrode D (j) transitions from the high voltage side voltage Vd to the low voltage side voltage 0 (V), it is applied to the data electrode D (j−1) adjacent to the data electrode D (j). Similarly, the voltage transits from the high-voltage side voltage Vd to the low-voltage side voltage 0 (V), but the voltage applied to the data electrode D (j + 1) adjacent to the data electrode D (j) remains the low-voltage side voltage 0 (V). If it does not change (or remains at the high-voltage side voltage Vd), the substantial load capacity in the second transition period Tb of the data electrode D (j) is the capacity (Cg + Cc).

When the voltage applied to the data electrode D (j + 2) transitions from the high voltage side voltage Vd to the low voltage side voltage 0 (V), the data electrode D (j + 1) and the data electrode D (( If the voltage applied to j + 3) remains unchanged at the low voltage 0 (V) (or remains at the high voltage Vd), the substantial load capacitance of the data electrode D (j + 2) in the second transition period Tb is the capacitance (Cg + 2Cc).

As described above, the substantial load capacity that affects the transition of the voltage applied to the data electrode 22 varies according to the image data. That is, when the voltage applied to the data electrode 22 of interest and the voltage applied to the two data electrodes 22 adjacent to the data electrode 22 of interest transition in the same way, the substantial load capacitance at the data electrode 22 of interest is The capacity is Cg. In addition, when only the voltage applied to the data electrode 22 of interest and the voltage applied to one data electrode 22 adjacent to the data electrode 22 of interest change in the same manner, the substantial load capacitance at the data electrode 22 of interest is Capacity (Cg + Cc). In addition, when the voltage applied to the data electrode 22 of interest transitions and the voltages applied to the two data electrodes 22 adjacent to the data electrode 22 of interest do not change, the substantial load capacitance at the data electrode 22 of interest is Capacity (Cg + 2Cc).

Then, the load calculation unit 52 (p) calculates a substantial load capacity in each of the plurality of data electrodes 22 driven by the data driver 40 (p), and calculates the total of the calculated load capacity. That is, the load calculation unit 52 (p) determines the substantial load capacitance of the data electrode 22 depending on whether or not the voltage applied to the data electrode 22 during the writing period changes in phase between the adjacent data electrodes 22. calculate. Then, the sum of the load capacities of the plurality of data electrodes 22 driven by the data driver 40 (p) is calculated.

FIG. 9 is a circuit diagram schematically showing the configuration of the load calculation unit 52 of the plasma display device 30 in one embodiment of the present invention. In FIG. 9, only a part of the circuit blocks configuring the load calculation unit 52 is illustrated, and other circuit blocks having the same configuration are omitted.

The load calculation unit 52 includes a shift register unit 61, a load calculation unit 63, a first load summation unit 65, and a second load summation unit 66.

The shift register unit 61 is a shift register. The shift register unit 61 includes the same number or more latches 62 as the N (for example, N = 384) data electrodes 22 driven by the data driver 40. Each latch 62 is connected in series, and forwards (shifts) the input signal to the subsequent latch 62 in synchronization with the clock signal (clock Dck). And the serial data transmitted from the data converter (not shown) mentioned above are converted into parallel data.

That is, like the shift register unit 41, the shift register unit 61 converts N pieces of serial image data Q corresponding to each of the N data electrodes 22 transmitted from the data conversion unit for each subfield into N pieces. Are converted into N-bit parallel image data Q corresponding to each of the data electrodes 22 and output.

The load calculation unit 63 includes N electrode load calculation units 64 corresponding to each of N (for example, N = 384) data electrodes 22 driven by the data driver 40.

Each of the electrode load calculation units 64 includes a one-line delay 71, a logic gate 72, a logic gate 74, a logic gate 75, a logic gate 76, a logic gate 77, a logic gate 78, a logic gate 82, a logic gate 84, and a logic gate 85. , Logic gate 86, logic gate 87, and logic gate 88.

The logic gate 72 and the logic gate 82 are 2-input and 1-output AND gates (logic circuits that perform a logical product operation). The logic gate 74, the logic gate 75, the logic gate 76, the logic gate 78, the logic gate 84, the logic gate 85, the logic gate 86, and the logic gate 88 are three-input one-output AND gates. The logic gate 77 and the logic gate 87 are two-input one-output OR gates (logic circuits that perform a logical sum operation). In FIG. 9, the small circles at the input terminals of the logic gates are inverters (logic circuits that perform logic inversion).

Hereinafter, the operation of the electrode load calculation unit 64 will be described by taking as an example the case of calculating the substantial load capacity in the data electrode D (j). Therefore, the operation of the electrode load calculation unit 64 described below is the operation of the electrode load calculation unit 64 (j), but the other electrode load calculation units 64 have the same configuration and operation as the electrode load calculation unit 64 (j). It is.

The 1-line delay 71 (j) delays the image data Q (j) corresponding to the data electrode D (j) by 1 line and outputs the image data DQ (j).

The logic gate 72 (j) and the logic gate 82 (j) detect a change in voltage applied to the data electrode D (j) based on the image data DQ (j) and the image data Q (j).

When the image data DQ (j) is “L” and the image data Q (j) is “H”, the output of the logic gate 72 (j) is “H”. Therefore, if the output of the logic gate 72 (j) is “H”, the image data Q (j) changes from “L” to “H”, and the voltage applied to the data electrode D (j) is the low voltage side voltage. It can be determined that the voltage changes from 0 (V) to the high-voltage side voltage Vd (from “L” to “H”).

When the image data DQ (j) is “H” and the image data Q (j) is “L”, the output of the logic gate 82 (j) is “H”. Therefore, if the output of the logic gate 82 (j) is “H”, the image data Q (j) changes from “H” to “L”, and the voltage applied to the data electrode D (j) is the high voltage side voltage. It can be determined that the voltage changes from Vd to the low voltage 0 (V) (from “H” to “L”).

In other cases, the output of the logic gate 72 (j) and the output of the logic gate 82 (j) are “L”. At this time, the image data Q (j) maintains the “L” state or the “H” state, and the voltage applied to the data electrode D (j) is also the low-voltage side voltage 0 (V) (“L”). Or the high voltage side voltage Vd (“H”).

The logic gate 74 (j), logic gate 75 (j), logic gate 76 (j), logic gate 77 (j), logic gate 78 (j), logic gate 84 (j), logic gate 85 ( j), a logic gate 86 (j), a logic gate 87 (j), and a logic gate 88 (j) are composed of a data electrode D (j) and a data electrode adjacent to the data electrode D (j). This is a circuit for detecting a change in image data corresponding to D (j−1) and data electrode D (j + 1). In the present embodiment, the substantial load capacitance of the data electrode D (j) is calculated based on the detection result.

Hereinafter, specific operations of the above-described logic circuit will be described. In the following description, an example in which the substantial load capacity of the data electrode D (j) is calculated will be described. It is assumed that the data electrode 22 adjacent to the data electrode D (j) is the data electrode D (j−1) and the data electrode D (j + 1).

The image data Q (j) of the data electrode D (j) changes from “L” to “H”, and the image data Q (j−1) and the data electrode D (j + 1) of the data electrode D (j−1) When the image data Q (j + 1) is not changed (the “L” state is maintained or the “H” state is maintained), the output of the logic gate 74 (j) is “H”. At this time, the substantial load capacity of the data electrode D (j) is the capacity (Cg + 2Cc) as described above. The image data Q (j) of the data electrode D (j) changes from “L” to “H” during the first transition period Ta. Therefore, if the output of the logic gate 74 (j) is “H”, it can be determined that the substantial load capacitance of the data electrode D (j) in the first transition period Ta is the capacitance (Cg + 2Cc).

The image data Q (j) of the data electrode D (j) changes from “L” to “H”, and the image data Q (j−1) and the data electrode D (j + 1) of the data electrode D (j−1) When only one of the image data Q (j + 1) is changed from “L” to “H”, the output of the logic gate 77 (j) becomes “H”. At this time, the substantial load capacity of the data electrode D (j) is the capacity (Cg + Cc) as described above. Therefore, if the output of the logic gate 77 (j) is “H”, it can be determined that the substantial load capacitance of the data electrode D (j) in the first transition period Ta is the capacitance (Cg + Cc).

The image data Q (j) of the data electrode D (j) changes from “L” to “H”, and the image data Q (j−1) and the data electrode D (j + 1) of the data electrode D (j−1) When the image data Q (j + 1) of both change from “L” to “H”, the output of the logic gate 78 (j) becomes “H”. At this time, the substantial load capacity of the data electrode D (j) is the capacity Cg as described above. Therefore, if the output of the logic gate 78 (j) is “H”, it can be determined that the substantial load capacitance of the data electrode D (j) in the first transition period Ta is the capacitance Cg.

In other cases, for example, when the image data Q (j) of the data electrode D (j) maintains the “L” state or the “H” state, the output of the logic gate 74 (j), the logic The output of the gate 77 (j) and the output of the logic gate 78 (j) are all “L”. In such a case, since no voltage change occurs in the data electrode D (j), the substantial load capacitance of the data electrode D (j) may be regarded as “0”. Therefore, when the outputs of logic gate 74 (j), logic gate 77 (j), and logic gate 78 (j) are all “L”, the substantial load capacitance of data electrode D (j) in first transition period Ta Is “0”.

The image data Q (j) of the data electrode D (j) changes from “H” to “L”, and the image data Q (j−1) and the data electrode D (j + 1) of the data electrode D (j−1) When the image data Q (j + 1) is not changed (the “L” state is maintained or the “H” state is maintained), the output of the logic gate 84 (j) is “H”. At this time, the substantial load capacity of the data electrode D (j) is the capacity (Cg + 2Cc) as described above. The image data Q (j) of the data electrode D (j) changes from “H” to “L” during the second transition period Tb. Therefore, if the output of the logic gate 84 (j) is “H”, it can be determined that the substantial load capacitance of the data electrode D (j) in the second transition period Tb is the capacitance (Cg + 2Cc).

The image data Q (j) of the data electrode D (j) changes from “H” to “L”, and the image data Q (j−1) and the data electrode D (j + 1) of the data electrode D (j−1) When only one of the image data Q (j + 1) is changed from “H” to “L”, the output of the logic gate 87 (j) becomes “H”. At this time, the substantial load capacity of the data electrode D (j) is the capacity (Cg + Cc) as described above. Therefore, if the output of the logic gate 87 (j) is “H”, it can be determined that the substantial load capacitance of the data electrode D (j) in the second transition period Tb is the capacitance (Cg + Cc).

The image data Q (j) of the data electrode D (j) changes from “H” to “L”, and the image data Q (j−1) and the data electrode D (j + 1) of the data electrode D (j−1) When the image data Q (j + 1) of both change from “H” to “L”, the output of the logic gate 88 (j) becomes “H”. At this time, the substantial load capacity of the data electrode D (j) is the capacity Cg as described above. Therefore, if the output of the logic gate 88 (j) is “H”, it can be determined that the substantial load capacitance of the data electrode D (j) in the second transition period Tb is the capacitance Cg.

In other cases, for example, when the image data Q (j) of the data electrode D (j) is maintained in the “L” state or the “H” state, the output of the logic gate 84 (j), the logic The outputs of the gate 87 (j) and the logic gate 88 (j) are all “L”. In such a case, since no voltage change occurs in the data electrode D (j), the substantial load capacitance of the data electrode D (j) may be regarded as “0”. Therefore, when the outputs of the logic gate 84 (j), the logic gate 87 (j), and the logic gate 88 (j) are all “L”, the substantial load capacitance of the data electrode D (j) in the second transition period Tb. Is “0”.

The above is the operation of the electrode load calculation unit 64 (j) that calculates the substantial load capacity in the data electrode D (j). The load calculation unit 52 includes a plurality of electrode load calculation units 64 that operate in the same manner as the electrode load calculation unit 64 (j). The number of the load calculation units 52 is the same as that of the data electrodes 22 driven by one data driver 40. It is the same number as the number (for example, 384).

The output of all the logic gates 74, logic gates 77, and logic gates 78 provided in the load calculation unit 52 is input to the first load summation unit 65. The first load summing unit 65 determines which of the output signals of the logic gate 74, the logic gate 77, and the logic gate 78 is “L” and which is “H”. 77, the substantial load capacity in each data electrode 22 is calculated from the relationship between the outputs of 77 and logic gate 78 and the substantial load capacity, and the sum of them is calculated. Therefore, this calculation result is the sum of substantial load capacities of the data electrode 22 in the first transition period Ta.

In this way, the first load summation unit 65 sums the substantial load capacitance in the first transition period Ta of all the data electrodes 22 (for example, 384 data electrodes 22) driven by one data driver 40. Is calculated.

The outputs of all the logic gates 84, logic gates 87, and logic gates 88 provided in the load calculation unit 52 are input to the second load summation unit 66. The second load summing unit 66 determines which of the output signals of the logic gate 84, the logic gate 87, and the logic gate 88 is “L” and which is “H”, and the logic gate 84, logic gate, and the like described above. Based on the relationship between each output of 87 and logic gate 88 and the substantial load capacity, the substantial load capacity in each data electrode 22 is calculated, and the sum of them is calculated. Therefore, this calculation result is the sum of substantial load capacities of the data electrode 22 in the second transition period Tb.

In this way, the second load summation unit 66 sums the substantial load capacitance in the second transition period Tb of all the data electrodes 22 (for example, 384 data electrodes 22) driven by one data driver 40. Is calculated.

In this manner, the load calculating unit 52 substantially includes the first transition period Ta and the second transition period Tb of all the data electrodes 22 (for example, 384 data electrodes 22) driven by one data driver 40. Total load capacity is calculated.

Next, the operation of the write timing generation unit 54 will be described.

FIG. 10 is a timing chart showing an example of the operation of the write timing generation unit 54 of the plasma display device 30 in one embodiment of the present invention.

In FIG. 10, the write timing signal LLP (p-1) output from the write timing generation unit 54 (p-1), the write timing signal LLP (p) output from the write timing generation unit 54 (p), Write timing signal LLP (p + 1) output from the timing generator 54 (p + 1), and write output from each data driver 40 of the data driver 40 (p−1), the data driver 40 (p), and the data driver 40 (p + 1) And pulse.

The write timing generation unit 54 (p) generates a write timing signal LLP (p) based on the substantial sum of the load capacities calculated by the load calculation unit 52 (p), and the generated write timing signal LLP (p) Is output. Accordingly, the write timing generation unit 54 (p−1) generates and outputs the write timing signal LLP (p−1) based on the substantial sum of the load capacities calculated by the load calculation unit 52 (p−1). . Further, the write timing generation unit 54 (p + 1) generates and outputs a write timing signal LLP (p + 1) based on the substantial sum of the load capacities calculated by the load calculation unit 52 (p + 1).

In the present embodiment, when the write timing signal LLP is “H”, the output buffer 45 turns off the recovery switch QC and turns on the high-voltage side switch QH or the low-voltage side switch QL, and the data electrode 22 Is clamped to the high voltage Vd or the low voltage 0 (V). When the write timing signal LLP is “L”, the output buffer unit 45 turns on the recovery switch QC, turns off the high-voltage side switch QH and the low-voltage side switch QL, and sets the load capacity of the data electrode 22 and the recovery coil. It is assumed that power is supplied from the recovery capacitor C40 to the data electrode 22 by LC resonance with L40, or power is recovered from the data electrode 22 to the recovery capacitor C40.

In the present embodiment, the time when the write timing signal LLP falls (hereinafter referred to as “falling timing”) represents the start time of the first transition period Ta or the second transition period Tb. The time when the write timing signal LLP rises (hereinafter referred to as “rise timing”) represents the end time of the first transition period Ta or the second transition period Tb.

In this embodiment, the write timing signal is set so that the time length of the first transition period Ta and the second transition period Tb becomes longer as the total sum of the substantial load capacities calculated by the load calculation unit 52 becomes larger. Generate LLP.

However, in the present embodiment, the start time of the first transition period Ta is set independently of the calculation result in the load calculation unit 52.

For example, in FIG. 10, the start time of the first transition period Ta of the write cycle T (i-1) is time t11, the start time of the first transition period Ta of the write cycle T (i) is time t31, The start time of the first transition period Ta of the write cycle T (i + 1) is time t51, but these times are predetermined times and do not change depending on the calculation result in the load calculation unit 52.

On the other hand, the end time of the first transition period Ta changes according to the calculation result in the load calculation unit 52.

For example, in the first transition period Ta of the write cycle T (i−1), the calculation result in the load calculation unit 52 (p + 1) is larger than the calculation result in the load calculation unit 52 (p−1), and the load calculation unit 52 ( When the calculation result in p) is larger than the calculation result in the load calculation unit 52 (p + 1), each resonance period is as follows.

The resonance period between the sum of substantial load capacities of N (for example, N = 384) data electrodes 22 driven by the data driver 40 (p + 1) and the recovery coil L40 (p + 1) is the data driver 40 (p−1). ) Is longer than the total sum of the substantial load capacities of the N data electrodes 22 driven and the resonance period of the recovery coil L40 (p-1). The resonance period between the sum of the substantial load capacities of the N data electrodes 22 driven by the data driver 40 (p) and the recovery coil L40 (p) is determined by N data drivers 40 (p + 1). It becomes longer than the total sum of the substantial load capacities of the data electrodes 22 and the resonance period of the recovery coil L40 (p + 1).

The LC resonance frequency f can be obtained by the following equation.
f = 1 / (2π√ (LC))
L: Inductance of recovery coil L40 C: Sum of substantial load capacities calculated in load calculator 52 And write timing generator 54 includes first transition period Ta and second transition calculated in load calculator 52 Based on the total sum of the substantial load capacities in each of the periods Tb, the resonance period in each of the first transition period Ta and the second transition period Tb is calculated from the above formula. Then, a write timing signal LLP is generated based on the calculated resonance period.

Hereinafter, in the first transition period Ta, the sum of the substantial load capacities of the N data electrodes 22 driven by the data driver 40 (p−1) and the resonance period of the recovery coil L40 (p−1) A time length of ½ is time Ta (p−1). Further, the time length of the sum of the substantial load capacities of the N data electrodes 22 driven by the data driver 40 (p) and the half of the resonance period of the recovery coil L40 (p) is defined as time Ta (p). To do. In addition, a time length that is half of the total load capacity of the N data electrodes 22 driven by the data driver 40 (p + 1) and a resonance period of the recovery coil L40 (p + 1) is a time Ta (p + 1). To do.

Therefore, for example, in the first transition period Ta of the write cycle T (i−1), the calculation result in the load calculation unit 52 (p + 1) is larger than the calculation result in the load calculation unit 52 (p−1), and the load calculation unit If the calculation result at 52 (p) is larger than the calculation result at the load calculation unit 52 (p + 1), the time Ta (p + 1) is longer than the time Ta (p−1), and the time Ta (p) is equal to the time Ta. It becomes longer than (p + 1).

In order to use as much power stored in the recovery capacitor C40 as possible and increase the power consumption reduction effect, the first transition is performed at the time when half the resonance period has elapsed from the start of the first transition period Ta. It is desirable to end the period Ta.

For the data driver 40 (p−1), in order to end the first transition period Ta at the time when half the resonance period has elapsed from the start of the first transition period Ta, the write timing signal LLP The rising timing of (p−1) may be the time t12 (p−1) when the time Ta (p−1) has elapsed from the time t11 in the writing cycle T (i−1). In i), the time Ta (p-1) from the time t31 may be set to the time t32 (p-1). In the write cycle T (i + 1), the time Ta (p-1) is set from the time t51. The elapsed time t52 (p-1) may be set.

For the data driver 40 (p), in order to end the first transition period Ta at the time when half the resonance period has elapsed from the start of the first transition period Ta, the write timing signal LLP (p ) Rise timing may be the time t12 (p) when the time Ta (p) has elapsed from the time t11 in the write cycle T (i-1), and from the time t31 in the write cycle T (i). The time t32 (p) at which the time Ta (p) has elapsed may be set, and in the writing cycle T (i + 1), the time t52 (p) at which the time Ta (p) has elapsed from the time t51 may be set.

For the data driver 40 (p + 1), in order to end the first transition period Ta at the time when half the resonance period has elapsed from the start of the first transition period Ta, the write timing signal LLP (p + 1 ) May be set at time t12 (p + 1) when the time Ta (p + 1) has elapsed from time t11 in the write cycle T (i-1), and from time t31 in the write cycle T (i). The time t32 (p + 1) at which the time Ta (p + 1) has elapsed may be set, and the time t52 (p + 1) at which the time Ta (p + 1) has elapsed from the time t51 may be set in the writing cycle T (i + 1).

Therefore, for example, in the first transition period Ta of the write cycle T (i−1), the calculation result in the load calculation unit 52 (p + 1) is larger than the calculation result in the load calculation unit 52 (p−1), and the load calculation unit If the calculation result at 52 (p) is larger than the calculation result at the load calculation unit 52 (p + 1), as shown in FIG. 10, the time t12 (p + 1) is later than the time t12 (p−1), and the time t12 (p) is further later than time t12 (p + 1).

Alternatively, for example, in the first transition period Ta of the write cycle T (i), the calculation result in the load calculation unit 52 (p) is larger than the calculation result in the load calculation unit 52 (p−1), and the load calculation unit 52 ( If the calculation result at (p + 1) is larger than the calculation result at the load calculation unit 52 (p), as shown in FIG. 10, the time t32 (p) is later than the time t32 (p−1) and the time t32 (p−1) p + 1) is later than time t32 (p).

Alternatively, for example, in the first transition period Ta of the write cycle T (i + 1), the calculation result in the load calculation unit 52 (p) is larger than the calculation result in the load calculation unit 52 (p + 1), and the load calculation unit 52 (p− If the calculation result in 1) is larger than the calculation result in the load calculation unit 52 (p), the time t52 (p) is later than the time t52 (p + 1) and the time t52 (p−) as shown in FIG. 1) is later than time t52 (p).

In the present embodiment, the end time of the second transition period Tb is set independently of the calculation result in the load calculation unit 52.

For example, in FIG. 10, the end time of the second transition period Tb of the write cycle T (i−1) is time t22, and the end time of the second transition period Tb of the write cycle T (i) is time t42. The end time of the second transition period Tb of the write cycle T (i + 1) is time t62, but these times are predetermined times and do not change depending on the calculation result in the load calculation unit 52.

On the other hand, the start time of the second transition period Tb changes according to the calculation result in the load calculation unit 52.

For example, in the second transition period Tb of the write cycle T (i + 1), the calculation result in the load calculation unit 52 (p + 1) is larger than the calculation result in the load calculation unit 52 (p−1), and the load calculation unit 52 (p) When the calculation result in is larger than the calculation result in the load calculation unit 52 (p + 1), each resonance period is as follows.

Hereinafter, in the second transition period Tb, the sum of the substantial load capacities of the N data electrodes 22 driven by the data driver 40 (p−1) and the resonance period of the recovery coil L40 (p−1) The time length of ½ is time Tb (p−1). Further, the total length of the substantial load capacities of the N data electrodes 22 driven by the data driver 40 (p) and the time length ½ of the resonance period of the recovery coil L40 (p) are defined as time Tb (p). To do. In addition, a time length ½ of a resonance period of the total load capacity of the N data electrodes 22 driven by the data driver 40 (p + 1) and the recovery coil L40 (p + 1) is defined as a time Tb (p + 1). To do.

Therefore, for example, in the second transition period Tb of the write cycle T (i + 1), the calculation result in the load calculation unit 52 (p + 1) is larger than the calculation result in the load calculation unit 52 (p−1), and the load calculation unit 52 ( If the calculation result in p) is larger than the calculation result in the load calculation unit 52 (p + 1), the time Tb (p + 1) is longer than the time Tb (p−1), and the time Tb (p) is the time Tb (p + 1). ) Is even longer.

In order to recover as much power as possible in the recovery capacitor C40, it is desirable to end the second transition period Tb at the time when half the resonance period has elapsed since the start of the second transition period Tb.

For the data driver 40 (p−1), in order to end the second transition period Tb at the time when ½ of the resonance period has elapsed from the start of the second transition period Tb, the write timing signal LLP The falling timing of (p-1) may be the time t21 (p-1) before the time Tb (p-1) from the time t22 in the write cycle T (i-1). In i), time t41 (p-1) before time Tb (p-1) from time t42 may be set. In write cycle T (i + 1), time Tb (p-1) before time t62. Time t61 (p-1) may be set.

For the data driver 40 (p), in order to end the second transition period Tb at the time when half the resonance period has elapsed from the start of the second transition period Tb, the write timing signal LLP (p ) May be set to the time t21 (p) before the time Tb (p) from the time t22 in the write cycle T (i-1), and from the time t42 in the write cycle T (i). The time t41 (p) before the time Tb (p) may be set, and the time t61 (p) before the time Tb (p) from the time t62 may be set in the writing cycle T (i + 1).

For the data driver 40 (p + 1), in order to end the second transition period Tb at the time when a half of the resonance period has elapsed from the start of the second transition period Tb, the write timing signal LLP (p + 1 ) In the write cycle T (i−1) may be the time t21 (p + 1) before the time Tb (p + 1) from the time t22, and from the time t42 in the write cycle T (i). Time t41 (p + 1) before time Tb (p + 1) may be set, and time t61 (p + 1) before time Tb (p + 1) from time t62 may be set in the write cycle T (i + 1).

Therefore, for example, in the second transition period Tb of the write cycle T (i−1), the calculation result in the load calculation unit 52 (p) is larger than the calculation result in the load calculation unit 52 (p + 1), and the load calculation unit 52 ( If the calculation result at p-1) is larger than the calculation result at the load calculation unit 52 (p), as shown in FIG. 10, time t21 (p) is earlier than time t21 (p + 1), and time t21 (p + 1) p-1) is earlier than time t21 (p).

Alternatively, for example, in the second transition period Tb of the write cycle T (i), the calculation result in the load calculation unit 52 (p + 1) is larger than the calculation result in the load calculation unit 52 (p), and the load calculation unit 52 (p− If the calculation result in 1) is larger than the calculation result in the load calculation unit 52 (p + 1), as shown in FIG. 10, the time t41 (p + 1) is earlier than the time t41 (p), and the time t41 (p− 1) is earlier than time t41 (p + 1).

Alternatively, for example, in the second transition period Tb of the write cycle T (i + 1), the calculation result in the load calculation unit 52 (p + 1) is larger than the calculation result in the load calculation unit 52 (p−1), and the load calculation unit 52 ( If the calculation result at p) is larger than the calculation result at the load calculation unit 52 (p + 1), as shown in FIG. 10, the time t61 (p + 1) is earlier than the time t61 (p-1), and the time t61 (p-1) p) is earlier than time t61 (p + 1).

As described above, the data electrode driving circuit 32 according to the present embodiment calculates the sum of substantial load capacities of N (for example, N = 384) data electrodes 22 driven by the data driver 40, and A resonance period between the calculation result and the recovery coil L40 is calculated. Based on the result, each switch of the output buffer unit 45 is controlled, and the length of time for supplying power from the recovery capacitor C40 to the data electrode 22 (first transition period Ta), or the power from the data electrode 22 to the recovery capacitor C40. The time length (second transition period Tb) for collecting the data is controlled. When the resonance period is long, each switch is controlled so that the first transition period Ta or the second transition period Tb is long. When the resonance period is short, the first transition period Ta or the second transition period Tb is short. Control each switch.

That is, in the first transition period, the data driver 40 having a relatively large sum of substantial load capacities in the first transition period than the data driver 40 having a relatively small sum of substantial load capacities. Increase the length of time. For example, if the start time of the first transition period is the same timing for each data driver 40, the end time of the first transition period is substantially the same for the data driver 40 having a relatively large sum of substantial load capacities. The total load capacity is slower than that of the data driver 40, which is relatively small.

Similarly, in the second transition period, the data driver 40 having a relatively large sum of substantial load capacities has a second transition period compared to the data driver 40 having a relatively small sum of substantial load capacities. Increase the time length of. For example, if the end time of the second transition period is the same timing for each data driver 40, the start time of the second transition period is substantially the same for the data driver 40 having a relatively large sum of substantial load capacities. The total sum of the load capacities is faster than that of the data driver 40, which is relatively small.

Further, according to the present embodiment, the power consumption of the data electrode driving circuit 32 can be reduced by the configuration and operation described above even if each recovery switch QC is configured by one MOSFET in the output buffer unit 45. Is possible. Further, the time for applying the voltage Vd of the write pulse can be extended, and the write operation using the drive time can be performed effectively.

In the present embodiment, as shown in FIG. 7, an example in which the recovery switch QC is configured using a P-channel MOSFET has been described. However, the present invention is not limited to this configuration. FIG. 11 is a circuit diagram schematically showing another configuration example of the output buffer unit of the plasma display device in accordance with the exemplary embodiment of the present invention. For example, as shown in FIG. 11, in the output buffer unit, the recovery switch QC can be configured using an N-channel MOSFET.

In the present embodiment, the data electrode driving circuit 32 calculates the total sum of substantial load capacities of N (for example, N = 384) data electrodes 22 driven by the data driver 40 based on the image data, The configuration in which the calculation result and the resonance period of the recovery coil L40 are calculated to control each switch of the output buffer unit 45 has been described. However, for example, the data electrode drive circuit 32 detects the resonance period between the load capacitance and the recovery coil based on the change in the voltage applied to the data electrode 22, and controls each switch of the output buffer unit 45 based on the detection result. Even in the configuration, the same effect as described above can be obtained.

The drive voltage waveforms shown in FIGS. 4, 8, and 10 are merely examples in the embodiment of the present invention, and the present invention is not limited to these drive voltage waveforms.

Further, the circuit configurations shown in FIGS. 5, 6, 7, and 9 are merely examples in the embodiment of the present invention, and the present invention is not limited to these circuit configurations. .

Note that each circuit block shown in the embodiment of the present invention may be configured as an electric circuit that performs each operation shown in the embodiment, or a microcomputer that is programmed to perform the same operation. May be used.

In the embodiment of the present invention, an example in which one field is composed of eight subfields has been described. However, in the present invention, the number of subfields constituting one field is not limited to the above number. For example, by increasing the number of subfields, the number of gradations that can be displayed on the panel 10 can be further increased.

In the embodiment of the present invention, an example in which one pixel is constituted by discharge cells of three colors of red, green, and blue has been described. However, a panel in which one pixel is constituted by discharge cells of four colors or more. However, it is possible to apply the configuration shown in the embodiment of the present invention, and the same effect can be obtained.

The specific numerical values shown in the embodiment of the present invention are set based on the characteristics of the panel 10 having a screen size of 50 inches and the number of display electrode pairs 14 of 1024. It is just an example. The present invention is not limited to these numerical values, and each numerical value is desirably set optimally in accordance with panel specifications, panel characteristics, plasma display device specifications, and the like. Each of these numerical values is allowed to vary within a range where the above-described effect can be obtained. Also, the number of subfields constituting one field, the luminance weight of each subfield, etc. are not limited to the values shown in the embodiment of the present invention, and the subfield configuration is based on the image signal or the like. It may be configured to switch.

The present invention can stably supply power to a data electrode driving circuit to perform a stable address operation and reduce power consumption of the data electrode driving circuit. Therefore, the present invention provides a plasma display device and a plasma display device driving method. Useful.

DESCRIPTION OF SYMBOLS 10 Panel 11 Front substrate 12 Scan electrode 13 Sustain electrode 14

Display electrode pair

15, 23 Dielectric layer 16 Protective layer 21 Back substrate 22 Data electrode 24 Partition 25, 25R, 25G, 25B Phosphor layer 30 Plasma display device 31 Image signal processing Circuit 32 Data electrode drive circuit 33 Scan electrode drive circuit 34 Sustain electrode drive circuit 35 Timing generation circuit 40

Data driver

41, 61

Shift register unit

42, 44, 62 Latch 43 Data latch unit 45 Output buffer unit 46 Output buffer 52 Load calculation unit 52 54 write timing generation unit 63 load calculation unit 64 electrode load calculation unit 65 first load summation unit 66 second load summation unit 71 one

line delay

72, 74, 75, 76, 77, 78, 82, 84, 85, 86, 87,88 Logic gate C40 Recovery capacitor L40 Recovery coil LLP Write timing signal QH High voltage side switch QL Low voltage side switch QC Recovery switch

Claims

A plasma display panel having a plurality of display electrode pairs and a plurality of data electrodes, and a data electrode driving circuit for applying an address pulse to the data electrodes, wherein the data electrode driving circuit performs the writing for each writing cycle in a writing period. A plasma display apparatus that applies a high voltage side voltage of a pulse or a low voltage side voltage of the write pulse to the data electrode,
The data electrode driving circuit includes a recovery capacitor and a recovery coil connected in series to the recovery capacitor, and includes a high-voltage side switch that outputs the high-voltage side voltage, a low-voltage side switch that outputs the low-voltage side voltage, and the recovery An output buffer having a recovery switch connected to a capacitor for each of the data electrodes;
The output buffer turns on the recovery switch during the first transition period provided in the write cycle when the voltage of the write pulse changes from the low-voltage side voltage to the high-voltage side voltage. The output capacitance is increased by resonating the load capacity of the recovery coil and the recovery coil, and then the recovery switch is turned off and the high-voltage side switch is turned on to clamp the output voltage to the high-voltage side voltage,
When transitioning the voltage of the write pulse from the high-voltage side voltage to the low-voltage side voltage, the recovery switch is turned on in the second transition period provided in the write cycle and the load capacitance of the data electrode and the Resonate with the recovery coil to lower the output voltage, then turn off the recovery switch and turn on the low-voltage side switch to clamp the output voltage to the low-voltage side voltage,
The plasma display apparatus characterized by temporally separating the second transition period and the first transition period immediately after the second transition period.
The data electrode driving circuit is configured by using a plurality of integrated circuits in which a plurality of output buffers are integrated, and calculates a sum of substantial load capacities of the plurality of data electrodes driven by the integrated circuit. Controlling the high-pressure side switch, the low-pressure side switch, and the recovery switch based on the sum so that the time length of the first transition period or the second transition period is longer when the sum is smaller than when the sum is small. The plasma display device according to claim 1.
One field is composed of a plurality of subfields having an address period and a sustain period,
In the write period, a write pulse from a data driver that drives a plurality of data electrodes by causing a recovery capacitor and a recovery coil to resonate with the data electrodes of a plasma display panel having a plurality of display electrode pairs and a plurality of data electrodes. A method of driving a plasma display device that applies
Calculating a sum of substantial load capacities of the plurality of data electrodes driven by the data driver;
A time length of a first transition period in which the voltage of the write pulse is changed from a low voltage to a high voltage and a second transition period in which the voltage of the write pulse is changed from the high voltage to the low voltage is the sum. The method of driving a plasma display device according to claim 1, wherein the time length of the first transition period or the second transition period is made longer when the sum is large than when the sum is small.